High-noise-immunity and low-delay level shift circuit for GAN half-bridge drive chip

Abstract

A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge drive chip, relating to the technical field of power management in integrated circuits. By additionally providing a path from a floating power rail VDDH to the ground, the level shift circuit simulates the noise effect caused by a sudden change in the voltage of the floating power rail in the level shift circuit. The level shift circuit has a good noise immunity capability and a simple structure.

Description

High-noise-immunity and low-delay level shift circuit for GaN half-bridge driving chip TECHNICAL FIELD

[0001] The application belongs to the technical field of power management in integrated circuits, and relates to a high-noise-immunity and low-delay level shift circuit for a GaN half-bridge driving chip. BACKGROUND

[0002] Because the turn-on and turn-off output point voltage of the power tube in the half-bridge topology structure works in a floating state, the power supply voltage of the high-voltage side driving circuit also works in a floating state. Generally, the floating power supply of the high-voltage side driving circuit is obtained by using an external bootstrap capacitor. Because the power supply of the high-voltage side driving circuit is floating, when the floating power supply voltage changes, a very high dv / dt noise will be generated. Because the parasitic capacitance of the LDMOS drain end is large, the potential of the LDMOS drain end cannot closely follow the change of the floating voltage, and a certain voltage drop will be generated. Once the voltage drop reaches the threshold voltage of the subsequent circuit, the driving circuit will be mis-triggered and even burned out. Compared with traditional Si-based devices, the switching frequency of a GaN device is in the MHZ level, the turn-on and turn-off time is extremely fast, and the dv / dt noise generated by the floating power supply rail is larger. Therefore, the level shift circuit required by the GaN device needs higher noise immunity and lower delay.

[0003] In order to eliminate the dv / dt noise, a traditional solution is to connect a narrow pulse filter circuit to the subsequent stage of the level shift circuit, as shown in FIG. 1. When there is a large dv / dt noise, the delay of the required narrow pulse filter circuit will be larger, which will cause a large delay of the driving chip. In addition, many scholars increase the noise immunity by shunting without increasing the circuit delay, but the noise immunity can be further improved. SUMMARY

[0004] Therefore, the purpose of the application is to provide a GaN level shift circuit with ultra-high dv / dt noise suppression. The application effectively blocks the influence of noise on the output without affecting the normal signal transmission of the circuit, and improves the stability and reliability of the circuit.

[0005] To achieve the above purpose, the application provides the following technical scheme:

[0006] A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge driving chip, by additionally increasing a path of a floating power supply rail VDDH to the ground, the influence of noise caused by the sudden change of the voltage of the floating power supply rail in the level shift circuit is simulated. This scheme can theoretically achieve very good noise immunity, only six PMOS tubes (MP9-MP14), one NLDMOS (LD3), and one inverter (INV5) are added, and the structure is simple.

[0007] The circuit specifically comprises first to fourteenth PMOS transistors MP1-MP14, first to seventh NMOS transistors MN1-MN7, a first resistor R1, a second resistor R2, first to third NLDMOS transistors LD1-LD3, and first to fifth inverters INV1-INV5.

[0008] The gates of the first and second NLDMOS transistors LD1 and LD2 are connected to a low-voltage narrow pulse signal, the sources thereof are connected to ground, and the drains thereof are connected to the drains of the first and seventh PMOS transistors MP1 and MP7 respectively; the gate and source of the third NLDMOS transistor LD3 are connected to ground, and the drain thereof is connected to the drain of the thirteenth PMOS transistor MP13.

[0009] The gate and source of the first NMOS transistor MN1 are connected to a floating ground VSW, and the drain thereof is connected to the drain of the first NLDMOS transistor LD1; the source of the second NMOS transistor MN2 is connected to the floating ground VSW, the gate and drain thereof are connected in short, and the gate and drain thereof are connected to the floating ground VSW through the first resistor R1; the gate of the third NMOS transistor MN3 is connected to the gate of the second NMOS transistor MN2, the source thereof is connected to the floating ground VSW, and the drain thereof is connected to the drain of the eleventh PMOS transistor MP11; the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN5, the source thereof is connected to the floating ground VSW, and the drain thereof is connected to the drain of the tenth PMOS transistor MP10; the gate and drain of the fifth NMOS transistor MN5 are connected in short, and the gate and drain thereof are connected to the floating ground VSW through the second resistor R2, and the source thereof is connected to the floating ground VSW; the gate and source of the sixth NMOS transistor MN6 are connected to the floating ground VSW, and the drain thereof is connected to the drain of the second NLDMOS transistor LD2; the gate and source of the seventh NMOS transistor MN7 are connected to the floating ground VSW, and the drain thereof is connected to the drain of the third NLDMOS transistor LD3.

[0010] The gate and the drain of the first PMOS transistor MP1 are shorted, the source thereof is connected to the drain of the first NLDMOS transistor LD1, and the source thereof is connected to the floating power supply rail VDDH; the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, the source thereof is connected to the floating power supply rail VDDH, and the drain thereof is connected to the source of the ninth PMOS transistor MP9; the gate of the third PMOS transistor MP3 is connected to the gate of the first PMOS transistor MP1, the source thereof is connected to the floating power supply rail VDDH, and the drain thereof is connected to the source of the tenth PMOS transistor MP10; the gate and the source of the fourth PMOS transistor MP4 are shorted, the drain thereof is connected to the gate of the first PMOS transistor MP1, and the source thereof is connected to the floating power supply rail VDDH; the source of the fifth PMOS transistor MP5 is connected to the floating power supply rail VDDH, the gate thereof is connected to the drain of the second NLDMOS transistor LD2, and the drain thereof is connected to the source of the eleventh PMOS transistor MP11; the source of the sixth PMOS transistor MP6 is connected to the floating power supply rail VDDH, the gate thereof is connected to the gate of the fifth PMOS transistor MP5, and the drain thereof is connected to the source of the twelfth PMOS transistor MP12; the gate and the drain of the seventh PMOS transistor MP7 are shorted, the source thereof is connected to the gate of the fifth PMOS transistor MP5, and the source thereof is connected to the floating power supply rail VDDH; the gate and the source of the eighth PMOS transistor MP8 are shorted, the drain thereof is connected to the gate of the fifth PMOS transistor MP5, and the source thereof is connected to the floating power supply rail VDDH; the drain of the ninth PMOS transistor MP9 is connected to the drain of the second NMOS transistor MN2; the drain of the twelfth PMOS transistor MP12 is connected to the drain of the fifth NMOS transistor MN5; the gates of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are connected to the output terminal of the fifth inverter INV5; the source of the thirteenth PMOS transistor MP13 is connected to the floating power supply rail VDDH, the gate and the drain thereof are shorted, and the drain thereof is connected to the drain of the third NLDMOS transistor LD3; the gate and the source of the fourteenth PMOS transistor PM14 are shorted, the drain thereof is connected to the drain of the third NLDMOS transistor LD3, and the source thereof is connected to the floating power supply rail VDDH.

[0011] The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 are connected between the floating power supply rail VDDH and the floating ground VSW; the input of the first inverter INV1 is connected to the drain of the third NMOS transistor MN3, and the output thereof is connected to the drain of the fourth NMOS transistor MN4; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the output thereof is connected to the input of the first inverter INV1; the input of the third inverter INV3 is connected to the input of the first inverter INV1, and the output thereof is connected to OUT+; the input of the fourth inverter INV4 is connected to the output of the first inverter INV1, and the output thereof is connected to OUT-.

[0012] Further, when there is positive dVSW / dt noise, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are turned off to prevent the noise from being transmitted to the output end, and the noise elimination capability is infinite in the ideal case, which depends on the tolerance of the devices connected to the nodes G1, G2 and G3 (i.e., the gate-source breakdown voltage and the source-drain breakdown voltage of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the thirteenth PMOS tube MP13, and the source-drain breakdown voltage of the fourth PMOS tube MP4, the eighth PMOS tube MP8 and the fourteenth PMOS tube MP14), thereby ensuring the stability of the circuit.

[0013] Further, when there is positive dVSW / dt noise, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are turned off to prevent the noise from being transmitted to the output end, and the noise elimination capability is infinite in the ideal case, which depends on the tolerance of the devices connected to the nodes G1, G2 and G3 (i.e., the gate-source breakdown voltage and the source-drain breakdown voltage of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7 and the thirteenth PMOS tube MP13, and the source-drain breakdown voltage of the fourth PMOS tube MP4, the eighth PMOS tube MP8 and the fourteenth PMOS tube MP14), thereby ensuring the stability of the circuit.

[0014] The present application has the advantages that the circuit can effectively prevent the influence of dv / dt noise on the output without increasing the circuit delay, has strong noise resistance and can be effectively applied to GaN half-bridge driving chips.

[0015] Other advantages, objects, and features of the application will be apparent from the following specification and appended claims, and from the foregoing description. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to make the objectives, technical solutions and advantages of the present application clearer, the preferred embodiments of the present application will be described in detail below with reference to the drawings, it should be noted that the voltage changes of the node signals are relative to the floating voltage VSW except the input signal IN. Among them:

[0017] FIG. 1 is a conventional level shift circuit;

[0018] FIG. 2 is a level shift circuit suitable for GaN half-bridge driving chips according to the present application;

[0019] FIG. 3 is a working waveform diagram without noise interference;

[0020] Fig. 4 is a delay waveform of the level shift circuit;

[0021] Fig. 5 is a working waveform diagram when there is noise interference;

[0022] Fig. 6 is a working waveform diagram when there is 3500V / ns noise interference. DETAILED DESCRIPTION

[0023] The advantages and effects of the present application can be easily understood by those skilled in the art from the description of the specific embodiments. The present application can also be implemented or applied in other different embodiments, and various modifications or changes can be made to the details based on different views and applications without departing from the spirit of the present application. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner, and the embodiments and features in the embodiments can be combined with each other without conflict.

[0024] The drawings are only used for exemplary illustration, and the representation is only a schematic diagram, not a physical diagram, and should not be understood as a limitation of the present application. In order to better illustrate the embodiments of the present application, some components in the drawings may be omitted, enlarged or reduced, and do not represent the actual size of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions in the drawings may be omitted.

[0025] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only used for exemplary illustration, and should not be understood as a limitation of the present application. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0026] Please refer to Figs. 2-6, as shown in Fig. 2, the level shift circuit of the present application is composed of first to fourteenth PMOS transistors MP1-MP14, first to seventh NMOS transistors MN1-MN7, first and second resistors R1 and R2, first to third NLDMOS transistors LD1-LD3, and first to fifth inverters INV1-INV5. VDDH is a floating power rail voltage, and VSW is a floating ground. The resistors R1 and R2 prevent the mis-conduction of MN3 and MN4 during the non-working period.

[0027] When there is no noise, the waveform is shown in Figure 3. After the input square wave signal passes through the narrow pulse generator, a narrow pulse signal is formed, and LD1 and LD2 are turned on at the rising edge and falling edge of the input square wave, respectively. When LD1 is turned on, the generated pull-down current will lower the potential of node G1 to turn on MP2 and MP3. MN1 adopts a diode connection mode, which clamps the potential of node G1 to prevent the voltage drop from being too large to break MP1, MP2, and MP3. After MP2 and MP3 are turned on, the pull-down current generated by MP9 and MP10 with a low gate will pull node F1 to a high level, and then the current mirror formed by MN2 and MN3 will pull node H1 to a low level; at the same time, node H2 will be maintained at a high level, and finally the output OUT+ will be pulled to a high level by the inverter INV3. When LD2 is turned on, the generated pull-down current will lower the potential of node G2 to turn on MP5 and MP6. MN6 adopts a diode connection mode, which clamps the potential of node G2 to prevent the voltage drop from being too large to break MP5, MP6, and MP7. After MP5 and MP6 are turned on, the pull-down current generated by MP11 and MP12 with a low gate will pull node F2 to a high level, and then the current mirror formed by MN4 and MN5 will pull node H2 to a low level; at the same time, node H1 will be maintained at a high level, and finally the output OUT- will be pulled to a high level by the inverter INV4. The functions of INV1 and INV2 are to generate positive feedback and accelerate signal transmission. As shown in Figure 4, the delay of the rising edge is 2.72 ns, and the delay of the falling edge is 2.72 ns.

[0028] However, in practical application to the internal of the GaN half-bridge drive chip, the upper tube of the half-bridge structure is turned on, which quickly raises the voltage of the floating ground VSW. Since the high-voltage area of the GaN half-bridge drive chip adopts a bootstrap capacitor for power supply, the voltage of the floating power rail VDDH is also raised. However, the parasitic capacitance of the NLDMOS drain to ground is large, which causes the drain voltage to be unable to change in time with the change of the floating power rail, forming a voltage drop and turning on MP2, MP3, MP5, and MP6, and transmitting noise to the output end, causing logic function disorder.

[0029] In the present application, an additional floating power supply VDDH to ground path is introduced. The on-resistance of MP13 is about 3 times larger than that of MP1, MP7. When positive dVSW / dt comes, the potential of node G3 changes more slowly than that of nodes G1, G2. When the potential of nodes G1, G2 drops relative to the floating power supply rail, MP2, MP3, MP5, MP6 are turned on, node G3 has triggered the inverter output high level, turn off MP9, MP10, MP11, MP12, so that the noise cannot be transmitted to the output, the ideal case is to eliminate the ability of noise is infinite, depending on the device itself connected to the nodes G1, G2, G3 resistance (i.e. the first PMOS MP1, MP2, MP3, the fifth PMOS PM5, the sixth PMOS MP6, the seventh PMOS MP7, the thirteenth PMOS MP13 gate-source, source-drain breakdown voltage size and the fourth PMOS MP4, MP8 and the fourteenth PMOS MP14 source-drain breakdown voltage size), to ensure the stability of the circuit work. When negative dVSW / dt comes, MP2, MP3, MP5, MP6 are turned off, which will not affect the output. The role of MP4, MP8, MP14 is to clamp the voltage of nodes G1, G2, G3, to protect the circuit. Figures 5 and 6 are the working waveforms when there is noise, it can be seen that when dVSW / dt = 3500V / ns, it will not affect the stability of the work.

[0030] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should be covered by the scope of the claims of the present application.

Claims

1. A high-noise-immunity, low-latency level-shifting circuit for a GaN half-bridge driver chip, characterized in that, The first PMOS tube MP1 to the fourteenth PMOS tube MP14, the first NMOS tube MN1 to the seventh NMOS tube MN7, the first resistance R1, the second resistance R2, the first NLDMOS tube LD1 to the third NLDMOS tube LD3, and the first inverter INV1 to the fifth inverter INV5 are included; The gate of the first NLDMOS tube LD1 and the gate of the second NLDMOS tube LD2 are connected to a low-voltage narrow pulse signal, the source is connected to the ground, and the drain is connected to the drain of the first PMOS tube MP1 and the drain of the seventh PMOS tube MP7 respectively; the gate and the source of the third NLDMOS tube LD3 are connected to the ground, and the drain is connected to the drain of the thirteenth PMOS tube MP13; The gate and the source of the first NMOS tube MN1 are connected to the floating ground VSW, and the drain is connected to the drain of the first NLDMOS tube LD1; the source of the second NMOS tube MN2 is connected to the floating ground VSW, the gate and the drain are connected in short, and are connected to the floating ground VSW through the first resistance R1; the gate of the third NMOS tube MN3 is connected to the gate of the second NMOS tube MN2, the source is connected to the floating ground VSW, and the drain is connected to the drain of the eleventh PMOS tube MP11; the gate of the fourth NMOS tube MN4 is connected to the gate of the fifth NMOS tube MN5, the source is connected to the floating ground VSW, and the drain is connected to the drain of the tenth PMOS tube MP10; the gate and the drain of the fifth NMOS tube MN5 are connected in short, and are connected to the floating ground VSW through the second resistance R2, and the source is connected to the floating ground VSW; the gate and the source of the sixth NMOS tube MN6 are connected to the floating ground VSW, and the drain is connected to the drain of the second NLDMOS tube LD2; the gate and the source of the seventh NMOS tube MN7 are connected to the floating ground VSW, and the drain is connected to the drain of the third NLDMOS tube LD3; The gate and the drain of the first PMOS transistor MP1 are short-circuited, the drain is connected to the drain of the first NLDMOS transistor LD1, and the source is connected to the floating power supply rail VDDH; the gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, the source is connected to the floating power supply rail VDDH, and the drain is connected to the source of the ninth PMOS transistor MP9; the gate of the third PMOS transistor MP3 is connected to the gate of the first PMOS transistor MP1, the source is connected to the floating power supply rail VDDH, and the drain is connected to the source of the tenth PMOS transistor MP10; the gate and the source of the fourth PMOS transistor MP4 are short-circuited, the drain is connected to the floating power supply rail VDDH, and the gate is connected to the gate of the first PMOS transistor MP1; the source of the fifth PMOS transistor MP5 is connected to the floating power supply rail VDDH, the gate is connected to the drain of the second NLDMOS transistor LD2, and the drain is connected to the source of the eleventh PMOS transistor MP11; the source of the sixth PMOS transistor MP6 is connected to the floating power supply rail VDDH, the gate is connected to the gate of the fifth PMOS transistor MP5, and the drain is connected to the source of the twelfth PMOS transistor MP12; the gate and the drain of the seventh PMOS transistor MP7 are short-circuited, the source is connected to the floating power supply rail VDDH, and the gate is connected to the gate of the fifth PMOS transistor MP5; the source and the gate of the eighth PMOS transistor MP8 are short-circuited, the drain is connected to the gate of the fifth PMOS transistor MP5, and the source is connected to the floating power supply rail VDDH; the drain of the ninth PMOS transistor MP9 is connected to the drain of the second NMOS transistor MN2; the drain of the twelfth PMOS transistor MP12 is connected to the drain of the fifth NMOS transistor MN5; the gates of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are connected to the output of the fifth inverter INV5; the source of the thirteenth PMOS transistor MP13 is connected to the floating power supply rail VDDH, the gate and the drain are short-circuited, and the drain is connected to the drain of the third NLDMOS transistor LD3; the gate and the source of the fourteenth PMOS transistor PM14 are short-circuited, the drain is connected to the drain of the third NLDMOS transistor LD3, and the source is connected to the floating power supply rail VDDH; The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 are connected between the floating power supply rail VDDH and the floating ground VSW; the input of the first inverter INV1 is connected to the drain of the third NMOS transistor MN3, and the output is connected to the drain of the fourth NMOS transistor MN4; the input of the second inverter INV2 is connected to the output of the first inverter INV1, and the output is connected to the input of the first inverter INV1; the input of the third inverter INV3 is connected to the input of the first inverter INV1, and the output is connected to OUT+; the input of the fourth inverter INV4 is connected to the output of the first inverter INV1, and the output is connected to OUT-.

2. The high noise immunity, low latency level shifting circuit of claim 1, wherein, When a positive dVSW / dt noise comes, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11 and the twelfth PMOS transistor MP12 are used to cut off the noise in time, so as to ensure the stability of the circuit.

3. The high noise immunity, low latency level shifting circuit of claim 2, wherein, When positive dVSW / dt comes, the ninth PMOS MP9, the tenth PMOS MP10, the eleventh PMOS MP11 and the twelfth PMOS MP12 are turned off, so that the noise cannot be transmitted to the output, and the ability of eliminating the noise is ideally infinite, which depends on the gate-source breakdown voltage and the source-drain breakdown voltage of the first PMOS MP1, the second PMOS MP2, the third PMOS MP3, the fifth PMOS MP5, the sixth PMOS MP6, the seventh PMOS MP7 and the thirteenth PMOS MP13, and the source-drain breakdown voltage of the fourth PMOS MP4, the eighth PMOS MP8 and the fourteenth PMOS MP14, so that the stability of the circuit is ensured; when negative dVSW / dt comes, the second PMOS MP2, the third PMOS MP3, the fifth PMOS MP5 and the sixth PMOS MP6 are turned off, and the output is not affected.

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