Three-dimensional semiconductor integrated structure

Abstract

A three-dimensional semiconductor integrated structure 1 comprises a glass substrate 10 and a plurality of bare chips 70 placed on the glass substrate 10. A circuit 30 formed from a polysilicon TFT is formed on the glass substrate 10, and at least a part of the circuit 30 is provided in regions overlapping the bare chips 70 when the glass substrate 10 is viewed in a plan view. This makes it possible to obtain a three-dimensional semiconductor integrated structure with small size and low wiring impedance while using a glass substrate interposer.

Description

3D semiconductor integrated structure

[0001] The present invention relates to a three-dimensional semiconductor integrated structure using a glass substrate.

[0002] In recent years, a technology that can be called a chiplet integration structure has been attracting attention as a semiconductor post-processing technology, in which multiple semiconductor chips with individual functions are placed on an interposer and functional circuits are integrated to create a semiconductor system.

[0003] Recently, a new proposal has been made to construct a chiplet integration structure using a glass substrate interposer (see, for example, Non-Patent Document 1). By using a glass substrate instead of a silicon substrate as the interposer material, large-sized components can be obtained, and the number of interposers that can be produced increases, which is expected to lead to significant cost reductions.

[0004] "Intel to Replace CPU Substrates with Glass, Aiming to Improve Performance with AI and Other Technologies from the Late 2020s," [online], September 19, 2023, Dempa Shimbun, Inc. [Retrieved May 20, 2024], Internet (URL: https: / / dempa-digital.com / article / 475073)

[0005] Special Publication No. 2021-501990

[0006] In chiplet integration, functional circuit chips with different operating power supply voltages are often assembled on a single interposer due to different process rules, requiring a separate power supply circuit to generate the required power supply voltage. Furthermore, separate level conversion circuits are required to transmit and receive signals between functional circuits with different signal levels. Furthermore, other circuits that could not be mounted on the functional circuit chip may also be required.

[0007] Currently, such peripheral circuits can be integrated into separate functional circuit chips or provided on dedicated chips separate from the functional circuit chips. However, the former approach requires mixing IP (Intellectual Property) based on fine design rules with IP based on relatively large design rules on a single chip, which increases the manufacturing process and makes it unrealistic. The latter approach also increases the number of chips to be mounted, reducing space utilization efficiency and hindering miniaturization. Furthermore, the need for wiring between chips poses the risk of the impedance of this wiring hindering high-speed operation.

[0008] The present invention has been made in view of the above circumstances, and has as its object to obtain a three-dimensional semiconductor integrated structure that is small in size and has reduced wiring impedance while using a glass substrate interposer.

[0009] The three-dimensional semiconductor integrated structure of the present invention is a three-dimensional semiconductor integrated structure comprising a glass substrate and a plurality of bare chips placed on the glass substrate, characterized in that a circuit made of polysilicon TFTs is formed on the glass substrate, and when the glass substrate is viewed in a plane, at least a portion of the circuit is provided in an area that overlaps with the bare chips.

[0010] According to the present invention, even though a glass substrate interposer is used, power supply circuits, level conversion circuits, and other circuits can be provided within the glass substrate interposer and directly below the functional circuit chip, thereby making it possible to obtain a smaller three-dimensional semiconductor integrated structure with reduced wiring impedance.

[0011] 1 is a diagram illustrating a three-dimensional semiconductor integrated structure 1 according to a first aspect of embodiment 1. FIG. 2 is a cross-sectional view illustrating a three-dimensional semiconductor integrated structure 2 according to a second aspect of embodiment 1. FIG. 3 is a cross-sectional view illustrating a three-dimensional semiconductor integrated structure 3 according to a first aspect of embodiment 2. FIG. 4 is a cross-sectional view illustrating a three-dimensional semiconductor integrated structure 4 according to a second aspect of embodiment 2.

[0012] The three-dimensional semiconductor integrated structure of the present invention will be described below with reference to the drawings. In the drawings, although the symbols indicating the components are given consecutive numbers (for example, the bare chip 70), １ , 70 ２ In the specification, the serial numbers may be omitted (e.g., bare chip 70). For configurations and structures common to the figures, the reference numbers in the previous figures may be used, and the reference numbers may be omitted in subsequent figures.

[0013] [Embodiment 1] 1. Configuration of Three-Dimensional Semiconductor Integrated Structures 1 and 2 According to Embodiment 1 FIG. 1 is a diagram shown to explain a three-dimensional semiconductor integrated structure 1 according to a first aspect of embodiment 1. FIG. 1(a) is a plan view of the three-dimensional semiconductor integrated structure 1, and FIG. 1(b) is a cross-sectional view taken along the line A-A in FIG. 1(a). In FIG. 1, a circuit 30 is formed on the upper surface 11 of a glass substrate 10. FIG. 2 is a cross-sectional view shown to explain a three-dimensional semiconductor integrated structure 2 according to a second aspect of embodiment 1. FIG. 2 corresponds to the cross-sectional view of FIG. 1(b) (the same applies to FIGS. 3 and 4 below), and shows a variation in which the circuit 30 is formed on the lower surface 12 of the glass substrate 10.

[0014] (1) Three-dimensional semiconductor integrated structure 1, 2 As shown in FIGS. 1 and 2, the three-dimensional semiconductor integrated structure 1 has a glass substrate 10 and a plurality of bare chips 70 mounted on the glass substrate 10, and can be called a chiplet integrated structure.

[0015] (2) Bare Chip 70 The bare chip 70 refers to a semiconductor chip that is not packaged by a mold or the like. The bare chip 70 (chiplet) may be cut out in any unit, but may also be cut out as a bare chip in functional circuit units such as AI processing, processor, graphics processing, memory, and communication.

[0016] (3) Glass Substrate 10 The glass substrate 10 is a substrate on which a plurality of bare chips 70 are mounted, and serves as a relay member (interposer) for electrical connection between the bare chips 70 and connection between the bare chips 70 and a motherboard (not shown). The glass substrate 10 has two main surfaces, and for convenience, the surface on which the bare chips 70 are mounted is referred to as the upper surface 11, and the surface opposite to the side on which the bare chips 70 are mounted is referred to as the lower surface 12.

[0017] The glass substrate 10 is a plate made of glass in the broad sense, which is obtained by heat-treating a material whose main component is silicon dioxide. The glass substrate 10 of the first embodiment is a substrate on which polysilicon TFTs (described later) can be formed. The glass substrate 10 may be made of, for example, general industrial glass, which is economical and used in semiconductor devices and liquid crystal display devices, or may be made of quartz glass, which has excellent heat resistance and a high melting point.

[0018] (4) Circuit 30 A circuit 30 made of polysilicon TFTs is formed on the glass substrate 10. In a narrow sense, polysilicon TFTs refer to thin film transistors (TFTs) that contain polysilicon. Here, the "circuit 30 made of polysilicon TFTs" refers to a circuit that includes active elements (transistors, diodes, etc.) made of polysilicon TFTs in the narrow sense, and may also include passive elements (capacitors, coils, resistors), wiring, etc. made of metal, etc.

[0019] The polysilicon TFT is preferably a "low-temperature polysilicon TFT," which is a thin-film transistor having low-temperature polysilicon. Because low-temperature polysilicon TFTs can be fabricated at relatively low temperatures, general industrial glass can be used as the base material for the glass substrate 10. This allows for a cheaper and larger glass substrate 10 to be employed than when quartz glass is used.

[0020] On the other hand, polysilicon TFTs are also preferably so-called "high-temperature polysilicon TFTs." High-temperature polysilicon TFTs are thin-film transistors with higher carrier mobility than low-temperature polysilicon TFTs, enabling faster switching and handling of faster signals (high-frequency signals). When fabricating high-temperature polysilicon TFTs, thin-film transistors are fabricated in an environment that is even hotter than when fabricating low-temperature polysilicon TFTs, so quartz glass is generally used as the base material for the glass substrate 10.

[0021] (4a) Function of Circuit 30 Circuit 30 is configured as a "peripheral circuit" for operating the functional circuits included in bare chip 70. This peripheral circuit may be, for example, a power supply circuit for supplying power to be used by the functional circuits of bare chip 70, or a circuit for interfacing between the functional circuits of the bare chip and the functional circuits of another bare chip (for example, a level conversion circuit for adjusting the signal levels of signals input / output by the functional circuits of bare chip 70), or further, any other circuit (excluding the power supply circuit and the level conversion circuit) that could not be mounted on the functional circuit chip (bare chip 70) integrated as a chiplet.

[0022] The power supply circuit can also be described as a circuit that generates and supplies power to operate bare chip 70. The level conversion circuit can also be described as a circuit that converts levels so that signal levels are consistent when signals are exchanged (interfaced) between multiple bare chips 70 with different signal level specifications. Here, "signal level" refers to the magnitude of the voltage in the case of a voltage signal, and the magnitude of the current in the case of a current signal. A circuit generally known as a level shifter can also be said to be a "level conversion circuit" when handling voltage signals. Of course, circuit 30 may include circuits other than the peripheral circuits described above.

[0023] (4b) Arrangement of Circuit 30 (Thickness Direction) Next, the arrangement of the circuit 30 in the thickness direction of the glass substrate 10 will be described. Active elements and passive elements (not referenced) that constitute the circuit 30 are formed on at least one of the upper surface 11 or the lower surface 12 of the glass substrate 10. Wiring (not referenced) that constitutes the circuit 30 includes a wiring pattern 20, a through-glass electrode (TGV (Through-Glass Via)) 15, etc. The wiring pattern 20 is formed on at least one of the upper surface 11 or the lower surface 12 of the glass substrate 10. The through-glass electrode 15 is formed so as to penetrate between the upper surface 11 and the lower surface 12.

[0024] In the three-dimensional semiconductor integrated structure 1 according to the first embodiment, as shown in FIG. 1, the circuit 30 is formed on the upper surface 11 of the glass substrate 10 and is disposed between the bare chip 70 and the glass substrate 10. In more detail, the circuit 30 １ is bare chip 70 １ and the glass substrate 10, and the bare chip 70 １ The connection terminals (bumps, etc.) of the circuit 30 １ Similarly, the circuit 30 is connected to a connection terminal (land, pad, etc.) of the ２ is bare chip 70 ２ and the glass substrate 10, and the bare chip 70 ２ The connection terminals (bumps, etc.) of the circuit 30 ２ Other circuits 30 are connected to the connection terminals (lands, etc.) of ３ , 30 ４ The same is true for...

[0025] 2 , in the three-dimensional semiconductor integrated structure 2 according to the second embodiment, a circuit 30 (mainly a circuit portion including active elements) is disposed on a bottom surface 12, which is a main surface of a glass substrate 10 and is the surface opposite to the side on which the bare chip is mounted, and the circuit 30 and the bare chip 70 are connected via glass through electrodes 15 provided on the glass substrate 10. In the example shown in the figure, the circuit 30 is appropriately connected to a wiring pattern 20 on the bottom surface 12, which is connected from the wiring pattern 20 on the bottom surface 12 to a wiring pattern 20 on the top surface 11 via the glass through electrodes 15, and the connection terminals (bumps, etc.) of the bare chip 70 are connected to the wiring pattern 20 on the top surface 11 (lands, etc. in this case).

[0026] It should be noted that the prior art (for example, Patent Document 1) can be used as appropriate for the technique of providing the polysilicon TFT on the glass substrate 10 and the technique of providing the glass through electrode 15 .

[0027] (4c) Arrangement of the Circuit 30 (Direction of Spread of Main Surface) Next, the arrangement of the circuit 30 in the direction of spread of the main surface of the glass substrate 10 will be described. When the glass substrate 10 is viewed from above, at least a portion of the circuit 30 is provided in an area overlapping with the bare chip 70 (overlap areas R1, R2, etc.). For example, when looking more closely at FIG. 1, the circuit 30 １ At least a part of the bare chip 70 １ In other words, the bare chip 70 is provided in an overlap region R1 that overlaps the bare chip 70. １ In the overlap region R1 corresponding to the circuit 30 １ As shown in FIG. 1A, a circuit 30 is provided in a part of the overlap region R1. １ Alternatively, the circuit 30 may be provided so as to cover the entire overlap region R1. １ Also, as shown in FIG. １ A part of the circuit 30 may be provided outside the overlap region R1. In this case, it is desirable that at least the active element (thin film transistor) is disposed in the overlap region R1. ２ , 30 ３ , 30４ The same can be said for the other overlap regions R2, R3, R4, etc. The same is also true for the three-dimensional semiconductor integrated structure 2 according to the second embodiment illustrated in FIG.

[0028] Here, the "area that overlaps with the bare chip 70 when the glass substrate 10 is viewed in a plane" can also be rephrased as the projection area of ​​the bare chip 70 when parallel light is projected perpendicular to the main surface of the glass substrate 10.

[0029] 2. Effects of the Three-Dimensional Semiconductor Integrated Structures 1 and 2 According to the First Embodiment (1) In the three-dimensional semiconductor integrated structures 1 and 2 according to the first embodiment, the glass substrate 10 is used as the interposer instead of a silicon substrate. This makes it possible to obtain large-sized components (components of the glass substrate 10), and the number of interposers that can be obtained increases, which is expected to result in a significant cost reduction.

[0030] Furthermore, the three-dimensional semiconductor integrated structures 1 and 2 according to the first embodiment include a glass substrate 10 and a plurality of bare chips 70 mounted on the glass substrate 10. The glass substrate 10 has a circuit 30 made of polysilicon TFTs formed thereon, with at least a portion of the circuit 30 being provided in an area overlapping the bare chips (overlap areas R1, R2, R3, etc.). In other words, the circuit 30 is formed directly below the bare chip 70. This allows the bare chip 70 and the circuit 30 to be connected via the shortest possible route, thereby shortening the wiring length between the functional circuits in the bare chip 70 and the circuit 30.

[0031] Because the wiring length can be shortened in this way, the wiring impedance can be suppressed (reduced), which in turn enables high-speed signal exchange between bare chip 70 and circuit 30, and between different bare chips 70 via circuit 30. Furthermore, because the wiring impedance is suppressed, it is possible to suppress noise generated by the wiring itself and the effects of external noise. For example, in a power supply circuit, the power supply voltage can be stabilized, and in a level conversion circuit, the signal level can be stabilized. These are extremely important matters because signal amplitude decreases due to scaling laws in semiconductor elements that are becoming increasingly miniaturized.

[0032] Furthermore, in the three-dimensional semiconductor integrated structures 1 and 2 according to embodiment 1, as explained in [Problem to be Solved by the Invention], the "peripheral circuit" is not provided on a dedicated chip separate from the functional circuit chip, but is provided on the glass substrate 10 as a circuit 30 made of polysilicon TFTs, and furthermore, the circuit 30 is provided in the overlap regions R1, R2, etc. (in other words, the region where the bare chip 70 is mounted, the region directly below the bare chip 70, etc.), so that a small three-dimensional semiconductor integrated structure with high space efficiency can be achieved.

[0033] From the above, according to the first embodiment, even though a glass substrate interposer is used, a power supply circuit, a level conversion circuit, and other circuits can be provided within the interposer of the glass substrate 10 and directly below the functional circuit chip (bare chip 70), thereby making it possible to obtain a more compact three-dimensional semiconductor integrated structure with reduced wiring impedance. Note that "within the interposer of the glass substrate 10" can also be rephrased as "within the category of the interposer of the glass substrate 10."

[0034] In addition, since the circuit 30 is provided in an area that is, so to speak, shaded by the bare chip 70, the bare chip 70 can block light projected from the front side (the upper side in the figure), which also makes it possible to suppress fluctuations in the characteristics of the thin-film transistors that make up the circuit 30.

[0035] (2) When circuit 30 is a peripheral circuit for operating a functional circuit included in bare chip 70 (for example, when circuit 30 is a power supply circuit for supplying power to the functional circuit, or a level conversion circuit for adjusting the signal levels of signals input and output by the functional circuit), three-dimensional semiconductor integrated structures 1 and 2 are even more suitable for these circuits. Since circuits necessary for the operation of the functional circuit of bare chip 70 are arranged in close proximity to bare chip 70, the wiring can be configured to be approximately the shortest, as described above, wiring impedance can be suppressed, and three-dimensional semiconductor integrated structures 1 and 2 can be configured to be small and space-saving.

[0036] (3) According to the first aspect of the first embodiment, the circuit 30 is disposed between the bare chip 70 and the glass substrate 10. In this configuration, the circuit 30 is not disposed on the lower surface 12 of the glass substrate 10, which makes it easy to mount the three-dimensional semiconductor integrated structure 1 on a motherboard (not shown) through the lower surface 12.

[0037] (4) According to the second aspect of the first embodiment, the circuit 30 is disposed on the main surface of the glass substrate 10, on the surface (lower surface 12) opposite to the side on which the bare chip 70 is mounted, and the circuit 30 and the bare chip 70 are connected via through electrodes (through-glass electrodes 15) provided in the glass substrate 10. With this configuration, it is possible to configure a complex circuit 30 having many more elements and wiring by utilizing the space three-dimensionally (in the thickness direction of the glass substrate 10) while making full use of the through electrodes (through-glass electrodes 15).

[0038] [Embodiment 2] Fig. 3 is a cross-sectional view shown for explaining a three-dimensional semiconductor integrated structure 3 according to a first aspect of embodiment 2. Fig. 4 is a cross-sectional view shown for explaining a three-dimensional semiconductor integrated structure 4 according to a second aspect of embodiment 2.

[0039] The three-dimensional semiconductor integrated structures 3 and 4 of embodiment 2 basically have the same configuration as the three-dimensional semiconductor integrated structures 1 and 2 of embodiment 1, but differ from the three-dimensional semiconductor integrated structures 1 and 2 of embodiment 1 in that they further include a light-shielding layer 40.

[0040] In the three-dimensional semiconductor integrated structures 3 and 4 according to the second embodiment, when the glass substrate 10 is viewed from above, a light-shielding layer 40 is provided on the glass substrate 10 in an area overlapping with the circuit 30 (see FIGS. 3 and 4). For example, in FIG. 3, １ In the overlapping region with the light-shielding layer 40 １ Also, the circuit 30 ２ In the overlapping region with the light-shielding layer 40 ２ Other circuits 30 ３ , 30 ４ The same is true for the overlapping area (see FIG. 1).

[0041] The light-shielding layer 40 may be any material that blocks light that is about to enter the circuit 30. The light-shielding layer 40 may also be referred to as a light-shielding film, a light-shielding body, etc. In the second embodiment, by providing the light-shielding layer 40 in this manner, it is possible to block light that is about to enter the circuit 30, and to suppress fluctuations in the characteristics of the thin-film transistors that constitute the circuit 30.

[0042] Furthermore, the light-shielding layer 40 is preferably provided in an area where the polysilicon TFTs that make up the circuit 30 are arranged. With this configuration, it is possible to block the incidence of light mainly on transistor elements whose characteristics are easily changed by light.

[0043] For reference, the light-shielding layer 40 may be provided so as to correspond to the overlap regions R1, R2, etc. of the bare chip. Furthermore, the light-shielding layer 40 may be provided over a wide range including areas other than the area corresponding to the circuit 30 (the area overlapping with the circuit 30).

[0044] It is also preferable that this light-shielding layer 40 also shields the active surface of the bare chip 70 from light. Since the active surface of the bare chip 70 can also be shielded from light, it can also contribute to preventing malfunction of the bare chip 70 due to incident light. Note that the "active surface" of the bare chip 70 is the surface on which various circuit patterns centered on active elements are formed, and in the examples of Figures 3 and 4, it is assumed to be the bottom surface of the bare chip 70.

[0045] Furthermore, it is preferable that the light-shielding layer 40 is provided on the side opposite to the side on which the bare chip 70 is disposed (the lower side of the glass substrate 10). With this configuration, on the upper side as viewed from the circuit 30, the bare chip 70 blocks light that attempts to enter from above, and on the lower side as viewed from the circuit 30, the light-shielding layer 40 blocks light that attempts to enter from below, thereby completely preventing light from entering the circuit 30. This configuration is particularly suitable when using a glass substrate 10 that easily transmits light in the thickness direction of the plate material.

[0046] Furthermore, it is preferable that the light-shielding layer 40 is made of a material containing metal and is connected to the GND (Ground) level in terms of the electrical circuitry. In this way, the light-shielding layer 40 made of a metal material and fixed to the GND level covers the circuit 30, and the light-shielding layer 40 functions as an electromagnetic shield, so that the noise resistance of the circuit 30 can be improved.

[0047] The three-dimensional semiconductor integrated structures 3 and 4 according to the second embodiment are basically configured in the same manner as the three-dimensional semiconductor integrated structures 1 and 2 according to the first embodiment, except that they further include a light-shielding layer 40. Therefore, the three-dimensional semiconductor integrated structures 3 and 4 according to the second embodiment have the same effects as the three-dimensional semiconductor integrated structures 1 and 2 according to the first embodiment.

[0048] Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment and can be embodied in various forms without departing from the spirit of the present invention.

[0049] 1, 2, 3, 4... Three-dimensional semiconductor integrated structure, 10... Glass substrate, 11... Upper surface (of glass substrate), 12... Lower surface (of glass substrate), 15... Glass through via (TGV), 20... Wiring pattern, 30... Circuit, 40... Light-shielding layer, 70... Bare chip

Claims

1. A three-dimensional semiconductor integrated structure comprising a glass substrate and a plurality of bare chips mounted on the glass substrate, wherein a circuit made of polysilicon TFTs is formed on the glass substrate, and when the glass substrate is viewed in a plane, at least a portion of the circuit is provided in an area that overlaps with the bare chips.

2. A three-dimensional semiconductor integrated structure according to claim 1, wherein the circuit is a peripheral circuit for operating a functional circuit included in the bare chip.

3. A three-dimensional semiconductor integrated structure according to claim 2, wherein the peripheral circuit is a power supply circuit for supplying power to be used by the functional circuit.

4. A three-dimensional semiconductor integrated structure according to claim 2, wherein the peripheral circuit is a level conversion circuit for adjusting the signal levels of signals input and output by the functional circuit.

5. A three-dimensional semiconductor integrated structure according to any one of claims 1 to 4, wherein the circuit is arranged on a main surface of the glass substrate opposite to the side on which the bare chip is placed, and the circuit and the bare chip are connected via through electrodes provided in the glass substrate.

6. A three-dimensional semiconductor integrated structure according to any one of claims 1 to 4, characterized in that the circuit is disposed between the bare chip and the glass substrate.

7. A three-dimensional semiconductor integrated structure according to any one of claims 1 to 6, characterized in that, when the glass substrate is viewed in plan, a light-shielding layer is provided on the glass substrate in an area that overlaps with the circuit.

8. A three-dimensional semiconductor integrated structure according to claim 7, characterized in that the light-shielding layer is provided in an area where the polysilicon TFTs constituting the circuit are arranged when the glass substrate is viewed in a plane.

9. A three-dimensional semiconductor integrated structure according to claim 7 or 8, characterized in that the light-shielding layer is provided on the side opposite to the side on which the bare chip is arranged.

10. A three-dimensional semiconductor integrated structure according to any one of claims 7 to 9, characterized in that the light-shielding layer is made of a material containing metal and is connected to the GND level.

11. A three-dimensional semiconductor integrated structure according to any one of claims 7 to 10, wherein the light-shielding layer also shields the active surface of the bare chip from light.

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