Transistor drive circuit

Abstract

A transistor drive circuit (100a) is a circuit for controlling a transistor switch (T1) connected between a battery stack (200) and a load (300) and comprises: a pair of capacitor connection terminals (CP terminal and CN terminal) to which a flying capacitor (104) is connected; an internal reference voltage buffer (101) for generating a voltage for activating the transistor switch (T1) and being applied between the two terminals of the transistor switch (T1); and a logic control unit (102) for activating the transistor switch (T1) in such a way that after temporarily connecting the internal reference voltage buffer (101) and the pair of capacitor connection terminals to charge the voltage generated by the internal reference voltage buffer (101) into the flying capacitor (104), the transistor switch (T1) and one of the pair of capacitor connection terminals are temporarily connected.

Description

Transistor drive circuit

[0001] The present invention relates to a transistor drive circuit, and more particularly to a transistor drive circuit that controls a transistor switch connected between a battery stack and a load.

[0002] A battery management system (BMS) with MOSFET switch control uses a special type of transistor called a MOSFET (metal-oxide semiconductor field-effect transistor) to manage the connection between the battery pack and the load. The MOSFET acts like a voltage-controlled switch. By applying a voltage to the gate terminal, the switch can be turned on (allowing current to pass) or off (blocking current). In a BMS, an analog front end (AFE) manages the gate voltage of the MOSFET switch. When the AFE needs to disconnect the battery (due to overcharge, undercharge, or other safety concerns), it turns off the MOSFET, stopping the flow of current from the battery to the load or from the charger to the battery.

[0003] There are two types of AFE control of MOSFET switches. The first type is high-side MOSFET switch control, in which a MOSFET is placed between the most positive terminal of the Li-ion battery stack and the positive terminal of the load (or the positive terminal of the charger) (see, for example, Patent Document 1). The second type is low-side MOSFET switch control, in which a MOSFET is placed between the most negative terminal of the Li-ion battery stack and the negative terminal of the load (or the negative terminal of the charger). The high-side MOSFET allows or blocks current flow along the power-side (high-voltage) connection. On the other hand, the low-side MOSFET allows or blocks current flow along the ground-side (low-voltage) connection.

[0004] Japanese Patent Application Laid-Open No. 2021-158752

[0005] The first type, a transistor driver circuit that controls a high-side MOSFET switch, and the second type, a transistor driver circuit that controls a low-side MOSFET switch, each have their own advantages and disadvantages, are realized as independent and different circuits, and are selectively used depending on the application.

[0006] An object of the present invention is to provide a single transistor drive circuit that can selectively control both a high-side transistor switch and a low-side transistor switch.

[0007] In order to achieve the above object, a transistor drive circuit according to one embodiment of the present invention is a transistor drive circuit that controls a transistor switch connected between a battery stack including one or more battery cells and a load, and includes: a pair of capacitor connection terminals to which a flying capacitor is connected; an internal reference voltage buffer that generates a voltage to be applied between two terminals of the transistor switch to activate the transistor switch; and a control circuit that temporarily connects the internal reference voltage buffer to the pair of capacitor connection terminals to charge the flying capacitor with the voltage generated by the internal reference voltage buffer, and then temporarily connects the transistor switch to one of the pair of capacitor connection terminals to activate the transistor switch.

[0008] The present invention provides a single transistor driver circuit that can selectively control both a high-side transistor switch and a low-side transistor switch.

[0009] FIG. 1 is a block diagram showing a conventional transistor driver circuit for controlling a high-side MOSFET switch. FIG. 2 is a block diagram showing a conventional transistor driver circuit for controlling a low-side MOSFET switch. FIG. 3 is a diagram showing two operation modes of a transistor driver circuit (FET driver) according to an embodiment. FIG. 4A is a block diagram showing the internal circuit configuration of FIG. 3A when the FET driver according to an embodiment is in a high-side configuration. FIG. 4B is a block diagram showing the internal circuit configuration of FIG. 3B when the FET driver according to an embodiment is in a low-side configuration. FIG. 5A is a timing chart showing the output of a logic control unit when the FET driver according to an embodiment operates in high-side mode. FIG. 5B is a timing chart showing the output of a logic control unit when the FET driver according to an embodiment operates in low-side mode. FIG. 6A is a diagram showing an operation sequence (SW_A) of an FET driver according to an embodiment in high-side mode when Loside_EN=low. FIG. 6B is a diagram showing an operation sequence (SW_B) of an FET driver according to an embodiment in high-side mode when Loside_EN=low, following FIG. 6A. 6C is a diagram showing an operation sequence (SW_C) of the FET driver according to the embodiment in high-side mode when Loside_EN=low, following FIG. 6B . FIG. 7A is a diagram showing an operation sequence (SW_A) of the FET driver according to the embodiment in low-side mode when Loside_EN=high, following FIG. 7A . FIG. 7B is a diagram showing an operation sequence (SW_B) of the FET driver according to the embodiment in low-side mode when Loside_EN=high, following FIG. 7A . FIG. 7C is a diagram showing an operation sequence (SW_C) of the FET driver according to the embodiment in low-side mode when Loside_EN=high, following FIG. 7B . FIG. 8 is a block diagram showing a circuit configuration of a transistor drive circuit according to a modified embodiment, which drives a transistor switch connected to the positive terminal of a battery stack. FIG. 9 is a diagram showing two operation modes of the transistor drive circuit according to the modified embodiment.FIG. 10 is a block diagram showing the main circuit configuration of the FET driver according to the embodiment, which is a simplified combination of FIGS. 4A and 4B.

[0010] (Discoveries Obtained by the Inventors) The use of lithium-ion (Li-ion) batteries has had a significant impact on human daily life, enabling the development of powerful, portable electronic devices. Lithium-ion batteries' high energy density, long life, and rechargeability make them ideal for portable electronic devices such as laptops and mobile phones, and their adoption surged in the 2000s. Applications have expanded to digital cameras, power tools, medical devices, and more recently, electric vehicles (EVs) and energy storage. Much research continues to improve Li-ion technology, focusing on safety, energy density, charging speed, and cost reduction. It is expected that Li-ion batteries will remain popular in portable electronic devices, energy storage, and EVs for the foreseeable future.

[0011] A stacked Li-ion battery system combines multiple lithium-ion cells electrically connected in series or parallel to achieve the required voltage or capacity. To ensure safety and optimal performance, the system requires a battery management system (BMS) that closely monitors various parameters of the stacked cells. In a stacked Li-ion BMS, two key components—the analog front end (AFE) and the microcontroller unit (MCU)—work together to handle measurement, control, and communication. The AFE and MCU form a complementary team. The AFE provides high-precision measurements of the battery's analog characteristics, while the MCU interprets this data to make control decisions and enable communication. The BMS uses safety cutoffs to prevent the battery from operating outside its safe operating area, protecting the battery itself, the devices it powers, and the surrounding environment. These cutoffs typically focus on voltage, current, and temperature and can prevent fires, explosions, and performance degradation that could occur if the battery were to operate outside its safe limits.

[0012] Li-ion batteries benefit greatly from integration with a battery management system (BMS). In a BMS, the AFE acts as the interface between the MCU and the physical battery pack. The AFE processes the battery's analog signals, which are continuous electrical signals representing voltage, current, and temperature. Li-ion batteries are inherently unstable compared to other battery technologies. They are susceptible to overheating, overcharging, and over-discharging, which can lead to fires and explosions. The AFE continuously monitors critical parameters such as voltage, current, and temperature for each cell in the battery pack.

[0013] If the AFE detects a dangerous condition, it can take corrective action, such as disconnecting the battery to prevent damage or reducing the charge / discharge current to allow the battery to cool. Monitoring individual cell voltages is crucial. The AFE continuously measures the voltage of each cell in the stack. If a cell's voltage exceeds a safe limit, the AFE can trigger protective actions, such as balancing the cells or disconnecting the battery. If a cell is discharged below a certain safe voltage, deep discharge occurs, which can permanently damage the cell. The BMS can prevent this by disconnecting the battery before it reaches a critical undervoltage.

[0014] The AFE monitors the total current flowing into and out of the battery stack, thereby preventing overcurrent. If the charge or discharge current exceeds a safe limit, it can be limited to protect the cells from damage. By monitoring the current, it is possible to track Li-ion energy flow. The BMS can estimate the remaining capacity of the battery and provide information on the discharge rate.

[0015] Li-ion batteries are temperature sensitive. The AFE monitors the temperature of the battery stack at multiple locations, preventing overheating. If the temperature exceeds a safe limit, the BMS can trigger actions such as reducing charge / discharge current or disconnecting the battery. Temperature also affects battery performance. The BMS can adjust the charging algorithm based on temperature measurements by the AFE to optimize charging efficiency.

[0016] A battery management system (BMS) with MOSFET switch control uses a special type of transistor called a MOSFET (metal-oxide semiconductor field-effect transistor) to manage the connection between the battery pack and the load. The MOSFET acts like a voltage-controlled switch. By applying a voltage to the gate terminal, the switch can be turned on (allowing current to pass) or off (blocking current). In a BMS, an AFE manages the gate voltage of the MOSFET switch. When the AFE needs to disconnect the battery (due to overcharge, undercharge, or other safety concerns), it turns off the MOSFET, stopping the flow of current from the battery to the load or from the charger to the battery.

[0017] There are two types of AFE control for MOSFET switches. The first type is high-side MOSFET switch control, in which a MOSFET is placed between the most positive terminal of a Li-ion battery stack and the positive terminal of a load (or the positive terminal of a charger), as shown in FIG. 1. FIG. 1 is a block diagram showing a transistor drive circuit (High Side FET Driver) 10 that controls a conventional high-side MOSFET switch. The CHG terminal and DIS terminal are terminals that control MOSFET switches T1 and T2, respectively, that are provided in a path connecting the positive terminal of a battery stack 200 and the positive terminal of a load 300. To turn on switch T1, the CHG terminal must output a threshold voltage referenced to the VBAT terminal. To turn on switch T2, the DIS terminal must output a threshold voltage referenced to the VPACK terminal.

[0018] The second type is low-side MOSFET switch control, in which a MOSFET is placed between the most negative terminal of the Li-ion battery stack and the negative terminal of the load (or the negative terminal of the charger), as shown in FIG. 2. FIG. 2 is a block diagram showing a transistor drive circuit (Low Side FET Driver) 20 that performs conventional low-side MOSFET switch control. The CHG terminal and DIS terminal are terminals that control MOSFET switches T3 and T4, respectively, that are provided in the path connecting the negative terminal of the battery stack 200 and the negative terminal of the load 300. To turn on switch T3, the DIS terminal must output a threshold voltage referenced to the VSS terminal. To turn on switch T4, the CHG terminal must output a threshold voltage referenced to the negative terminal of the load 300.

[0019] The high-side MOSFET allows or blocks current flow along the power-side (high voltage) connection, while the low-side MOSFET allows or blocks current flow along the ground-side (low voltage) connection.

[0020] Due to the output requirements of the transistor drivers, an AFE designed for a high-side system cannot be used for a low-side system (and vice versa). Different AFE models must be selected for different types of MOSFET switch systems. Manufacturers manufacture different product applications, but they must select different AFEs for either switch system. Designed AFE system boards are not compatible between high-side and low-side MOSFET switches. Therefore, it costs more for manufacturers to produce different AFE system boards.

[0021] The choice between a high-side or low-side MOSFET switch in the AFE depends on a variety of factors, including battery voltage and current requirements, system cost constraints, design complexity considerations, and safety priorities.

[0022] N-channel power MOSFETs are used for both the high-side and low-side switches. N-channel power MOSFETs generally offer several advantages over P-channel power MOSFETs for many applications, particularly stacked lithium-ion battery management systems (BMS). N-channel MOSFETs use electrons for conduction, which inherently have higher mobility compared to holes used in P-channel MOSFETs. This means that N-channel devices have a lower on-resistance (resistance when conducting current). Lower on-resistance is particularly important for battery-powered devices, as less energy is lost as heat during operation, resulting in higher efficiency in BMS circuits and longer operating times. N-channel power MOSFETs generally tend to be more widely available and less expensive than similarly configured P-channel devices. This can be an important factor, especially in cost-sensitive BMS designs.

[0023] High-side MOSFET switches are the recommended switching technique in situations where a short circuit to ground is more likely than a short circuit to the positive power line. For example, this occurs when most of the structure, such as a vehicle or machine, is connected to ground. In such cases, disconnecting the load from the battery is safer than disconnecting it from ground. Dangerously high voltages are not present at the BMS system output terminals. Also, connector corrosion is reduced because the load is not subject to voltage in the off state due to aging. Another benefit is that all devices in the BMS share a common ground reference. That is, the negative terminal of the battery pack is often connected to system ground for easy reference and control circuit grounding. Complex ground isolation is not required. Even when the AFE disconnects the battery, the system ground remains connected, allowing communication with the AFE for critical functions such as safety monitoring.

[0024] High-side MOSFET switches have the following disadvantages: They are generally more complex to manufacture than low-side switches, which means the cost of the BMS is higher compared to designs using low-side switches. The additional circuitry required to drive the high-side switch (often requiring a level shifter or dedicated driver IC) complicates the BMS design and increases PCB space. Fully turning on the switch requires a gate drive voltage higher than the total battery voltage, which may require a separate charge pump circuit to generate the high voltage required for reliable operation. This additional circuitry increases complexity and potential points of failure within the BMS.

[0025] Low-side MOSFET switches offer several advantages in certain applications. They are generally easier to manufacture than high-side switches, which translates into lower BMS system costs. Because they operate from the low-voltage side (negative / ground terminal) of the battery, they do not require complex gate drive circuitry. They also do not require a separate charge pump circuit. This reduces the number of components and simplifies the BMS design. Low-side switches are sometimes available with higher current ratings than high-side switches with similar voltage specifications. This is advantageous for applications requiring high discharge currents. Additionally, co-locating a low-side switch with an AFE low-side current sense greatly simplifies the wiring connection on the positive / power side of the battery, resulting in cost savings and a simplified connection design.

[0026] However, low-side switches also have significant drawbacks that make them unsuitable for most BMS applications. When the switch is turned off, only the ground-side circuit is open, limiting safety control and potentially leaving high voltage connected to the load, creating a safety risk in the event of a fault. The low-side MOSFET switch controls the ground connection; when the switch is turned on, current flows, but when turned off, it only opens the ground-side circuit. When the AFE opens the connection, it disconnects the system ground, potentially disrupting communication and control between devices. The additional circuitry and complex control logic required increases design complexity, potentially negating the cost and simplicity benefits.

[0027] In summary, high-side switches are the preferred choice for most BMS applications due to their superior safety control and compatibility with common ground connections, although low-side switches may be considered for certain non-common ground BMS designs or other applications with lower safety requirements and cost constraints, as long as safety can be addressed by alternative means.

[0028] Therefore, the inventors have created a single transistor driver circuit that can be used to control both high-side and low-side transistor switches. This allows a single AFE to be used for two different applications, thereby reducing product and test development time. It also simplifies customer integration by eliminating the need to extensively rewrite separate MCU code for two different FET driver applications.

[0029] (Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that each of the embodiments described below represents a specific example of the present invention. The numerical values, shapes, materials, components, component placement and connection configurations, control procedures, control signals, etc. shown in the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concept of the present invention will be described as optional components. Furthermore, each figure is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations will be omitted or simplified.

[0030] 3 is a diagram showing two operating modes of a transistor driver circuit (FET driver) 100 according to an embodiment. The transistor driver circuit 100 according to the present disclosure is an innovative FET driver (hereinafter also referred to as FET driver 100) that functions as both a high-side driver and a low-side driver and can select its operating mode based on a control signal. The disclosed technology provides a dual-mode FET driver 100 that utilizes a dynamically adjustable switching sequence and a charged flying capacitor CF, allowing the same circuit configuration to drive FETs (transistor switches T1 and T2 that form a bidirectional switch) in either high-side or low-side applications.

[0031] 3A shows an embodiment of the FET driver 100 in high-side FET driver mode. FIG. 3B shows an embodiment of the FET driver 100 in low-side FET driver mode. This embodiment of the present invention includes a CHG terminal output for driving a first FET (T1) that connects between a battery power supply (the positive terminal VBAT of the battery stack 200) or ground (the negative terminal VPACK_N of the load 300) and a second FET (T2), a DIS terminal output for driving a second FET (T2) that connects between the first FET (T1) and a load input (the positive terminal VPACK_P of the load 300) or ground (the negative terminal of the battery stack 200), a flying capacitor CF that connects between the CP terminal and the CN terminal, and a logic input Loside_EN terminal that is a selection terminal for selecting the operating mode of the FET driver 100. The VBAT terminal is a power supply input from the battery stack 200 to the FET driver 100, and the VPACK terminal is an output terminal to the load 300. Flying capacitor CF is charged by an internal circuit that provides the charge necessary to turn on the two FETs (T1 and T2). FET driver 100 functions as a low-side driver when the Loside_EN terminal (selection terminal) is set high, and as a high-side driver when set low. A logic input to this Loside_EN terminal changes the connection of the CP and CN terminals of flying capacitor CF, placing the two FETs (T1 and T2) in high-side or low-side mode accordingly. In high-side mode, flying capacitor CF is internally connected to T1 or T2 with respect to the battery power supply. In low-side mode, flying capacitor CF is internally connected to T1 or T2 with respect to the battery ground.

[0032] Advantages of the FET driver 100 of this embodiment include a reduced number of components required to drive the FET, reduced PCB space requirements, reduced development and testing time, and ease of integration into various system architectures. Additionally, the FET driver 100 of this embodiment reduces the need to rewrite microcontroller unit (MCU) code for various applications (high-side driver and low-side driver), significantly improving the efficiency of product development.

[0033] 4A is a block diagram showing the internal circuit configuration of FIG. 3A when the FET driver 100 according to the embodiment is configured as a high-side FET. The switches in the SW_A block are connected between an internal reference voltage buffer 101 (also referred to as the "internal VREF buffer 101") and a flying capacitor CF via the CP terminal and the CN terminal. The flying capacitor CF is charged by the internal reference voltage buffer 101 when both switches in the SW_A block are closed. The switches B1 and B2 in the SW_B block are connected between the VBAT terminal and the CN terminal, and between the CHG terminal and the CP terminal, respectively. When both switches in the SW_B block are closed, the first FET (T1) connected to the CHG terminal is turned on by the voltage across the flying capacitor CF, which is connected with the VBAT terminal as a reference. The switches C1 and C2 in the SW_C block are connected between the VPACK terminal and the CP terminal, and between the DIS terminal and the CN terminal, respectively. When both switches in the SW_C block are closed, the second FET (T2) connected to the DIS terminal is turned on by the voltage across the flying capacitor CF, which is connected referenced to the VPACK terminal. SW_OFF1 is connected between the VPACK and DIS terminals. SW_OFF2 is connected between the VBAT and CHG terminals. SW_OFF1 and SW_OFF2 can be used to turn off the first FET (T1) and the second FET (T2), respectively. The logic control unit 102 is an example of a control circuit that provides all the necessary control signals for SW_A, SW_B, SW_C, SW_OFF1, and SW_OFF2.

[0034] 4B is a block diagram showing the internal circuit configuration of FIG. 3B when the FET driver 100 according to the embodiment is configured as a low-side driver. The difference between FIG. 4B and FIG. 4A is the switching conditions of the SW_B, SW_C, and SW_OFF2 blocks to enable the FET driver 100 to operate in the low-side configuration. The switch B1 in the SW_B block is always open because the output voltage of the CHG terminal connected to the first FET (T1) must be referenced to ground. The switch C2 in the SW_C block is closed when the switch B2 or the switch C1 is closed, thereby shorting the CN terminal (i.e., the negative terminal of the flying capacitor CF) to ground via the VPACK terminal. When the negative terminal of the flying capacitor CF is shorted to ground by the switch C2, the voltages of the CHG terminal and the DIS terminal are appropriately output, enabling the first FET (T1) and the second FET (T2) in the low-side driver configuration to be turned on. It should be noted that the embodiment regarding the connection of the negative terminal of the flying capacitor CF is not limited to the VPACK terminal, but can also be connected to any other ground terminal within the FET driver 100.

[0035] 4A and 4B, the internal reference voltage buffer 101 may be provided outside the FET driver 100 and connected to the SW_A block included in the FET driver 100 from outside the FET driver 100.

[0036] 5A is a timing diagram illustrating the output of the logic control unit 102 when the FET driver 100 according to the embodiment operates in high-side mode. The diagram illustrates the on (high) and off (low) timing of SW_A, SW_B, and SW_C. In this mode of operation, SW_A turns on both switches A1 and A2, SW_B turns on both switches B1 and B2, and SW_C turns on both switches C1 and C2. The operation sequence is as follows: SW_A is first momentarily turned on to charge the flying capacitor CF ("CF charge to VREF"), then SW_B is momentarily turned on to turn on the first FET (T1) ("CF discharge to CHG pin"), then SW_A is momentarily turned on again to refresh the flying capacitor CF ("CF charge to VREF"), and then SW_C is momentarily turned on to turn on the second FET (T2) ("CF discharge to DIS pin"). This cycle repeats, keeping the voltages across the flying capacitor CF, the gate-source of the first FET (T1), and the gate-source of the second FET (T2) constant. During operation, the gate-source capacitances of the first FET (T1) and the second FET (T2) hold the voltage across the flying capacitor CF, keeping both FETs on until the next cycle update. These operations are repeated.

[0037] 5B is a timing diagram showing the output of the logic control unit 102 when the FET driver 100 according to the embodiment operates in low-side mode. The operation sequence is similar to that of the high-side mode shown in FIG. 5A, repeating the cycle of SW_A, SW_B, SW_A, SW_C. As explained in FIG. 4B, the difference lies in the switching states of switches B1 and C2, which enable operation of the low-side FET driver. Switch B1 is always off during all periods of SW_A, SW_B, and SW_C. Switch C2 is on during periods of SW_B and SW_C.

[0038] The above describes an implementation of the example FET driver 100 of FIGS. 3(a) and 3(b), in which the use of a flying capacitor CF can be used to control two FETs (T1 and T2) in a high-side or low-side system by dynamically changing the connection of the flying capacitor CF to the battery stack or ground and to the two FETs (T1 and T2).

[0039] 6A, 6B, and 6C are diagrams illustrating the operational sequence of FET driver 100 according to an embodiment in high-side mode when Lowside_EN=low, as described in FIG. 4A. The arrows in these diagrams indicate the charging and discharging of flying capacitor CF.

[0040] The switching sequence is SW_A→SW_B→SW_A→SW_C as described in FIG. 5A.

[0041] 6A shows the operation of the high-side FET driver 100 when SW_A is on. The internal VREF buffer 101 is connected to the flying capacitor CF via the CP and CN terminals by a switch in the SW_A block. This allows the internal VREF buffer 101 to charge the flying capacitor CF while SW_A is on.

[0042] 6B shows the operation of the high-side FET driver 100 when SW_B is on. The CP terminal of the flying capacitor CF is connected to the CHG terminal via switch B2 in the SW_B block. The CN terminal of the flying capacitor CF is connected to the VBAT terminal via switch B1 in the SW_B block. As a result, the first FET (T1) connected to the CHG terminal is turned on by the voltage of the flying capacitor CF, which is connected with the VBAT terminal as a reference.

[0043] 6C shows the operation of the high-side FET driver 100 when SW_C is on. The CP terminal of the flying capacitor CF is connected to the DIS terminal via a switch C1 in the SW_C block. The CN terminal of the flying capacitor CF is connected to the VPACK terminal via a switch C2 in the SW_C block. As a result, the second FET (T2) connected to the DIS terminal is turned on by the voltage of the flying capacitor CF, which is connected with the VPACK terminal as a reference.

[0044] Through the above series of operations, the voltages at the CHG terminal of the first FET (T1) and the DIS terminal of the second FET (T2) are continuously refreshed by the CP terminal and the CN terminal of the flying capacitor CF, so that the first FET (T1) and the second FET (T2) remain on. Similarly, the voltage of the flying capacitor CF is also continuously refreshed by the internal VREF buffer 101.

[0045] If only the second FET (T2) connected to the DIS terminal needs to be turned on, the switches B1 and B2 in the SW_B block remain off during the SW_B period in the switching sequence, thereby preventing the flying capacitor CF from turning on the first FET (T1) connected to the CHG terminal.

[0046] Also, when only the first FET (T1) connected to the CHG terminal needs to be turned on, the switches C1 and C2 in the SW_C block remain off during the SW_C period in the switching sequence, thereby preventing the flying capacitor CF from turning on the second FET (T2) connected to the DIS terminal.

[0047] Furthermore, when both the first FET (T1) connected to the CHG terminal and the second FET (T2) connected to the DIS terminal are turned off, all switches in the SW_B and SW_C blocks remain off during the SW_B and SW_C periods in the switching sequence.

[0048] In all the above events, the switch in the SW_A block is always turned on when SW_A is selected, which keeps the flying capacitor CF refreshed for the next FET turn on.

[0049] 7A, 7B, and 7C are diagrams illustrating the operational sequence of FET driver 100 according to an embodiment of the low-side mode when Loside_EN=high, as described in FIG. 4B. The arrows in these diagrams indicate the charging and discharging of flying capacitor CF.

[0050] The switching sequence is SW_A → SW_B → SW_A=0N → SW_C as described in FIG. 5A.

[0051] 7A shows the operation of the low-side FET driver 100 when SW_A is on. The internal VREF buffer 101 is connected to the flying capacitor CF via the CP and CN terminals by a switch in the SW_A block. This allows the internal VREF buffer 101 to charge the flying capacitor CF while SW_A is on.

[0052] 7B shows the operation of the low-side FET driver 100 when SW_B is on. The CP terminal of the flying capacitor CF is connected to the CHG terminal via switch B2 in the SW_B block. The CN terminal of the flying capacitor CF is connected to the VPACK terminal via switch C2 in the SW_C block. As a result, the first FET (T1) connected to the CHG terminal is turned on by the voltage of the connected flying capacitor CF, with the ground level being used as a reference via the VPACK terminal.

[0053] 7C shows the operation of the low-side FET driver 100 in the case of SW_C. The CP terminal of the flying capacitor CF is connected to the DIS terminal via a switch C1 in the SW_C block. The CN terminal of the flying capacitor CF is connected to the VPACK terminal via a switch C2 in the SW_C block. As a result, the second FET (T2) connected to the DIS terminal is turned on by the voltage of the connected flying capacitor CF, with the VPACK terminal being used as a reference for the ground level.

[0054] By the above series of operations, the voltage across both terminals of the flying capacitor CF is continuously refreshed by the CP terminal and the CN terminal, so that the first FET (T1) connected to the CHG terminal and the second FET (T2) connected to the DIS terminal remain on. Similarly, the voltage across the flying capacitor CF is also continuously refreshed by the internal VREF buffer 101.

[0055] When only the second FET (T2) connected to the DIS terminal is turned on, the switch B2 in the SW_B block and the switch C2 in the SW_C block remain off during the SW_B period in the switching sequence, thereby preventing the flying capacitor CF from turning on the first FET (T1) connected to the CHG terminal.

[0056] Furthermore, when only the first FET (T1) connected to the CHG terminal is turned on, the switches C1 and C2 in the SW_C block remain off during the SW_C period in the switching sequence, thereby preventing the flying capacitor CF from turning on the second FET (T2) connected to the DIS terminal.

[0057] Furthermore, when both the first FET (T1) connected to the CHG terminal and the second FET (T2) connected to the DIS terminal are turned off, all switches in the SW_B and SW_C blocks remain off during the SW_B and SW_C periods in the switching sequence.

[0058] In all the above events, the switch in the SW_A block is always on when SW_A is on, which keeps the flying capacitor CF refreshed for the next FET on.

[0059] As described above, the FET driver 100 configuration according to this embodiment shows that the high-side FET driver configuration can be used as a low-side FET driver configuration by changing the switching sequence. These configurations can be selected by the logic state represented by Loside_EN. By using a flying capacitor CF via the CP and CN terminals, the voltage can be used to turn on either the high-side FET or the low-side FET.

[0060] The FET driver 100 of the present embodiment reduces product and test development time by allowing one product to be used for two different applications, and simplifies customer integration by eliminating the need to extensively rewrite separate MCU code for two different FET driver applications.

[0061] In the above embodiment, two transistor switches (T1 and T2) are provided in the FET driver 100 as bidirectional switches, but only one of the two transistor switches (T1 or T2) may be provided as a unidirectional switch.

[0062] 8 is a block diagram showing the circuit configuration of a transistor driver circuit 100a according to a modified embodiment, which drives a transistor switch T1 connected to the positive terminal of a battery stack 200. The transistor driver circuit 100a according to this modified embodiment is a transistor driver circuit for a battery stack 200 including one or more battery cells. The transistor driver circuit 100a includes a driver circuit 110 for the transistor switch T1, which disconnects a load 300 connected to the battery stack 200. The driver circuit 110 can activate the transistor switch T1 regardless of the position of the transistor switch T1 at the positive terminal 400 or the negative terminal 500 of the battery stack 200 (i.e., whether the transistor switch T1 is in high-side mode or low-side mode). The position of the transistor switch T1 can be selected by a logic input 112 (Loside_EN terminal in this embodiment).

[0063] The transistor driver circuit 100a according to this modification includes a logic control unit 102, which is not shown in FIG. 8, that controls each switch shown in FIG. 8 so that the transistor driver circuit 100a operates in high-side mode or low-side mode depending on the logic input from the logic input 112.

[0064] 9A and 9B are diagrams showing two operation modes of a transistor drive circuit 100a according to a modified example of the embodiment. More specifically, (a) of Fig. 9 shows the circuit configuration of the transistor drive circuit 100a when driving the transistor switch T1 connected to the positive electrode of the battery stack 200, and (b) of Fig. 9 shows the circuit configuration of the transistor drive circuit 100a when driving the transistor switch T1 connected to the negative electrode of the battery stack 200.

[0065] As shown in FIG. 8, the transistor drive circuit 100a according to this modified example includes an internal reference voltage buffer 101 and a flying capacitor 104 connected to the internal reference voltage buffer 101. As shown in FIG. 9(b), when the transistor switch T1 is disposed between the negative electrode 500 (VBAT_N) of the battery stack 200 and the negative terminal VBAT_N_OUT of the load 300, the CN terminal of the flying capacitor 104 is switched to the first reference voltage 600. When the transistor switch T1 is disposed between the positive electrode 400 (VBAT_P) of the battery stack 200 and the positive terminal VBAT_P_OUT of the load 300, the CN terminal of the flying capacitor 104 is switched to the second reference voltage 700 (VBAT_P).

[0066] Here, the first reference voltage 600 is the voltage of the negative electrode 500 of the battery stack 200, and the second reference voltage 700 is the voltage of the positive electrode 400 of the battery stack 200. In addition, in the transistor drive circuit 100a according to this modification, the transistor switch T1 is an FET.

[0067] The transistor driver circuit 100a according to this modified example can selectively control both the high-side transistor switch and the low-side transistor switch, similar to the FET driver 100 according to the embodiment.

[0068] As described above, the transistor drive circuit 100a according to the modified example of the present embodiment is a transistor drive circuit that controls the transistor switch T1 connected between the load 300 and the battery stack 200 including one or more battery cells, and includes: a pair of capacitor connection terminals (CP terminal and CN terminal) to which the flying capacitor 104 is connected; an internal reference voltage buffer 101 that generates a voltage to be applied between two terminals of the transistor switch T1 to activate the transistor switch T1; and a logic control unit 102 (not shown) that temporarily connects the internal reference voltage buffer 101 to the pair of capacitor connection terminals (CP terminal and CN terminal) to charge the flying capacitor 104 with the voltage generated by the internal reference voltage buffer 101, and then temporarily connects the transistor switch T1 to one of the pair of capacitor connection terminals (CP terminal and CN terminal), thereby activating the transistor switch T1.

[0069] As a result, in the transistor drive circuit 100a, the transistor switch T1 is controlled via the flying capacitor 104 under the control of the logic control unit 102 (not shown), thereby realizing a single transistor drive circuit that can selectively control both the high-side transistor switch and the low-side transistor switch.

[0070] The internal reference voltage buffer 101 may be provided outside the transistor driver circuit 100a and connected to the transistor driver circuit 100a from outside the transistor driver circuit 100a.

[0071] Here, the transistor drive circuit 100 a further includes a selection terminal (logic input 112) to which a logic signal for selecting whether the transistor switch T1 is connected to the positive electrode or the negative electrode of the battery stack 200 is input. When the logic signal input to the selection terminal indicates that the transistor switch T1 is connected to the negative electrode of the battery stack 200, the logic control unit 102 (not shown) may perform control such that when the transistor switch T1 and one of the pair of capacitor connection terminals (CP terminal and CN terminal) are temporarily connected, the reference terminal of the two terminals of the transistor switch T1 is connected to the first reference voltage 600. When the logic signal input to the selection terminal indicates that the transistor switch T1 is connected to the positive electrode of the battery stack 200, the logic control unit 102 may perform control such that when the transistor switch T1 and one of the pair of capacitor connection terminals (CP terminal and CN terminal) are temporarily connected, the reference terminal of the two terminals of the transistor switch T1 is connected to the second reference voltage 700.

[0072] This allows the operation mode of the transistor drive circuit 100a to be selectively switched between an operation mode for controlling the high-side transistor switch and an operation mode for controlling the low-side transistor switch, depending on the logic signal input to the selection terminal.

[0073] Furthermore, the first reference voltage 600 may be the voltage of the negative electrode of the battery stack 200, and the second reference voltage 700 may be the voltage of the positive electrode of the battery stack 200. This allows the transistor switch T1 to be activated using the voltages of the positive electrode and negative electrode of the battery stack 200 as reference voltages.

[0074] The transistor switch T1 may also be a field effect transistor, thereby realizing a transistor drive circuit 100a in which the widely used FET is used as the transistor switch T1.

[0075] The transistor driver circuit 100a may further include a flying capacitor 104. The transistor driver circuit 100a may further include a pair of switches that temporarily connect the internal reference voltage buffer 101 to a pair of capacitor connection terminals (CP terminal and CN terminal), and a switch that temporarily connects the transistor switch T1 to one of the pair of capacitor connection terminals (CP terminal and CN terminal).

[0076] 4A and 4B , the FET driver 100 according to the embodiment is a transistor drive circuit that controls a bidirectional switch including two series-connected transistor switches T1 and T2, which is connected between a battery stack 200 including one or more battery cells and a load 300, and includes a pair of capacitor connection terminals (CP terminal and CN terminal) to which a flying capacitor 104 is connected, and a voltage for activating the two transistor switches T1 and T2, which the transistor switches T1 and T2 have. and a logic control unit 102 (not shown in FIG. 10 ) that temporarily connects the internal reference voltage buffer 101 to a pair of capacitor connection terminals (CP terminal and CN terminal) to charge the flying capacitor 104 with the voltage generated by the internal reference voltage buffer 101, and then temporarily connects each of the two transistor switches T1 and T2 to one of the pair of capacitor connection terminals (CP terminal and CN terminal) to activate the transistor switches T1 and T2.

[0077] As a result, in the FET driver 100, the transistor switches T1 and T2 are controlled via the flying capacitor 104 under the control of the logic control unit 102 (not shown in FIG. 10), thereby realizing a single transistor drive circuit that can selectively control both the high-side transistor switch and the low-side transistor switch.

[0078] The internal reference voltage buffer 101 may be provided outside the transistor drive circuit 100 and connected to the transistor drive circuit 100 from outside the transistor drive circuit 100 .

[0079] Here, the FET driver 100 further includes a selection terminal (Loside_EN terminal) to which a logic signal indicating whether the bidirectional switches T1 and T2 are connected to the positive electrode or the negative electrode of the battery stack 200 is input. The logic control unit 102 (not shown in FIG. 10 ) may temporarily connect the transistor switch T1 or T2 to one of the pair of capacitor connection terminals (CP terminal and CN terminal) when the CN terminal is connected to the first reference voltage 600, if the logic signal input to the selection terminal indicates that the bidirectional switch should be connected to the negative electrode of the battery stack 200, and may temporarily connect the transistor switch T1 or T2 to one of the pair of capacitor connection terminals (CP terminal and CN terminal) when the CN terminal is connected to the second reference voltage 700, if the logic signal input to the selection terminal indicates that the bidirectional switch should be connected to the positive electrode of the battery stack 200.

[0080] This allows the operation mode of the FET driver 100 to be selectively switched between an operation mode for controlling the high-side transistor switch and an operation mode for controlling the low-side transistor switch, depending on the logic signal input to the selection terminal.

[0081] Furthermore, the first reference voltage 600 may be the voltage of the negative electrode of the battery stack 200, and the second reference voltage 700 may be the voltage of the positive electrode of the battery stack 200. This allows the transistor switches T1 and T2 to be activated using the voltages of the positive electrode and negative electrode of the battery stack 200 as reference voltages.

[0082] Furthermore, each of the two transistor switches T1 and T2 may be a field effect transistor, thereby realizing the transistor driver circuit 100a in which the widely used FETs are used as the transistor switches T1 and T2.

[0083] The FET drivers 100 and 100a may further include a flying capacitor 104. The FET drivers 100 and 100a may further include a pair of switches SW_A that temporarily connect the internal reference voltage buffer 101 to a pair of capacitor connection terminals (CP terminal and CN terminal), and switches SW_B and SW_C that temporarily connect each of the two transistor switches T1 and T2 to one of the pair of capacitor connection terminals (CP terminal and CN terminal).

[0084] The internal reference buffer 101 used to charge the flying capacitors can also be configured external to the transistor driver circuits 100 and 100a, further simplifying the design of the transistor driver circuits 100 and 100a while also providing greater flexibility in the reference voltages needed to drive different types of transistor switches.

[0085] Although the transistor driver circuit according to the present invention has been described above based on the embodiments and modifications thereof, the present invention is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present invention, various modifications that would occur to those skilled in the art to the present embodiments and modifications, and other forms constructed by combining some of the components of the embodiments and modifications, are also included within the scope of the present invention.

[0086] For example, in the embodiment and the modified example, FETs are used as the transistor switches, but this is not limiting, and other semiconductor switches such as IGBTs (insulated gate bipolar transistors) may also be used.

[0087] Furthermore, in the embodiment and modified examples, the transistor drive circuit controls a transistor switch connected between a battery stack including one or more battery cells and a load, but the transistor switch controlled by the transistor drive circuit is not limited to this type of connection and may be connected, for example, between a DC voltage source and a load.

[0088] The present invention can be used as a transistor drive circuit, and in particular as a transistor drive circuit that controls a transistor switch connected between a battery stack and a load.

[0089] 100, 100a Transistor drive circuit (FET driver) 101 Internal reference voltage buffer (internal VREF buffer) 102 Logic control unit (control circuit) 104, CF Flying capacitor 110 Drive circuit 112 Logic input (selection terminal) 200 Battery stack 300 Load 400 Positive terminal of battery stack 500 Negative terminal of battery stack 600 First reference voltage 700 Second reference voltage T1 First FET (transistor switch) T2 Second FET (transistor switch) VBAT_P Positive terminal of battery stack VBAT_N Negative terminal of battery stack VPACK_P, VBAT_P_OUT Positive terminal of load VPACK_N, VBAT_N_OUT Negative terminal of load

Claims

1. A transistor drive circuit that controls a transistor switch connected between a battery stack including one or more battery cells and a load, comprising: a pair of capacitor connection terminals to which a flying capacitor is connected; an internal reference voltage buffer that generates a voltage to be applied between two terminals of the transistor switch to activate the transistor switch; and a control circuit that temporarily connects the internal reference voltage buffer to the pair of capacitor connection terminals to charge the flying capacitor with the voltage generated by the internal reference voltage buffer, and then temporarily connects the transistor switch to one of the pair of capacitor connection terminals to activate the transistor switch.

2. The transistor drive circuit according to claim 1, further comprising a selection terminal to which a logic signal indicating whether the transistor switch is connected to the positive electrode or the negative electrode of the battery stack is input, wherein the control circuit, when the logic signal input to the selection terminal indicates that the transistor switch is connected to the negative electrode of the battery stack, controls the reference terminal of the two terminals of the transistor switch to be connected to a first reference voltage when the transistor switch is temporarily connected to one of the pair of capacitor connection terminals, and when the logic signal input to the selection terminal indicates that the transistor switch is connected to the positive electrode of the battery stack, controls the reference terminal of the two terminals of the transistor switch to be connected to a second reference voltage when the transistor switch is temporarily connected to one of the pair of capacitor connection terminals.

3. The transistor drive circuit according to claim 2, wherein the first reference voltage is a voltage at the negative electrode of the battery stack, and the second reference voltage is a voltage at the positive electrode of the battery stack.

4. The transistor drive circuit according to any one of claims 1 to 3, wherein the transistor switch is a field effect transistor.

5. The transistor drive circuit according to any one of claims 1 to 4, further comprising the flying capacitor.

6. The transistor drive circuit according to any one of claims 1 to 5, further comprising: a pair of switches that temporarily connect the internal reference voltage buffer to the pair of capacitor connection terminals; and a switch that temporarily connects the transistor switch to one of the pair of capacitor connection terminals.

7. A transistor drive circuit for controlling a bidirectional switch including two transistor switches connected in series, which is connected between a load and a battery stack including one or more battery cells, comprising: a pair of capacitor connection terminals to which a flying capacitor is connected; an internal reference voltage buffer that generates a voltage for activating the two transistor switches, the voltage being applied between two terminals of each of the two transistor switches; and a control circuit that temporarily connects the internal reference voltage buffer to the pair of capacitor connection terminals to charge the flying capacitor with the voltage generated by the internal reference voltage buffer, and then temporarily connects each of the two transistor switches to one of the pair of capacitor connection terminals to activate the transistor switch.

8. The transistor drive circuit according to claim 7, further comprising a selection terminal to which a logic signal indicating whether the bidirectional switch is connected to the positive electrode or the negative electrode of the battery stack is input, wherein the control circuit, when the logic signal input to the selection terminal indicates that the bidirectional switch is connected to the negative electrode of the battery stack, performs control so that the reference terminal of the two terminals of one of the two transistor switches is connected to a first reference voltage when one of the two transistor switches is temporarily connected to one of the pair of capacitor connection terminals, and when the logic signal input to the selection terminal indicates that the bidirectional switch is connected to the positive electrode of the battery stack, performs control so that the reference terminal of the two terminals of one of the two transistor switches is connected to a second reference voltage when one of the two transistor switches is temporarily connected to one of the pair of capacitor connection terminals.

9. The transistor drive circuit according to claim 8, wherein the first reference voltage is a voltage at the negative electrode of the battery stack, and the second reference voltage is a voltage at the positive electrode of the battery stack.

10. The transistor drive circuit according to any one of claims 7 to 9, wherein each of the two transistor switches is a field effect transistor.

11. The transistor drive circuit according to any one of claims 7 to 10, further comprising the flying capacitor.

12. A transistor drive circuit according to any one of claims 7 to 11, further comprising: a pair of switches that temporarily connect the internal reference voltage buffer to the pair of capacitor connection terminals; and a switch that temporarily connects each of the two transistor switches to one of the pair of capacitor connection terminals.

13. A transistor drive circuit for controlling a transistor switch connected between a load and a battery stack including one or more battery cells, comprising: a pair of capacitor connection terminals to which a flying capacitor is connected; an internal reference voltage buffer connected externally to the transistor drive circuit, which generates a voltage to activate the transistor switch and to be applied between two terminals of the transistor switch; and a control circuit that temporarily connects the pair of capacitor connection terminals to charge the flying capacitor with the voltage generated by the internal reference voltage buffer, and then temporarily connects the transistor switch to one of the pair of capacitor connection terminals to activate the transistor switch.

14. A transistor drive circuit for controlling a bidirectional switch including two transistor switches connected in series, which is connected between a load and a battery stack including one or more battery cells, comprising: a pair of capacitor connection terminals to which a flying capacitor is connected; an internal reference voltage buffer connected externally to the transistor drive circuit, which generates a voltage for activating the two transistor switches and which is to be applied between two terminals of each of the two transistor switches; and a control circuit that temporarily connects the pair of capacitor connection terminals to charge the flying capacitor with the voltage generated by the internal reference voltage buffer, and then temporarily connects each of the two transistor switches to one of the pair of capacitor connection terminals to activate the transistor switch.

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