Dram module

Abstract

Designs of a memory module can be configured for multiple rank configurations by varying the number of stacked die within each memory package on the module. Package arrangements help to support short command / address, clock, and data signal routing distances on the module. Heat dissipation may be reduced by limiting each package to one active die per package. Data buffers and short data channels to the packages are also supported. Stacked die of a module may be accessed as two separate time "slices." Combined registering clock driver and data buffer devices may be used. Some configuration are able to support Diekill error correction capability. Some configurations are able to support Packagekill error correction capability.

Description

DRAM MODULEBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure l is a diagram illustrating a first package and channel arrangement for a memory module.

[0002] Figure 2 is a diagram illustrating an example command / address signal distribution.

[0003] Figures 3A-3C are diagrams illustrating example memory module die / rank organizations.

[0004] Figure 4 is a diagram illustrating a second package and channel arrangement for a memory module.

[0005] Figure 5 is a diagram illustrating a third package and channel arrangement for a memory module.

[0006] Figures 6A-6B are diagrams illustrating example multiplexed registered memory module die / rank organizations with Diekill capability.

[0007] Figures 7A-7B are diagrams illustrating example multiplexed registered memory module die / rank organizations with Packagekill capability.

[0008] Figure 8 is a diagram illustrating a fourth package and channel arrangement for a memory module.

[0009] Figure 9 is a diagram illustrating a single-sided package and channel arrangement for a memory module.

[0010] Figure 10 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] A form of reliability, accessibility, and serviceability (RAS) functions for memories (e.g., dynamic random access memories - DRAMs) and / or memory modules uses error detection and correction codes to allow a system to continue to function when one of multiple memory devices on, for example, a memory module, fail. This is commonly known as “Chipkill” or Single-Device Data Correction (SDDC). Thus, for example, an additional 25% of memory capacity to store EDC coding (e.g., 8 DRAMs assigned to hold data and 2 DRAMS assigned to hold EDC information) can allow any one of the DRAMs to fail (e.g., one of ten) and the errors caused by that failure would be correctable from the information stored by the remaining (e.g., nine) functioning DRAMs.

[0012] However, for memory die packages with more than one die per package (e.g., stacked dies), two types of failures are possible. First, a single die of the package (or stack)may fail. Or, all of the dies of a package may exhibit failure (e.g., power is disconnected from a package or stack). For the purposes of this discussion, the former will be referred to herein as having “Diekill” capability and the EDC coding technique described above is sufficient to correct for errors caused by a single die of a multi -die stack / package. The latter will be referred to as having “Packagekill” capability (i.e., the failure of an entire package of multiple dies would be correctable).

[0013] In an embodiment, various designs of a memory module can be configured for multiple rank configurations by varying the number of stacked die within each memory package on the module. Various package arrangements help to support short command / address, clock, and data signal routing distances on the module. Heat dissipation may be reduced by limiting each package to one active die per package. Data buffers and short data channels to the packages are also supported. In an embodiment, ten memory device packages per channel allows the use of Packagekill error correction capability - where one entire package, regardless of the number of die in that package malfunctions and the errors caused thereby can be corrected.

[0014] In an embodiment, multiplexed modules are supported. For example, five packages per channel using two (or more) stacked memory die per package where each stacked die is accessed as two separate sub-data blocks (a.k.a., “data slices” , which are, for example, equal size portions of a cache line) is able to support Diekill error correction capability. In an example with two die per package, and five packages, the ten total die accessed via the channel may be allocated such that eight of the die store data, and two of the die store error detection and correction information. In another example, ten packages per channel using two (or more) stacked memory die per package where each stacked die (or pairs of stacked die) are accessed as separate channels (e.g., separate command / address buses) is able to support Packagekill error correction capability.

[0015] Figure l is a diagram illustrating a first package and channel arrangement for a memory module. In Figure 1, module 100 comprises substrate 101, registering clock driver 120a, registering clock driver 120b, memory die packages 131af-135af, memory die packages 13 lbf-135bf, memory die packages 131ab-135ab, memory die packages 13 lbb-135bb, power management hub integrated circuit (PMIC) 150, and connector 190. In an embodiment, PMIC 150 may include security circuitry and / or functions (e.g., anti-counterfeiting). In some embodiments, RCD 120a and RCD 120b may further include data buffer (DB) circuitry / functionality, multiplexing RCD (MRCD) circuitry / functionality, and / or multiplexing data buffer (MDB) circuitry / functionality.

[0016] Each of memory die packages 131af-135af, memory die packages 13 Ibf- 135bf, memory die packages 131ab-135ab, and memory die packages 13 lbb-135bb includes at least one memory die (e.g., DRAM die). In some embodiments, memory die packages 131af- 135af, memory die packages 13 Ibf- 135bf, memory die packages 131ab-135ab, and memory die packages 13 lbb-135bb may include multiple (e.g., two, four, eight) stacked memory dies. Each of memory die packages 131af-135af, memory die packages 13 lbf-135bf, memory die packages 131ab-135ab, memory die packages 13 lbb-135bb, RCDs 120a-120b, and PMIC 150 are rectangular in shape and rotationally oriented in Figure 1 with the short side of the rectangle closest to the connector 190. It should be understood from Figure 1 and subsequent figures, that shape (square vs. rectangular), rotational orientations, and location (e.g., front or back) of the packages (e.g., RCD, memory, and PMIC) illustrated are merely examples. For example, one or more of memory die packages 131af-135af, 131bf-135bf, 131ab-135ab 13 lbb-135bb and / or RCDs 120a may be square. In another example, one or more of memory die packages 131af-135af, 131bf-135bf, 131ab-135ab 131bb-135bb and / or RCDs 120a may be rotated with a long side of a rectangular package closes to connector 190. However, regardless of the package rotations selected, the generally central location of a respective RCD 120a-120b among the memory die packages 131af-135af, 13 lbf-135bf, 13 lab-135ab 13 lbb-135bb interconnected with that RCD 120a-120b helps to reduce signal routing distances and / or signal loading.

[0017] Memory die packages 13 laf-135af and registering clock driver (RCD) 120a are illustrated arranged in two rows and three columns to the left of PMIC 150 (as viewed from a first — hereinafter “front” side — of module 100 in Figure 1). Memory die packages 13 Ibf- 135bf and RCD 120b are illustrated arranged in two rows and three columns to the right of PMIC 150. Memory die packages 131af-135af, memory die packages 13 lbf-135bf, RCD 120a, RCD 120b, and PMIC 150 are illustrated disposed on the front side of module 100. In some embodiments, one or more of RCDs 120a- 120b and PMIC 150 may be disposed on the back side of module 100. In Figure 1, the row of packages closest to connector 190 (hereinafter “bottom” row) and to the left of PMIC 150 includes, from left to right, package 13 laf, RCD 120a, and package 132af. The bottom row of packages to the right of PMIC 150 includes, from left to right, package 13 Ibf, RCD 120b, and package 132bf. The row of packages farthest from connector 190 (hereinafter “top” row) and to the left of PMIC 150 includes, from left to right, package 133af, package 134af, and package 135af. The top row of packages to the right of PMIC 150 includes, from left to right, package 133bf, package 134bf, and package 135bf

[0018] Also in Figure 1, memory die packages 131ab-135ab and memory die packages 13 lbb-135bb are illustrated disposed on the back side of module 100. The disposition of memory die packages 131ab-135ab and memory die packages 13 lbb-135bb on the back side of module 100 is shown in Figure 1 by illustrating memory die packages 131ab-135ab and memory die packages 13 lbb-135bb using dotted lines. Memory die packages 131ab-135ab and memory die packages 13 lbb-135bb are respectively located opposite (i.e., directly on the other side of substrate 100) of memory die packages 131af-135af and memory die packages 131bf-135bf.

[0019] In an embodiment, RCD 120a at least buffers command / address signals from connector 190 and distributes buffered command / address signals to memory die packages 131af-135af and memory die packages 131ab-135ab. RCD 120b at least buffers command / address signals from connector 190 and distributes buffered command / address signals to memory die packages 13 lbf-135bf and memory die packages 13 lbb-135bb.

[0020] In an embodiment, RCD 120a distributes five (5) copies of respective command / address signals from connector 190 to corresponding front / back aligned pairs of packages 131af-135af (front) and 131ab-135ab (back). For example, RCD 120a may distribute a first copy of the command / address signals to memory die package 131af and memory die packagel31ab, a second copy to memory die package 132af and memory die packagel32ab, a third copy to memory die package 133af and memory die packagel32ab, a fourth copy to memory die package 134af and memory die packagel34ab, and a fifth copy to memory die package 135af and memory die packagel35ab. RCD 120b may similarly distribute command / address signals from connector 190 to corresponding front / back aligned pairs of packages 13 lbf-135bf (front) and 13 lbb-135bb (back).

[0021] Accordingly, it should be understood that memory die packages 13 laf-135af and memory die packages 131ab-135ab, which are all disposed to the left of PMIC 150 and surround RCD 120a, are connected with RCD 120a and connector 190 (e.g., by contacts, traces, and / or vias of substrate 101) to form a first memory sub-channel (a.k.a., channel “A”). Likewise, memory die packages 13 lbf-135bf and memory die packages 13 lbb-135bb, which are all disposed to the right of PMIC 150 and surround RCD 120b, are connected with RCD 120b and connector 190 to form a second memory sub-channel (a.k.a., channel “B”). Accordingly, channel A and channel B both interface with devices external to module 100 via connector 190. Also note that channel A accesses a set of memory die packages 131af-135af and memory die using RCD 120a that is nonoverlapping with the set of memory die packages 13 lbf-135bf and memory die packages 13 lbb-135bb packages 131ab-135ab that channel Baccesses using RCD 120b. Accordingly, channel A and channel B interfaces of module 100 each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the channel A and channel B interface.

[0022] As discussed herein, RCD’s (e.g., RCD120a and RCD 120b) may distribute multiple copies of command / address signals to corresponding front / back aligned pairs of packages. Figure 2 is a diagram illustrating an example command / address signal distribution. In Figure 2, command / address signal buffering system 200 comprises RCD 220, substrate via 221, transmission line 222, front side memory die package 23 If, and back side memory die package 23 lb. A first command / address signal (e.g., CA[x]) from a module interface (e.g., connector 190) is buffered and multiple copies (e.g., CAl[x], CA2[x], etc.) are output by RCD 220. In Figure 2, a first copy CAl[x] is operatively coupled (e.g., connected) to a first end of transmission line 222 (e.g., signal trace of module 100). The second end of transmission line 222 is connected to via 221 such that the buffered signal CAl[x] is operatively coupled to front side disposed memory die package 23 If (e.g., package 131af) and a back side disposed memory die package 23 If (e.g., package 13 lab). Other copies (e.g., CAl[x], CA2[x], etc.) of the first command / address signal CA[x] may be distributed by similar transmission lines and vias to other front / back side pairs of packages (e.g., package 132af and package 132ab, package 133af and package 133ab, etc.) In an embodiment, transmission line 222 may be less than 25 mm in length.

[0023] Figures 3A-3C are diagrams illustrating example memory module die / rank organizations. The module die / rank organizations illustrated in Figures 3A-3C may be used by, for example, module 100 and its components. Also in Figures 3A-3C, a limited number of signals (e.g., CA[], DQ[], etc.) are depicted. Additional signals may interconnect the illustrated devices (e.g., CK, CS, DQS, etc.). However, those signals have been omitted for the sake of brevity and visual clarity.

[0024] In Figure 3A, example channel 301 comprises RCD 320, and single die package 360a. Single die package 360a includes a single memory die 0 341 Single die package 360a may be an example of memory die packages 131af-135af, memory die packages 13 Ibf- 135bf, memory die packages 131ab-135ab, and memory die packages 13 lbb-135bb. Command / address signals CA[] are transmitted by RCD 320 to die 0 341. Die 0 341 bidirectionally communicates data signal DQ[] (e.g., 4-bits of data) with either a module connector (e.g., connector 190) or a data buffer device. Package 360a includes only a single die, die 0 341 that is accessed (or configured) as part of a single rank (e.g., rank #0) on thechannel (e.g., channel A) of the module (e.g., module 100). With a channel of ten packages (e.g., channel A of module 100), the single die per package, one rank per channel configuration as partially illustrated in Figure 3 A has Packagekill RAS capabilities.

[0025] In Figure 3B, example channel 302 comprises RCD 320, and two (dual) die package 360b. Dual die package 360b includes two memory die stack 342 having memory die 0 342a and memory die 1 342b. Dual die package 360b may be an example of memory die packages 131af-135af, memory die packages 13 lbf-135bf, memory die packages 131ab- 135ab, and memory die packages 13 lbb-135bb. Command / address signals CA[] are transmitted by RCD 320 to package 360b and distributed to die 0 342a and die 1 342b. Die 0 342a and die 1 342b bidirectionally communicate via shared data signals DQ[] (e.g., 4-bits of data) with either a module connector (e.g., connector 190) or a data buffer device. The two dies of dual die package 360b are each accessed as parts of separate ranks (e.g., die 0 342a accessed as part of rank #0 and die 1 342b accessed as part of rank #1) on the channel (e.g., channel A) of the module (e.g., module 100). With a channel of ten packages (e.g., channel A of module 100), the two die per package, two ranks per package (one for each die), channel configuration as partially illustrated in Figure 3B has Packagekill RAS capabilities.

[0026] In Figure 3C, example channel 303 comprises RCD 320, and four (quad) die package 360c. Quad die package 360c includes four memory die stack 343 having memory die 0 343a, memory die 1 343b, memory die 2 343c, and memory die 3 343d. Quad die package 360c may be an example of memory die packages 131af-135af, memory die packages 13 lbf-135bf, memory die packages 131ab-135ab, and memory die packages 13 Ibb- 135bb . Command / address signals CA[] are transmitted by RCD 320 to package 360c and distributed to memory die 0 343a, memory die 1 343b, memory die 2 343c, and memory die 3 343d. Memory die 0 343a, memory die 1 343b, memory die 2 343c, and memory die 3 343d bidirectionally communicate via shared data signals DQ[] (e.g., 4-bits of data) with either a module connector (e.g., connector 190) or a data buffer device. The four dies of quad die package 360b are each accessed as parts of separate ranks (e.g., die 0 342a accessed as part of rank #0, and die 1 342b accessed as part of rank #1, etc.) on the channel (e.g., channel A) of the module (e.g., module 100). With a channel of ten packages (e.g., channel A of module 100), the four die per package, four ranks per package (one for each die), channel configuration as partially illustrated in Figure 3C has Packagekill RAS capabilities.

[0027] It should be noted that package 360a includes one die that is accessed part of one rank. Package 360b has two dies that are each accessed as parts of two separate ranks. Package 360c has four die that are each accessed as parts of four separate ranks.Accordingly, it should be understood that the number of memory ranks accessed via the channel A interface and the channel B interface of module 100 may be determined by the number of DRAM die stacked in each of the memory die packages 131af-135af, memory die packages 13 lbf-135bf, memory die packages 131ab-135ab, memory die packages 13 Ibb- 135bb of module 100.

[0028] Figure 4 is a diagram illustrating a second package and / or channel arrangement for a memory module. In Figure 4, module 400 comprises substrate 401, registering clock drivers 420a-420d, memory die packages 431af-435af, memory die packages 431bf-435bf, memory die packages 431cf-435cf, memory die packages 431df-435df, memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, memory die packages 431db-435db, power management hub integrated circuit (PMIC) 450, and connector 490. In an embodiment, PMIC 450 may include security circuitry and / or functions (e.g., anti -counterfeiting). Similar to module 100, in some embodiments, RCDs 420a-420d may further include data buffer (DB) circuitry / functionality, multiplexing RCD (MRCD) circuitry / functionality, and / or multiplexing data buffer (MDB) circuitry / functionality.

[0029] Each of memory die packages 431af-435af, memory die packages 431bf-435bf, memory die packages 431cf-435cf, memory die packages 431df-435df, memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, memory die packages 431db-435db, include at least one memory die (e.g., DRAM die). In some embodiments, memory die packages 431af-435af, memory die packages 431bf-435bf, memory die packages 431cf-435cf, memory die packages 431df-435df, memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, memory die packages 431db-435db, may include multiple (e.g., two, four, eight) stacked memory dies. Each of memory die packages 43 laf-435af, memory die packages 43 Ibf- 435bf, memory die packages 431cf-435cf, memory die packages 431df-435df, memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb- 435cb, memory die packages 431db-435db, RCDs 420a-420d, and PMIC 450 are rectangular in shape and rotationally oriented in Figure 4 with the short side of the rectangle closest to the connector 490.

[0030] Memory die packages 43 laf-435af, memory die packages 43 lbf-435bf, RCD 420a, and RCD 420b are illustrated arranged in two rows and three columns to the left of PMIC 450. Memory die packages 431cf-435cf, memory die packages 431df-435df, RCD 420c, and RCD 420d are illustrated arranged in two rows and three columns to the right ofPMIC 450. Memory die packages 431af-435af, memory die packages 431bf-435bf, memory die packages 431cf-435cf, memory die packages 431df-435df, RCD 420a, RCD 420b, RCD 420c, RCD 420d and PMIC 450 are illustrated disposed on the front side of module 400. . In some embodiments, one or more of RCDs 420a-420d and PMIC 450 may be disposed on the back side of module 400. In Figure 4, the bottom row of to the left of PMIC 450 includes, from left to right, package 43 laf, RCD 420a, package 432af, package 43 Ibf, RCD 420b, and package 432bf. The bottom row of packages to the right of PMIC 450 includes, from left to right, package 431cf, RCD 420c, package 432cf, package 431df, RCD 420d, and package 432df. The top row of packages to the left of PMIC 450 includes, from left to right, package 433af, package 434af, package 435af, package 433bf, package 434bf, and package 435bf. The top row of packages to the right of PMIC 450 includes, from left to right, package 433cf, package 434cf, package 435cf, package 433df, package 434df, and package 435df.

[0031] Also in Figure 4, memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, and memory die packages 431db-435db are disposed on the back side of module 400. The disposition of memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, and memory die packages 431db-435db on the back side of module 400 is shown in Figure 4 by illustrating memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, and memory die packages 431db-435db using dotted lines. Memory die packages 431ab-435ab, memory die packages 431bb-435bb, memory die packages 431cb-435cb, and memory die packages 431db-435db are respectively located opposite (i.e., directly on the other side of substrate 400) of memory die packages 431af- 435af, memory die packages 431bf-435bf, memory die packages 431cf-435cf, and memory die packages 431df-435df.

[0032] In an embodiment, RCD 420a at least buffers command / address signals from connector 490 and distributes buffered command / address signals to memory die packages 43 laf-435af and memory die packages 43 lab-435ab. RCD 420b at least buffers command / address signals from connector 490 and distributes buffered command / address signals to memory die packages 43 lbf-435bf and memory die packages 43 lbb-435bb. RCD 420c at least buffers command / address signals from connector 490 and distributes buffered command / address signals to memory die packages 431cf-435cf and memory die packages 43 lcb-435cb. RCD 420d at least buffers command / address signals from connector 490 and distributes buffered command / address signals to memory die packages 431df-435df and memory die packages 431db-435db.

[0033] In an embodiment, RCD 420a distributes five (5) copies of respective command / address signals from connector 490 to corresponding front / back aligned pairs of packages 43 laf-435af (front) and 43 lab-435ab (back). For example, RCD 420a may distribute a first copy of the command / address signals to memory die package 43 laf and memory die packagel31ab, a second copy to memory die package 432af and memory die packagel32ab, a third copy to memory die package 433af and memory die packagel32ab, a fourth copy to memory die package 434af and memory die packagel34ab, and a fifth copy to memory die package 435af and memory die packagel35ab. RCD 420b-420c may similarly distribute command / address signals from connector 490 to corresponding front / back aligned pairs of packages.

[0034] Accordingly, it should be understood that memory die packages 43 laf-435af and memory die packages 43 lab-435ab, which surround RCD 420a, are connected with RCD 420a and connector 490 (e.g., by contacts, traces, and / or vias of substrate 401) to form a first memory sub-channel (a.k.a., channel “A”). Memory die packages 431bf-435bf and memory die packages 431bb-435bb, which surround RCD 420b, are connected with RCD 420b and connector 490 to form a second memory sub-channel (a.k.a., channel “B”). Memory die packages 431cb-435cb, which surround RCD 420c, are connected with RCD 420c and connector 490 (e.g., by contacts, traces, and / or vias of substrate 401) to form a third memory sub-channel (a.k.a., channel “C”). Memory die packages 431df-435df and memory die packages 431db-435db, which surround RCD 420d, are connected with RCD 420d and connector 490 to form a fourth memory sub-channel (a.k.a., channel “D”).

[0035] Figure 5 is a diagram illustrating a third package and channel arrangement for a memory module. In Figure 5, module 500 comprises substrate 501, registering clock driver 520a, registering clock driver 520b, memory die packages 531af-535af, memory die packages 531bf-535bf, memory die packages 531ab-535ab, memory die packages 531bb-535bb, power management hub integrated circuit (PMIC) 550, and connector 590. Module 500 is substantially configured (e.g., into channel A with RCD 520a and memory die packages 531af-535af 531ab-535ab, and channel B with RCD 520b and memory die packages 53 Ibf- 535bf 531bb-535bb) and connected internally the same as module 100 in Figure 1. However, In Figure 5, memory die packages 531af, 532af, 534af, 531bf, 532bf, 534bf, 531ab, 532ab, 534ab, 53 Ibb, 532bb, and 534bb are rotationally oriented in Figure 5 with the long side of the rectangle closest to the connector 590. Thus, it should be understood that Figure 5 illustrates that the memory modules disclosed herein (e.g., module 100, module 400) include moduleswith one or more memory die packages, RCD’s, and / or PMIC’s rotated (e.g., 90°) with respect to one or more other packages on the module.

[0036] As discussed herein, RCDs 120a-120b, RCDs 420a-420d, and RCDs 520a-520b may include multiplexing RCD (MRCD) circuitry / functionality and / or multiplexing data buffer (MDB) circuitry / functionality. Figures 6A-6B are diagrams illustrating example multiplexed registered memory module die / rank organizations with Diekill capability. Figure 6A illustrates a two data slice one rank organization. In other words, the organization in Figure 6A accesses two dies concurrently where each die provides a portion (i.e., data slice) of a data block (e.g., cache line). In Figure 6A, example channel 601 comprises registering clock driver (RCD) 620, two (dual) die package 660a, and optionally data buffer (DB) 670. In some embodiments, RCD 620 may be a multiplexing RCD (MRCD). In some embodiments, if present, DB 670 may be a multiplexing DB (MDB). Dual die package 660a includes two memory die stack 641 having memory die 0 641a and memory die 1 641b. Dual die package 660a may be an example of one or more memory die packages described herein in relation to module 100, module 400, and / or module 500. In an embodiment, (M)DB 670 circuitry and / or functionality may be included in / with (M)RCD 620.

[0037] Command / address signals CA[] are transmitted by RCD 620 to package 660a and distributed to die 0 641a and die 1 641b. Die 0 641a bidirectionally communicates via data slice 0 data signals S0DQ[] (e.g., 4-bits of data) with (M)DB 670. Die 1 641b bidirectionally communicates via data slice 1 data signals S1DQ[] (e.g., 4-bits of data) with (M)DB 670. The two dies of dual die package 660a are each accessed as parts of the same rank but different data slices (e.g., different portions of the same cache line) on the channel (e.g., channel A) of the module (e.g., module 100). With a channel of ten packages (e.g., channel A of module 100), the two die per package, one rank per package channel configuration as partially illustrated in Figure 6A has Diekill RAS capabilities. For example, a configuration where five packages on front of module form one rank, and five packages on back of module form another rank, Reed-Solomon error detection and correction can provide Diekill RAS for each rank. Distributing only a single CA[] bus to dual die package 660a allows for a simpler trace routing design for the module than distributing multiple CA[] busses to each dual die package.

[0038] Figure 6B illustrates a two data slice two rank organization. In other words, the organization in Figure 6B accesses two of four dies concurrently where each die provides a portion (i.e., data slice) of a data block (e.g., cache line). In Figure 6B, example channel 602 comprises registering clock driver (RCD) 620, four (quad) die package 660b, and optionallydata buffer (DB) 670. In some embodiments, RCD 620 may be a multiplexing RCD (MRCD). In some embodiments, DB 670, if present, may be a multiplexing DB (MDB). Quad die package 660b includes four memory die stack 642 having memory die 0 642a, memory die 1 642b, memory die 2 642c, and memory die 3 642d. Quad die package 660b may be an example of one or more memory die packages described herein in relation to module 100, module 400, and / or module 500. In an embodiment, MDB 670 may be included in / with MRCD 620.

[0039] Command / address signals CA[] are transmitted by MRCD 620 to package 660b and distributed to memory die 0 642a, memory die 1 642b, memory die 2 642c, and memory die 3 642d. Die 0 642a and die 1 642b bidirectionally communicate via shared data slice 0 (SO) data signals S0DQ[] (e.g., 4-bits of data) with (M)DB 670. Die 2 642c and die 3 642d bidirectionally communicate via shared data slice 1 (SI) data signals S1DQ[] (e.g., 4-bits of data) with (M)DB 670. Die 0 642a and die 1 642b are each accessed as parts of separate ranks (e.g., die 0 642a is accessed as part of rank #0 and die 1 642b is accessed as part of rank #1) and the data slice (e.g., data slice SO) on the channel. Similarly, die 2 642c and die 3 642d are also each accessed as parts of the separate ranks (e.g., die 2 642c is accessed as part of rank #0 and die 3 642d is accessed as part of rank #1) and the same data slice (e.g., data slice SI) on the channel.

[0040] Die 0 642a and die 2 642c of quad die package 660a are each accessed as parts of the same rank (e.g., rank #0) but different data slices on the channel (e.g., channel A) of the module (e.g., module 100). Die 642b and die 642d of quad die package 660a are each accessed as parts of the same rank (e.g., rank #1) but different data slices on the channel (e.g., channel A) of the module (e.g., module 100). With a channel of ten packages (e.g., channel A of module 100), the quad die per package, channel configuration as partially illustrated in Figure 6B has Diekill RAS capabilities. Distributing only a single CA[] bus to quad die package 660b allows for a simpler trace routing design for the module than distributing multiple CA[] busses to each quad die package.

[0041] The organizations illustrated in Figures 6A-6B DRAM devices as described herein may be used to implement either RDIMM / LRDIMM or MRDIMM modules. To implement a RDIMM / LRDIMM only five memory die packages are needed per channel, since each memory die package provides two data slices (i.e., five memory die packages times two data slices per memory die package equals ten data slices). The module implementing this organization / arrangement would look similar to Figure 1, except with memory die packages only on the one (e.g., front) side of the module. The module may support either 1 or 2 ranks,depending on whether the one-rank (e.g., Figure 6A) or two-rank (e.g., Figure 6B) memory die packages are used.

[0042] To implement a MRDIMM, twice as much data is communicated to / from MDB devices. Thus, five memory die packages are needed on both front and back of the module for each channel. The five memory die packages on the front may form a rank that provides a cache line for one of the two multiplexed pseudo-channels, and the five devices on the back may form another rank that provides a separate cache line for the other pseudo-channel. The two ranks are accessed concurrently (e.g., in lockstep), with each rank having its own separate CA signals - these are the ‘time multiplexed ranks’ for a given channel. If one-rank memory die packages (Figure 6A) are used, each pseudo-channel will have a single rank. If two-rank memory die packages (Figure 6B) are used, each pseudo-channel will have two ranks.

[0043] Figures 7A-7B are diagrams illustrating example multiplexed registered memory module die / rank organizations with Packagekill capability. In Figure 7A, example channel 701 comprises multiplexing registering clock driver (MRCD) 720, two (dual) die package 760a, and multiplexing data buffer (MDB) 770. Dual die package 760a includes two memory die stack 741 having memory die 0 741a and memory die 1 741b. Dual die package 760a may be an example of one or more memory die packages described herein in relation to module 100, module 400, and / or module 500. In an embodiment, MDB 770 may be included in / with MRCD 720.

[0044] Time-data slice SO command / address signals CAS0[] are transmitted by MRCD 720 to package 760a and die 0 741a. Time-data slice SI command / address signals CAS1[] are transmitted by MRCD 720 to package 760a and die 1 741b. Die 0 741a bidirectionally communicates via time-data slice 0 data signals S0DQ[] (e.g., 4-bits of data) with MDB 770. Die 1 741b bidirectionally communicates via time-data slice 1 data signals S1DQ[] (e.g., 4- bits of data) with MDB 770. The two dies of dual die package 760a are thus each accessed as different channels of the module (e.g., module 100) that communicate data using different time time-data slices (e.g., alternating time multiplexed data time slots SO and SI). A channel of ten packages, two die per package, two time multiplexed channels per package (alternating time slots for each die), configuration as partially illustrated in Figure 7A has Packagekill RAS capabilities.

[0045] In Figure 7B, example channel 702 comprises multiplexing registering clock driver (MRCD) 720, four (quad) die package 760b, and multiplexing data buffer (MDB) 770. Quad die package 760b includes four memory die stack 742 having memory die 0 742a,memory die 1 742b, memory die 2 742c, memory die 3 742d. Quad die package 760a may be an example of one or more memory die packages described herein in relation to module 100, module 400, and / or module 500. In an embodiment, MDB 770 may be included in / with MRCD 720.

[0046] Time-data slice SO command / address signals CAS0[] are transmitted by MRCD 720 to package 760b and distributed to die 0 742a and die 742b. Time-data slice SI command / address signals CAS1[] are transmitted by MRCD 720 to package 760b and distributed to die 2 742c and die 742d. Die 0 742a and die 1 742b bidirectionally communicate via shared time-data slice 0 data signals S0DQ[] (e.g., 4-bits of data) with MDB 770. Die 3 741c and die 4 bidirectionally communicate via shared time-data slice 1 data signals S1DQ[] (e.g., 4-bits of data) with MDB 770. Dies 742a-742b and dies 742c- 742d of quad die package 760a are thus respectively accessed as different channels of the module (e.g., module 100) that communicate data using different time-data slices (e.g., alternating time multiplexed data time slots SO and SI).

[0047] Die 0 742a and die 2 742c are accessed as parts of the same rank (e.g., rank #0) but different time-data slices (e.g., alternating time multiplexed data time slots SO and SI) on channel (e.g., channel A) of the module (e.g., module 100). Die 742b and die 742d of quad die package 760a are each accessed as parts of the same rank (e.g., rank #1) but different time-data slices (e.g., alternating time multiplexed data time slots SO and SI) on the channel (e.g., channel B) of the module (e.g., module 100). A channel of ten packages, four die per package, two time multiplexed channels per package (alternating time slots for each die), two ranks per package, configuration as partially illustrated in Figure 7B has Packagekill RAS capabilities.

[0048] Figure 8 is a diagram illustrating a fourth package and channel arrangement for a memory module. In Figure 8, module 800 comprises substrate 801, registering clock driver 820a, registering clock driver 820b, memory die packages 831af-835af, memory die packages 831bf-835bf, memory die packages 831ab-835ab, memory die packages 831bb-835bb, power management hub integrated circuit (PMIC) 850, data buffer (DB) devices 871af-873af, DB device 871ab, DB device 873ab, DB devices 871bf-873bf, DB device 871bb, DB device 873bb and connector 890. In an embodiment, PMIC 850 may include security circuitry and / or functions (e.g., anti-counterfeiting). In some embodiments, RCD 820a and RCD 820b may further include, multiplexing RCD (MRCD) circuitry / functionality and DB devices 871af-873af, DB device 871ab, DB device 873ab, DB devices 871bf-873bf, DB device 871bb, DB device 873bb may include multiplexing data buffer (MDB) circuitry / functionality.

[0049] Each of memory die packages 83 laf-835af, memory die packages 83 lbf-835bf, memory die packages 83 lab-835ab, and memory die packages 831bb-835bb includes at least one memory die (e.g., DRAM die). In some embodiments, memory die packages 831af- 835af, memory die packages 83 lbf-835bf, memory die packages 831ab-835ab, and memory die packages 831bb-835bb may include multiple (e.g., two, four, eight) stacked memory dies. Each of memory die packages 831af-835af, memory die packages 831bf-835bf, memory die packages 831ab-835ab, memory die packages 831bb-835bb, RCDs 820a-820b, and PMIC 850 are rectangular in shape and rotationally oriented in Figure 8 with the short side of the rectangle closest to the connector 890. Each of DB devices 871af-873af, DB device 871ab, DB device 873ab, DB devices 871bf-873bf, DB device 871bb, DB device 873bb are rectangular in shape and rotationally oriented in Figure 8 with the long side of the rectangle closest to the connector 890.

[0050] Memory die packages 83 laf-835af and registering clock driver (RCD) 820a are illustrated arranged in two rows and three columns to the left of PMIC 850 (as viewed from a first — hereinafter “front” side — of module 800 in Figure 8). DB devices 871af-873af are illustrated arranged in a single row immediately above connector 890 and to the left of PMIC 850. Memory die packages 83 lbf-835bf and RCD 820b are illustrated arranged in two rows and three columns to the right of PMIC 850. DB devices 871bf-873bf are illustrated arranged in a single row immediately above connector 890 and to the right of PMIC 850. Memory die packages 831af-835af, memory die packages 83 lbf-835bf, RCD 820a, RCD 820b, PMIC 850, DB devices 871af-873af, and DB device 871bf-873bf are disposed on the front side of module 800. In Figure 8, the row of memory device packages closest to connector 890 (hereinafter “middle” row) and to the left of PMIC 850 includes, from left to right, package 83 laf, RCD 820a, and package 832af. The middle row of packages to the right of PMIC 850 includes, from left to right, package 83 Ibf, RCD 820b, and package 832bf. The row of memory device packages farthest from connector 890 (hereinafter “top” row) and to the left of PMIC 850 includes, from left to right, package 833af, package 834af, and package 835af. The top row of packages to the right of PMIC 850 includes, from left to right, package 833bf, package 834bf, and package 835bf. The row of DB devices closest to connector 890 (hereinafter “bottom” row) to the left of PMIC 850 includes, from left to right, DB device 87 laf, DB device 872af, and DB device 873 af. The bottom row of DB devices to the right of PMIC 850 includes, from left to right, DB device 87 Ibf, DB device 872bf, and DB device 873bf.

[0051] Also in Figure 8, memory die packages 831ab-835ab, memory die packages 831bb-835bb, DB device 871ab, DB device 873ab, DB device 871bb, and DB device 873bb are disposed on the back side of module 800. The disposition of memory die packages 831ab-835ab memory die packages 831bb-835bb, DB device 871ab, DB device 873ab, DB device 871bb, and DB device 873bb on the back side of module 800 is shown in Figure 8 by illustrating memory die packages 83 lab-835ab, memory die packages 831bb-835bb, DB device 871ab, DB device 873ab, DB device 871bb, and DB device 873bb using dotted lines. Memory die packages 831ab-835ab and memory die packages 831bb-835bb are respectively located opposite (i.e., directly on the other side of substrate 800) of memory die packages 831af-835af and memory die packages 831bf-835bf. DB device 871ab, DB device 873ab, DB device 871bb, and DB device 873bb are respectively located opposite (i.e., directly on the other side of substrate 800) of DB device 871af, DB device 873af, DB device 871bf, and DB device 873bf.

[0052] Similar to module 100, memory die packages 831af-835af, memory die packages 831ab-835ab, DB devices 871af-873af, DB device 871ab, DB device 873ab, are all disposed to the left of PMIC 850 and surround RCD 820a, are connected with RCD 120a and connector 890 (e.g., by contacts, traces, and / or vias of substrate 801) to form a first memory sub-channel (a.k.a., channel “A”) having data signals that are buffered by DB devices 871af- 873af, DB device 871ab, DB device 873ab. Likewise, memory die packages 831bf-835bf, memory die packages 831bb-835bb, DB devices 871bf-873bf, DB device 871bb, DB device 873bb, which are all disposed to the right of PMIC 850 and surround RCD 820b, are connected with RCD 820b and connector 890 to form a second memory sub-channel (a.k.a., channel “B”) having data signals that are buffered by 831bb-835bb, DB devices 871bf-873bf, DB device 871bb, DB device 873bb. Accordingly, channel A and channel B both interface with devices external to module 800 via connector 890. Also note that channel A accesses a set of memory die packages 831af-835af and memory die memory die packages 831ab-835ab using RCD 820a that is nonoverlapping with the set of memory die packages 83 lbf-835bf and memory die packages 831bb-835bb that channel B accesses using RCD 820b.Accordingly, channel A and channel B interfaces of module 800 each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the channel A and channel B interfaces.

[0053] Figure 9 is a diagram illustrating a single-sided package and channel arrangement for a memory module. In Figure 9, module 900 comprises substrate 901, combination registering clock driver and data buffer (RCD / DB) 920a, RCD / DB 920b, memory diepackages 931a-935a, memory die packages 931b-935b, power management hub integrated circuit (PMIC) 950, and connector 990. Module 900 is configured (e.g., into channel A with RCD / DB 920a and memory die packages 931a-935a, and channel B with RCD / DB 920b and memory die packages 931b-935b) and connected internally similar to module 100 in Figure 1 except with memory die packages only on one side of substrate 901. In addition, in Figure 9, memory die packages 932a, 934a, 935a, RCD / DB 920a, and RCD / DB 920a are rotationally oriented in Figure 9 with the long side of the rectangle closest to the connector 990. In an embodiment, memory die packages 931a-935a and memory die packages 931b-935b each include at least two memory dies that are accessed concurrently. Thus, because there are two active dies per memory die package, module 900 illustrated in Figure 9 has Diekill RAS capabilities.

[0054] It should be understood from the foregoing figures and associated descriptions that the channel configurations with an RCD, DB, or combination integrated circuit that is generally centrally located among a plurality of memory die packages may be considered an arrangement, (or pattern, or tile) that may be, in some embodiments, located and / or repeated in various ways on a module. For example, multiple arrangements may be placed asymmetrically with respect to the PMIC (e.g., two channel arrangements left of, and one right of, or three left of, and none right of). In addition, in some embodiments, different numbers of channel arrangements than have been illustrated herein on a module are contemplated (e.g., three, five, six, eight, etc.)

[0055] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of module 100, system 200, channel 301, channel 302, channel 303, module 400, module 500, channel 601, channel 602, channel 701, channel 702, module 800, and / or module 900, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0056] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometrydescription languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0057] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating, a representation of a circuit component 1020. Processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communications devices 1006. Processors 1002, memory 1004, and communications devices 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0058] Processors 1002 execute instructions of one or more processes 1012 stored in a memory 1004 to process and / or generate circuit component 1020 responsive to user inputs 1014 and parameters 1016. Processes 1012 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1020 includes data that describes all or portions of module 100, system 200, channel 301, channel 302, channel 303, module 400, module 500, channel 601, channel 602, channel 701, channel 702, module 800, and / or module 900, and their components, as shown in the Figures.

[0059] Representation 1020 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1020 may be stored on storage media or communicated by carrier waves.

[0060] Data formats in which representation 1020 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0061] User inputs 1014 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1016 may include specifications and / or characteristics that are input to help define representation 1020. For example, parameters 1016 may include information thatdefines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0062] Memory 1004 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1012, user inputs 1014, parameters 1016, and circuit component 1020.

[0063] Communications devices 1006 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1006 may transmit circuit component 1020 to another system. Communications devices 1006 may receive processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 and cause processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 to be stored in memory 1004.

[0064] Implementations discussed herein include, but are not limited to, the following examples:

[0065] Example 1: A module, comprising: a first memory channel interface and a second memory channel interface that each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the first memory channel interface and the second memory channel interface, the first memory channel interface having a first plurality of command / address (CA) signals, the second memory channel interface having a second plurality of CA signals; a first registering clock driver (RCD) device coupled with the first memory channel interface to at least generate a plurality of buffered versions of the first plurality of CA signals to be provided to unique subsets of a first plurality of dynamic random access memory (DRAM) device packages disposed on the module; a second RCD device coupled with the second memory channel interface to at least generate a plurality of buffered versions of the second plurality of CA signals to be provided to unique subsets of a second plurality of DRAM device packages disposed on the module; the first RCD device disposed on a first side of the module and adjacent on three respective sides to respective ones of the first plurality of DRAM device packages disposed on the first side of the module; and the second RCD device disposed on the first side of the module and adjacent on three respective sides to respective ones of the second plurality of DRAM device packages disposed on the first side of the module, a number of memory ranks accessed via the first memory channel interface and the secondmemory channel interface being determined by a number of DRAM die stacked in each of the first plurality of DRAM packages and second plurality of DRAM packages.

[0066] Example 2: The module of example 1, wherein an equal number of the first plurality of DRAM device packages are disposed on the first side of the module and a second side of the module, and the equal number of the second plurality of DRAM device packages are disposed on the first side of the module and the second side of the module.

[0067] Example 3: The module of example 1, further comprising: a first plurality of data buffer devices coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface; and a second plurality of data buffer devices coupled with the second memory channel interface and the second plurality of DRAM packages to communicate data between the second plurality of DRAM packages and the second memory channel interface.

[0068] Example 4: The module of example 1, wherein the first RCD device is further coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface, and the second RCD device is further coupled with the second memory channel interface and the second plurality of DRAM packages to communicate data between the second plurality of DRAM packages and the second memory channel interface.

[0069] Example 5: The module of example 1, wherein accesses directed to a first memory rank of the first memory channel interface access a respective single die in each of the first plurality of DRAM packages and accesses directed to a second memory rank of the second memory channel interface access a respective single die in each of the second plurality of DRAM packages.

[0070] Example 6: The module of example 4, wherein the first memory channel interface has a third plurality of CA signals and the second memory channel interface has a fourth plurality of CA signals.

[0071] Example 7: The module of example 6, wherein the first RCD device is further coupled with the first memory channel interface to further generate a plurality of buffered versions of the third plurality of CA signals to be provided to the unique subsets of a first plurality of DRAM device packages disposed on the module, and the second RCD device is further coupled with the second memory channel interface to further generate a plurality of buffered versions of the fourth plurality of CA signals to be provided to the unique subsets of a second plurality of DRAM device packages disposed on the module.

[0072] Example 8: The module of example 7, wherein the first RCD device is to time multiplex and time demultiplex data communicated between the first plurality of DRAM packages and the first memory channel interface, and the second RCD device is to time multiplex and time demultiplex data communicated between the second plurality of DRAM packages and the second memory channel interface.

[0073] Example 9: A module, comprising: a plurality of memory channel interfaces that each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the plurality of memory channel interfaces; at least one registering clock driver (RCD) device coupled with at least one of the plurality of memory channel interfaces to at least generate a plurality of buffered versions of a plurality of CA signals of the at least one of the plurality of memory channel interfaces to be provided to respective unique subsets of a plurality of dynamic random access memory (DRAM) device packages disposed on the module; the at least one RCD device being disposed on a first side of the module and being adjacent on at least three respective sides to at least three respective ones of the plurality of DRAM device packages disposed on the first side of the module; and a number of memory ranks accessed via respective accesses via plurality of memory channel interfaces being determined by a number of DRAM die stacked in each of the plurality of DRAM device packages.

[0074] Example 10: The module of example 9, wherein an equal number of the plurality of DRAM device packages are disposed on the first side of the module and a second side of the module.

[0075] Example 11: The module of example 9, further comprising: a plurality of data buffer devices coupled with the plurality of memory channel interfaces and the plurality of DRAM packages to communicate data between the plurality of DRAM packages and the a plurality of memory channel interfaces.

[0076] Example 12: The module of example 9, wherein the at least one RCD device is further coupled with the plurality of memory channel interfaces and the plurality of DRAM packages to communicate data between the plurality of DRAM packages and the plurality of memory channel interfaces.

[0077] Example 13: The module of example 9, wherein accesses directed to respective memory ranks of respective ones of the plurality of memory channel interfaces access respective single dies in a subsets of the plurality of DRAM packages corresponding to each of the respective ones of plurality of memory channel interfaces.

[0078] Example 14: The module of example 13, wherein the plurality of memory channel interfaces each have a plurality of CA signal groups that access a same subset of the plurality of DRAM packages.

[0079] Example 15: The module of example 14, wherein the at least one RCD device is to time multiplex and time demultiplex data communicated between at least one subset of the plurality of DRAM packages and a corresponding one of the plurality of memory channel interfaces.

[0080] Example 16: A module, comprising: a first plurality of dynamic random access memory (DRAM) device packages; a first RCD device disposed on a first side of the module and disposed adjacent on three respective sides of the first RCD device to a subset of the first plurality of DRAM device packages that are also disposed on the first side of the module; a plurality of memory channel interfaces that each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the plurality of memory channel interfaces, the plurality of memory channel interfaces including a first memory channel interface coupled with the first RCD device; and the first RCD device to at least generate a plurality of buffered versions of a first plurality of command / address (CA) signals of the first memory channel interface that are to be provided to the first plurality of DRAM device packages, where accesses using the first plurality of CA signals of the first memory channel interface during a single access transaction are to not access more than one DRAM die that is stacked within the first plurality of DRAM device packages.

[0081] Example 17: The module of example 16, wherein an equal number of the first plurality of DRAM device packages are disposed on the first side of the module and a second side of the module that is opposite of the first side of the module.

[0082] Example 18: The module of example 16, further comprising: a first plurality of data buffer devices coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface.

[0083] Example 19: The module of example 16, wherein the first RCD device is further coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface.

[0084] Example 20: The module of example 16, wherein the first memory channel interface includes a second plurality of CA signals and the first RCD device is to furthergenerate a plurality of buffered versions of a second plurality of CA signals of the first memory channel interface that are to be provided to the first plurality of DRAM device packages.

[0085] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A module, comprising: a first memory channel interface and a second memory channel interface that each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the first memory channel interface and the second memory channel interface, the first memory channel interface having a first plurality of command / address (CA) signals, the second memory channel interface having a second plurality of CA signals; a first registering clock driver (RCD) device coupled with the first memory channel interface to at least generate a plurality of buffered versions of the first plurality of CA signals to be provided to unique subsets of a first plurality of dynamic random access memory (DRAM) device packages disposed on the module; a second RCD device coupled with the second memory channel interface to at least generate a plurality of buffered versions of the second plurality of CA signals to be provided to unique subsets of a second plurality of DRAM device packages disposed on the module; the first RCD device disposed on a first side of the module and adjacent on three respective sides to respective ones of the first plurality of DRAM device packages disposed on the first side of the module; and the second RCD device disposed on the first side of the module and adjacent on three respective sides to respective ones of the second plurality of DRAM device packages disposed on the first side of the module, a number of memory ranks accessed via the first memory channel interface and the second memory channel interface being determined by a number of DRAM die stacked in each of the first plurality of DRAM packages and second plurality of DRAM packages.

2. The module of claim 1, wherein an equal number of the first plurality of DRAM device packages are disposed on the first side of the module and a second side of the module, andthe equal number of the second plurality of DRAM device packages are disposed on the first side of the module and the second side of the module.

3. The module of claim 1, further comprising: a first plurality of data buffer devices coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface; and a second plurality of data buffer devices coupled with the second memory channel interface and the second plurality of DRAM packages to communicate data between the second plurality of DRAM packages and the second memory channel interface.

4. The module of claim 1, wherein the first RCD device is further coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface, and the second RCD device is further coupled with the second memory channel interface and the second plurality of DRAM packages to communicate data between the second plurality of DRAM packages and the second memory channel interface.

5. The module of claim 1, wherein accesses directed to a first memory rank of the first memory channel interface access a respective single die in each of the first plurality of DRAM packages and accesses directed to a second memory rank of the second memory channel interface access a respective single die in each of the second plurality of DRAM packages.

6. The module of claim 4, wherein the first memory channel interface has a third plurality of CA signals and the second memory channel interface has a fourth plurality of CA signals.

7. The module of claim 6, wherein the first RCD device is further coupled with the first memory channel interface to further generate a plurality of buffered versions of the third plurality of CA signals to be provided to the unique subsets of a first plurality of DRAM device packages disposed on the module, and the second RCD device is further coupled with the second memory channel interface to further generate a plurality of buffered versions ofthe fourth plurality of CA signals to be provided to the unique subsets of a second plurality of DRAM device packages disposed on the module.

8. The module of claim 7, wherein the first RCD device is to time multiplex and time demultiplex data communicated between the first plurality of DRAM packages and the first memory channel interface, and the second RCD device is to time multiplex and time demultiplex data communicated between the second plurality of DRAM packages and the second memory channel interface.

9. A module, comprising: a plurality of memory channel interfaces that each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the plurality of memory channel interfaces; at least one registering clock driver (RCD) device coupled with at least one of the plurality of memory channel interfaces to at least generate a plurality of buffered versions of a plurality of CA signals of the at least one of the plurality of memory channel interfaces to be provided to respective unique subsets of a plurality of dynamic random access memory (DRAM) device packages disposed on the module; the at least one RCD device being disposed on a first side of the module and being adjacent on at least three respective sides to at least three respective ones of the plurality of DRAM device packages disposed on the first side of the module; and a number of memory ranks accessed via respective accesses via plurality of memory channel interfaces being determined by a number of DRAM die stacked in each of the plurality of DRAM device packages.

10. The module of claim 9, wherein an equal number of the plurality of DRAM device packages are disposed on the first side of the module and a second side of the module.

11. The module of claim 9, further comprising: a plurality of data buffer devices coupled with the plurality of memory channel interfaces and the plurality of DRAM packages to communicate data betweenthe plurality of DRAM packages and the a plurality of memory channel interfaces.

12. The module of claim 9, wherein the at least one RCD device is further coupled with the plurality of memory channel interfaces and the plurality of DRAM packages to communicate data between the plurality of DRAM packages and the plurality of memory channel interfaces.

13. The module of claim 9, wherein accesses directed to respective memory ranks of respective ones of the plurality of memory channel interfaces access respective single dies in a subsets of the plurality of DRAM packages corresponding to each of the respective ones of plurality of memory channel interfaces.

14. The module of claim 13, wherein the plurality of memory channel interfaces each have a plurality of CA signal groups that access a same subset of the plurality of DRAM packages.

15. The module of claim 14, wherein the at least one RCD device is to time multiplex and time demultiplex data communicated between at least one subset of the plurality of DRAM packages and a corresponding one of the plurality of memory channel interfaces.

16. A module, comprising: a first plurality of dynamic random access memory (DRAM) device packages; a first RCD device disposed on a first side of the module and disposed adjacent on three respective sides of the first RCD device to a subset of the first plurality of DRAM device packages that are also disposed on the first side of the module; a plurality of memory channel interfaces that each include command, address, and data transfer functions that operate independently of the command, address, and data transfer function of the other of the plurality of memory channel interfaces, the plurality of memory channel interfaces including a first memory channel interface coupled with the first RCD device; and the first RCD device to at least generate a plurality of buffered versions of a first plurality of command / address (CA) signals of the first memory channel interface that are to be provided to the first plurality of DRAM devicepackages, where accesses using the first plurality of CA signals of the first memory channel interface during a single access transaction are to not access more than one DRAM die that is stacked within the first plurality of DRAM device packages.

17. The module of claim 16, wherein an equal number of the first plurality of DRAM device packages are disposed on the first side of the module and a second side of the module that is opposite of the first side of the module.

18. The module of claim 16, further comprising: a first plurality of data buffer devices coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface.

19. The module of claim 16, wherein the first RCD device is further coupled with the first memory channel interface and the first plurality of DRAM packages to communicate data between the first plurality of DRAM packages and the first memory channel interface.

20. The module of claim 16, wherein the first memory channel interface includes a second plurality of CA signals and the first RCD device is to further generate a plurality of buffered versions of a second plurality of CA signals of the first memory channel interface that are to be provided to the first plurality of DRAM device packages.

Images