High current-sharing accuracy and high dynamic constant on-time control system and method for multiphase buck converter

Abstract

Disclosed in the present invention is a high current-sharing accuracy and high dynamic constant on-time (COT) control system and method for a multiphase Buck converter. The system comprises an analog main control loop, an all-digital steady-state current-sharing loop, a high-performance PWM control module, and a high-precision on-time generation module. According to the present invention, a high current-sharing accuracy and high dynamic COT control method is used, improving the multiphase PWM overlapping capability of a VRM during load transients, reducing an output voltage undershoot, ensuring precise dynamic current sharing and output voltage stability during the load transients, and facilitating adaptation to high-frequency load transient scenarios of 100 KHz and above. The all-digital steady-state current-sharing loop uses Sigma-delta modulation technology and, in combination with a hybrid high-resolution DPWM in the high-precision on-time generation module, reduces a system requirement for high bandwidth in the steady-state current-sharing loop, thereby reducing the dependency of a COT-controlled multiphase digital power supply on a high-speed multiplexed ADC, reducing the volume of a circuit, and lowering chip costs.

Description

High current sharing and high dynamic constant on-time control system and method for multiphase buck TECHNICAL FIELD

[0001] The present application belongs to the field of switching power supply, and particularly relates to a high current sharing and high dynamic constant on-time control system and method for multiphase Buck. BACKGROUND

[0002] With the development of 5G / 6G data communication, artificial intelligence, high-performance computing and other technologies, CPUs and AI chips need to have more powerful computing power and execute more complex methods, which poses a series of challenges to the front-end voltage regulation module (VRM): 1. VRM needs to cope with low-voltage and large-current application scenarios; 2. VRM needs to ensure high conversion efficiency in a wide load current range; 3. VRM needs to have fast load response performance to reduce output voltage overshoot / undershoot; 4. VRM needs to maintain stable working state under high-frequency load shedding.

[0003] For low-voltage and large-current application scenarios, multiphase Buck converter is the first choice of topology, which reduces the current stress of each phase and reduces the size of input / output capacitors through ripple interleaving cancellation. In order to ensure high conversion efficiency in a wide load range, the multiphase power controller generally adopts APS (Auto Phase Shedding) strategy, that is, the number of active phases of VRM is determined according to the current load current. In addition, further improving the transient performance is also the main consideration factor of current VRM design. The multiphase product MP2882 based on COT (Constant On-time) control reaches the maximum duty cycle during load transient, where blank_time is the minimum interval of each phase PWM trigger signal, and phase_number is the current working phase number of VRM. The disadvantage of this method is that there is a compromise between loop stability and transient performance, and VRM strictly follows phase interleaving during transient, so more phase numbers cannot further improve the dynamic. Another multiphase controller product ISL68227 of Renesas uniformly pulls up each phase PWM during load transient to minimize output voltage undershoot, but this method is easy to cause inductance current uneven during transient and output voltage ringback and other problems. During CPU high-frequency load shedding, transient current unevenness will cause the current deviation of each phase to become larger and larger, eventually triggering overcurrent protection and even damaging the device, and ringback will cause output voltage oscillation.

[0004] In summary, for the application scenario of high-frequency load shedding, multiphase Buck VRM must consider high dynamic performance, dynamic current sharing and output voltage stability. SUMMARY

[0005] The application aims to provide a high-current-sharing high-dynamic constant conduction time control system and method for a multi-phase Buck, so as to solve the technical problem that a multi-phase converter must consider high dynamic performance, dynamic current sharing and output voltage stability.

[0006] To solve the above technical problem, the application provides a high-current-sharing high-dynamic constant conduction time control system for a multi-phase Buck in a first aspect, which comprises an analog main control loop, a full-digital steady-state current sharing loop, a high-performance PWM (Pulse Width Modulation) control module and a high-precision conduction time generation module.

[0007] The input end of the analog main control loop is connected with the output end of a voltage sampling module and a current sampling module respectively, the output end of the analog main control loop is connected with the input end of the high-performance PWM control module, which is used to amplify the difference between a reference voltage and the output feedback voltage of the voltage sampling module to obtain an error signal, and then compare the error signal, a total inductance current signal output by the current sampling module and a slope compensation signal through a high-speed high-precision comparator to obtain a main loop control signal SET.

[0008] The input end of the full-digital steady-state current sharing loop is connected with the output end of the current sampling module, and the output end is connected with the input end of the high-precision conduction time generation module; the full-digital steady-state current sharing loop calculates the error of the current of each phase (the MOS switch and the output inductance in parallel in the multi-phase Buck topology are called an independent phase) and the average current and makes proportional integral PI (Proportion and Integration) compensation, the compensation signal is processed by a Sigma-delta modulator and sent to a high-precision DPWM (Digital Pulse Width Modulator) in the high-precision conduction time generation module, which is used to fine-tune the high-level width of each phase PWM to realize accurate steady-state current sharing effect.

[0009] The input end of the high-performance PWM control module is connected with the output end of the analog main control loop and the full-digital steady-state current sharing loop respectively, and the output end is connected with the input end of the high-precision conduction time generation module; the high-performance PWM control module is responsible for distributing the PWM trigger signals of each phase to realize phase interleaving during the steady state; the high-performance PWM control module is responsible for generating more intensive PWM trigger signals during the load transient state; the high-performance PWM control module suspends the generation of PWM trigger signals to improve dynamic performance during the unloading transient state; and the high-performance PWM control module truncates or skips the subsequent PWM of the phase with excessively large inductance current increment during the transient state after the load transient state ends to improve the dynamic current sharing effect.

[0010] The input end of the high-precision conduction time generation module is connected with the output end of the all-digital steady-state current sharing loop and the high-performance PWM control module respectively, and the output end is connected with the driving module; the high-precision conduction time generation module comprises a Ton coarse adjustment counter, a Ton fine adjustment delay chain and an SR flip-flop shared by each phase, the output end of the Ton coarse adjustment counter is connected with the input end of the Ton fine adjustment delay chain through a DLL (Delay Locked Line) multiplexing arbitrator, and the output end of the Ton fine adjustment delay chain is connected with the input end of the SR flip-flop, so as to realize the high-precision PWM regulation function.

[0011] The application further discloses a high-current-sharing high-dynamic constant conduction time control method for a multi-phase Buck, characterized by comprising the following steps.

[0012] Step 1, when the load current is greatly increased to make the main loop control signal SET high, the multi-phase Buck enters a transient enhancement mode after the length of the high level of the SET signal is detected to exceed a threshold value flag_count_long for the first time, each phase enters a turbo current acceleration state at intervals of a parameter flag_count_short, and the inductance current is accelerated in the turbo state without needing to comply with the phase interleaving principle;

[0013] Step 2, after the inductance current exceeds the load current, the SET signal is pulled low by the analog main control loop, the high-performance PWM control module records the number of times of turning on each phase during the load transient state and stores the number of times in an array times [0: phasenum-1], phasenum is the number of working phases of the multi-phase Buck converter, and the minimum value and the maximum value of the array elements are time_min and time_max respectively; for any kth (1≤k≤phasenum) phase, if times [k-1] = times_min, it represents that the number of times of turning on the phase during the load transient state is less, and the converter exits the transient enhancement mode and preferentially turns on the phase, that is, the phase interleaving is restored from the kth phase as the starting point, if times [i-1] = times [i]... = times [j-1] = times_min (i <j) occurs, the ith phase is selected as the starting point of the phase interleaving after the converter exits the transient enhancement mode, and for any kth phase, if times [k-1] = times_max ≥ (times_min+2), it represents that the number of times of turning on the phase during the load transient state is more, and the subsequent steady-state PWM of the phase needs to be truncated or skipped after the converter exits the transient enhancement mode, so as to achieve a better dynamic current sharing effect.

[0014] Step 3, if the duration of the high level of the subsequent SET signal again exceeds the threshold value flag_count_long, the transformer sequentially pulls up the PWM of each phase with the parameter flag_count_medium as the interval under the premise of ensuring phase staggering, and the increasing speed of the inductor current tends to be stable, so as to realize the smooth transition from the transient enhancement mode to the steady state mode; if the duration of the high level of the subsequent SET signal no longer exceeds the threshold value flag_count_long, directly enter step 4;

[0015] Step 4, the SET signal is no longer pulled up for a long time, indicating that the transition process from the transient enhancement mode to the steady state mode is over, and the transformer returns to the steady state mode, and the PWM of each phase is sequentially pulled up with the rising edge of the SET signal as the reference;

[0016] The parameters satisfy the following requirements: flag_count_short < flag_count_medium < flag_count_long.

[0017] Further, the truncation processing of the subsequent steady state PWM of the phase which is turned on more times during the loading transient period includes the following steps:

[0018] When the SET signal is pulled down, if the PWM of the kth phase is high and times[k-1] >= (times_min+2), the PWM of the kth phase is immediately pulled down, and the on-time count value in the DPWM is stored, recorded as extra, and when the kth phase is turned on again after the multi-phase Buck converter exits the transient enhancement mode, the new conduction time is obtained by subtracting extra from the original conduction time Ton, and the PWM high level pulse with the corresponding width is generated.

[0019] Further, the skipping processing of the subsequent steady state PWM of the phase which is turned on more times during the loading transient period includes the following steps:

[0020] When the SET signal is pulled down, if the PWM of the kth phase is low and times[k-1] >= (times_min+2), it indicates that the kth phase has opened twice or more than twice than the phase with the least opening times in the transient enhancement mode, and when the kth phase is turned on again after the multi-phase Buck converter exits the transient enhancement mode, the kth phase is directly pulled up.

[0021] The high uniform current high dynamic constant conduction time control system and method for the multi-phase Buck of the application have the following beneficial effects:

[0022] (1) The application adopts a high-current uniformity high-dynamic COT control method, compared with a traditional COT control method (such as CMCOT Control of MPS and D-CAP+ of TI), the multi-phase PWM overlap ability of the VRM under a load transient is improved, the output voltage undershoot is reduced, and the accurate dynamic current uniformity and output voltage stability during the load transient can be ensured, so as to facilitate coping with a high-frequency load switching scene of 100KHz and above.

[0023] (2) The all-digital steady-state current uniformity loop utilizes a Sigma-delta modulation technology, cooperates with a mixed high-precision DPWM in the on-time generation module, can reduce the high-bandwidth demand of the steady-state current uniformity loop of the system, and then reduces the dependence of the COT control multi-phase digital power supply on a high-speed multiplexing ADC, reduces the circuit volume, reduces the chip cost, and has high universality.

[0024] (3) The application adopts a digital-analog hybrid control scheme, in the control system, except that the analog main control loop is an analog circuit, other digital circuits such as the all-digital steady-state current uniformity loop and the high-performance PWM control module are digital circuits, compared with the existing pure analog control scheme, the degree of intelligence and module is higher, the parameters of the digital controller can be configured by the user, and high flexibility is obtained.

[0025] (4) The application adopts a high-current uniformity high-dynamic COT control method, the phase interleaving between the phases is broken during the load transient, therefore, the transient performance of the converter can be improved along with the increase of the working phase number of the VRM, and has good application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0026] Fig. 1 is a high-current uniformity high-dynamic constant on-time control system block diagram for a multi-phase Buck provided by the application;

[0027] Fig. 2 is a specific design diagram of a high-precision Ton generation module provided by the application;

[0028] Fig. 3 is a waveform schematic diagram of a high-current uniformity high-dynamic constant on-time control method for a multi-phase Buck provided by the application;

[0029] Fig. 4 is a principle diagram in which the high-current uniformity high-dynamic method improves the output voltage stability;

[0030] Fig. 5 is a SIMPLIS simulation waveform diagram of a traditional CMCOT control system in the application of a 12-phase Buck power supply;

[0031] Fig. 6(a) is a SIMPLIS simulation waveform diagram of the system of the embodiment of the application before the output voltage stability is optimized in the application of a 12-phase Buck power supply;

[0032] Figure 6(b) is a SIMPLIS simulation waveform diagram of the system of the embodiment of the application in 12-phase Buck power supply application after optimization of output voltage stability. DETAILED DESCRIPTION

[0033] In order to better understand the purposes, structures and functions of the present application, the high uniform current high dynamic constant conduction time control system and method for multi-phase Buck provided by the present application will be described in further detail below with reference to the accompanying drawings.

[0034] Figure 1 is a block diagram of the high uniform current high dynamic constant conduction time control system for multi-phase Buck provided by the present application. The control system mainly includes an analog main control loop, a full-digital steady-state uniform current loop, a high-performance PWM control module and a high-precision conduction time generation module. The analog main control loop is mainly responsible for the stability of the steady-state output voltage of the VRM, the full-digital steady-state uniform current loop and the high-precision conduction time generation module are mainly responsible for the improvement of the steady-state uniform current accuracy, and the high-performance PWM control module is mainly responsible for the improvement of the dynamic response of the VRM, while ensuring accurate dynamic uniform current and dynamic voltage stability.

[0035] The input end of the analog main control loop is connected with the output end of the voltage sampling module and the current sampling module respectively, and the output end of the analog main control loop is connected with the input end of the high-performance PWM control module, for amplifying the difference between the reference voltage and the output feedback voltage of the voltage sampling module to obtain an error signal, and comparing the error signal, the total inductance current signal of the current sampling module and a slope compensation signal through a high-speed high-precision comparator to obtain a main loop control signal SET.

[0036] The input end of the full-digital steady-state uniform current loop is connected with the output end of the current sampling module, and the output end is connected with the input end of the high-precision conduction time generation module. The full-digital steady-state uniform current loop calculates the error of the current of each phase (the MOS switch and the output inductor in parallel in the multi-phase Buck topology are called an independent phase) and the average current and makes PI (Proportion and Integration) compensation. The compensation signal is processed by a Sigma-delta modulator and sent to the high-precision DPWM (Digital Pulse Width Modulator) in the high-precision conduction time generation module, for fine-tuning the high-level width of each phase PWM, so as to realize accurate steady-state uniform current effect.

[0037] The input end of the high-performance PWM control module is connected with the output end of the analog main control loop and the full-digital steady-state current sharing loop respectively, and the output end is connected with the input end of the high-precision on-time generation module. The main functions of the module are: (1) during the steady state, responsible for distributing the PWM trigger signals of each phase to realize phase stagger; (2) during the transient state, responsible for generating more dense (loading transient) or sparse (unloading transient) PWM trigger signals to improve the dynamic performance; (3) after the loading transient ends, cutting off or skipping the subsequent PWM of the phase whose upper tube (referring to the MOS tube connected with the input voltage in the Buck topology) opens too many times during the transient state to improve the dynamic current sharing effect.

[0038] The input end of the high-precision on-time generation module is connected with the output end of the full-digital steady-state current sharing loop and the high-performance PWM control module respectively, and the output end is connected with the driving module. The module includes a Ton coarse adjustment counter, a Ton fine adjustment delay chain shared by each phase, and an SR flip-flop independent of each phase. The output end of the Ton coarse adjustment counter is connected with the input end of the delay chain after passing through a DLL (Delay Locked Line) multiplexing arbitrator, and the output end of the Ton fine adjustment delay chain is connected with the input end of the SR flip-flop, so as to realize the high-precision PWM regulation function.

[0039] Fig. 2 is a specific design diagram of the high-precision on-time generation module provided by the application, which includes a Ton coarse adjustment counter independent of each phase, a Ton fine adjustment delay chain shared by each phase, and an SR flip-flop independent of each phase. The output end of the Ton coarse adjustment counter is connected with the input end of the delay chain after passing through a DLL multiplexing arbitrator, and the output end of the Ton fine adjustment delay chain is connected with the input end of the SR flip-flop. The 10-bit signals on-time1-on-time12 output by the full-digital steady-state current sharing loop are used as the input signals of the high-precision Ton generation module. The 7-bit high signals are sent to the counter to generate a coarse adjustment Ton pulse, and the 3-bit low signals are sent to the delay chain to generate a fine adjustment Ton pulse. Finally, the PWM signals of each phase are obtained through the integration of the SR flip-flop.

[0040] Fig. 3 is a waveform schematic diagram of the high-current-sharing high-dynamic constant on-time control method for the multi-phase Buck provided by the application, and the method is described in more detail with reference to the diagram.

[0041] After the load is greatly increased, the main loop control signal SET is pulled high, and the rising edge triggers a high-level pulse of flag. At this time, the next phase PWM is still pulled high in accordance with the phase distribution phase stagger sequence.

[0042] When the SET signal is detected to be high for more than the threshold value flag_count_long, the controller enters the transient enhancement mode from the steady state control mode. In the transient enhancement mode, the generation of the flag high level pulse (i.e. the flag1-flag12 pulse in FIG. 1) is no longer dependent on the rising edge of the SET signal, but is emitted at a fixed frequency with the parameter flag_count_short as an interval. Each phase enters the turbo state in turn based on the pulse, and in the turbo state, each phase PWM is no longer controlled by the flag signal, but works at a fixed frequency with the minimum off time (for DRMOS safety and output voltage ripple considerations) to reduce the output voltage undershoot as much as possible. To ensure loop stability and avoid sub-harmonic oscillation, the parameter flag_count_long is generally set to a large value; to achieve better dynamic performance, the parameter flag_count_short is generally set to a small value. Obviously, this method breaks the compromise between stability and dynamic performance in traditional multi-phase COT control.

[0043] In the turbo state, each phase PWM is no longer controlled by the flag pulse sequential counting, i.e. the phase staggering between phases is broken, which further leads to the problem that the number of times of turning on the upper tube of each phase is uneven, and the current increment during the dynamic period is different. To improve the dynamic current sharing effect of this method, the following two measures are taken after the SET signal is pulled low: 1. For the phase with a small number of times of turning on the upper tube during the loading transient period, the controller resumes the phase staggering by preferentially counting sequentially from this phase as the starting point after exiting the transient enhancement mode; 2. For the phase with a large number of times of turning on the upper tube during the loading transient period, the controller performs truncation / skipping processing on the subsequent steady state PWM after exiting the transient enhancement mode, and the specific operation is as follows.

[0044] The high-performance PWM control module records the on-time of each phase during the load transient and stores it in the array times[0:phasenum-1], phasenum is the number of working phases of the multi-phase Buck converter, and the minimum and maximum values of the array elements are time_min and time_max, respectively. For any kth(1≤k≤phasenum) phase, if times[k-1]=times_min, it represents that the on-time of the phase during the load transient is less, and the converter exits the transient enhancement mode and preferentially turns on this phase, i.e., the kth phase is taken as the starting point to restore the phase interleaving, and if times[i-1]=times[i]...=times[j-1]=times_min(i<j) occurs, the ith phase is selected as the starting point of the phase interleaving after the converter exits the transient enhancement mode; for any kth phase, if times[k-1]=times_max≥(times_min+2), it represents that the on-time of the phase during the load transient is more, and the converter exits the transient enhancement mode and needs to perform truncation or skipping processing on the subsequent steady-state PWM of the phase, referring to the shaded part of FIG. 3.

[0045] The specific operation of the truncated PWM is that when the SET signal is pulled low, if the kth phase PWM is high and times[k-1]≥(times_min+2), the PWM of the phase is immediately pulled low, and the on-time count value in the DPWM is stored, denoted as extra, when the kth phase is turned on again after the converter exits the transient enhancement mode, the new conduction time is obtained by subtracting extra from the original conduction time Ton, and the PWM high-level pulse with the corresponding width is generated; the specific operation of the skipped PWM is that when the SET signal is pulled low, if the kth phase PWM is low and times[k-1]≥(times_min+2), it is indicated that the kth phase has opened twice or more than twice than the phase with the least on-time in the transient enhancement mode, when the kth phase is turned on again after the converter exits the transient enhancement mode, the kth+1 phase PWM is directly pulled high.

[0046] FIG. 4 is a principle diagram for improving the stability of the output voltage by the high-average-current high-dynamic method, the essence of the above high-average-current high-dynamic COT method is still a nonlinear transient enhancement method, and there are inherent problems of the nonlinear method: the output voltage ringing caused by over-regulation and the difficulty in achieving smooth transition between linear / nonlinear modes. If the values of flag_count_short and Toff_min are small, the voltage loop gain is large, the bandwidth of the above method is high, and the inductor current is easily over-regulated, which causes the VRM to switch between the transient enhancement mode and the steady-state mode multiple times before it stabilizes.

[0047] The application further divides the loading response process of the VRM into a nonlinear stage, a transition stage and a steady state stage to improve the dynamic stability of the method. After the load current increases greatly, the comparator output SET signal is pulled high for the first time for a long time, at which time the VRM enters the nonlinear stage, the high dynamic COT method is used to quickly increase the inductance current of each phase and improve the response speed. When the SET signal is pulled high for a long time again subsequently, the difference between the total inductance current and the load current is not large, the VRM enters the transition stage, each phase keeps phase interleaving in this stage, the flag pulse interval is flag_count_medium (flag_count_short < flag_count_medium < flag_count_long), the inductance current increasing speed tends to be stable, and the smooth transition between the nonlinear enhancement method and the steady state linear method is facilitated. Finally, the VRM enters the steady state working mode, the SET signal is no longer pulled high for a long time, the traditional CMCOT control is restored, and the loading transient response process ends.

[0048] Figure 5 is a SIMPLIS simulation waveform diagram of the traditional CMCOT control system in the application of a 12-phase Buck power supply, the load shedding rate is 1000A / us, the load shedding frequency is 100KHz, and the output voltage undershoot amplitude is 80mv.

[0049] Figure 6 is a SIMPLIS simulation waveform diagram of the system according to the embodiment of the application in the application of a 12-phase Buck power supply, and Figures 6(a) and 6(b) are simulation waveform diagrams before / after the output voltage stability optimization. It can be seen that the voltage undershoot amplitude is improved from 80mv of the traditional COT control to 45mv, and the VRM working state can still remain stable under repeated load shedding, and there is almost no voltage ringing phenomenon, which proves that the method of the application can greatly improve the transient performance of the COT control under the premise of ensuring accurate dynamic current sharing and output voltage stability, and effectively improve the output voltage undershoot.

[0050] It can be understood that the application is described through some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the application. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the application without departing from the spirit and scope of the application. Therefore, the application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the application are within the scope of the application.

Claims

1. A high current sharing high dynamic constant conduction time control system for multiphase buck, characterized in that, It comprises an analog main control loop, a full-digital steady-state current sharing loop, a high-performance PWM (pulse width modulation) control module and a high-precision on-time generation module; The input end of the analog main control loop is connected with the output end of a voltage sampling module and a current sampling module respectively, and the output end of the analog main control loop is connected with the input end of the high-performance PWM control module, which is used to amplify the difference between a reference voltage and the output feedback voltage of the voltage sampling module to obtain an error signal, and then compare the error signal, the total inductance current signal output by the current sampling module and a slope compensation signal through a high-speed high-precision comparator to obtain a main loop control signal SET; The input end of the full-digital steady-state current sharing loop is connected with the output end of the current sampling module, and the output end is connected with the input end of the high-precision on-time generation module; the full-digital steady-state current sharing loop calculates the error of each phase current and average current and makes proportional integral PI compensation, and the compensation signal is processed by a Sigma-delta modulator and sent to a high-precision DPWM (digital pulse width modulator) in the high-precision on-time generation module, which is used to fine-tune the high-level width of each phase PWM; The input end of the high-performance PWM control module is connected with the output end of the analog main control loop and the full-digital steady-state current sharing loop respectively, and the output end is connected with the input end of the high-precision on-time generation module; the high-performance PWM control module is responsible for distributing each phase PWM trigger signal to realize phase interleaving during the steady state; the high-performance PWM control module is responsible for generating more intensive PWM trigger signals during the load transient state; the high-performance PWM control module suspends the generation of PWM trigger signals during the unloading transient state; and the high-performance PWM control module truncates or skips the subsequent PWM of the phase with excessively large inductance current increment after the end of the loading transient state; The input end of the high-precision on-time generation module is connected with the output end of the full-digital steady-state current sharing loop and the high-performance PWM control module respectively, and the output end is connected with a driving module; the high-precision on-time generation module comprises a Ton coarse adjustment counter, a Ton fine adjustment delay chain shared by each phase and an SR flip-flop, the output end of the Ton coarse adjustment counter is connected with the input end of the Ton fine adjustment delay chain through a DLL (delay chain) multiplexing arbitrator, and the output end of the Ton fine adjustment delay chain is connected with the input end of the SR flip-flop.

2. A transient algorithm for high dynamic constant on-time control system of multi-phase Buck with high current sharing for claim 1, characterized by, It comprises the following steps: Step 1, when the load current increases, the main loop control signal SET is pulled high, and when it is detected that the high-level duration first exceeds the threshold value flag_count_long, the multi-phase Buck enters a transient enhancement mode: each phase enters a turbo current acceleration state at intervals of a parameter flag_count_short, and in the turbo state, each phase PWM only needs to meet the minimum off-time requirement and does not need to comply with the phase interleaving principle; Step 2, after the inductor current exceeds the load current, the analog main control loop pulls down the SET signal, the high-performance PWM control module records the number of times each phase is turned on during the load transient and stores it in the array times[0:phasenum-1], phasenum is the number of working phases of the multi-phase Buck converter, and the minimum and maximum values of the array elements are time_min and time_max respectively; for any kth phase, where 1≤k≤phasenum, if times[k-1]=times_min, it represents that the number of times this phase is turned on during the load transient is small, and the multi-phase Buck converter exits the transient enhancement mode and preferentially turns on this phase, that is, the kth phase is taken as the starting point to restore phase interleaving; if times[i-1]=times[i]...=times[j-1]=times_min occurs, where i<j, the ith phase is selected as the starting point of phase interleaving after the multi-phase Buck converter exits the transient enhancement mode; for any kth phase, if times[k-1]=times_max≥(times_min+2), it represents that the number of times this phase is turned on during the load transient is large, and the multi-phase Buck converter needs to perform truncation or skipping processing on the subsequent steady-state PWM of this phase after exiting the transient enhancement mode; Step 3, if the duration of the subsequent SET signal high level again exceeds the threshold flag_count_long, the multi-phase Buck converter sequentially pulls up the PWM of each phase with the parameter flag_count_medium as the interval under the premise of ensuring phase interleaving, and the inductor current growth rate tends to be stable, so as to realize smooth transition from the transient enhancement mode to the steady-state mode; if the duration of the subsequent SET signal high level no longer exceeds the threshold flag_count_long, directly enter step 4; Step 4, the SET signal is no longer pulled high for a long time, indicating that the transition process from the transient enhancement mode to the steady-state mode is over, and the multi-phase Buck converter returns to the steady-state mode, and the PWM of each phase is sequentially pulled high with the rising edge of the SET signal as the reference; The parameters satisfy the following requirements: flag_count_short<flag_count_medium<flag_count_long.

3. A method for high current sharing and high dynamic constant on-time control system for multiphase Buck of claim 1, characterized by, The truncation processing performed on the subsequent steady-state PWM of the phase with a large number of times during the load transient includes the following steps: When the SET signal is pulled down, if the kth phase PWM is high and times[k-1]≥(times_min+2), the PWM of this phase is immediately pulled down and the on-time count value in DPWM is stored, denoted as extra, when the kth phase is turned on again after the multi-phase Buck converter exits the transient enhancement mode, the new conduction time is obtained by subtracting extra from the original conduction time Ton, and the PWM high level pulse with the corresponding width is generated.

4. A method for high current sharing and high dynamic constant on-time control system for multiphase Buck of claim 1, characterized by, The skipping processing performed on the subsequent steady-state PWM of the phase with a large number of times during the load transient includes the following steps: When the SET signal is pulled low, if the kth-phase PWM is low and times[k-1]≥(times_min+2), it indicates that the kth-phase has the least number of on times in the transient enhancement mode, and the kth-phase has turned on twice or more than twice. When the kth-phase turns on again after the multi-phase Buck converter exits the transient enhancement mode, the kth-phase skips this time of turning on and directly pulls up the PWM of the k+1th-phase.

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