Passive electronic component and method for manufacturing passive electronic component

Abstract

A passive electronic component 1 includes: a semiconductor substrate 10; an insulating layer 15 provided on one main surface of the semiconductor substrate 10; and a first capacitor 21 and a second capacitor 22 respectively arranged in a first region and a second region on the insulating layer 15. The first capacitor 21 and the second capacitor 22 are MIM type capacitors each including a laminated structure of an internal electrode layer-dielectric film-internal electrode layer in a thickness direction of the semiconductor substrate 10. At least one dielectric film of the same type as the dielectric film contained between the internal electrode layers of the first capacitor 21 is disposed between the insulating layer 15 and the internal electrode layer of the second capacitor 22 that is closest to the semiconductor substrate 10.

Description

Passive electronic component and method for manufacturing the passive electronic component

[0001] The present invention relates to a passive electronic component and a method for manufacturing a passive electronic component.

[0002] Patent Document 1 discloses an electronic component having a plurality of conductor layers stacked on a substrate, the electronic component having a first capacitor formed by two of the plurality of conductor layers adjacent in the stacking direction and a dielectric film located between them, and a second capacitor formed by two of the plurality of conductor layers adjacent in the stacking direction and a dielectric film located between them, wherein the thicknesses of the dielectric film constituting the first capacitor and the dielectric film constituting the second capacitor are different from each other.

[0003] Japanese Patent Application Laid-Open No. 2022-130066

[0004] In the electronic component described in Patent Document 1, a plurality of capacitors having a metal-insulator-metal (MIM) structure are arranged on the same chip.

[0005] In such MIM type capacitors, the higher the Q value, which is the reciprocal of the dielectric loss, the smaller the power loss, while the lower the Q value, the larger the power loss.

[0006] One of the factors that reduces the Q value of a capacitor is the parasitic capacitance that occurs between electrodes in an MIM structure. This parasitic capacitance is mainly generated via the conductivity of a semiconductor substrate such as a silicon substrate. When multiple capacitors are arranged on the same chip, as in the electronic component described in Patent Document 1, the parasitic capacitance due to the semiconductor substrate is constant regardless of the capacitance of the capacitors, so the lower the capacitance of the capacitor, the greater the impact of the parasitic capacitance.

[0007] In order to reduce the influence of parasitic capacitance due to the semiconductor substrate, it is common to increase the resistance of the semiconductor substrate itself and to thicken the insulating layer provided between the semiconductor substrate and the electrode. However, forming a thick insulating layer raises the problem of increased costs for the film formation and etching steps in the manufacturing process.

[0008] The present invention has been made to solve the above problems, and has an object to provide a passive electronic component in which the parasitic capacitance due to the semiconductor substrate is reduced and which has a high Q characteristic. Another object of the present invention is to provide a method for manufacturing a passive electronic component in which the parasitic capacitance due to the semiconductor substrate is reduced and which has a high Q characteristic without increasing the number of manufacturing steps or costs.

[0009] The passive electronic component of the present invention comprises a semiconductor substrate, an insulating layer provided on one main surface of the semiconductor substrate, and a first capacitor and a second capacitor respectively disposed in a first region and a second region on the insulating layer. The first capacitor and the second capacitor are each an MIM type capacitor having a laminated structure of an internal electrode layer-a dielectric film-an internal electrode layer in the thickness direction of the semiconductor substrate. At least one dielectric film of the same type as the dielectric film included between the internal electrode layers of the first capacitor is disposed between the internal electrode layer of the second capacitor that is closest to the semiconductor substrate and the insulating layer.

[0010] A method for manufacturing a passive electronic component of the present invention includes the steps of preparing a semiconductor substrate having an insulating layer on one main surface thereof, and forming a first capacitor and a second capacitor in a first region and a second region on the insulating layer, respectively. The first capacitor and the second capacitor are each an MIM type capacitor having an internal electrode layer-dielectric film-internal electrode layer laminated structure in the thickness direction of the semiconductor substrate. At least one dielectric film of the same type as the dielectric film included between the internal electrode layers of the first capacitor is formed between the internal electrode layer of the second capacitor that is closest to the semiconductor substrate and the insulating layer.

[0011] According to the present invention, it is possible to provide a passive electronic component in which the parasitic capacitance due to the semiconductor substrate is reduced and which has a high Q characteristic. Furthermore, according to the present invention, it is possible to provide a method for manufacturing a passive electronic component in which the parasitic capacitance due to the semiconductor substrate is reduced and which has a high Q characteristic without increasing the number of manufacturing steps or costs.

[0012] FIG. 1 is a plan view schematically showing an example of a passive electronic component according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 1 taken along line A-A'. FIG. 3 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 1 taken along line B-B'. FIG. 4 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 1 taken along line X-X'. FIG. 5 is a plan view schematically showing an example of a passive electronic component according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 5 taken along line A-A'. FIG. 7 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 5 taken along line B-B'. FIG. 8 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 5 taken along line X-X'. FIG. 9 is a plan view schematically showing an example of a passive electronic component according to a third embodiment of the present invention. FIG. 10 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 9 taken along line A-A'. FIG. 11 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 9 taken along line B-B'. FIG. 12 is a plan view schematically showing an example of a passive electronic component according to a fourth embodiment of the present invention. FIG. 13 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 12 taken along line A-A'. FIG. 14 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 12 taken along line B-B'. FIG. 15 is a plan view schematically showing an example of a passive electronic component according to a fifth embodiment of the present invention. FIG. 16 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 15 taken along line A-A'. FIG. 17 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in FIG. 15 taken along line B-B'. Fig. 18 is a cross-sectional view schematically showing an example of a cross section along line CC' of the passive electronic component shown in Fig. 15. Fig. 19 is a plan view schematically showing an example of a passive electronic component according to a sixth embodiment of the present invention. Fig. 20 is a cross-sectional view schematically showing an example of a cross section along line AA' of the passive electronic component shown in Fig. 19. Fig. 21 is a cross-sectional view schematically showing an example of a cross section along line BB' of the passive electronic component shown in Fig. 19. Fig. 22 is a cross-sectional view schematically showing a step of preparing a semiconductor substrate in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.FIG. 23 is a cross-sectional view schematically showing a step of forming a charge trap layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 24 is a cross-sectional view schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 25 is a cross-sectional view schematically showing a step of patterning an insulating layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 26 is a cross-sectional view schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 27 is a cross-sectional view schematically showing a step of patterning a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 28 is a cross-sectional view schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 29 is a cross-sectional view schematically showing a step of patterning the first dielectric film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 30 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 31 is a cross-sectional view schematically showing a step of patterning a second internal electrode layer in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention. FIG. 32 is a cross-sectional view schematically showing a step of forming a second dielectric film in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention. FIG. 33 is a cross-sectional view schematically showing a step of patterning the second dielectric film in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention. FIG. 34 is a cross-sectional view schematically showing a step of forming a third internal electrode layer in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention. FIG. 35 is a cross-sectional view schematically showing a step of patterning a third internal electrode layer in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention. FIG. 36 is a cross-sectional view schematically showing a step of forming a protective film in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention. FIG. 37 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a manufacturing method for a passive electronic component according to the first embodiment of the present invention.FIG. 38 is a cross-sectional view schematically showing a step of preparing a semiconductor substrate in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 39 is a cross-sectional view schematically showing a step of forming a charge trap layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 40 is a cross-sectional view schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 41 is a cross-sectional view schematically showing a step of patterning an insulating layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 42 is a cross-sectional view schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 43 is a cross-sectional view schematically showing a step of patterning a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 44 is a cross-sectional view schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 45 is a cross-sectional view schematically showing a step of patterning a first dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 46 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 47 is a cross-sectional view schematically showing a step of patterning a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 48 is a cross-sectional view schematically showing a step of forming a second dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 49 is a cross-sectional view schematically showing a step of patterning the second dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 50 is a cross-sectional view schematically showing a step of forming a third internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 51 is a cross-sectional view schematically showing a step of patterning a third internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. Fig. 52 is a cross-sectional view schematically showing a step of forming a third dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.FIG. 53 is a cross-sectional view schematically showing a step of patterning a third dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 54 is a cross-sectional view schematically showing a step of forming a fourth internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 55 is a cross-sectional view schematically showing a step of patterning a fourth internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 56 is a cross-sectional view schematically showing a step of forming a protective film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 57 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention. FIG. 58 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the sixth embodiment of the present invention. FIG. 59 is a cross-sectional view schematically showing a step of forming an inductor in an example of a method for manufacturing a passive electronic component according to the sixth embodiment of the present invention. FIG. 60 is a cross-sectional view schematically showing a step of forming another resin protective layer in an example of a method for manufacturing a passive electronic component according to the sixth embodiment of the present invention.

[0013] The passive electronic component of the present invention will be described below. Note that the present invention is not limited to the following configurations and may be modified as appropriate without departing from the spirit of the present invention. Furthermore, a combination of multiple individual preferred configurations described below also constitutes the present invention.

[0014] In the passive electronic component of the present invention, at least one dielectric film of the same type as the dielectric film between the internal electrode layers of the first capacitor is disposed between the insulating layer and the internal electrode layer of the second capacitor that is closest to the semiconductor substrate. This increases the distance between the semiconductor substrate and the second capacitor, thereby reducing the parasitic capacitance of the semiconductor substrate. As a result, the Q value of the second capacitor is increased, thereby reducing power loss.

[0015] In the past, when manufacturing passive electronic components with multiple MIM-type capacitors arranged on the same chip, unnecessary internal electrode layers and dielectric films were removed. In contrast, in the present invention, the unnecessary dielectric film is intentionally left unremoved and placed on the bottom layer of the second capacitor. This allows for a large distance between the semiconductor substrate and the second capacitor without forming a thick insulating layer on the semiconductor substrate. Therefore, it is possible to reduce the parasitic capacitance of the semiconductor substrate and manufacture passive electronic components with high Q characteristics without increasing the number of manufacturing steps or costs.

[0016] The following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, descriptions of matters common to the first embodiment will be omitted, and differences will be mainly described. In particular, similar effects resulting from similar configurations will not be mentioned one after the other for each embodiment.

[0017] In the following description, when there is no need to particularly distinguish between the embodiments, they will simply be referred to as "passive electronic components of the present invention."

[0018] In the following, an electronic component having a capacitor will be shown as an example of the passive electronic component of the present invention. The passive electronic component of the present invention may be a capacitor itself.

[0019] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, and other scales may differ from those of the actual product. In the drawings, the same or equivalent parts will be designated by the same reference numerals. In addition, the same elements will be designated by the same reference numerals in each drawing, and duplicate explanations will be omitted.

[0020] In this specification, unless otherwise specified, terms indicating the relationship between elements (e.g., "parallel," "perpendicular," "orthogonal," etc.) and terms indicating the shape of elements not only mean the strict literal aspects, but also mean a range that is substantially equivalent, for example, a range that includes a difference of about a few percent.

[0021] First Embodiment In a passive electronic component according to a first embodiment of the present invention, the number of stacked internal electrode layers in a first capacitor is 3. Furthermore, the internal electrode layer closest to the semiconductor substrate extends to the outside of the other internal electrode layers.

[0022] Fig. 1 is a plan view schematically showing an example of a passive electronic component according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in Fig. 1 taken along line A-A'. Fig. 3 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in Fig. 1 taken along line B-B'. Fig. 4 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in Fig. 1 taken along line XX'.

[0023] The passive electronic component 1 shown in FIG. 1 comprises a semiconductor substrate 10, an insulating layer 15 provided on one main surface (top surface in FIGS. 2 to 4) of the semiconductor substrate 10, and a first capacitor 21 (see FIGS. 2 and 4) and a second capacitor 22 (see FIGS. 3 and 4) arranged in a first region and a second region, respectively, on the insulating layer 15.

[0024] The first capacitor 21 and the second capacitor 22 are each an MIM type capacitor including a laminated structure of an internal electrode layer-dielectric film-internal electrode layer in the thickness direction of the semiconductor substrate 10 (the vertical direction in FIGS. 2 to 4).

[0025] The semiconductor substrate 10 is preferably made of silicon (Si), and more preferably made of single crystal silicon. That is, the semiconductor substrate 10 is preferably a silicon substrate, and more preferably a single crystal silicon substrate.

[0026] The resistivity of the semiconductor substrate 10 is preferably 3 kΩ·cm or more, and more preferably 5 kΩ·cm or more, while the resistivity of the semiconductor substrate 10 is, for example, 20 kΩ·cm or less.

[0027] When the semiconductor substrate 10 is a silicon substrate such as a single crystal silicon substrate, it may be a p-type silicon substrate or an n-type silicon substrate.

[0028] Although not shown in FIGS. 2 to 4, the passive electronic component 1 may further include a charge trapping layer made of polycrystalline silicon or amorphous silicon between the semiconductor substrate 10 and the insulating layer 15 .

[0029] The resistivity of the charge trapping layer is preferably equal to or higher than the resistivity of the semiconductor substrate 10 .

[0030] The insulating layer 15 may be provided so as to cover the entire one main surface of the semiconductor substrate 10, or may be provided so as to cover a part of the one main surface of the semiconductor substrate 10. As shown in Figures 2 and 3, the insulating layer 15 needs to be larger than the internal electrode layer closest to the semiconductor substrate 10 and to be provided in a region that overlaps the entire area of ​​the internal electrode layer closest to the semiconductor substrate 10.

[0031] The material for the insulating layer 15 is not particularly limited, but is preferably SiO ２ , SiN, Al ２ O ３ , HfO ２ , Ta ２ O ５ , ZrO ２ Examples of insulating materials include:

[0032] The first capacitor 21 shown in Figure 2 includes a first internal electrode layer 31, a first dielectric film 41 provided on the first internal electrode layer 31, a second internal electrode layer 32 provided on the first dielectric film 41, a second dielectric film 42 provided on the second internal electrode layer 32, and a third internal electrode layer 33 provided on the second dielectric film 42 and connected to the first internal electrode layer 31.

[0033] In the example shown in FIG. 2, the first internal electrode layer 31 which is the internal electrode layer closest to the semiconductor substrate 10 extends to the outside of the second internal electrode layer 32 and the third internal electrode layer 33 .

[0034] In the first capacitor 21, a first internal electrode layer 31, a first dielectric film 41, a second internal electrode layer 32, a second dielectric film 42, and a third internal electrode layer 33 are stacked in this order to form an MIM capacitor structure.

[0035] 2 , no dielectric film such as the first dielectric film 41 is disposed between the insulating layer 15 and the first internal electrode layer 31, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the first capacitor 21. Therefore, the first internal electrode layer 31, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the first capacitor 21, is disposed directly on the insulating layer 15.

[0036] The second capacitor 22 shown in FIG. 3 includes a second internal electrode layer 32, a second dielectric film 42 provided on the second internal electrode layer 32, and a third internal electrode layer 33 provided on the second dielectric film 42.

[0037] In the example shown in FIG. 3 , the second internal electrode layer 32 , which is the internal electrode layer closest to the semiconductor substrate 10 , extends to the outside of the third internal electrode layer 33 .

[0038] In the second capacitor 22, a second internal electrode layer 32, a second dielectric film 42, and a third internal electrode layer 33 are laminated in this order to form an MIM capacitor structure.

[0039] The number of stacked internal electrode layers in the second capacitor 22 is smaller than the number of stacked internal electrode layers in the first capacitor 21. Therefore, the capacitance of the second capacitor 22 is smaller than the capacitance of the first capacitor 21.

[0040] In the example shown in FIG. 3 , a first dielectric film 41 is disposed between the second internal electrode layer 32, which is the internal electrode layer of the second capacitor 22 that is closest to the semiconductor substrate 10, and the insulating layer 15.

[0041] By disposing the first dielectric film 41 in addition to the insulating layer 15 between the semiconductor substrate 10 and the second capacitor 22, the distance between the semiconductor substrate 10 and the second capacitor 22 increases, thereby reducing power loss due to parasitic capacitance occurring between the semiconductor substrate 10 and the internal electrode layer of the second capacitor 22.

[0042] The first dielectric film 41 formed between the semiconductor substrate 10 and the second capacitor 22 is unnecessary, and so has conventionally been removed by a process such as etching. In this process, not only the first dielectric film 41 but also part of the surface of the insulating layer 15 may be etched. This may increase the parasitic capacitance in the thinned portion of the insulating layer 15. Furthermore, variations in the thickness of the insulating layer 15 increase the variation in parasitic capacitance, which may degrade the capacitance accuracy of the second capacitor 22.

[0043] In contrast, in the present invention, the first dielectric film 41 formed between the semiconductor substrate 10 and the second capacitor 22 is not removed but is intentionally left as it is and is arranged as the bottom layer of the second capacitor 22. This makes it possible to reduce the parasitic capacitance caused by the semiconductor substrate 10 and manufacture a passive electronic component 1 with a high Q characteristic without increasing the number of manufacturing steps or costs.

[0044] The capacitance of the second capacitor 22 may be the same as the capacitance of the first capacitor 21 , but is preferably smaller than the capacitance of the first capacitor 21 .

[0045] The number of stacked internal electrode layers in the second capacitor 22 may be the same as the number of stacked internal electrode layers in the first capacitor 21 , but is preferably smaller than the number of stacked internal electrode layers in the first capacitor 21 .

[0046] The configuration of each capacitor will be described in detail below.

[0047] The first internal electrode layer 31 is preferably provided at a position away from the end of the semiconductor substrate 10. In other words, the end of the first internal electrode layer 31 is preferably located more inward than the end of the semiconductor substrate 10.

[0048] The material constituting the first internal electrode layer 31 is not particularly limited, but preferably includes conductive materials such as Cu, Ag, Au, Al, Ni, Cr, or Ti, or alloys containing at least one of these metals (e.g., AlSi, AlCu, AlSiCu, etc.). The same applies to materials constituting the internal electrode layers other than the first internal electrode layer 31.

[0049] In the first capacitor 21, the second internal electrode layer 32 is provided opposite the first internal electrode layer 31 with the first dielectric film 41 interposed therebetween.

[0050] In the first capacitor 21 and the second capacitor 22, the third internal electrode layer 33 is provided opposite the second internal electrode layer 32 with the second dielectric film 42 interposed therebetween.

[0051] In the first capacitor 21, the first dielectric film 41 is preferably provided so as to cover the first internal electrode layer 31 except for the opening. In the example shown in Fig. 2, the first dielectric film 41 is also provided on the insulating layer 15. The end of the first dielectric film 41 may or may not extend to the end of the semiconductor substrate 10.

[0052] The material for the first dielectric film 41 is not particularly limited, but is preferably SiO ２ , SiN, SiON, SiOC, SiOF, HfO ２ , HfSiO, Al ２ O ３ , Ta ２ O ５ The same applies to the materials constituting the dielectric films other than the first dielectric film 41.

[0053] In the first capacitor 21 and the second capacitor 22, the second dielectric film 42 is preferably provided so as to cover the second internal electrode layer 32 except for the opening. In the example shown in Figures 2 and 3, the second dielectric film 42 is also provided on the first dielectric film 41. The end of the second dielectric film 42 may or may not extend to the end of the semiconductor substrate 10.

[0054] As shown in FIGS. 2 to 4, a protective film (also called a moisture-resistant film) 50 may be provided on the second dielectric film 42 and on the third internal electrode layer 33 .

[0055] The protective film 50 is preferably provided so as to cover the second dielectric film 42 and the third internal electrode layer 33 except for the openings. The provision of the protective film 50 improves the moisture resistance of the first capacitor 21 and the second capacitor 22, particularly the electrode materials such as the internal electrode layers. The protective film 50 does not necessarily have to be provided.

[0056] The material for forming the protective film 50 is not particularly limited, but is preferably SiO ２ , SiN, and other insulating materials.

[0057] As shown in Figures 2 and 3, the passive electronic component 1 may further include a resin protective layer 60 covering the first capacitor 21 or the second capacitor 22, a first external electrode 71 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the first capacitor 21, a second external electrode 72 penetrating the resin protective layer 60 and connected to the second internal electrode layer 32 of the first capacitor 21, a third external electrode 73 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the second capacitor 22, and a fourth external electrode 74 penetrating the resin protective layer 60 and connected to the second internal electrode layer 32 of the second capacitor 22.

[0058] The resin protective layer 60 is provided so as to cover the first capacitor 21 or the second capacitor 22 except for the openings. The resin protective layer 60 is provided with an opening overlapping the third internal electrode layer 33 of the first capacitor 21, an opening overlapping the second internal electrode layer 32 of the first capacitor 21, an opening overlapping the third internal electrode layer 33 of the second capacitor 22, and an opening overlapping the second internal electrode layer 32 of the second capacitor 22. By providing the resin protective layer 60, electrode materials such as the internal electrode layers are protected from external moisture and impact.

[0059] The material constituting the resin protective layer 60 is not particularly limited, but preferable examples include resin materials such as polyimide resin and resin in solder resist.

[0060] The material constituting the first external electrode 71 to the fourth external electrode 74 is not particularly limited, but preferably includes a conductive material such as Cu, Ni, Ag, Au, Al, or SnAg. The first external electrode 71 to the fourth external electrode 74 may have a single-layer structure or a multi-layer structure. The outermost surfaces of the first external electrode 71 to the fourth external electrode 74 are preferably made of Au, Sn, or SnAg.

[0061] Second Embodiment In a passive electronic component according to a second embodiment of the present invention, the number of stacked internal electrode layers in the first capacitor is 4. Furthermore, the internal electrode layer closest to the semiconductor substrate extends to the outside of the other internal electrode layers.

[0062] Fig. 5 is a plan view schematically showing an example of a passive electronic component according to a second embodiment of the present invention. Fig. 6 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in Fig. 5 taken along line A-A'. Fig. 7 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in Fig. 5 taken along line B-B'. Fig. 8 is a cross-sectional view schematically showing an example of a cross section of the passive electronic component shown in Fig. 5 taken along line XX'.

[0063] The passive electronic component 2 shown in Figure 5 comprises a semiconductor substrate 10, an insulating layer 15 provided on one main surface of the semiconductor substrate 10, and a first capacitor 21 (see Figures 6 and 8) and a second capacitor 22 (see Figures 7 and 8) arranged in a first region and a second region, respectively, on the insulating layer 15.

[0064] The passive electronic component 2 shown in FIG. 5 has a common configuration with the passive electronic component 1 shown in FIG. 1, except that the configurations of the first capacitor 21 and the second capacitor 22 are different.

[0065] The first capacitor 21 shown in Figure 6 includes a first internal electrode layer 31, a first dielectric film 41 provided on the first internal electrode layer 31, a second internal electrode layer 32 provided on the first dielectric film 41, a second dielectric film 42 provided on the second internal electrode layer 32, a third internal electrode layer 33 provided on the second dielectric film 42 and connected to the first internal electrode layer 31, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43 and connected to the second internal electrode layer 32.

[0066] In the example shown in FIG. 6, the first internal electrode layer 31, which is the internal electrode layer closest to the semiconductor substrate 10, extends to the outside of the second internal electrode layer 32, the third internal electrode layer 33, and the fourth internal electrode layer .

[0067] In the first capacitor 21, a first internal electrode layer 31, a first dielectric film 41, a second internal electrode layer 32, a second dielectric film 42, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are stacked in this order to form an MIM capacitor structure.

[0068] In the example shown in Figure 6, no dielectric film such as the first dielectric film 41 is arranged between the first internal electrode layer 31, which is the internal electrode layer of the first capacitor 21 that is closest to the semiconductor substrate 10, and the insulating layer 15.

[0069] The second capacitor 22 shown in Figure 7 includes a third internal electrode layer 33, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43.

[0070] In the example shown in FIG. 7, the third internal electrode layer 33 which is the internal electrode layer closest to the semiconductor substrate 10 extends to the outside of the fourth internal electrode layer 34 .

[0071] In the second capacitor 22, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are laminated in this order to form an MIM capacitor structure.

[0072] The number of stacked internal electrode layers in the second capacitor 22 is smaller than the number of stacked internal electrode layers in the first capacitor 21. Therefore, the capacitance of the second capacitor 22 is smaller than the capacitance of the first capacitor 21.

[0073] 7 , a first dielectric film 41 and a second dielectric film 42 are disposed between the insulating layer 15 and a third internal electrode layer 33, which is the internal electrode layer of the second capacitor 22 that is closest to the semiconductor substrate 10. Between the third internal electrode layer 33 and the insulating layer 15, only the first dielectric film 41 or only the second dielectric film 42 may be disposed.

[0074] The passive electronic component 2 shown in FIG. 5 also provides the same effects as the passive electronic component 1 shown in FIG.

[0075] The capacitance of the second capacitor 22 may be the same as the capacitance of the first capacitor 21 , but is preferably smaller than the capacitance of the first capacitor 21 .

[0076] The number of stacked internal electrode layers in the second capacitor 22 may be the same as the number of stacked internal electrode layers in the first capacitor 21, but is preferably smaller than the number of stacked internal electrode layers in the first capacitor 21. In that case, the number of stacked internal electrode layers in the second capacitor 22 may be two or three.

[0077] 6 to 8, a protective film 50 may be provided on the third dielectric film 43 and on the fourth internal electrode layer 34. Note that the protective film 50 does not necessarily have to be provided.

[0078] As shown in Figures 6 and 7, the passive electronic component 2 may further include a resin protective layer 60 covering the first capacitor 21 or the second capacitor 22, a first external electrode 71 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the first capacitor 21, a second external electrode 72 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the first capacitor 21, a third external electrode 73 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the second capacitor 22, and a fourth external electrode 74 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the second capacitor 22.

[0079] [Third Embodiment] In a passive electronic component according to a third embodiment of the present invention, the number of stacked internal electrode layers in the first capacitor is 3. Furthermore, a part of the other internal electrode layers extends to the outside of the internal electrode layer closest to the semiconductor substrate.

[0080] Fig. 9 is a plan view schematically showing an example of a passive electronic component according to a third embodiment of the present invention. Fig. 10 is a cross-sectional view schematically showing an example of a cross-section along line AA' of the passive electronic component shown in Fig. 9. Fig. 11 is a cross-sectional view schematically showing an example of a cross-section along line BB' of the passive electronic component shown in Fig. 9.

[0081] The passive electronic component 3 shown in Figure 9 comprises a semiconductor substrate 10, an insulating layer 15 provided on one main surface of the semiconductor substrate 10, and a first capacitor 21 (see Figure 10) and a second capacitor 22 (see Figure 11) arranged in a first region and a second region, respectively, on the insulating layer 15.

[0082] The passive electronic component 3 shown in FIG. 9 has a common configuration with the passive electronic component 1 shown in FIG. 1, except that the configurations of the first capacitor 21 and the second capacitor 22 are different.

[0083] The first capacitor 21 shown in Figure 10 includes a first internal electrode layer 31, a first dielectric film 41 provided on the first internal electrode layer 31, a second internal electrode layer 32 provided on the first dielectric film 41, a second dielectric film 42 provided on the second internal electrode layer 32, and a third internal electrode layer 33 provided on the second dielectric film 42 and connected to the first internal electrode layer 31.

[0084] In the example shown in FIG. 10 , a part of the second internal electrode layer 32 extends to the outside of the first internal electrode layer 31 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0085] In the first capacitor 21, a first internal electrode layer 31, a first dielectric film 41, a second internal electrode layer 32, a second dielectric film 42, and a third internal electrode layer 33 are stacked in this order to form an MIM capacitor structure.

[0086] 10 , no dielectric film such as the first dielectric film 41 is disposed between the insulating layer 15 and the first internal electrode layer 31, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the first capacitor 21. On the other hand, the first dielectric film 41 is disposed between the insulating layer 15 and the second internal electrode layer 32, which extends outside the first internal electrode layer 31.

[0087] The second capacitor 22 shown in Figure 11 includes a second internal electrode layer 32, a second dielectric film 42 provided on the second internal electrode layer 32, and a third internal electrode layer 33 provided on the second dielectric film 42.

[0088] In the example shown in FIG. 11 , a part of the third internal electrode layer 33 extends to the outside of the second internal electrode layer 32 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0089] In the second capacitor 22, a second internal electrode layer 32, a second dielectric film 42, and a third internal electrode layer 33 are laminated in this order to form an MIM capacitor structure.

[0090] The number of stacked internal electrode layers in the second capacitor 22 is smaller than the number of stacked internal electrode layers in the first capacitor 21. Therefore, the capacitance of the second capacitor 22 is smaller than the capacitance of the first capacitor 21.

[0091] 11 , a first dielectric film 41 is disposed between the insulating layer 15 and the second internal electrode layer 32, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the second capacitor 22. On the other hand, the first dielectric film 41 and a second dielectric film 42 are disposed between the insulating layer 15 and a third internal electrode layer 33 extending outside the second internal electrode layer 32.

[0092] The passive electronic component 3 shown in FIG. 9 also provides the same effects as the passive electronic component 1 shown in FIG.

[0093] The capacitance of the second capacitor 22 may be the same as the capacitance of the first capacitor 21 , but is preferably smaller than the capacitance of the first capacitor 21 .

[0094] The number of stacked internal electrode layers in the second capacitor 22 may be the same as the number of stacked internal electrode layers in the first capacitor 21 , but is preferably smaller than the number of stacked internal electrode layers in the first capacitor 21 .

[0095] 10 and 11, a protective film 50 may be provided on the second dielectric film 42 and on the third internal electrode layer 33. Note that the protective film 50 does not necessarily have to be provided.

[0096] As shown in Figures 10 and 11, the passive electronic component 3 may further include a resin protective layer 60 covering the first capacitor 21 or the second capacitor 22, a first external electrode 71 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the first capacitor 21, a second external electrode 72 penetrating the resin protective layer 60 and connected to the second internal electrode layer 32 of the first capacitor 21, a third external electrode 73 penetrating the resin protective layer 60 and connected to the second internal electrode layer 32 of the second capacitor 22, and a fourth external electrode 74 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the second capacitor 22.

[0097] [Fourth Embodiment] In a passive electronic component according to a fourth embodiment of the present invention, the number of stacked internal electrode layers in the first capacitor is 4. Furthermore, a part of the other internal electrode layers extends to the outside of the internal electrode layer closest to the semiconductor substrate.

[0098] Fig. 12 is a plan view schematically showing an example of a passive electronic component according to a fourth embodiment of the present invention. Fig. 13 is a cross-sectional view schematically showing an example of a cross-section along line AA' of the passive electronic component shown in Fig. 12. Fig. 14 is a cross-sectional view schematically showing an example of a cross-section along line BB' of the passive electronic component shown in Fig. 12.

[0099] The passive electronic component 4 shown in Figure 12 comprises a semiconductor substrate 10, an insulating layer 15 provided on one main surface of the semiconductor substrate 10, and a first capacitor 21 (see Figure 13) and a second capacitor 22 (see Figure 14) arranged in a first region and a second region, respectively, on the insulating layer 15.

[0100] The passive electronic component 4 shown in FIG. 12 has a common configuration with the passive electronic component 1 shown in FIG. 1, except that the configurations of the first capacitor 21 and the second capacitor 22 are different.

[0101] The first capacitor 21 shown in Figure 13 includes a first internal electrode layer 31, a first dielectric film 41 provided on the first internal electrode layer 31, a second internal electrode layer 32 provided on the first dielectric film 41, a second dielectric film 42 provided on the second internal electrode layer 32, a third internal electrode layer 33 provided on the second dielectric film 42 and connected to the first internal electrode layer 31, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43 and connected to the second internal electrode layer 32.

[0102] In the example shown in FIG. 13, a part of the second internal electrode layer 32 extends to the outside of the first internal electrode layer 31 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0103] In the first capacitor 21, a first internal electrode layer 31, a first dielectric film 41, a second internal electrode layer 32, a second dielectric film 42, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are stacked in this order to form an MIM capacitor structure.

[0104] 13 , no dielectric film such as the first dielectric film 41 is disposed between the insulating layer 15 and the first internal electrode layer 31, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the first capacitor 21. On the other hand, the first dielectric film 41 is disposed between the insulating layer 15 and the second internal electrode layer 32, which extends outside the first internal electrode layer 31.

[0105] The second capacitor 22 shown in Figure 14 includes a third internal electrode layer 33, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43.

[0106] In the example shown in FIG. 14, a part of the fourth internal electrode layer 34 extends to the outside of the third internal electrode layer 33 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0107] In the second capacitor 22, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are laminated in this order to form an MIM capacitor structure.

[0108] The number of stacked internal electrode layers in the second capacitor 22 is smaller than the number of stacked internal electrode layers in the first capacitor 21. Therefore, the capacitance of the second capacitor 22 is smaller than the capacitance of the first capacitor 21.

[0109] 14 , a first dielectric film 41 and a second dielectric film 42 are arranged between a third internal electrode layer 33, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the second capacitor 22, and the insulating layer 15. Only the first dielectric film 41 or only the second dielectric film 42 may be arranged between the third internal electrode layer 33 and the insulating layer 15. On the other hand, the first dielectric film 41, the second dielectric film 42, and the third dielectric film 43 are arranged between a fourth internal electrode layer 34 extending outside the third internal electrode layer 33 and the insulating layer 15. The first dielectric film 41 and the third dielectric film 43 may be arranged between the fourth internal electrode layer 34 extending outside the third internal electrode layer 33 and the insulating layer 15, or the second dielectric film 42 and the third dielectric film 43 may be arranged between the fourth internal electrode layer 34 extending outside the third internal electrode layer 33 and the insulating layer 15.

[0110] The passive electronic component 4 shown in FIG. 12 also provides the same effects as the passive electronic component 1 shown in FIG.

[0111] The capacitance of the second capacitor 22 may be the same as the capacitance of the first capacitor 21 , but is preferably smaller than the capacitance of the first capacitor 21 .

[0112] The number of stacked internal electrode layers in the second capacitor 22 may be the same as the number of stacked internal electrode layers in the first capacitor 21, but is preferably smaller than the number of stacked internal electrode layers in the first capacitor 21. In that case, the number of stacked internal electrode layers in the second capacitor 22 may be two or three.

[0113] 13 and 14, a protective film 50 may be provided on the third dielectric film 43 and on the fourth internal electrode layer 34. Note that the protective film 50 does not necessarily have to be provided.

[0114] As shown in Figures 13 and 14, the passive electronic component 4 may further include a resin protective layer 60 covering the first capacitor 21 or the second capacitor 22, a first external electrode 71 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the first capacitor 21, a second external electrode 72 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the first capacitor 21, a third external electrode 73 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the second capacitor 22, and a fourth external electrode 74 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the second capacitor 22.

[0115] Fifth Embodiment In a passive electronic component according to a fifth embodiment of the present invention, three or more capacitors are arranged on an insulating layer.

[0116] Fig. 15 is a plan view schematically showing an example of a passive electronic component according to a fifth embodiment of the present invention. Fig. 16 is a cross-sectional view schematically showing an example of a cross-section of the passive electronic component shown in Fig. 15 taken along line A-A'. Fig. 17 is a cross-sectional view schematically showing an example of a cross-section of the passive electronic component shown in Fig. 15 taken along line B-B'. Fig. 18 is a cross-sectional view schematically showing an example of a cross-section of the passive electronic component shown in Fig. 15 taken along line CC'.

[0117] The passive electronic component 5 shown in Figure 15 comprises a semiconductor substrate 10, an insulating layer 15 provided on one main surface of the semiconductor substrate 10, and a first capacitor 21 (see Figure 16), a second capacitor 22 (see Figure 17) and a third capacitor 23 (see Figure 18) arranged in a first region, a second region and a third region on the insulating layer 15, respectively.

[0118] 15, three capacitors are arranged on insulating layer 15, but four or more capacitors may be arranged. In that case, n-th capacitors are arranged in n-th regions on insulating layer 15 (n is a natural number).

[0119] The first capacitor 21, the second capacitor 22, and the third capacitor 23 are each an MIM type capacitor that includes a stacked structure of an internal electrode layer-dielectric film-internal electrode layer in the thickness direction of the semiconductor substrate 10 (the vertical direction in Figures 16, 17, and 18).

[0120] The first capacitor 21 shown in Figure 16 includes a first internal electrode layer 31, a first dielectric film 41 provided on the first internal electrode layer 31, a second internal electrode layer 32 provided on the first dielectric film 41, a second dielectric film 42 provided on the second internal electrode layer 32, a third internal electrode layer 33 provided on the second dielectric film 42 and connected to the first internal electrode layer 31, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43 and connected to the second internal electrode layer 32.

[0121] In the example shown in FIG. 16, a part of the second internal electrode layer 32 extends to the outside of the first internal electrode layer 31 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0122] In the first capacitor 21, a first internal electrode layer 31, a first dielectric film 41, a second internal electrode layer 32, a second dielectric film 42, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are stacked in this order to form an MIM capacitor structure.

[0123] 16 , no dielectric film such as the first dielectric film 41 is disposed between the insulating layer 15 and the first internal electrode layer 31, which is the internal electrode layer of the first capacitor 21 that is closest to the semiconductor substrate 10. On the other hand, the first dielectric film 41 is disposed between the first internal electrode layer 31 and the second internal electrode layer 32 that extends outside the first internal electrode layer 31.

[0124] The second capacitor 22 shown in Figure 17 includes a second internal electrode layer 32, a second dielectric film 42 provided on the second internal electrode layer 32, a third internal electrode layer 33 provided on the second dielectric film 42, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43 and connected to the second internal electrode layer 32.

[0125] In the example shown in FIG. 17, a part of the third internal electrode layer 33 extends to the outside of the second internal electrode layer 32 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0126] In the second capacitor 22, a second internal electrode layer 32, a second dielectric film 42, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are stacked in this order to form an MIM capacitor structure.

[0127] The number of stacked internal electrode layers in the second capacitor 22 is smaller than the number of stacked internal electrode layers in the first capacitor 21. Therefore, the capacitance of the second capacitor 22 is smaller than the capacitance of the first capacitor 21.

[0128] 17 , a first dielectric film 41 is disposed between the insulating layer 15 and the second internal electrode layer 32, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the second capacitor 22. On the other hand, the first dielectric film 41 and a second dielectric film 42 are disposed between the insulating layer 15 and a third internal electrode layer 33 extending outside the second internal electrode layer 32.

[0129] The third capacitor 23 shown in FIG. 18 includes a third internal electrode layer 33, a third dielectric film 43 provided on the third internal electrode layer 33, and a fourth internal electrode layer 34 provided on the third dielectric film 43.

[0130] In the example shown in FIG. 18, a part of the fourth internal electrode layer 34 extends to the outside of the third internal electrode layer 33 which is the internal electrode layer closest to the semiconductor substrate 10 .

[0131] In the third capacitor 23, a third internal electrode layer 33, a third dielectric film 43, and a fourth internal electrode layer 34 are laminated in this order to form an MIM capacitor structure.

[0132] The number of stacked internal electrode layers in the third capacitor 23 is less than the number of stacked internal electrode layers in the first capacitor 21, and is also less than the number of stacked internal electrode layers in the second capacitor 22. Therefore, the capacitance of the third capacitor 23 is smaller than the capacitance of the first capacitor 21, and is also smaller than the capacitance of the second capacitor 22.

[0133] 18 , a first dielectric film 41 and a second dielectric film 42 are arranged between a third internal electrode layer 33, which is the internal electrode layer closest to the semiconductor substrate 10 among the internal electrode layers of the third capacitor 23, and the insulating layer 15. Only the first dielectric film 41 or only the second dielectric film 42 may be arranged between the third internal electrode layer 33 and the insulating layer 15. On the other hand, the first dielectric film 41, the second dielectric film 42, and the third dielectric film 43 are arranged between a fourth internal electrode layer 34 extending outside the third internal electrode layer 33 and the insulating layer 15. The first dielectric film 41 and the third dielectric film 43 may be arranged between the fourth internal electrode layer 34 extending outside the third internal electrode layer 33 and the insulating layer 15, or the second dielectric film 42 and the third dielectric film 43 may be arranged between the fourth internal electrode layer 34 extending outside the third internal electrode layer 33 and the insulating layer 15.

[0134] The passive electronic component 5 shown in FIG. 15 also provides the same effects as the passive electronic component 1 shown in FIG.

[0135] The capacitance of the second capacitor 22 may be the same as the capacitance of the first capacitor 21 , but is preferably smaller than the capacitance of the first capacitor 21 .

[0136] The capacitance of the third capacitor 23 may be the same as the capacitance of the first capacitor 21, but is preferably smaller than the capacitance of the first capacitor 21. The capacitance of the third capacitor 23 may be the same as the capacitance of the second capacitor 22, or may be smaller than the capacitance of the second capacitor 22.

[0137] The number of stacked internal electrode layers in the second capacitor 22 may be the same as the number of stacked internal electrode layers in the first capacitor 21 , but is preferably smaller than the number of stacked internal electrode layers in the first capacitor 21 .

[0138] The number of stacked internal electrode layers in the third capacitor 23 may be the same as the number of stacked internal electrode layers in the first capacitor 21, but is preferably smaller than the number of stacked internal electrode layers in the first capacitor 21. In addition, the number of stacked internal electrode layers in the third capacitor 23 may be the same as the number of stacked internal electrode layers in the second capacitor 22, or may be smaller than the number of stacked internal electrode layers in the second capacitor 22.

[0139] 16, 17, and 18, a protective film 50 may be provided on the third dielectric film 43 and on the fourth internal electrode layer 34. Note that the protective film 50 does not necessarily have to be provided.

[0140] 16 , 17 and 18 , the passive electronic component 5 may further include a resin protective layer 60 covering the first capacitor 21, the second capacitor 22 or the third capacitor 23, a first external electrode 71 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the first capacitor 21, a second external electrode 72 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the first capacitor 21, a third external electrode 73 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the second capacitor 22, a fourth external electrode 74 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the second capacitor 22, a fifth external electrode 75 penetrating the resin protective layer 60 and connected to the third internal electrode layer 33 of the third capacitor 23, and a sixth external electrode 76 penetrating the resin protective layer 60 and connected to the fourth internal electrode layer 34 of the third capacitor 23.

[0141] When three or more capacitors are arranged on an insulating layer, as in the passive electronic component according to the fifth embodiment of the present invention, the nth capacitor (n is a natural number) from the third capacitor onwards may include a capacitor in which a dielectric film is arranged between the insulating layer and the internal electrode layer closest to the semiconductor substrate, or may include a capacitor in which a dielectric film is not arranged between the insulating layer and the internal electrode layer closest to the semiconductor substrate, or may include both.

[0142] Sixth Embodiment In a passive electronic component according to a sixth embodiment of the present invention, an inductor electrically connected to the first capacitor or the second capacitor is provided inside or on the surface of the resin protective layer.

[0143] Fig. 19 is a plan view schematically showing an example of a passive electronic component according to a sixth embodiment of the present invention. Fig. 20 is a cross-sectional view schematically showing an example of a cross-section along line AA' of the passive electronic component shown in Fig. 19. Fig. 21 is a cross-sectional view schematically showing an example of a cross-section along line BB' of the passive electronic component shown in Fig. 19.

[0144] The passive electronic component 6 shown in Figure 19 comprises a semiconductor substrate 10, an insulating layer 15 provided on one main surface of the semiconductor substrate 10, and a first capacitor 21 (see Figure 20) and a second capacitor 22 (see Figure 21) arranged in a first region and a second region, respectively, on the insulating layer 15.

[0145] The first capacitor 21 has, for example, the configuration described in the first to fifth embodiments. For example, the first capacitor 21 shown in Fig. 20 has a common configuration with the first capacitor 21 shown in Fig. 6.

[0146] Similarly, the second capacitor 22 has, for example, the configuration described in the first to fifth embodiments. For example, the second capacitor 22 shown in Fig. 21 has a common configuration with the second capacitor 22 shown in Fig. 7.

[0147] 19 and 20 , the passive electronic component 6 further includes an inductor 80 electrically connected to the first capacitor 21. Although not shown, the passive electronic component 6 may further include an inductor 80 electrically connected to the second capacitor 22 in addition to the inductor 80 electrically connected to the first capacitor 21 or instead of the inductor 80 electrically connected to the first capacitor 21.

[0148] 20 , an inductor 80 is provided on the surface of a resin protective layer 60, and a resin protective layer 61 is provided on the surface of the inductor 80. The inductor 80 may be provided on the surface of the resin protective layer 60 or the resin protective layer 61, or may be provided inside the resin protective layer 60 or the resin protective layer 61.

[0149] By including an inductor in a passive electronic component, the parasitic capacitance between the semiconductor substrate and the capacitor can be reduced. This increases the Q characteristic of the capacitor, improving the performance of the entire circuit. Furthermore, reducing the parasitic capacitance between the inductor and capacitor via the semiconductor substrate can improve the Q characteristic of filters and resonators.

[0150] Furthermore, in passive electronic components that function as filters or resonators by connecting a capacitor and an inductor inside or on the surface of a resin protective layer, the pass band of the filter and the resonant frequency of the resonator can be made more accurate than in a configuration in which the capacitor and inductor are connected via a mounting substrate.

[0151] When three or more capacitors are arranged on an insulating layer, as in the passive electronic component of the fifth embodiment of the present invention, the nth capacitor (n is a natural number) from the third capacitor onwards may include a capacitor to which an inductor is electrically connected, a capacitor to which an inductor is not electrically connected, or both.

[0152] The passive electronic component of the present invention is not limited to the above-described embodiment, and various applications and modifications can be made within the scope of the present invention with respect to the configuration of the semiconductor substrate, insulating layer or capacitor, manufacturing conditions, etc.

[0153] In the passive electronic component of the present invention, the number of stacked internal electrode layers in the first capacitor is not particularly limited and may be, for example, 3 or more, or 4 or more. The number of stacked internal electrode layers in the second capacitor is not particularly limited and may be, for example, 2 or more, or 3 or more, or 4 or more.

[0154] In the passive electronic component of the present invention, when three or more capacitors are arranged on an insulating layer, the number of stacked internal electrode layers in the nth capacitor (n is a natural number) from the third capacitor onwards is not particularly limited.

[0155] The passive electronic component of the present invention has a high Q characteristic and is therefore suitable for use in a matching circuit or a filter circuit.

[0156] [Method for Producing Passive Electronic Component] The passive electronic component of the present invention is produced, for example, by the following method.

[0157] For example, the passive electronic component according to the first embodiment of the present invention is manufactured by the following steps.

[0158] As an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention, each step will be described based on a cross section of the passive electronic component 1 taken along line XX' shown in FIG.

[0159] FIG. 22 is a cross-sectional view schematically showing a step of preparing a semiconductor substrate in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0160] As shown in FIG. 22, a semiconductor substrate 10 is prepared.

[0161] FIG. 23 is a cross-sectional view schematically showing a step of forming a charge trap layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0162] 23, a charge trapping layer 13 made of polycrystalline silicon or amorphous silicon may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like on one main surface (upper surface in FIG. 23) of a semiconductor substrate 10. Note that the charge trapping layer 13 is omitted from FIG. 24 and subsequent drawings.

[0163] 24 and 25 are cross-sectional views schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0164] 24, an insulating layer 15 made of an insulating material is formed on one main surface of the semiconductor substrate 10 by a method such as CVD or PVD. Then, as shown in Fig. 25, the insulating layer 15 is patterned by a combination of photolithography and etching. As a result, the semiconductor substrate 10 having the insulating layer 15 provided on one main surface is obtained.

[0165] When the charge trap layer 13 shown in FIG. 23 is formed on one main surface of the semiconductor substrate 10 , an insulating layer 15 may be formed on the charge trap layer 13 .

[0166] 26 and 27 are cross-sectional views schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention, respectively.

[0167] As shown in Fig. 26, a first internal electrode layer 31 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 25 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 27, the first internal electrode layer 31 is patterned by a combination of photolithography and etching.

[0168] 27, the first internal electrode layer 31 formed in the first region is left, while the first internal electrode layer 31 formed in the second region is removed. As a result, the first internal electrode layer 31 is formed on the insulating layer 15 in the first region, and the first internal electrode layer 31 is not formed on the insulating layer 15 in the second region.

[0169] 28 and 29 are cross-sectional views schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention, respectively.

[0170] 28, a first dielectric film 41 made of a dielectric material is formed by a method such as CVD, PVD, or atomic layer deposition (ALD) so as to cover the structure shown in FIG. 27 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in FIG. 29, the first dielectric film 41 is patterned by a combination of photolithography and etching.

[0171] 29, the first dielectric film 41 formed in the first region and the first dielectric film 41 formed in the second region are left. In this way, the first dielectric film 41 is formed on the first internal electrode layer 31 in the first region and on the insulating layer 15 in the second region.

[0172] 30 is a cross-sectional view schematically showing a step of forming a second internal electrode layer in the example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention. FIG. 31 is a cross-sectional view schematically showing a step of patterning the second internal electrode layer in the example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0173] As shown in Fig. 30, a second internal electrode layer 32 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 29 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 31, the second internal electrode layer 32 is patterned by a combination of photolithography and etching.

[0174] 31, the second internal electrode layer 32 formed in the first region and the second internal electrode layer 32 formed in the second region are left. In this way, the second internal electrode layer 32 is formed on the first dielectric film 41 in the first region and the second region.

[0175] 32 and 33 are cross-sectional views schematically showing a step of forming a second dielectric film in the example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention, respectively.

[0176] 32, a second dielectric film 42 made of a dielectric material is formed by a method such as CVD, PVD, or ALD so as to cover the structure shown in FIG. 31 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in FIG. 33, the second dielectric film 42 is patterned by a combination of photolithography and etching.

[0177] 33, the second dielectric film 42 formed in the first region and the second dielectric film 42 formed in the second region are left. In this way, the second dielectric film 42 is formed on the second internal electrode layer 32 in the first region and the second region.

[0178] 34 and 35 are cross-sectional views schematically showing a step of forming a third internal electrode layer in the example of the method for manufacturing a passive electronic component according to the first embodiment of the present invention, respectively.

[0179] As shown in Fig. 34, a third internal electrode layer 33 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 33 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 35, the third internal electrode layer 33 is patterned by a combination of photolithography and etching.

[0180] 35, the third internal electrode layer 33 formed in the first region and the third internal electrode layer 33 formed in the second region are left. In this way, the third internal electrode layer 33 is formed on the second dielectric film 42 in the first region and the second region.

[0181] FIG. 36 is a cross-sectional view schematically showing a step of forming a protective film in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0182] 36, a protective film 50 made of an insulating material may be formed by a method such as CVD or PVD so as to cover the structure shown in FIG. 35 from one main surface side of the semiconductor substrate 10. Thereafter, the protective film 50 is patterned by a combination of photolithography and etching.

[0183] FIG. 37 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the first embodiment of the present invention.

[0184] 37, a resin protective layer 60 made of a resin material is formed by a method such as spin coating so as to cover the structure shown in FIG. 36 from one main surface side of the semiconductor substrate 10. Thereafter, if the resin material of the resin protective layer 60 is photosensitive, only photolithography is used, or if the resin material of the resin protective layer 60 is non-photosensitive, a combination of photolithography and etching is used to pattern the resin protective layer 60. Although not shown in FIG. 37, through holes are provided through the resin protective layer 60 so as to expose portions of the internal electrode layers.

[0185] 37 , a first capacitor 21 and a second capacitor 22 are formed in a first region and a second region, respectively, on an insulating layer 15. In the above example, a first dielectric film 41 is formed between the insulating layer 15 and a second internal electrode layer 32, which is the internal electrode layer of the second capacitor 22 that is closest to the semiconductor substrate 10.

[0186] Although subsequent illustrations are omitted, the first external electrode 71, the second external electrode 72, the third external electrode 73, and the fourth external electrode 74 (see Figures 2 and 3) are then formed by a method such as lift-off, plating, or etching.

[0187] If necessary, the semiconductor substrate 10 may be thinned to a desired device thickness by back grinding.

[0188] In this manner, the passive electronic component 1 can be manufactured.

[0189] For example, the passive electronic component according to the second embodiment of the present invention is manufactured by the following steps.

[0190] As an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, each step will be described based on a cross section of the passive electronic component 2 taken along line XX' shown in FIG.

[0191] FIG. 38 is a cross-sectional view schematically showing a step of preparing a semiconductor substrate in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.

[0192] As shown in FIG. 38, a semiconductor substrate 10 is prepared.

[0193] FIG. 39 is a cross-sectional view schematically showing a step of forming a charge trap layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.

[0194] 39, a charge trap layer 13 made of polycrystalline silicon or amorphous silicon may be formed by a method such as CVD or PVD on one main surface (the upper surface in FIG. 39) of a semiconductor substrate 10. Note that the charge trap layer 13 is omitted from FIG. 40 and subsequent drawings.

[0195] 40 and 41 are cross-sectional views schematically showing a step of forming an insulating layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0196] As shown in Fig. 40, an insulating layer 15 made of an insulating material is formed on one main surface of a semiconductor substrate 10 by a method such as CVD or PVD. Thereafter, as shown in Fig. 41, the insulating layer 15 is patterned by a combination of photolithography and etching. As a result, a semiconductor substrate 10 having an insulating layer 15 provided on one main surface is obtained.

[0197] When the charge trap layer 13 shown in FIG. 39 is formed on one main surface of the semiconductor substrate 10 , an insulating layer 15 may be formed on the charge trap layer 13 .

[0198] 42 and 43 are cross-sectional views schematically showing a step of forming a first internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0199] As shown in Fig. 42, a first internal electrode layer 31 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 41 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 43, the first internal electrode layer 31 is patterned by a combination of photolithography and etching.

[0200] 43 , the first internal electrode layers 31 formed in the first region are left, while the first internal electrode layers 31 formed in the second region are removed. As a result, the first internal electrode layers 31 are formed on the insulating layers 15 in the first region, and the first internal electrode layers 31 are not formed on the insulating layers 15 in the second region.

[0201] 44 and 45 are cross-sectional views schematically showing a step of forming a first dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0202] 44, a first dielectric film 41 made of a dielectric material is formed by a method such as CVD, PVD, or ALD so as to cover the structure shown in Fig. 43 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 45, the first dielectric film 41 is patterned by a combination of photolithography and etching.

[0203] 45, the first dielectric film 41 formed in the first region and the first dielectric film 41 formed in the second region are left. In this way, the first dielectric film 41 is formed on the first internal electrode layer 31 in the first region and on the insulating layer 15 in the second region.

[0204] 46 and 47 are cross-sectional views schematically showing a step of forming a second internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0205] As shown in Fig. 46, second internal electrode layers 32 made of a conductive material are formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 45 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 47, the second internal electrode layers 32 are patterned by a combination of photolithography and etching.

[0206] 47, the second internal electrode layer 32 formed in the first region is left, while the second internal electrode layer 32 formed in the second region is removed. As a result, the second internal electrode layer 32 is formed on the first dielectric film 41 in the first region, and the second internal electrode layer 32 is not formed on the first dielectric film 41 in the second region.

[0207] 48 and 49 are cross-sectional views schematically showing a step of forming a second dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0208] As shown in Fig. 48, a second dielectric film 42 made of a dielectric material is formed by a method such as CVD, PVD, or ALD so as to cover the structure shown in Fig. 47 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 49, the second dielectric film 42 is patterned by a combination of photolithography and etching.

[0209] 49, the second dielectric film 42 formed in the first region and the second dielectric film 42 formed in the second region are left. In this way, the second dielectric film 42 is formed on the second internal electrode layer 32 in the first region and on the first dielectric film 41 in the second region.

[0210] 50 and 51 are cross-sectional views schematically showing a step of forming a third internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0211] As shown in Fig. 50, a third internal electrode layer 33 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 49 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 51, the third internal electrode layer 33 is patterned by a combination of photolithography and etching.

[0212] 51, the third internal electrode layer 33 formed in the first region and the third internal electrode layer 33 formed in the second region are left. In this way, the third internal electrode layer 33 is formed on the second dielectric film 42 in the first region and the second region.

[0213] 52 and 53 are cross-sectional views schematically showing a step of forming a third dielectric film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0214] 52, a third dielectric film 43 made of a dielectric material is formed by a method such as CVD, PVD, or ALD so as to cover the structure shown in Fig. 51 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 53, the third dielectric film 43 is patterned by a combination of photolithography and etching.

[0215] 53, the third dielectric film 43 formed in the first region and the third dielectric film 43 formed in the second region are left. In this way, the third dielectric film 43 is formed on the third internal electrode layer 33 in the first region and the second region.

[0216] 54 and 55 are cross-sectional views schematically showing a step of forming a fourth internal electrode layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention, respectively.

[0217] As shown in Fig. 54, a fourth internal electrode layer 34 made of a conductive material is formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 53 from one main surface side of the semiconductor substrate 10. Thereafter, as shown in Fig. 55, the fourth internal electrode layer 34 is patterned by a combination of photolithography and etching.

[0218] 55, the fourth internal electrode layer 34 formed in the first region and the fourth internal electrode layer 34 formed in the second region are left. In this way, the fourth internal electrode layer 34 is formed on the third dielectric film 43 in the first region and the second region.

[0219] FIG. 56 is a cross-sectional view schematically showing a step of forming a protective film in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.

[0220] 56, a protective film 50 made of an insulating material may be formed by a method such as CVD or PVD so as to cover the structure shown in Fig. 55 from one main surface side of the semiconductor substrate 10. Thereafter, the protective film 50 is patterned by a combination of photolithography and etching.

[0221] FIG. 57 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to the second embodiment of the present invention.

[0222] As shown in Fig. 57, a resin protective layer 60 made of a resin material is formed by a method such as spin coating so as to cover the structure shown in Fig. 56 from one main surface side of the semiconductor substrate 10. Thereafter, if the resin material of the resin protective layer 60 is photosensitive, only photolithography is used, or if the resin material of the resin protective layer 60 is non-photosensitive, a combination of photolithography and etching is used to pattern the resin protective layer 60. Although not shown in Fig. 57, through holes are provided through the resin protective layer 60 so as to expose portions of the internal electrode layers.

[0223] 57 , a first capacitor 21 and a second capacitor 22 are formed in a first region and a second region, respectively, on an insulating layer 15. In the above example, a first dielectric film 41 and a second dielectric film 42 are formed between the insulating layer 15 and a third internal electrode layer 33, which is the internal electrode layer of the second capacitor 22 that is closest to the semiconductor substrate 10.

[0224] Although subsequent illustrations are omitted, the first external electrode 71, the second external electrode 72, the third external electrode 73, and the fourth external electrode 74 (see Figures 6 and 7) are then formed by a method such as lift-off, plating, or etching.

[0225] If necessary, the semiconductor substrate 10 may be thinned to a desired device thickness by back grinding.

[0226] In this manner, the passive electronic component 2 can be manufactured.

[0227] For example, the passive electronic component according to the third embodiment of the present invention can be manufactured by the same method as the passive electronic component according to the first embodiment of the present invention, except that the range in which the internal electrode layer closest to the semiconductor substrate is formed is different.

[0228] For example, the passive electronic component according to the fourth embodiment of the present invention can be manufactured by a method similar to that of the passive electronic component according to the second embodiment of the present invention, except that the range in which the internal electrode layer closest to the semiconductor substrate is formed is different.

[0229] For example, the passive electronic component according to the fifth embodiment of the present invention can be manufactured by a method similar to that of the passive electronic component according to the first or second embodiment of the present invention, except that three or more capacitors are formed on an insulating layer.

[0230] For example, the passive electronic component according to the sixth embodiment of the present invention can be manufactured by the same method as the passive electronic component according to the first or second embodiment of the present invention, except that an inductor electrically connected to the first capacitor or the second capacitor is formed inside or on the surface of the resin protective layer.

[0231] FIG. 58 is a cross-sectional view schematically showing a step of forming a resin protective layer in an example of a method for manufacturing a passive electronic component according to a sixth embodiment of the present invention.

[0232] 58, after forming a resin protective layer 60 made of a resin material, the resin protective layer 60 is patterned. At this time, through holes are provided through the resin protective layer 60 so that parts of the internal electrode layers are exposed.

[0233] FIG. 59 is a cross-sectional view schematically showing a step of forming an inductor in an example of a method for manufacturing a passive electronic component according to a sixth embodiment of the present invention.

[0234] As shown in FIG. 59, an external electrode of the capacitor is formed inside the through-hole that penetrates the resin protective layer 60 by plating or other method, and an inductor 80 is formed on the surface of the resin protective layer 60 .

[0235] FIG. 60 is a cross-sectional view schematically showing a step of forming another resin protective layer in an example of a method for manufacturing a passive electronic component according to a sixth embodiment of the present invention.

[0236] 60, a resin protective layer 61 is formed on the surface of the inductor 80. At this time, a through hole penetrating the resin protective layer 61 is provided.

[0237] Thereafter, external electrodes are formed by plating or other methods.

[0238] If necessary, the semiconductor substrate 10 may be thinned to a desired device thickness by back grinding.

[0239] In this manner, the passive electronic component 6 can be manufactured.

[0240] The present specification discloses the following:

[0241] <1> A passive electronic component comprising: a semiconductor substrate; an insulating layer provided on one main surface of the semiconductor substrate; and a first capacitor and a second capacitor respectively arranged in a first region and a second region on the insulating layer, wherein the first capacitor and the second capacitor are MIM type capacitors each having a laminated structure of an internal electrode layer-a dielectric film-an internal electrode layer in a thickness direction of the semiconductor substrate, and at least one dielectric film of the same type as the dielectric film included between the internal electrode layers of the first capacitor is arranged between the internal electrode layer of the second capacitor that is closest to the semiconductor substrate and the insulating layer.

[0242] <2> The passive electronic component according to <1>, wherein the capacitance of the second capacitor is smaller than the capacitance of the first capacitor.

[0243] <3> The passive electronic component according to <1> or <2>, wherein the number of laminations of the internal electrode layers in the second capacitor is smaller than the number of laminations of the internal electrode layers in the first capacitor.

[0244] <4> The passive electronic component according to any one of <1> to <3>, wherein the semiconductor substrate is made of silicon and has a resistivity of 3 kΩ·cm or more.

[0245] <5> The passive electronic component according to <4>, further comprising a charge trapping layer made of polycrystalline silicon or amorphous silicon between the semiconductor substrate and the insulating layer.

[0246] <6> The passive electronic component according to any one of <1> to <5>, further comprising: a resin protective layer that covers the first capacitor and the second capacitor; and an inductor that is provided inside or on a surface of the resin protective layer and is electrically connected to the first capacitor or the second capacitor.

[0247] <7> The passive electronic component according to any one of <1> to <6>, wherein the internal electrode layer of the first capacitor that is closest to the semiconductor substrate is disposed directly on the insulating layer.

[0248] <8> A method for manufacturing a passive electronic component, comprising: a step of preparing a semiconductor substrate having an insulating layer provided on one main surface thereof; and a step of forming a first capacitor and a second capacitor in a first region and a second region on the insulating layer, respectively; wherein the first capacitor and the second capacitor are MIM type capacitors each having a stacked structure of an internal electrode layer-a dielectric film-an internal electrode layer in a thickness direction of the semiconductor substrate; and at least one layer of a dielectric film of the same type as the dielectric film included between the internal electrode layers of the first capacitor is formed between the internal electrode layer of the second capacitor that is closest to the semiconductor substrate and the insulating layer.

[0249] <9> The method for manufacturing a passive electronic component according to <8>, wherein the capacitance of the second capacitor is smaller than the capacitance of the first capacitor.

[0250] <10> The method for manufacturing a passive electronic component according to <8> or <9>, wherein the number of laminations of the internal electrode layers in the second capacitor is smaller than the number of laminations of the internal electrode layers in the first capacitor.

[0251] <11> The method for manufacturing a passive electronic component according to any one of <8> to <10>, wherein the step of forming the first capacitor and the second capacitor includes the steps of: forming a first internal electrode layer on the insulating layer in the first region, and not forming the first internal electrode layer on the insulating layer in the second region; forming a first dielectric film on the first internal electrode layer in the first region and on the insulating layer in the second region; forming a second internal electrode layer on the first dielectric film in the first region and the second region; forming a second dielectric film on the second internal electrode layer in the first region and the second region; and forming a third internal electrode layer on the second dielectric film in the first region and the second region.

[0252] <12> The step of forming the first capacitor and the second capacitor includes: a step of forming a first internal electrode layer on the insulating layer in the first region, and not forming the first internal electrode layer on the insulating layer in the second region; a step of forming a first dielectric film on the first internal electrode layer in the first region and on the insulating layer in the second region; a step of forming a second internal electrode layer on the first dielectric film in the first region, and not forming the second internal electrode layer on the first dielectric film in the second region; a step of forming a second dielectric film on the second internal electrode layer in the first region and on the first dielectric film in the second region; a step of forming a third internal electrode layer on the second dielectric film in the first region and the second region; and a step of forming a third dielectric film on the third internal electrode layer in the first region and the second region. and forming a fourth internal electrode layer on the third dielectric film in the first region and the second region.

[0253] <13> The method for manufacturing a passive electronic component according to any one of <8> to <12>, wherein the semiconductor substrate is made of silicon and has a resistivity of 3 kΩ·cm or more.

[0254] <14> The method for manufacturing a passive electronic component according to <13>, wherein the step of preparing the semiconductor substrate includes the steps of: forming a charge trapping layer made of polycrystalline silicon or amorphous silicon on the one main surface of the semiconductor substrate; and forming the insulating layer on the charge trapping layer.

[0255] <15> The method for manufacturing a passive electronic component according to any one of <8> to <14>, further comprising the steps of: forming a resin protective layer that covers the first capacitor and the second capacitor; and forming an inductor electrically connected to the first capacitor or the second capacitor inside or on a surface of the resin protective layer.

[0256] 1, 2, 3, 4, 5, 6 Passive electronic component 10 Semiconductor substrate 13 Charge trapping layer 15 Insulating layer 21 First capacitor 22 Second capacitor 23 Third capacitor 31 First internal electrode layer 32 Second internal electrode layer 33 Third internal electrode layer 34 Fourth internal electrode layer 41 First dielectric film 42 Second dielectric film 43 Third dielectric film 50 Protective film 60, 61 Resin protective layer 71 First external electrode 72 Second external electrode 73 Third external electrode 74 Fourth external electrode 75 Fifth external electrode 76 Sixth external electrode 80 Inductor

Claims

1. A passive electronic component comprising: a semiconductor substrate; an insulating layer provided on one main surface of the semiconductor substrate; and a first capacitor and a second capacitor respectively arranged in a first region and a second region on the insulating layer, wherein the first capacitor and the second capacitor are MIM type capacitors each having a laminated structure of internal electrode layer-dielectric film-internal electrode layer in the thickness direction of the semiconductor substrate, and at least one dielectric film of the same type as the dielectric film included between the internal electrode layers of the first capacitor is arranged between the internal electrode layer of the second capacitor that is closest to the semiconductor substrate and the insulating layer.

2. The passive electronic component of claim 1, wherein the capacitance of said second capacitor is smaller than the capacitance of said first capacitor.

3. A passive electronic component according to claim 1 or 2, wherein the number of laminations of the internal electrode layers in the second capacitor is smaller than the number of laminations of the internal electrode layers in the first capacitor.

4. A passive electronic component according to any one of claims 1 to 3, wherein the semiconductor substrate is made of silicon and has a resistivity of 3 kΩ·cm or more.

5. The passive electronic component of claim 4, further comprising a charge trapping layer made of polycrystalline silicon or amorphous silicon between said semiconductor substrate and said insulating layer.

6. A passive electronic component according to any one of claims 1 to 5, further comprising: a resin protective layer covering the first capacitor and the second capacitor; and an inductor provided inside or on the surface of the resin protective layer and electrically connected to the first capacitor or the second capacitor.

7. A passive electronic component according to any one of claims 1 to 6, wherein the internal electrode layer of the first capacitor that is closest to the semiconductor substrate is disposed directly on the insulating layer.

8. A method for manufacturing a passive electronic component, comprising the steps of: preparing a semiconductor substrate having an insulating layer on one main surface thereof; and forming a first capacitor and a second capacitor in a first region and a second region on the insulating layer, respectively; wherein the first capacitor and the second capacitor are MIM type capacitors each having a laminated structure of internal electrode layer-dielectric film-internal electrode layer in the thickness direction of the semiconductor substrate; and at least one dielectric film of the same type as the dielectric film included between the internal electrode layers of the first capacitor is formed between the internal electrode layer of the second capacitor that is closest to the semiconductor substrate and the insulating layer.

9. The method for manufacturing a passive electronic component according to claim 8, wherein the capacitance of the second capacitor is smaller than the capacitance of the first capacitor.

10. A method for manufacturing a passive electronic component according to claim 8 or 9, wherein the number of laminations of the internal electrode layers in the second capacitor is smaller than the number of laminations of the internal electrode layers in the first capacitor.

11. A method for manufacturing a passive electronic component according to any one of claims 8 to 10, wherein the step of forming the first capacitor and the second capacitor comprises the steps of: forming a first internal electrode layer on the insulating layer in the first region, and not forming the first internal electrode layer on the insulating layer in the second region; forming a first dielectric film on the first internal electrode layer in the first region and on the insulating layer in the second region; forming a second internal electrode layer on the first dielectric film in the first region and the second region; forming a second dielectric film on the second internal electrode layer in the first region and the second region; and forming a third internal electrode layer on the second dielectric film in the first region and the second region.

12. A method for manufacturing a passive electronic component according to any one of claims 8 to 10, wherein the step of forming the first capacitor and the second capacitor comprises the steps of: forming a first internal electrode layer on the insulating layer in the first region, and not forming the first internal electrode layer on the insulating layer in the second region; forming a first dielectric film on the first internal electrode layer in the first region and on the insulating layer in the second region; forming a second internal electrode layer on the first dielectric film in the first region, and not forming the second internal electrode layer on the first dielectric film in the second region; forming a second dielectric film on the second internal electrode layer in the first region and on the first dielectric film in the second region; forming a third internal electrode layer on the second dielectric film in the first region and the second region; forming a third dielectric film on the third internal electrode layer in the first region and the second region; and forming a fourth internal electrode layer on the third dielectric film in the first region and the second region.

13. The method for manufacturing a passive electronic component according to any one of claims 8 to 12, wherein the semiconductor substrate is made of silicon and has a resistivity of 3 kΩ·cm or more.

14. The method for manufacturing a passive electronic component according to claim 13, wherein the step of preparing the semiconductor substrate includes the steps of: forming a charge trapping layer made of polycrystalline silicon or amorphous silicon on the one main surface of the semiconductor substrate; and forming the insulating layer on the charge trapping layer.

15. A method for manufacturing a passive electronic component according to any one of claims 8 to 14, further comprising the steps of: forming a resin protective layer that covers the first capacitor and the second capacitor; and forming an inductor electrically connected to the first capacitor or the second capacitor inside or on the surface of the resin protective layer.

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