Digital-to-analog converter

Abstract

Disclosed in the present invention is a digital-to-analog converter. The digital-to-analog converter comprises a first conversion module, which is used for obtaining a corresponding analog signal on the basis of a plurality of input digital code values, wherein the first conversion module comprises an R-2R ladder resistor network architecture consisting of a plurality of first resistor branches and a plurality of impedance matching modules, and each impedance matching module comprises a first transistor and a first resistor that are connected in series. The digital-to-analog converter further comprises a second conversion module, which is used for obtaining, on the basis of the plurality of digital code values, a plurality of node control voltages corresponding to the plurality of impedance matching modules, wherein each node control voltage is used for controlling the turning-on and turning-off of a first transistor in a corresponding impedance matching module. Therefore, the output precision of the digital-to-analog converter can be improved.

Description

Digital to analog converter Cross-reference to related applications

[0001] This application claims priority to the Chinese Patent Application No. 202410843595.0, filed on June 26, 2024, and entitled “Digital to analog converter”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of integrated circuits, and in particular, to a digital to analog converter. BACKGROUND

[0003] There are many different kinds of architectures for digital to analog converters (DACs), and the R-2R ladder resistor network architecture is a common and simple one. In the R-2R ladder resistor network architecture, the accuracy of the output voltage is affected by the on-resistance of the switches. As the input digital code value changes, the on-resistance of the switches also changes accordingly, which further affects the output accuracy and linearity of the digital to analog converter.

[0004] FIG. 1 shows a circuit schematic diagram of a prior art digital to analog converter, and FIG. 2 shows an equivalent circuit diagram of the digital to analog converter in FIG. 1. The R and 2R identified in FIG. 1 and FIG. 2 are the impedances of the corresponding resistors, d0-d3 are 4-bit digital code values, r is the on-resistance of each switch, Vref is the reference voltage, and Vout is the output voltage.

[0005] Referring to FIG. 1, without considering the on-resistance 2r of the switches, the output voltage Vout can be expressed as: Referring to FIG. 2, when the on-resistance r of the switches is considered, the output voltage Vout cannot be expressed by equation (1), thereby affecting the accuracy of the output voltage Vout, and the on-resistance of the switches changes with the change of the input digital code value, thereby affecting the linearity of the output voltage Vout.

[0006] Therefore, a new R-2R ladder resistor network architecture digital to analog converter needs to be proposed to solve the above problems. SUMMARY

[0007] In view of the above problems, the purpose of the present application is to provide a digital to analog converter, so as to improve the output accuracy of the digital to analog converter.

[0008] According to an aspect of the present application, there is provided a digital-to-analog converter, comprising a first conversion module configured to generate an analog signal corresponding to a plurality of input digital code values, the first conversion module comprising an R-2R ladder network architecture comprising a plurality of first resistance branches and a plurality of impedance matching modules, wherein each impedance matching module comprises a first transistor and a first resistance connected in series, and the digital-to-analog converter further comprises a second conversion module configured to generate a plurality of node control voltages corresponding to the plurality of impedance matching modules according to the plurality of digital code values, each node control voltage being configured to control the turn-on and turn-off of the first transistor in the corresponding impedance matching module.

[0009] Optionally, the second conversion module further comprises a plurality of charge pump modules corresponding to the plurality of node control voltages, wherein the input end of each charge pump module is connected to the corresponding node control voltage, and the output end of each charge pump module is connected to the control end of the first transistor in the impedance matching module corresponding to the node control voltage.

[0010] Optionally, the plurality of impedance matching modules are connected in series, the first end of a first first resistance branch is connected to the first end of a second first resistance branch, the second end of the first first resistance branch is connected to a first reference voltage, and the second to last first resistance branch is selectively connected to the first reference voltage or a second reference voltage according to the corresponding digital code.

[0011] Optionally, each first resistance branch comprises a second resistance and a first switch connected in series, and the first end of the first resistance branch is the end of the second resistance not connected to the first switch.

[0012] Optionally, the first switch is a gate voltage bootstrap switch, and the first transistor is an NMOS transistor.

[0013] Optionally, the sum of the on-resistance of the first switch and the resistance of the second resistance of each first resistance branch is twice the sum of the on-resistance of the first transistor and the resistance of the first resistance of each impedance matching module.

[0014] Optionally, the on-resistance of each first switch is twice the on-resistance of each first transistor, and the resistance of each second resistance is twice the resistance of each first resistance.

[0015] Optionally, the second conversion module further comprises an R-2R ladder network architecture comprising a plurality of second resistance branches and a plurality of third resistances.

[0016] Optionally, the plurality of third resistors are connected in series, the first end of the first second resistor branch is connected to the first end of the second second resistor branch, the second end of the first second resistor branch is connected to the first reference voltage, the second to last second resistor branch, the first end of two adjacent second resistor branches is connected with a third resistor, the second end of the second to last second resistor branch is selectively connected to the first reference voltage or the second reference voltage according to the corresponding digital code, and the plurality of node control voltages are provided by the common nodes of the second resistor branches and the third resistors.

[0017] Optionally, the first second resistor branch comprises a fourth resistor connected between the first end and the second end, and each of the second resistor branches comprises the fourth resistor and a second switch connected in series, and the end of the fourth resistor not connected to the second switch is the first end of the second resistor branch.

[0018] The digital-to-analog converter provided by the embodiment of the present application comprises a first conversion module and a second conversion module, and the resistance of the impedance matching module of the first conversion module is matched with the resistance of the first resistor branch. When performing digital-to-analog conversion, the plurality of input digital code values are provided to the second conversion module, thereby obtaining a plurality of node control voltages, and then the first transistors of the corresponding impedance matching modules are controlled to be turned on by the plurality of node control voltages, thereby starting the first conversion module, so that the first conversion module can generate a corresponding analog signal according to the plurality of digital code values, thereby improving the output precision of the digital-to-analog converter.

[0019] In the preferred embodiment, the plurality of node control voltages are provided to the control ends of the first transistors of the corresponding impedance matching modules through a plurality of charge pump modules, so that the on-resistance of the first transistors does not change with the change of the input signal.

[0020] In the preferred embodiment, the first switch of the first resistor branch adopts a gate voltage self-boosting switch, so that the on-resistance of the first switch does not change with the change of the input digital code value, thereby further improving the output precision and linearity of the digital-to-analog converter. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0022] FIG. 1 shows a circuit schematic diagram of a digital-to-analog converter of the prior art;

[0023] FIG. 2 shows an equivalent circuit diagram of the digital-to-analog converter in FIG. 1;

[0024] FIG. 3 shows a structural schematic diagram of a digital-to-analog converter according to an embodiment of the present application;

[0025] Fig. 4 shows a circuit schematic diagram of a digital-to-analog converter according to an embodiment of the application;

[0026] Fig. 5 shows an equivalent circuit diagram of a first conversion module in a digital-to-analog converter according to an embodiment of the application. DETAILED DESCRIPTION

[0027] Various embodiments of the present application will be described in detail with reference to the accompanying drawings. In the various drawings, like reference numerals refer to like elements or modules throughout. The drawings are not drawn to scale for the sake of clarity.

[0028] It should be understood that, in the following description, "circuitry" can include a single or multiple components of hardware, programmable circuitry, state machine circuitry, and / or elements storing instructions to be executed by the programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled to the other element or can have intervening elements between it and the other element, and the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there is no intervening element between them.

[0029] Meanwhile, certain terms have been used throughout this patent document and claims to refer to particular components. As one skilled in the art will appreciate, manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the specification and claims, the terms "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" can be used to indicate that two or more elements are in direct physical or logical contact with each other, while "coupled" can be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or logical contact with each other.

[0030] Furthermore, it should be understood that the terms "first", "second", etc. are used herein only to distinguish one element from other elements, and do not imply the existence of a relationship or order between the elements. Also, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements in the list, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0031] Fig. 3 shows a structural schematic diagram of a digital-to-analog converter according to an embodiment of the application.

[0032] Referring to FIG. 3, the digital-to-analog converter provided by the embodiment of the present application comprises a first conversion module 100 and a second conversion module 200. The first conversion module 100 and the second conversion module 200 have the same number of bits, which is N bits, where N is an arbitrary positive integer.

[0033] Referring to FIG. 3, the first conversion module 100 and the second conversion module 200 are connected, and the second conversion module 200 receives a multi-bit digital code value [d0-d(N-1)].

[0034] The first conversion module 100 receives the multi-bit digital code value [d0-d(N-1)], and obtains a corresponding analog signal Vout according to the multi-bit digital code value [d0-d(N-1)], where the analog signal Vout is the output voltage of the digital-to-analog converter.

[0035] FIG. 4 shows a circuit schematic diagram of the digital-to-analog converter according to the embodiment of the present application, and FIG. 5 shows an equivalent circuit diagram of the first conversion module in the digital-to-analog converter according to the embodiment of the present application.

[0036] Referring to FIG. 4, the first conversion module 100 comprises an R-2R ladder resistance network architecture composed of a plurality of first resistance branches and a plurality of impedance matching modules, where each impedance matching module comprises a first transistor M2i (i∈[1,N-1]) and a first resistance R2i connected in series, and each first resistance branch comprises a second resistance R1j (j∈[0,N]) and a first switch S1j connected in series.

[0037] Specifically, each significant bit of the first conversion module 100 comprises a first resistance branch. Except for the last significant bit (the most significant bit, MSB), each significant bit further comprises an impedance matching module, and the plurality of impedance matching modules are connected in series. Each impedance matching module is connected between the first end of the first resistance branch of the significant bit and the first end of the first resistance branch of the bit higher than the significant bit. The first conversion module 100 further comprises a non-significant bit, which comprises a first resistance branch. The second resistance R1j of each significant bit, which is not connected to the first switch S1j, has one end as the first end of the first resistance branch. The first resistance branches from the non-significant bit to the most significant bit are the first first resistance branch, the second first resistance branch, and the last first resistance branch in sequence.

[0038] In the embodiment of the present application, the first transistor M2i of the first to the (N-1)th significant bits of the first conversion module 100 are M21, M22, …, M2(N-1) in sequence, and the first resistor R2i of the first to the (N-1)th significant bits are R21, R22, …, R2(N-1) in sequence. The second resistor R1j of the first to the Nth significant bits are R11, R12, …, R1N in sequence, and the first switch S1j of the first to the Nth significant bits are S11, S12, …, S1N in sequence. The digital code value of the first to the Nth significant bits are d0, d1, …, d(N-1) in sequence.

[0039] The first switch S1j of the first resistor branch of each significant bit of the first conversion module 100 selectively connects its second resistor R1j to the first reference voltage or the second reference voltage according to its corresponding digital code value. When the digital code values [d0-d(N-1)] are input to the first conversion module 100, the second resistor R10 of the non-significant bit is connected to the first reference voltage. The first reference voltage is, for example, the ground voltage, and the second reference voltage is, for example, the reference voltage Vref, which is greater than the ground voltage.

[0040] Referring to FIG. 5, when the first switch S1j is turned on, the voltage of one end (hereinafter referred to as the first end) of the first switch S1j connected to the first reference voltage or the second reference voltage is Vref*di (i∈[0,N-1]). The voltage of one end of the first switch S10 not connected to the second resistor R10 of the non-significant bit is 0.

[0041] Taking the first significant bit (the least significant bit, LSB) of the first conversion module 100 as an example, if the digital code value d0 received by the first switch S11 of the first significant bit is 1, the second resistor R11 of the first significant bit is connected to the reference voltage Vref, at this time, the first end voltage of the first switch S11 is 1*Vref, and if the digital code value d0 received by the first switch S11 of the first significant bit is 0, the second resistor R11 of the first significant bit is connected to the reference ground, at this time, the first end voltage of the first switch S11 is 0*Vref.

[0042] Further, the sum of the on-resistance r1j of the first switch S1j and the resistance value of the second resistor R1j of each first resistor branch is twice the sum of the on-resistance r2i of the first transistor M2i and the resistance value of the first resistor R2i of each impedance matching module.

[0043] Further, the resistance value of the second resistor R1j of any first resistor branch is equal, and the on-resistance of the first switch S1j of any first resistor branch is equal. The resistance value of the first resistor R2i of any impedance matching module is equal, and the on-resistance of the first transistor M2i of any impedance matching module is equal.

[0044] Further, the on-resistance of the first switch S1j is twice the on-resistance of the first transistor M2i. For example, this can be achieved by setting the size of the first transistor M2i to be twice the size of the first switch S1j.

[0045] Further, the resistance of the second resistor R1j is twice the resistance of the first resistor R2i

[0046] Further, the first switch S1j is a gate voltage bootstrap switch, so that its on-resistance does not change with the input digital code value.

[0047] Further, the first transistor M2i is implemented as an NMOS (N-type Metal-Oxide-Semiconductor Field-Effect Transistor).

[0048] The first end of the first resistor R1N of the last significant bit of the first conversion module 100 provides the output voltage Vout of the digital-to-analog converter. Assuming that the on-resistance of the first switch S1j is 2r, the on-resistance of the first transistor M2i is r, the resistance of the second resistor R1j is 2R, and the resistance of the first resistor R2i is R, the equivalent impedance of the output voltage Vout is R+r, and the formula of the output voltage Vout can be expressed as: The second conversion module 200 is configured to obtain a plurality of node control voltages 5i-5(N-1) corresponding to the plurality of impedance matching modules of the first conversion module 100 according to a plurality of input digital code values [d0-d(N-1)], and each node control voltage 5i (i∈[1,N-1]) is configured to control the on and off of the first transistor M2i of the corresponding impedance matching module.

[0049] The second conversion module 200 includes a plurality of charge pump modules 6i-6(N-1) corresponding to the plurality of node control voltages 5i-5(N-1), the input end of each charge pump module 6i is connected to the corresponding node control voltage 5i, and the output end is connected to the control end of the first transistor M2i of the impedance matching module corresponding to the node control voltage 5i. In the present application, the charge pump module 6i can be implemented by any charge pump circuit in the prior art.

[0050] The second conversion module 200 further comprises an R-2R ladder resistance network architecture composed of a plurality of second resistance branches and a plurality of third resistances R4i. The first second resistance branch comprises a fourth resistance R30 connected between the first end and the second end. In addition to the first second resistance branch, each second resistance branch comprises a fourth resistance R3t (t∈[1, N]) and a second switch S3t connected in series, and a plurality of third resistances R4i are connected in series, and a third resistance R4i is connected between the first ends of two adjacent second resistance branches, and the first end of the second resistance branch refers to the end of the fourth resistance R3t not connected to the second switch S3t. The common node of the second resistance branch and the third resistance R4i provides the plurality of node control voltages 51-5(N-1).

[0051] Specifically, each significant bit of the second conversion module 200 comprises a second resistance branch. In addition to the last significant bit (the most significant bit, MSB), each significant bit further comprises a third resistance R4i. The fourth resistance R3t of each significant bit is connected to its third resistance R4i.

[0052] In the embodiment of the present application, the third resistances R4i of the first to the (N-1)th significant bits of the second conversion module 200 are R41, R42, …, R4(N-1) in turn. The fourth resistances R3t of the first to the Nth significant bits are R31, R32, …, R3N in turn, and the second switches S3t of the first to the Nth significant bits are S31, S32, …, S3N in turn. The digital code values of the first to the Nth significant bits are d0, d1, …, d(N-1) in turn.

[0053] In addition to the last significant bit, the common node of the second resistance branch and the third resistance R4i of each significant bit of the second conversion module 200 generates a node control voltage 5i. The corresponding relationship between the node control voltage 5i and the significant bit of the second conversion module 200 is that the first significant bit (the least significant bit, LSB) generates a node control voltage 51, the second significant bit generates a node control voltage 52, …, and the (N-1)th significant bit generates a node control voltage 5(N-1). The corresponding relationship between the plurality of node control voltages 51-5(N-1) and the first transistors M21-M2(N-1) in the plurality of impedance matching modules is that the node control voltage 51 corresponds to the first transistor M21, the node control voltage 52 corresponds to the first transistor M22, …, and the node control voltage 5(N-1) corresponds to the first transistor M2(N-1).

[0054] In addition to the last significant bit, each significant bit of the second conversion module 200 further comprises a charge pump module 6i connected to its node control voltage 5i.

[0055] The second switch S3t of the second resistance branch of each effective bit of the second conversion module 200 selectively connects the fourth resistance R3t thereof to the first reference voltage or the second reference voltage according to the corresponding digital code value. The first reference voltage is, for example, the ground voltage, and the second reference voltage is, for example, the reference voltage Vref, which is greater than the ground voltage.

[0056] Referring to FIG. 5, when the second switch S3t is turned on, the voltage of one end (hereinafter referred to as the first end) of the first reference voltage or the second reference voltage connected by the second switch S3t of each effective bit of the second conversion module 200 is Vref*di (i∈[0,N-1]).

[0057] Taking the first effective bit of the second conversion module 200 as an example, if the digital code value d0 received by the second switch S31 of the first effective bit is 1, the fourth resistance R31 of the first effective bit is connected to the reference voltage Vref, at this time, the first end voltage of the second switch S31 is 1*Vref, and if the digital code value d0 received by the second switch S31 of the first effective bit is 0, the fourth resistance R31 of the first effective bit is connected to the reference ground, at this time, the first end voltage of the second switch S31 is 0*Vref.

[0058] Further, the resistance value of the fourth resistance R3t of each second resistance branch is twice the resistance value of each third resistance R4i.

[0059] Further, the second switch S3t can be implemented by a CMOS transmission gate.

[0060] The digital-to-analog converter provided by the embodiment of the present application comprises a first conversion module 100 and a second conversion module 200, and the resistance of the impedance matching module of the first conversion module 100 matches the resistance of the first resistance branch. When performing digital-to-analog conversion, the input multiple digital code values [d0-d(N-1)] are provided to the second conversion module 200, thereby obtaining multiple node control voltages 51-5(N-1), and the first transistors M2i of the corresponding impedance matching modules are controlled to be turned on by the multiple node control voltages 5i, so that the first conversion module 100 can generate a corresponding analog signal Vout according to the multiple digital code values [d0-d(N-1)], and the analog signal is the output voltage Vout of the digital-to-analog converter, so that the output analog voltage Vout satisfies the above formula (2) without considering the influence of the multiple digital code values [d0-d(N-1)], thereby improving the output accuracy of the digital-to-analog converter.

[0061] Further, the multiple node control voltages 5i are provided to the control end of the first transistor M2i after passing through the charge pump module 6i, so that the on-resistance of the first transistor M2i does not change with the change of the input signal.

[0062] Further, the first switch S1j of the first resistance branch is a gate voltage self-boosting switch, so that the on-resistance of the first switch S1j does not change with the change of the input digital code value, thereby further improving the output accuracy and linearity of the digital-to-analog converter.

[0063] In accordance with the embodiments of the present application as described above, the embodiments are not described in detail with all of the details and are not limited to the specific embodiments. Obviously, many modifications and variations can be made in light of the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The scope of protection of the present application should be defined by the scope of the claims of the present application and their equivalents.

Claims

1. A digital-to-analog converter, comprising: The first conversion module is used to obtain the corresponding analog signal based on the multiple input digital code values. The first conversion module includes an R-2R ladder resistor network architecture composed of multiple first resistor branches and multiple impedance matching modules. Each impedance matching module includes a first transistor and a first resistor connected in series, and the digital-to-analog converter further includes: The second conversion module is used to obtain multiple node control voltages corresponding to multiple impedance matching modules based on the multiple digital code values. Each node control voltage is used to control the conduction and cutoff of the first transistor in the corresponding impedance matching module.

2. The digital-to-analog converter according to claim 1, wherein, The second conversion module also includes multiple charge pump modules corresponding to multiple node control voltages. The input terminal of each charge pump module is connected to the corresponding node control voltage, and the output terminal is connected to the control terminal of the first transistor in the impedance matching module corresponding to the node control voltage.

3. The digital-to-analog converter according to claim 1, wherein, Multiple impedance matching modules are connected in series. The first terminal of the first resistor branch is connected to the first terminal of the second resistor branch, and the second terminal of the first resistor branch is connected to the first reference voltage. For the second to last resistor branches, an impedance matching module is provided between the first ends of the two adjacent first resistor branches, and the second ends of the second to last resistor branches are selectively connected to the first reference voltage or the second reference voltage according to the corresponding digital code.

4. The digital-to-analog converter according to claim 3, wherein, Each of the first resistor branches includes a second resistor and a first switch connected in series, wherein the end of the second resistor not connected to the first switch is the first end of the first resistor branch.

5. The digital-to-analog converter according to claim 4, wherein, The first switch is a gate voltage bootstrap switch, and the first transistor is an NMOS transistor.

6. The digital-to-analog converter according to claim 5, wherein, The sum of the on-resistance of the first switch in each of the first resistor branches and the resistance of the second resistor is twice the sum of the on-resistance of the first transistor and the resistance of the first resistor in each impedance matching module.

7. The digital-to-analog converter according to claim 5, wherein, The on-resistance of each of the first switches is twice that of each of the first transistors, and the resistance of each of the second resistors is twice that of each of the first resistors.

8. The digital-to-analog converter according to claim 2, wherein, The second conversion module also includes an R-2R ladder resistor network architecture consisting of multiple second resistor branches and multiple third resistors.

9. The digital-to-analog converter according to claim 8, wherein, Multiple third resistors are connected in series. The first terminal of the first second resistor branch is connected to the first terminal of the second second resistor branch, and the second terminal of the first second resistor branch is connected to the first reference voltage. The second to last second resistor branch has a third resistor connected between the first ends of two adjacent second resistor branches. The second ends of the second to last second resistor branches are selectively connected to the first reference voltage or the second reference voltage according to the corresponding digital code. The control voltage of multiple nodes is provided by the common node of the second resistor branch and the third resistor.

10. The digital-to-analog converter according to claim 9, wherein, The first second resistor branch includes a fourth resistor connected between the first end and the second end. Except for the first second resistor branch, each second resistor branch includes a fourth resistor and a second switch connected in series. The end of the fourth resistor that is not connected to the second switch is the first end of the second resistor branch.

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