Power semiconductor module and power conversion device

Abstract

This power semiconductor module may comprise: a first substrate having a first region and a second region at a first side of the first region; a power semiconductor element disposed over the first region of the first substrate; a second substrate disposed over the power semiconductor element; and a first terminal disposed over the second region of the first substrate and horizontally overlapping the second substrate. The upper surface of the first terminal and the upper surface of the second substrate may be parallel.

Description

Power semiconductor modules and power conversion devices

[0001] The present disclosure relates to a power semiconductor module and a power conversion device.

[0002] Unlike system semiconductors or memory that process and store information or signals, power semiconductor devices are core components that convert, store, distribute, and control the power entering electronic devices, and are widely used in most electronic products.

[0003] In recent years, in line with the global trend toward strengthening environmental protection, eco-friendly vehicles such as electric and hydrogen-powered vehicles are gaining widespread attention, replacing conventional fossil fuel-powered vehicles. Eco-friendly vehicles utilize numerous power semiconductor components. Eco-friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0004] In particular, eco-friendly vehicles require high-current inverters, such as those capable of 200 to 900 A. The inverter comprises multiple power semiconductor modules to convert power. Each of the multiple power semiconductor modules comprises multiple power semiconductor elements.

[0005] As illustrated in Fig. 1, the power semiconductor device includes power semiconductor devices (30, 40). The plurality of power semiconductor devices (30, 40) are arranged between a first substrate (10) and a second substrate (20). A gate electrode (30a) and a source electrode (30b) of each of the first power semiconductor devices (30) are electrically connected to the second substrate (20), and a gate electrode (40a) and a source electrode (40b) of each of the second power semiconductor devices (40) are electrically connected to the first substrate (10).

[0006] Meanwhile, the power semiconductor module includes a terminal (or lead frame) (50) arranged between a first substrate (10) and a second substrate (20).

[0007] As previously mentioned, in power semiconductor modules employed in inverters for eco-friendly automobiles, the higher the current, the larger the cross-sectional area of ​​the terminal (50) must be. Typically, because the area of ​​the inverter is limited, the larger the required current, the thicker the terminal (50) becomes.

[0008] In this case, since the thickness of the terminal (50) is greater than the thickness of the power semiconductor element (30, 40), the upper or lower portion of the power semiconductor element (30, 40) is spaced apart from the first substrate (10) or the second substrate (20). To compensate for this spacing, a spacer (70, 80) is placed on the upper or lower portion of the power semiconductor element (30, 40), so there is a problem that the thickness of the power semiconductor module increases. In addition, since a spacer (70, 80) is provided for each of the power semiconductor elements (30, 40), as the number of power semiconductor elements (30, 40) increases, the number of spacers (70, 80) also increases, so there is a problem that the material cost increases.

[0009] The present disclosure is intended to solve the above-mentioned and other problems.

[0010] Accordingly, the present disclosure provides a power semiconductor module and a power conversion device capable of reducing thickness.

[0011] In addition, the present disclosure provides a power semiconductor module and a power conversion device capable of reducing material costs.

[0012] In addition, the present disclosure provides a higher power semiconductor module and power conversion device.

[0013] The present disclosure is not limited to what has been described, but includes things that can be understood through the description of the disclosure.

[0014] According to one aspect of the present disclosure to achieve the above or other purposes, a power semiconductor module includes a first substrate having a first region and a second region on a first side of the first region; a power semiconductor element disposed on the first region of the first substrate; a second substrate disposed on the power semiconductor element; and a first terminal disposed on the second region of the first substrate and horizontally overlapping the second substrate; wherein an upper surface of the first terminal and an upper surface of the second substrate are parallel.

[0015] The power semiconductor module may include a support molding portion that extends from a first side of the first substrate and supports at least a portion of the lower portion of the first terminal.

[0016] A step portion is formed on the upper surface of the second region, and the first terminal can be coupled to the step portion.

[0017] The first substrate includes an insulating layer; a first metal layer disposed on an upper side of the insulating layer; and a second metal layer disposed on a lower side of the insulating layer; and the step portion may be provided in the first metal layer.

[0018] The first substrate may further have a third region on a second side of the first region. The power semiconductor module may further include a second terminal disposed on the third region of the first substrate and horizontally overlapping the second substrate.

[0019] The second substrate may be provided between the second region and the third region.

[0020] The second substrate may have a third region on the first region and a fourth region extending horizontally from the third region. The power semiconductor module may include a second terminal disposed on a lower side of the fourth region and horizontally overlapping the first substrate.

[0021] According to another aspect of the present disclosure, a power semiconductor module includes a first substrate having a first region and a second region on a first side of the first region; a power semiconductor element disposed on the first region of the first substrate; a second substrate disposed on the power semiconductor element; a first terminal disposed on the second region of the first substrate and horizontally overlapping the second substrate; and a molding portion extending from one side of the second substrate and covering at least a portion of an upper surface of the first terminal, wherein an upper surface of the molding portion and an upper surface of the second substrate are parallel.

[0022] The power semiconductor module may include a support molding portion that extends from a first side of the first substrate and supports at least a portion of the lower portion of the first terminal.

[0023] A step portion is formed on the upper surface of the second region, and the first terminal can be coupled to the step portion.

[0024] The first substrate includes an insulating layer; a first metal layer disposed on an upper side of the insulating layer; and a second metal layer disposed on a lower side of the insulating layer; and the step portion may be provided in the first metal layer.

[0025] The above first substrate may further have a third region on the second side of the above first region.

[0026] The power semiconductor module may further include a second terminal disposed on the third region of the first substrate and horizontally overlapping the second substrate.

[0027] The second substrate may be provided between the second region and the third region.

[0028] According to another aspect of the present disclosure, a power conversion device includes the power semiconductor module.

[0029] The effects of the power semiconductor module and power conversion device according to the above aspects are described as follows.

[0030] According to at least one of the above aspects, there is an advantage in that material costs can be reduced because no spacer is required.

[0031] According to at least one of the above aspects, there is an advantage that the thickness can be reduced because no spacer is required.

[0032] According to at least one of the above aspects, there is an advantage in that a higher power semiconductor module can be implemented by increasing the thickness of the first terminal and / or the second terminal without increasing the overall thickness.

[0033] According to at least one of the above aspects, there is an advantage in that the process is simplified and the process time can be shortened because a lead frame is not used.

[0034] The accompanying drawings are included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. Furthermore, the accompanying drawings may serve to illustrate features of the present disclosure and, together with the description of the disclosure, to explain the principles of the present disclosure.

[0035] In the drawing:

[0036] Figure 1 is a cross-sectional view illustrating a conventional power semiconductor module.

[0037] FIG. 2 is a circuit diagram illustrating an inverter according to one aspect of the present disclosure.

[0038] FIG. 3 is a plan view illustrating a power semiconductor module according to the first aspect of the present disclosure.

[0039] FIG. 4 is a cross-sectional view illustrating a power semiconductor module according to the second aspect of the present disclosure.

[0040] FIG. 5 is a cross-sectional view illustrating a power semiconductor module according to a third aspect of the present disclosure.

[0041] Fig. 6 is a perspective view illustrating the first substrate (210) of Fig. 5.

[0042] FIG. 7 is a cross-sectional view illustrating a power semiconductor module according to the fourth aspect of the present disclosure.

[0043] FIG. 8 is a plan view illustrating a power semiconductor module according to the fifth aspect of the present disclosure.

[0044] FIG. 9 is a cross-sectional view illustrating a power semiconductor module according to the sixth aspect of the present disclosure.

[0045] The sizes, shapes, and dimensions of components depicted in the drawings may differ from the actual components. Furthermore, even if the same components are depicted with different sizes, shapes, and dimensions across drawings, this is merely an example within the drawings, and the same components may have the same sizes, shapes, and dimensions across drawings.

[0046] Hereinafter, aspects disclosed in the present specification will be described in detail with reference to the attached drawings, and regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' used for components in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to facilitate easy understanding of aspects disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element, or that other intermediate elements may exist therebetween.

[0047] FIG. 2 is a circuit diagram illustrating an inverter according to one aspect of the present disclosure.

[0048] Referring to FIG. 2, an inverter (1000) according to one aspect of the present disclosure may be applied to applications such as three-phase motors or compressors. The inverter (1000) may output three-phase power. The inverter (1000) may be a power conversion device or may be included in a power conversion device. The inverter (1000) may include a switching circuit.

[0049] An inverter (1000) according to one aspect of the present disclosure can convert DC power into AC power and supply the converted AC power to a load (1200) to drive the load. In the inverter (1000) according to one aspect of the present disclosure, a converter may be connected to the input side to convert AC power into DC power. In this case, the DC power converted by the converter can be converted into AC power by the inverter (1000) and then used to drive the load (1200). The load (1200) may be a motor or an electric motor, but is not limited thereto.

[0050] An inverter (1000) according to one aspect of the present disclosure may include, but is not limited to, a three-phase inverter. In this case, a phase difference of 120 degrees may be present between the first phase, the second phase, and the third phase. An inverter (1000) according to one aspect of the present disclosure may include a plurality of legs (100A, 100B, 100C). For example, the first leg (100A), the second leg (100B), and the third leg (100C) may be connected in parallel to a load (1200), i.e., a motor, through a first node (N1), a second node (N2), and a third node (N3), respectively. The first leg (100A) may include a first arm (100a) and a second arm (100b) that are connected in series to each other, the second leg (100B) may include a third arm (100c) and a fourth arm (100d) that are connected in series to each other, and the third leg (100C) may include a fifth arm (100e) and a sixth arm (100f) that are connected in series to each other. Here, the first arm (100a), the third arm (100c), and the fifth arm (100e) may be referred to as upper arms, and the second arm (100b), the fourth arm (100d), and the sixth arm (100f) may be referred to as lower arms. Each of the first arm (100a) to the sixth arm (100f) may be referred to as a switching module, a submodule, or the like.

[0051] The first arm (100a) to the sixth arm (100f) may each include switching units (Q1 to Q6) and diodes (100a-2 to 100f-2). The switching units (Q1 to Q6) and the diodes (100a-2 to 100f-2) may be formed simultaneously using the same semiconductor process. The switching units (Q1 to Q6) may include power semiconductor devices.

[0052] In order for DC power to be converted into AC power by the inverter (1000) according to one aspect of the present disclosure, the switching units (Q1 to Q6) of each of the first arm (100a) to the sixth arm (100f) can be controlled to turn on / off.

[0053] For example, when the first switching unit (Q1) of the first arm (100a) of the first leg (100A) is in the ON state, the fourth switching unit (Q4) of the fourth arm (100d) of the second leg (100B) and / or the sixth switching unit (Q6) of the sixth arm (100f) of the third leg (100C) may be in the ON state. Accordingly, DC power may be supplied to the first phase inductor of the motor.

[0054] For example, when the third switching unit (Q3) of the third arm (100c) of the second leg (100B) is turned on, the sixth switching unit (Q6) of the sixth arm (100f) of the third leg (100C) and / or the second switching unit (Q2) of the second arm (100b) of the first leg (100A) may be turned on. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be 120 degrees behind the first phase.

[0055] For example, when the fifth switching unit (Q5) of the fifth arm (100e) of the third leg (100C) is turned on, the second switching unit (Q2) of the second arm (100b) of the first leg (100A) and / or the fourth switching unit (Q4) of the fourth arm (100d) of the second leg (100B) may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be 120 degrees behind the second phase.

[0056] Accordingly, AC power can be generated by DC power supplied to each of the first phase inductor, the second phase inductor, and the third inductor.

[0057] Meanwhile, although not shown, in order to increase the internal pressure characteristics, the switching units of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple numbers, each connected in series with each other.

[0058] Although not shown, in order to increase the current characteristics, the switching units of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple units connected in parallel with each other.

[0059] Meanwhile, the switching units (Q1 to Q6) and diodes (100a-2 to 100f-2) constituting the first arm (100a) to the sixth arm (100f) can be packaged to form a power semiconductor module.

[0060] As an example, the first leg (100A), the second leg (100B), and the third leg (100C) may be configured as a first power semiconductor module, a second power semiconductor module, and a third power semiconductor module, respectively. For example, the first arm (100a) and the second arm (100b) of the first leg (100A) may be packaged to form a first power semiconductor module. For example, the third arm (100c) and the fourth arm (100d) of the second leg (100B) may be packaged to form a second power semiconductor module. For example, the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) may be packaged to form a third power semiconductor module.

[0061] As another example, the first leg (100A), the second leg (100B), and the third leg (100C) may be configured as a single power semiconductor module. That is, the first arm (100a) and the second arm (100b) of the first leg (100A), the third arm (100c) and the fourth arm (100d) of the second leg (100B), and the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) may be single-packaged to form a single power semiconductor module.

[0062] Meanwhile, VDC represents the input voltage, which can be, for example, DC voltage. CDC represents a capacitor that can charge the input voltage (VDC).

[0063] Fig. 3 is a plan view illustrating a power semiconductor module according to the first aspect of the present disclosure. Fig. 4 is a cross-sectional view illustrating a power semiconductor module according to the second aspect of the present disclosure. The cross-sectional view illustrated in Fig. 4 may be a view taken along line AA' of the power semiconductor module of Fig. 3.

[0064] Referring to FIGS. 3 and 4, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a first terminal (250), and a molding portion (265).

[0065] The first substrate (210) and the second substrate (220) may each include an insulating layer (211, 221), a first metal layer (213, 223), a second metal layer (215, 225), etc. The insulating layers (211, 221) may be made of a material having excellent insulating properties, heat transfer properties, and / or heat dissipation properties. For example, the insulating layers (211, 221) may be made of an inorganic material, a ceramic material, an alumina material, a plastic material, a glass material, etc.

[0066] The first metal layer (213, 223) may include a plurality of circuit patterns. The plurality of circuit patterns may be electrically connected to the first power semiconductor element (230) and the second power semiconductor element (240). To this end, the first metal layer (213, 223) may be formed of a metal material having excellent electrical conductivity. For example, the first metal layer (213, 223) may have a single-layer structure or a multi-layer structure made of copper (Cu), gold (Au), aluminum (Al), platinum (Pt), or the like.

[0067] The second metal layer (215, 225) can quickly discharge heat generated from the first power semiconductor element (230) and the second power semiconductor element (240) to the outside. Therefore, the second metal layer (215, 225) can be formed of a material having excellent heat dissipation properties. For example, the second metal layer (215, 225) can be aluminum (Al) or an aluminum alloy, but is not limited thereto. The second metal layer (215, 225) can be called a heat dissipation layer or a heat dissipation plate.

[0068] The first power semiconductor element (230) and the second power semiconductor element (240) may be disposed between the first substrate (210) and the second substrate (220). The first power semiconductor element (230) and the second power semiconductor element (240) may be bonded to the first substrate (210) and the second substrate (220), respectively, using a flip-chip bonding method, but this is not limited thereto.

[0069] In the present disclosure, the first power semiconductor element (230) and the second power semiconductor element (240) may each include at least two power semiconductor elements. The two or more power semiconductor elements may be connected in parallel with each other, but this is not limited thereto.

[0070] The first power semiconductor element (230) may include a first semiconductor layer (231), a first drain electrode (234), a first gate electrode (232), a first source electrode (233), etc. The second power semiconductor element (240) may include a second semiconductor layer (241), a second drain electrode (244), a second gate electrode (242), and a second source electrode (243).

[0071] The first semiconductor layer (231) and the second semiconductor layer (241) can be formed using a semiconductor process on a substrate based on a semiconductor compound such as SiC, GaN, or Ga2O3. At this time, the substrate is a growth substrate and can include a sapphire substrate, a compound semiconductor substrate such as GaN, a ceramic series substrate, etc.

[0072] In the first power semiconductor element (230), the first drain electrode (234) may be disposed on the lower side of the first semiconductor layer (231), and the first gate electrode (232) and the first source electrode (233) may be disposed on the upper side of the first semiconductor layer (231). The first drain electrode (234) of the first power semiconductor element (230) may be electrically connected to the first substrate (210), and the first gate electrode (232) and the first source electrode (233) of the first power semiconductor element (230) may be electrically connected to the second substrate (220).

[0073] Since the first gate electrode (232) and the first source electrode (233) are disposed on the same surface of the first semiconductor layer (231), the first gate electrode (232) and the first source electrode (233) can be positioned spaced apart from each other so that a short circuit does not occur between them. Since the first gate electrode (232) and the first source electrode (233) are disposed on the same surface of the first semiconductor layer (231), the first power semiconductor element (230) can have a flip-chip structure.

[0074] The second drain electrode (244) may be disposed on the lower side of the second semiconductor layer (241), and the second gate electrode (242) and the second source electrode (243) may be disposed on the upper side of the second semiconductor layer (241). The second drain electrode (244) of the second power semiconductor element (240) may be electrically connected to the second substrate (220), and the second gate electrode (242) and the second source electrode (243) of the second power semiconductor element (240) may be electrically connected to the first substrate (210).

[0075] Since the second gate electrode (242) and the second source electrode (243) are disposed on the same surface of the second semiconductor layer (241), the second gate electrode (242) and the second source electrode (243) can be positioned spaced apart from each other so that a short circuit does not occur between them. Since the second gate electrode (242) and the second source electrode (243) are disposed on the same surface of the second semiconductor layer (241), the second power semiconductor element (240) can have a flip-chip structure.

[0076] Meanwhile, as described above, the first metal layer (213, 223) in the first substrate (210) and the second substrate (220) may include a plurality of circuit patterns.

[0077] The second substrate (220) may include a first circuit pattern, a second circuit pattern, a third circuit pattern, etc. In this case, the first gate electrode (232) of the first power semiconductor element (230) may be electrically connected to the first circuit pattern, and the first source electrode (233) may be connected to the second circuit pattern. In the second power semiconductor element (240), the second drain electrode (244) may be connected to the third circuit pattern.

[0078] The first substrate (210) may include a first circuit pattern to a fifth circuit pattern. In this case, the first drain electrode (234) of the first power semiconductor element (230) and the second source electrode (243) of the second power semiconductor element (240) may be electrically connected to the first circuit pattern. That is, the first drain electrode (234) of the first power semiconductor element (230) may be electrically connected to the second source electrode (243) of the second power semiconductor element (240) via the first circuit pattern. The second gate electrode (242) of the second power semiconductor element (240) may be electrically connected to the second circuit pattern.

[0079] Meanwhile, although not shown, a first connecting member for electrically connecting the first circuit pattern of the second substrate (220) and the third circuit pattern of the first substrate (210) may be disposed between the first substrate (210) and the second substrate (220). Accordingly, the first circuit pattern of the second substrate (220), which is connected to the first gate electrode (232) of the first power semiconductor element (230), may be electrically connected to the third circuit pattern of the first substrate (210) through the first connecting member.

[0080] Although not shown, a second connecting member for electrically connecting the second circuit pattern of the second substrate (220) and the fourth circuit pattern of the first substrate (210) may be disposed between the first substrate (210) and the second substrate (220). Accordingly, the second circuit pattern of the second substrate (220), which is connected to the first source electrode (233) of the first power semiconductor element (230), may be electrically connected to the fourth circuit pattern of the first substrate (210) through the second connecting member.

[0081] Although not shown, a third connecting member for electrically connecting the third circuit pattern of the second substrate (220) and the fifth circuit pattern of the first substrate (210) may be disposed between the first substrate (210) and the second substrate (220). Accordingly, the third circuit pattern of the second substrate (220), which is connected to the second drain electrode (244) of the second power semiconductor element (240), may be electrically connected to the fifth circuit pattern of the first substrate (210) through the third connecting member.

[0082] The first connecting member, the second connecting member, and the third connecting member may each include a post, clip, or the like having excellent electrical conductivity.

[0083] Meanwhile, the sizes of the first substrate (210) and the second substrate (220) may be different. For example, the size of the first substrate (210) may be larger than the size of the second substrate (220).

[0084] The first substrate (210) may have a first region (210-1) and a second region (210-2). The second region (210-2) may be positioned on the first side of the first region (210-1). In this case, the first power semiconductor element (230) and the second power semiconductor element (240) may be disposed on the first region (210-1) of the first substrate (210). For example, the size of the second substrate (220) may be the same as or similar to the size of the first region (210-1) of the first substrate (210). That is, the second substrate (220) may vertically overlap the first region (210-1) of the first substrate (210).

[0085] Meanwhile, referring again to FIGS. 3 and 4, the first terminal (250) may be placed on the second region (210-2) of the first substrate (210). In this case, the first terminal (250) may not vertically overlap the second substrate (220).

[0086] A plurality of first terminals (250) may be provided along the second direction (Y). The plurality of first terminals (250) may be electrically connected to some of the circuit patterns among the plurality of circuit patterns of the first substrate (210).

[0087] Since the first terminal (250) must have a large cross-sectional area, a high current must flow through it. However, since multiple first terminals (250) must be arranged within a preset area in the second direction (Y), it is difficult to increase the width, so the thickness (T11) increases.

[0088] Accordingly, the thickness (T11) of the first terminal (250) may be greater than the thickness of the first power semiconductor element (230) or the second power semiconductor element (240). For example, the thickness (T11) of the first terminal (250) may be equal to or greater than the sum of the thickness of the first power semiconductor element (230) (or the second power semiconductor element (240)) and the thickness of the second substrate (220). In this case, the first terminal (250) may horizontally overlap the second substrate (220). That is, the first terminal (250) may be positioned higher than the upper surface of the first power semiconductor element (230) (or the second power semiconductor (240)) and may be positioned so as to be level with the upper surface of the second substrate (220). In other words, the upper surface of the first terminal (250) and the upper surface of the second substrate (220) may be positioned on the same horizontal line. The upper surface of the first terminal (250) and the upper surface of the second substrate (220) can be parallel.

[0089] Meanwhile, as illustrated in Fig. 1, in a conventional power semiconductor module, a terminal (50) larger than the thickness of the power semiconductor element (30, 40) is placed between the first substrate (10) and the second substrate (20). In this case, a spacer (70, 80) must be placed on the upper or lower portion of the power semiconductor element (30, 40). Accordingly, the thickness of the power semiconductor module increases and the material cost increases.

[0090] However, in the present disclosure, the size of the second substrate (220) is made smaller than the size of the first substrate (210), so that the first terminal (250) can be placed on the second region (210-2) of the first substrate (210) that does not vertically overlap with the second substrate (220). Therefore, a spacer is not required, so material costs can be reduced. In addition, even if a first terminal (250) having the same thickness as the existing one is employed, the thickness of the power semiconductor module can be reduced at least by the thickness of the existing spacer.

[0091] Meanwhile, the power semiconductor module may include a second terminal (260).

[0092] The second terminal (260) may be placed on the first substrate (210). For this purpose, the first substrate (210) may have a third region (210-3) adjacent to the first region (210-1). For example, the second region (210-2), the first region (210-1), and the third region (210-3) may be positioned in this order along the first direction (X). For example, the first region (210-1) may be positioned between the second region (210-2) and the third region (210-3). For example, the second substrate (220) may be provided between the second region (210-2) and the third region (210-3).

[0093] The second terminal (260) may be placed on the third region (210-3) of the first substrate (210). In this case, the second terminal (260) may not vertically overlap the second substrate (220).

[0094] A second terminal (260) may be provided in plurality along the second direction (Y). Among the plurality of circuit patterns of the first substrate (210), some of the circuit patterns may be electrically connected to the plurality of first circuit patterns, and the remaining circuit patterns, excluding some of the circuit patterns, may be electrically connected to the plurality of second circuit patterns.

[0095] A plurality of first terminals (250) and a plurality of second terminals (260) can be assigned as input terminals, power terminals, output terminals, etc.

[0096] The signal terminal may be a member for providing a gate signal (or switching control signal) to the gate electrode of each of the first power semiconductor element (230) and the second power semiconductor element (240) through the circuit pattern of the first substrate (210).

[0097] The power terminal may be a member for providing a first power voltage to a source electrode of a first power semiconductor element (230). The power terminal may be a member for providing a second power voltage to a drain electrode of a second power semiconductor element (240). The first power voltage may be higher than the second power voltage. The first power voltage may be referred to as a high-potential voltage, and the second power voltage may be referred to as a low-potential voltage.

[0098] The output terminal may be a member electrically connected to the first circuit pattern of the first substrate (210) to output an output voltage generated by turning on / off the first power semiconductor element (230) and the second power semiconductor element (240).

[0099] Since the second terminal (260) must have a large cross-sectional area because a high current must flow through it. However, since multiple second terminals (260) must be arranged within a preset area in the second direction (Y), it is difficult to increase the width, so the thickness increases.

[0100] Accordingly, the thickness (T12) of the second terminal (260) may be greater than the thickness of the first power semiconductor element (230) or the second power semiconductor element (240). For example, the thickness (T12) of the second terminal (260) may be equal to or greater than the sum of the thickness of the first power semiconductor element (230) (or the second power semiconductor element (240)) and the thickness of the second substrate (220). In this case, the second terminal (260) may horizontally overlap the second substrate (220). That is, the second terminal (260) may be positioned higher than the upper surface of the first power semiconductor element (230) (or the second power semiconductor (240)) and may be positioned so as to be level with the upper surface of the second substrate (220). In other words, the upper surface of the second terminal (260) and the upper surface of the second substrate (220) may be positioned on the same horizontal line. The upper surface of the second terminal (260) and the upper surface of the second substrate (220) can be parallel.

[0101] Alternatively, the first terminal (250) and / or the second terminal (260) may be positioned lower than the upper surface of the second substrate (220), so that the molding portion (265) may be positioned on the upper side of the first terminal (250) and / or the second terminal (260).

[0102] Meanwhile, as illustrated in Fig. 1, in a conventional power semiconductor module, a terminal (50) larger than the thickness of a power semiconductor element (30, 40) is disposed between the first substrate (10) and the second substrate (20). In this case, a spacer (70, 80) must be disposed on the upper or lower portion of the power semiconductor element (30, 40). Accordingly, the thickness of the power semiconductor module increases. In addition, when the power semiconductor module is equipped with eight first power semiconductor elements and eight power semiconductor elements, 16 spacers are required, which increases material costs.

[0103] However, in the present disclosure, the size of the second substrate (220) is made smaller than the size of the first substrate (210), so that the second terminal (260) can be placed on the third region (210-3) of the first substrate (210) that does not vertically overlap with the second substrate (220). Therefore, a spacer is not required, so material costs can be reduced. In addition, even if a second terminal (260) having the same thickness as the existing one is employed, the thickness of the power semiconductor module can be reduced at least by the thickness of the existing spacer.

[0104] Meanwhile, the first terminal and the second terminal do not need to be formed by processing the leaf frame. Conventionally, as illustrated in Fig. 1, a lead frame was placed on a first substrate (10) using a pick and place process, and the lead frame was cut using a cutting and bending process, thereby forming a terminal (50) on the first substrate (10).

[0105] In contrast, in the present disclosure, the first terminal and the second terminal may be individually manufactured conductive dot members, conductive clips, etc., in advance. Accordingly, since a conventional lead frame is not used, equipment or processes for performing the pick-and-place process, cutting, and bending processes are not required, thereby simplifying the process and shortening the process time.

[0106] Referring again to FIGS. 3 and 4, the molding portion (265) may be placed on the first substrate (210). The molding portion (265) may be formed to extend from one side of the second substrate (220) and cover at least a portion of the upper surface of the first terminal (250).

[0107] The molding portion (265) can surround the side of the first substrate (210). The molding portion (265) can be disposed on the first region (210-1), the second region (210-2), and the third region (210-3) of the first substrate (210). The molding portion (265) can surround the side of each of the first power semiconductor element (230) and the second power semiconductor element (240). The molding portion (265) can surround the side of the second substrate (220). The molding portion (265) can be disposed between the side of the first terminal (250) and the side of the first power semiconductor element (230). The molding portion (265) can be disposed between the side of the first terminal (250) and the side of the second substrate (220). The molding portion (265) may be disposed between the side of the second terminal (260) and the side of the second power semiconductor element (240). The molding portion (265) may be disposed between the side of the second terminal (260) and the side of the second substrate (220). The molding portion (265) may be formed of a resin material having excellent insulating performance. For example, the molding portion (265) may be formed of an EMC (Epoxy Molding Compound) molding material, but is not limited thereto. The EMC molding material may be a sealing material that protects the first power semiconductor element (230) and the second power semiconductor element (240) from heat, moisture, impact, insulation breakdown, etc.

[0108] Meanwhile, the molding part (265) may not be disposed on the upper side of the first terminal (250) and / or the second terminal (260), but this is not limited thereto. For example, the upper surface of the first terminal (250) and / or the second terminal (260) may be exposed to the outside. When the upper surface of the first terminal (250) and / or the second terminal (260) is exposed to the outside, electrical connection between the upper surface of the first terminal (250) and / or the second terminal (260) and the external power line is facilitated, thereby preventing defects that may occur during the electrical connection process. In addition, when the upper surface of the first terminal (250) and / or the second terminal (260) is exposed to the outside, a sufficient contact area for electrical connection with the external power line is secured, thereby preventing electrical disconnection due to contact defects and minimizing current loss.

[0109] Meanwhile, the power semiconductor module may include a support molding portion (270) that extends from the first side of the first substrate (210) and supports at least a portion of the lower portion of the first terminal (250). The support molding portion (270) may be formed of the same material as the molding portion (265) and may constitute a portion of the molding portion (265), but is not limited thereto.

[0110] Fig. 5 is a cross-sectional view illustrating a power semiconductor module according to a third aspect of the present disclosure. Fig. 6 is a perspective view illustrating the first substrate (210) of Fig. 5.

[0111] The cross-sectional view illustrated in Fig. 5 may be a view of the power semiconductor module of Fig. 3 cut along line AA'.

[0112] The third aspect of the present disclosure may be similar to the second aspect of the present disclosure (Fig. 4) except that the first substrate (210) is provided with a step portion (280, 285). Components having the same shape, structure, and / or function as those of the second aspect of the present disclosure (Fig. 4) in the third aspect of the present disclosure are given the same drawing reference numerals, and a detailed description thereof is omitted.

[0113] Referring to FIGS. 3 and 5, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a first terminal (250), a second terminal (260), and a molding portion (266). One of the first terminal (250) and the second terminal (260) may be omitted.

[0114] The first substrate (210) may have a first region (210-1), a second region (210-2), and a third region (210-3). The first power semiconductor element (230) and the second power semiconductor element (240) may be disposed on the first region (210-1) of the first substrate (210). The first terminal (250) may be disposed on the second region (210-2) of the first substrate (210), and the second terminal (260) may be disposed on the third region (210-3) of the first substrate (210). In addition, the first power semiconductor element (230) and the second power semiconductor element (240) may be disposed between the first substrate (210) and the second substrate (220).

[0115] Meanwhile, as illustrated in FIG. 6, the first substrate (210) may have a first step portion (280) having an upper surface (210-2a) of the second region (210-2) that is lower than an upper surface (210-1a) of the first region (210-1). For example, the first metal layer (213) corresponding to the first region (210-1) of the first substrate (210) may not be removed, and the upper surfaces of the first metal layers (213) corresponding to the second region (210-2) and the third region (210-3) of the first substrate (210) may be removed. Accordingly, a first step portion (280) having an upper surface (210-2a) of a second region (210-2) that is lower than an upper surface (210-1a) of a first region (210-1) and a second step portion (285) having an upper surface (210-3a) of a third region (210-3) that is lower than an upper surface (210-1a) of the first region (210-1) can be formed. The depth removed from the step portion can be set in consideration of the thickness of the first metal layer (213), the thickness (T11, T12) of each of the first terminal (250) and / or the second terminal (260), etc.

[0116] The first terminal (250) can be coupled to the first step (280), and the second terminal (260) can be coupled to the second step (285).

[0117] When the thickness (T11) of the first terminal (250) is the same as the thickness (T11) of the first terminal (250) in the second side (FIG. 4) of the present disclosure, the first terminal (250) may be positioned on the first step portion (280), so that the upper surface of the first terminal (250) may be positioned lower. That is, the upper surface of the first terminal (250) may be positioned lower than the upper surface of the second substrate (220). In this case, the molding portion (266) may be formed to extend from one side of the second substrate (220) and cover at least a portion of the upper surface of the first terminal (250). Since the molding portion (266) is positioned on the first terminal (250), the first terminal (250) may not be exposed to the outside. Accordingly, since the upper side of the first terminal (250) is covered by the molding part (266), the first terminal (250) can be protected from external foreign substances.

[0118] When the thickness (T12) of the second terminal (260) is the same as the thickness (T12) of the second terminal (260) in the second side (FIG. 4) of the present disclosure, the second terminal (260) may be positioned on the second step portion (285), so that the upper surface of the second terminal (260) may be positioned lower. That is, the upper surface of the second terminal (260) may be positioned lower than the upper surface of the second substrate (220). In this case, the molding portion (266) may be positioned on the second terminal (260), so that the second terminal (260) may not be exposed to the outside. Accordingly, since the upper side of the second terminal (260) is covered by the molding portion (266), the second terminal (260) may be protected from external foreign substances. The upper surface of the molding portion (266) and the upper surface of the second substrate (220) may be parallel, but this is not limited thereto.

[0119] Meanwhile, in FIG. 6, the first step portion (280) and the second step portion (285) may have the same shape along the second direction (Y).

[0120] Alternatively, although not shown, a plurality of first step portions (280) and a plurality of second step portions (285) may be formed to correspond to each of a plurality of first terminals (250) and a plurality of second terminals (260). That is, in the second region (210-2) of the first substrate (210), a first step portion (280) may be formed such that the upper surface (210-2a) of the second region (210-2) corresponding to the plurality of first terminals (250) is lower than the upper surface (210-1a) of the first region (210-1). In the third region (210-3) of the first substrate (210), a second step portion (285) may be formed on the upper surface (210-3a) of the third region (210-3) corresponding to the plurality of second terminals (260) lower than the upper surface (210-1a) of the first region (210-1).

[0121] FIG. 7 is a cross-sectional view illustrating a power semiconductor module according to the fourth aspect of the present disclosure.

[0122] The cross-sectional view illustrated in Fig. 7 may be a view of the power semiconductor module of Fig. 3 cut along line AA'.

[0123] A fourth aspect of the present disclosure may be similar to the third aspect of the present disclosure (Fig. 5) except that the thicknesses (T21, T22) of the terminals (250, 260) are increased. Components having the same shape, structure, and / or function as those of the third aspect of the present disclosure (Fig. 5) in the fourth aspect of the present disclosure are given the same drawing reference numerals, and a detailed description thereof is omitted.

[0124] Referring to FIGS. 3 and 7, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a first terminal (250), a second terminal (260), and a molding portion (265). One of the first terminal (250) and the second terminal (260) may be omitted.

[0125] In a fourth aspect of the present disclosure, the thickness (T21) of the first terminal (250) may be greater than the thickness (T11) of the first terminal (250) in the third aspect (Fig. 5) of the present disclosure. Accordingly, since the thickness (T21) of the first terminal (250) increases, the cross-sectional area may increase even if the width of the first terminal (250) is the same as the width of the first terminal (250) in the third aspect (Fig. 5) of the present disclosure. Accordingly, the first terminal (250) allows a larger current to flow, so that a high-power semiconductor module may be implemented.

[0126] In the fourth aspect of the present disclosure, the thickness (T22) of the second terminal (260) may be greater than the thickness (T22) of the second terminal (260) in the third aspect (Fig. 5) of the present disclosure. Accordingly, since the thickness (T22) of the second terminal (260) increases, the cross-sectional area may increase even if the width of the second terminal (260) is the same as the width of the second terminal (260) in the third aspect (Fig. 5) of the present disclosure. Accordingly, the second terminal (260) allows a larger current to flow, so that a high-power semiconductor module may be implemented.

[0127] Meanwhile, the first terminal (250) and the second terminal (260) may each be horizontally overlapped with the second substrate (220). The upper surface of the first terminal (250) and the upper surface of the second substrate (220) may be parallel. The upper surface of the second terminal (260) and the upper surface of the second substrate (220) may be parallel. The first terminal (250) and the second terminal (260) may each be exposed to the outside.

[0128] Fig. 8 is a plan view illustrating a power semiconductor module according to the fifth aspect of the present disclosure. Fig. 9 is a cross-sectional view illustrating a power semiconductor module according to the sixth aspect of the present disclosure.

[0129] The cross-sectional view illustrated in Fig. 9 may be a view of the power semiconductor module of Fig. 8 cut along the line BB'.

[0130] A fifth aspect of the present disclosure may be similar to the second aspect of the present disclosure (Fig. 4) except that the first substrate (210) and the second substrate (220) are arranged so as to be offset from each other. In the fifth aspect of the present disclosure, components having the same shape, structure, and / or function as those in the second aspect of the present disclosure (Fig. 4) are given the same drawing reference numerals, and a detailed description thereof is omitted.

[0131] Referring to FIGS. 8 and 9, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a first terminal (250), a second terminal (290), and a molding portion (265).

[0132] The first substrate (210) and the second substrate (220) may be arranged to be offset from each other along the first direction (X). That is, some areas of the first substrate (210) and some areas of the second substrate (220) may vertically overlap, but other areas of the first substrate (210) may not vertically overlap with the second substrate (220), and other areas of the second substrate (220) may not vertically overlap with the first substrate (210).

[0133] The horizontal width of the first substrate (210) and the horizontal width of the second substrate (220) may be the same, but are not limited thereto.

[0134] The first substrate (210) may have a first region (210-1) and a second region (210-2). The second region (210-2) of the first substrate (210) may extend horizontally from the first region (210-1). The second region (220) may have a third region (220-1) and a fourth region (220-2). The fourth region (220-2) of the second substrate (220) may extend horizontally from the third region (220-1).

[0135] The first region (210-1) of the first substrate (210) and the third region (220-1) of the second substrate (220) may vertically overlap. The second region (210-2) of the first substrate (210) may not vertically overlap with the second substrate (220). The fourth region (220-2) of the second substrate (220) may not vertically overlap with the first substrate (210).

[0136] The first terminal (250) is disposed on the upper side of the second extension (210-2) of the first substrate (210) and can be electrically connected to the first substrate (210). The second terminal (290) is disposed on the lower side of the second extension (220-2) of the second substrate (220) and can be electrically connected to the second substrate (220).

[0137] The first terminal (250) may be horizontally overlapped with the second substrate (220), and the second terminal (290) may be horizontally overlapped with the first substrate (210).

[0138] In the second aspect (Fig. 4), the third aspect (Fig. 5) and the fourth aspect (Fig. 7) of the present disclosure, the first terminal (250) and the second terminal (290) are arranged on the same surface, i.e., on the upper surface of the first substrate (210), so that the first terminal (250) and the second terminal (290) can be positioned on the same horizontal line.

[0139] In contrast, in the fifth aspect of the present disclosure, the first terminal (250) may be disposed on the upper side of the second extension (210-2) of the first substrate (210), and the second terminal (290) may be disposed on the lower side of the second extension (220-2) of the second substrate (220).

[0140] Accordingly, the first terminal (250) and the second terminal (290) are not located on the same horizontal line. For example, the first horizontal line passing through the lower surface of the first terminal (250) may be located between the third horizontal line passing through the lower surface of the second terminal (290) and the fourth horizontal line passing through the upper surface of the second terminal (290). For example, the fourth horizontal line passing through the upper surface of the second terminal (290) may be located between the first horizontal line passing through the lower surface of the first terminal (250) and the second horizontal line passing through the upper surface of the first terminal (250). Accordingly, the first horizontal line passing through the lower surface of the first terminal (250) and the third terminal passing through the lower surface of the second terminal (290) may be different from each other, and the second horizontal line passing through the upper surface of the first terminal (250) and the fourth horizontal line passing through the upper surface of the second terminal (290) may be different from each other.

[0141] According to the fifth aspect of the present disclosure, since the plurality of circuit patterns of the second substrate (220) are directly electrically connected to the plurality of second terminals (290), the first connecting member, the second connecting member, and the third connecting member as described above in the second aspect of the present disclosure (Fig. 4) do not need to be provided. Accordingly, the third circuit pattern, the fourth circuit pattern, and the fifth circuit pattern do not need to be provided on the first substrate (210) to be connected to the first connecting member, the second connecting member, and the third connecting member, respectively. Therefore, material costs can be reduced and the structure can be simplified.

[0142] Although not shown, a modified structure of the third aspect (Fig. 5) or the fourth aspect (Fig. 7) of the present disclosure may be applied to a structure in which the first substrate and the second substrate (220) are arranged to be misaligned with each other in the fifth aspect of the present disclosure.

[0143] For example, in the fifth aspect of the present disclosure, the first substrate (210) and the second substrate (220) may be arranged to be misaligned with each other, and as a modification of the third aspect of the present disclosure (Fig. 3), the first step portion (280) may be provided on the first substrate (210) and the second step portion (285) may be provided on the second substrate (220).

[0144] For example, in the fifth aspect of the present disclosure, the first substrate (210) and the second substrate (220) are arranged to be misaligned with each other, and as a modification of the fourth aspect of the present disclosure (Fig. 7), the first step portion (280) is provided on the first substrate (210) and the second step portion (285) is provided on the second substrate (220), and each of the first terminal (250) and the second terminal (290) may have a thicker thickness (T21, T22).

[0145] In the above, the thickness (T11, T12) of the first terminal (250) and the thickness (T21, T22) of the second terminal (260, 290) may be the same, but are not limited thereto. The first terminal (250) and the second terminal (260, 290) may have the same size and shape, but are not limited thereto.

[0146] The power semiconductor module illustrated in FIGS. 3 to 9 may be one of the first power semiconductor module, the second power semiconductor module, and the third power semiconductor module illustrated in FIG. 1.

[0147] The above detailed description should not be construed as limiting in any respect and should be considered illustrative. The scope of the above-described aspects should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalency range of the above-described aspects are intended to be included within the scope of the above-described aspects.

Claims

1. A first substrate having a first region and a second region on a first side of the first region; A power semiconductor element disposed on the first region of the first substrate; A second substrate disposed on the power semiconductor element; and A first terminal disposed on the second region of the first substrate and horizontally overlapping the second substrate; The upper surface of the first terminal and the upper surface of the second substrate are parallel, Power semiconductor modules.

2. In paragraph 1, A support molding part formed to extend from the first side of the first substrate and support at least a portion of the lower portion of the first terminal; Power semiconductor modules.

3. In paragraph 1, A step portion is formed on the upper surface of the second region, The above first terminal is coupled to the step portion, Power semiconductor modules.

4. In paragraph 3, The above first substrate, insulation layer; A first metal layer disposed on the upper side of the insulating layer; and A second metal layer disposed on the lower side of the insulating layer; The above step portion is provided in the first metal layer, Power semiconductor modules.

5. In any one of paragraphs 1 to 4, The first substrate further has a third region on the second side of the first region, Further comprising a second terminal disposed on the third region of the first substrate and horizontally overlapping the second substrate; Power semiconductor modules.

6. In paragraph 5, The second substrate is provided between the second region and the third region, Power semiconductor modules.

7. In any one of paragraphs 1 to 4, The second substrate has a third region on the first region and a fourth region extending horizontally from the third region; A second terminal disposed on the lower side of the fourth region and horizontally overlapping the first substrate; Power semiconductor modules.

8. A first substrate having a first region and a second region on a first side of the first region; A power semiconductor element disposed on the first region of the first substrate; A second substrate disposed on the power semiconductor element; A first terminal disposed on the second region of the first substrate and horizontally overlapping the second substrate; and A molding portion formed to extend from one side of the second substrate and cover at least a portion of the upper surface of the first terminal; The upper surface of the molding part and the upper surface of the second substrate are parallel, Power semiconductor modules.

9. In paragraph 8, A support molding part formed to extend from the first side of the first substrate and support at least a portion of the lower portion of the first terminal; Power semiconductor modules.

10. In paragraph 8, A step portion is formed on the upper surface of the second region, The above first terminal is coupled to the step portion, Power semiconductor modules.

11. In paragraph 10, The above first substrate, insulation layer; A first metal layer disposed on the upper side of the insulating layer; and A second metal layer disposed on the lower side of the insulating layer; The above step portion is provided in the first metal layer, Power semiconductor modules.

12. In any one of paragraphs 8 to 11, The first substrate further has a third region on the second side of the first region, Further comprising a second terminal disposed on the third region of the first substrate and horizontally overlapping the second substrate; Power semiconductor modules.

13. In paragraph 12, The second substrate is provided between the second region and the third region, Power semiconductor modules.

14. A power semiconductor module comprising a power semiconductor module according to paragraph 1 or paragraph 8, Power conversion device.

Images