Electronic circuit for converter and electronic device including same

Abstract

This electronic circuit may include: a first direct current (DC)-DC converter including a first output terminal configured to generate a first output voltage for an input signal; a second DC-DC converter including a second output terminal configured to generate a second output voltage for the input signal; a pulse width modulation (PWM) circuit configured to control a duty cycle of a PWM signal for the second DC-DC converter; a driving circuit configured to control the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal; and an amplification circuit including input terminals connected to the first output terminal and the second output terminal and an output terminal connected to a compensation circuit of the PWM circuit. The amplification circuit may be configured to provide the compensation circuit with a signal corresponding to a difference between the first output voltage and the second output voltage.

Description

Electronic circuit for converter and electronic device including same

[0001] The descriptions below relate to control circuitry for a converter and an electronic device including the control circuitry.

[0002] A device (e.g., a power amplifier (PA), a radio frequency integrated circuit (RFIC), or a transceiver) used in an electronic device (e.g., a radio unit (RU) or a massive multiple input multiple output unit (MMU)) may have a specified range of operable voltages. Therefore, the electronic device may include a converter for converting power obtained from an external source into a range of operable voltages of the device.

[0003] The above information may be provided as background information to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above-described matters constitute prior art related to the present disclosure.

[0004] According to embodiments, an electronic circuit may include a first direct current (DC)-DC converter having a first output terminal for generating a first output voltage for an input signal. The electronic circuit may include a second DC-DC converter having a second output terminal for generating a second output voltage for the input signal. The electronic circuit may include a pulse width modulation (PWM) circuit for controlling a duty cycle of a PWM signal for the second DC-DC converter. The electronic circuit may include a driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal. The electronic circuit may include an amplifier circuit including input terminals connected to the first output terminal and the second output terminal and an output terminal connected to a compensation circuit of the PWM circuit. The above amplifier circuit may be configured to provide a signal corresponding to a difference between the first output voltage and the second output voltage to the compensation circuit.

[0005] According to embodiments, an electronic device may include a first direct current (DC)-DC converter including a first output terminal for generating a first output voltage for an input signal. The electronic device may include a second DC-DC converter including a second output terminal for generating a second output voltage for the input signal. The electronic device may include an electronic component for obtaining the first output voltage and the second output voltage. The electronic device may include a pulse width modulation (PWM) circuit for controlling a duty cycle of a PWM signal for the second DC-DC converter. The electronic device may include a driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal. The electronic device may include an amplifier circuit including input terminals connected to the first output terminal and the second output terminal, and an output terminal connected to a compensation circuit of the PWM circuit. The above amplifier circuit may be configured to provide a signal corresponding to a difference between the first output voltage and the second output voltage to the compensation circuit.

[0006] According to embodiments, an electronic circuit may include a first direct current (DC)-DC converter having a first output terminal for generating a first output voltage for an input signal. The electronic device may include a second DC-DC converter having a second output terminal for generating a second output voltage for the input signal. The electronic circuit may include a pulse width modulation (PWM) circuit for controlling a duty cycle of a PWM signal for the second DC-DC converter. The electronic circuit may include a driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal. The electronic circuit may include a sensing circuit having an output terminal for generating the control signal to monitor load information for the electronic circuit. The driving circuit may include an enable circuit connected to an output terminal of the sensing circuit. If the control signal indicates that the load of the electronic circuit is greater than or equal to a threshold, the enable circuit can control the driving circuit to provide the PWM signal to at least one transistor within the second DC-DC converter. If the control signal indicates that the load of the electronic circuit is less than a threshold, the enable circuit can control the driving circuit not to provide the PWM signal to at least one transistor within the second DC-DC converter.

[0007] Figure 1 illustrates an example of a wireless communication system.

[0008] Figure 2 illustrates the interface between an upper network node and a lower network node.

[0009] Figure 3 illustrates an example of an electronic device that converts power supplied from an external source.

[0010] Figures 4a and 4b illustrate examples of DC (direct current)-DC converters in electronic devices.

[0011] Figure 5 shows an example of a graph showing the efficiency characteristics of a DC-DC converter.

[0012] Figure 6 illustrates an example of an electronic circuit for improving the efficiency characteristics of a DC-DC converter.

[0013] Figure 7a illustrates an example of multiple pins included in a PWM (pulse width modulation) circuit.

[0014] Figure 7b illustrates an example of multiple pins included in a driving circuit.

[0015] Figure 8 illustrates an example of an electronic circuit including a sensing circuit for sensing an input signal.

[0016] Figure 9 illustrates an example of an electronic circuit including a PWM circuit and a driving circuit.

[0017] Figure 10a illustrates an example of an electronic circuit including a PWM circuit.

[0018] Figure 10b illustrates an example of an electronic circuit including a PWM circuit.

[0019] Figure 11 illustrates an example of an electronic circuit including a sensing circuit, a PWM circuit, an amplifier circuit, and a driving circuit.

[0020] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0021] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0022] In the following description, terms referring to components of electronic devices (e.g., circuitry, element, module, assembly, component), terms referring to signals (e.g., signal, output signal, input signal), terms referring to connections (e.g., pin, end, port, node), etc. are examples for convenience of explanation. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used. In addition, terms such as '... part', '... device', '... thing', '... body', etc. used below may mean at least one shape structure or a unit that processes a function.

[0023] In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled, but this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." A condition described as "more than" may be replaced with "more than," a condition described as "less than" may be replaced with "less than," and a condition described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of elements from A (including A) to B (including B). hereinafter, "C" and / or "D" mean at least one of "C" or "D," that is, including {"C", "D", "C" and "D"}.

[0024] Figure 1 illustrates an example of a wireless communication system.

[0025] Referring to FIG. 1, FIG. 1 illustrates a base station (110) and a terminal (120) as some of the nodes utilizing a wireless channel in a wireless communication system. Although FIG. 1 illustrates only one base station, the wireless communication system may further include other base stations identical or similar to the base station (110).

[0026] The base station (110) is a network infrastructure that provides wireless access to the terminal (120). The base station (110) has coverage defined based on the distance at which a signal can be transmitted. In addition to the base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', 'next generation nodeB (gNB)', 'wireless point', 'transmission / reception point (TRP)', or other terms having equivalent technical meanings.

[0027] The terminal (120) is a device used by a user and communicates with the base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) is referred to as a downlink (DL), and the link from the terminal (120) to the base station (110) is referred to as an uplink (UL). In addition, although not shown in FIG. 1, the terminal (120) and another terminal may communicate with each other via a wireless channel. In this case, the link between the terminal (120) and another terminal (device-to-device link, D2D) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some other embodiments, the terminal (120) may be operated without the involvement of a user. For example, the terminal (120) may be a device that performs machine type communication (MTC) and may not be carried by the user. Additionally, for example, the terminal (120) may be an NB (narrowband)-IoT (internet of things) device.

[0028] The terminal (120) may be referred to as a terminal, or other terms such as 'user equipment (UE),' 'customer premises equipment (CPE),' 'mobile station,' 'subscriber station,' 'remote terminal,' 'wireless terminal,' 'electronic device,' or 'user device,' or other terms having equivalent technical meanings.

[0029] The base station (110) and the terminal (120) can perform beamforming. The base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively low frequency band (e.g., FR 1 (frequency range 1) of NR). In addition, the base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively high frequency band (e.g., FR 2 (or, FR 2-1, FR 2-2, FR 2-3), FR 3 of NR), millimeter wave (mmWave) band (e.g., 28 GHz, 30 GHz, 38 GHz, 60 GHz)). To improve channel gain, the base station (110) and the terminal (120) can perform beamforming. Here, the beamforming can include transmission beamforming and reception beamforming. The base station (110) and the terminal (120) can impart directionality to the transmitted or received signal. To this end, the base station (110) and the terminal (120) can select serving beams through a beam search or beam management procedure. After the serving beams are selected, subsequent communication can be performed through resources that have a QCL relationship with the resource that transmitted the serving beams.

[0030] If large-scale characteristics of a channel carrying a symbol on a first antenna port can be inferred from a channel carrying a symbol on a second antenna port, the first antenna port and the second antenna port can be evaluated to have a QCL relationship. For example, the large-scale characteristics may include at least one of delay spread, Doppler spread, Doppler shift, average gain, average delay, and a spatial receiver parameter.

[0031] Although both the base station (110) and the terminal (120) are described as performing beamforming in FIG. 1, the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the terminal may or may not perform beamforming. Furthermore, the base station may or may not perform beamforming. That is, either only one of the base station and the terminal may perform beamforming, or neither the base station nor the terminal may perform beamforming.

[0032] In the present disclosure, a beam refers to a spatial flow of a signal in a wireless channel, and is formed by one or more antennas (or antenna elements), and this forming process may be referred to as beamforming. Beamforming may include at least one of analog beamforming and digital beamforming (e.g., precoding). Reference signals transmitted based on beamforming may include, for example, a demodulation-reference signal (DM-RS), a channel state information-reference signal (CSI-RS), a synchronization signal / physical broadcast channel (SS / PBCH), and a sounding reference signal (SRS). In addition, as a configuration for each reference signal, an IE such as a CSI-RS resource or an SRS-resource may be used, and this configuration may include information associated with the beam. Information associated with a beam may mean whether the configuration (e.g., a CSI-RS resource) uses the same spatial domain filter as another configuration (e.g., another CSI-RS resource within the same CSI-RS resource set) or a different spatial domain filter, or whether it is quasi-co-located (QCL) with a reference signal, and if so, what type it is (e.g., QCL type A, B, C, D).

[0033] In the past, in communication systems with relatively large cell radius of base stations, each base station was installed to include the functions of a digital processing unit (or distributed unit (DU)) and a radio frequency (RF) processing unit (or radio unit (RU)). However, as higher frequency bands are used in 4G (4th generation) and / or subsequent communication systems (e.g., 5G) and the cell coverage of base stations becomes smaller, the number of base stations to cover a specific area has increased. The installation costs for operators to install base stations have also increased. In order to minimize the installation costs of base stations, a structure has been proposed in which the DU and RU of a base station are separated, one or more RUs are connected to one DU via a wired network, and one or more RUs are geographically distributed to cover a specific area. Hereinafter, the deployment structure and expansion examples of base stations according to various embodiments of the present disclosure are described through FIG. 2.

[0034] Figure 2 illustrates the interface between an upper network node and a lower network node.

[0035] The interface between the upper network node and the lower network node may include a fronthaul interface. Unlike the backhaul between the base station and the core network, the fronthaul refers to the entity between the wireless LAN and the base station. While FIG. 2 illustrates an example of a fronthaul structure between an upper network node (210) and one lower network node (220), this is merely for convenience of explanation and the present disclosure is not limited thereto. In other words, embodiments of the present disclosure may also be applied to a fronthaul structure between one upper network node and multiple lower network nodes. For example, embodiments of the present disclosure may be applied to a fronthaul structure between one upper network node and two lower network nodes. Furthermore, embodiments of the present disclosure may also be applied to a fronthaul structure between one upper network node and three lower network nodes.

[0036] For example, an upper network node may include a digital unit / distributed unit (DU). The upper network node may be referred to as a DU. A lower network node may include a radio unit (RU) or a massive MIMO unit (MMU). The lower network node may be referred to as a RU or an MMU.

[0037] Referring to FIG. 2, a base station (110) may include an upper network node (210) and a lower network node (220). A fronthaul (215) between the upper network node (210) and the lower network node (220) may be operated via an Fx interface. For operation of the fronthaul (215), an interface such as an enhanced common public radio interface (eCPRI) or radio over ethernet (ROE) may be used, for example.

[0038] As communication technology develops, mobile data traffic increases, and accordingly, the bandwidth demand required in the fronthaul between the digital unit and the wireless unit has increased significantly. In a deployment such as a centralized / cloud radio access network (C-RAN), an upper network node (210) performs functions for packet data convergence protocol (PDCP), radio link control (RLC), media access control (MAC), and physical (PHY), and a lower network node (220) may be implemented to perform functions for the PHY layer in addition to the RF (radio frequency) function.

[0039] The upper network node (210) may be responsible for upper layer functions of a wireless network. For example, the upper network node (210) may perform functions of the MAC layer and a part of the PHY layer. Here, a part of the PHY layer refers to functions performed at a higher level among the functions of the PHY layer, and may include, for example, channel encoding (or channel decoding), scrambling (or descrambling), modulation (or demodulation), and layer mapping (or layer demapping). According to an embodiment, when the upper network node (210) complies with the O-RAN standard, it may be referred to as an O-DU (O-RAN DU) (or DU). The upper network node (210) may be replaced with a first network entity or DU for a base station (e.g., gNB) in embodiments of the present disclosure, as needed.

[0040] The lower network node (220) may be responsible for lower layer functions of the wireless network. For example, the lower network node (220) may perform a part of the PHY layer, an RF function. Here, a part of the PHY layer refers to functions of the PHY layer that are performed at a relatively lower level than the upper network node (210), and may include, for example, iFFT transformation (or FFT transformation), CP (cyclic prefix) insertion (CP removal), and digital beamforming. The lower network node (220) may be referred to as an 'access unit (AU)', 'access point (AP)', 'transmission / reception point (TRP)', 'remote radio head (RRH)', 'radio unit (RU)', or other terms having an equivalent technical meaning thereto. In one embodiment, if a lower network node (220) complies with the O-RAN standard, it may be referred to as an O-RU (O-RAN RU) (or RU). The lower network node (220) may be replaced with a second network entity or RU for a base station (e.g., gNB) in embodiments of the present disclosure, as needed.

[0041] Although the above example describes that the upper network node (210) includes a DU and the lower network node (220) includes an RU, the embodiments of the present disclosure are not limited thereto. A base station according to the embodiments may be implemented in a distributed deployment according to a centralized unit (CU) configured to perform functions of upper layers of an access network (e.g., packet data convergence protocol (PDCP), radio resource control (RRC)) and a distributed unit (DU) configured to perform functions of lower layers. At this time, the distributed unit (DU) may include a digital unit (DU) and a radio unit (RU). Between a core (e.g., 5GC (5G core) or NGC (next generation core)) network and a radio network (RAN), the base station may be implemented in a structure in which CU, DU, and RU are arranged in that order. The interface between the CU and the distributed unit (DU) may be referred to as an F1 interface.

[0042] For example, a centralized unit (CU) may be connected to one or more DUs and may be responsible for functions at a higher layer than the DU. For example, the CU may be responsible for functions at the RRC (radio resource control) and PDCP (packet data convergence protocol) layers, while the DU and RU may be responsible for functions at lower layers. The DU may perform some functions (high PHY) of the RLC (radio link control), MAC (media access control), and PHY (physical) layers, and the RU may be responsible for the remaining functions (low PHY) of the PHY layer. In addition, for example, a digital unit (DU) may be included in a distributed unit (DU) depending on the implementation of a distributed deployment of a base station. Hereinafter, unless otherwise defined, the operations of DU and RU are described, but various embodiments of the present disclosure can be applied to both a base station deployment including a CU and a deployment in which the DU is directly connected to the core network (i.e., a base station in which the CU and DU are integrated into a single entity (e.g., an NG-RAN node)).

[0043] FIG. 3 illustrates an example of an electronic device that converts power supplied from an external source. For example, the electronic device (300) of FIG. 3 may be an example of the base station (110) of FIG. 1 , the upper network node (210) of FIG. 2 , or the lower network node (220) of FIG. 2 . For example, the electronic device (300) may represent an example of communication equipment that obtains a voltage of a specific range from the outside, converts the obtained voltage, and utilizes the converted voltage. For example, the communication equipment may include a server (or server device).

[0044] Referring to FIG. 3, an electronic device (300) may be connected to a bus (350). For example, the bus (350) may represent a structure or component for supplying power to a plurality of electronic devices (300, 370). For example, the bus (350) may be implemented as a line. In FIG. 3, two electronic devices (300, 370) are illustrated as being connected to the bus (350), but the present disclosure is not limited thereto. For example, the bus (350) may be connected to one electronic device or to three or more electronic devices.

[0045] For example, the power supplied by the bus (350) may include a voltage. For example, the power may be a DC voltage within a specific range. For example, the specific range may include -36 V (voltage) to -60 V. The above examples are merely exemplary for convenience of explanation, and the present disclosure is not limited thereto. For example, the specific range may be defined by a business operator using the electronic device (300) and the bus (350). In other words, the bus (350) may be designed to provide the specific range while taking into account the fact that the power used by each business operator may vary.

[0046] For example, the electronic device (300) may include a power circuit (310), a control circuit (320), and an RF (radio frequency) component (330). Here, a circuit including the power circuit (310) and the control circuit (320) may be referred to as an electronic circuit. In FIG. 3, a case in which there is only one RF component (330) connected to the power circuit (310) is illustrated, but the present disclosure is not limited thereto. For example, the electronic device (300) may include a plurality of RF components connected to the power circuit (310). In addition, in FIG. 3, as described above, when the electronic device (300) is the lower network node (220), a case in which the electronic component connected to the power circuit (310) is the RF component (330) is illustrated, but the present disclosure is not limited thereto. For example, the electronic device (300) may include electronic components that are connected to a power circuit (310) and utilize power provided from the power circuit (310).

[0047] For example, the power circuit (310) of the electronic device (300) may include one or more DC-DC converters. For example, the DC-DC converter may use the DC voltage obtained from the bus (350) as an input voltage and convert the input voltage into a voltage (or output voltage) used by the RF component (330). In other words, the DC-DC converter may output the output voltage converted from the DC voltage obtained from the bus (350). For example, the output voltage may include a specific voltage (e.g., -48 V) usable by the RF component (330). For example, the DC-DC converter of the power circuit (310) may be referred to as an isolated bus converter or a resonant converter. For example, the resonant converter may include an LLC converter or a cap-isolation converter.

[0048] For example, the DC-DC converter may have a primary (1 stage) structure to generate the output voltage from the input voltage obtained from the bus (350). A specific example of the DC-DC converter having a primary structure is described below in FIG. 4a. Alternatively, the DC-DC converter may have a secondary (2 stage) structure to generate the output voltage from the input voltage obtained from the bus (350). A specific example of the DC-DC converter having a secondary structure is described below in FIG. 4b.

[0049] In the above example, the power circuit (310) is described as including the DC-DC converter, but the present disclosure is not limited thereto. For example, the power circuit (310) may include components for controlling power in addition to the DC-DC converter.

[0050] For example, the electronic device (300) may include a control circuit (320) for controlling the power circuit (310). For example, the control circuit (320) may include at least one of a sensing circuit, a pulse width modulation (PWM) circuit, an amplifier circuit, or a driving circuit. For example, the sensing circuit may generate a control signal indicating load information of the electronic device (300). For example, the PWM circuit or the driving circuit may control the operation of a DC-DC converter included in the power circuit (310) based on the generated control signal. Specific examples of control by the control signal are described below in FIGS. 8 to 11.

[0051] For example, the RF component (330) of the electronic device (300) may include at least one of a power amplifier, a radio frequency integrated circuit (RFIC), or a transceiver (e.g., an RF front end, a radiator (or antenna element)). However, the present disclosure is not limited thereto. The RF component (330) may represent an electronic component that utilizes an output voltage provided from a power circuit (310).

[0052] Figures 4a and 4b illustrate examples of DC (direct current)-DC converters in electronic devices.

[0053] FIG. 4a illustrates an example in which the power circuit (310) in the electronic device (300) of FIG. 3 is a DC-DC converter having a primary structure. FIG. 4b illustrates an example in which the power circuit (310) in the electronic device (300) of FIG. 3 is a DC-DC converter having a secondary structure.

[0054] Referring to FIG. 4A, the electronic device (300) may include DC-DC converters (400) having a primary structure. For example, the electronic device (300) may include a DC-DC converter (410) for a first RF component, a DC-DC converter (420) for a second RF component, and a DC-DC converter (430) for a third RF component. The DC-DC converters illustrated in FIG. 4A are merely for convenience of explanation, and the present disclosure is not limited thereto. For example, the components included in each of the DC-DC converters (400), the arrangement of the components, the number of the components, and the number of the DC-DC converters (400) may be changed.

[0055] Referring to Fig. 4a, the DC-DC converter (410) converts the input voltage (405) of the power source into an output resistance (R o ) may include a transformer for converting the output voltage (415) applied to the first portion (411) and the second portion (412). For example, the transformer may include a first portion (411) and a second portion (412). For example, the first portion (411) may be referred to as an input portion or input part. For example, the second portion (412) may be referred to as an output portion or output part. For example, the turns ratio (N) between the first portion (411) and the second portion (412) P : N S ), an output voltage (415) converted from the input voltage (405) can be determined. For example, the output voltage (415) can be input (or transmitted) to the first RF component (e.g., the first power amplifier (AMP_A)).

[0056] As described above, the description of the DC-DC converter (410) can be substantially equally applied to the DC-DC converter (420) for the second RF component (e.g., the second power amplifier (AMP_B)) or the DC-DC converter (430) for the third RF component (e.g., the transceiver (TRX)). The same description is omitted hereinafter.

[0057] As described above, an electronic device (300) including DC-DC converters (400) having a primary structure designed to satisfy an insulation condition can output relatively high efficiency with a relatively simple structure. However, an electronic device (300), such as a lower network node (220), requires a high-capacity power design, and DC-DC converters (400) designed in parallel may be used due to stress limitations (or allowable voltages) of elements within the DC-DC converter while supplying the high-capacity power. When the electronic device (300) includes DC-DC converters (400), since each DC-DC converter includes a transformer, the size of the electronic device (300) (or the power circuit (310)) may increase and the production cost may increase. In addition, since the electronic device (300) (or power circuit (310)) has a primary signal and a secondary signal to implement the off sequence required by the system, the size of the electronic device (300) (or power circuit (310)) may increase. To solve the problem described above, the electronic device (300) may utilize a DC-DC converter having a secondary structure. Specific details related thereto may be referred to as FIG. 4B below.

[0058] Referring to FIG. 4B, the electronic device (300) may include a DC-DC converter (450) having a secondary structure. For example, the DC-DC converter (450) of the electronic device (300) may include a primary circuit (460) including a transformer for providing output voltages to a first circuit (470), a second circuit (480), and a third circuit (490), and a secondary circuit including the first circuit (470), the second circuit (480), and the third circuit (490). For example, the secondary circuit may include a first circuit (470) for a first RF component, a second circuit (480) for a second RF component, and a third circuit (490) for a third RF component. The DC-DC converter (450) illustrated in FIG. 4B is merely for convenience of description, and the present disclosure is not limited thereto. For example, the components included in the DC-DC converter (450), the arrangement of the components, the number of the components, and the number of DC-DC converters (400) may be changed.

[0059] Referring to Fig. 4b, the primary circuit (460) of the DC-DC converter (450) supplies the input voltage (455) of the power source to a capacitor (C Bus ) may include a transformer for converting the output voltage (465) applied to the first portion (461) and the second portion (462). For example, the transformer may include a first portion (461) and a second portion (462). For example, the first portion (461) may be referred to as an input portion or input part. For example, the second portion (462) may be referred to as an output portion or output part. For example, the turns ratio (N) between the first portion (461) and the second portion (462) P : N S), an output voltage (455) converted from an input voltage (455) can be determined. For example, the output voltage (465) can be input (or transmitted) to the first RF component (e.g., the first power amplifier (AMP_A)) through the first circuit (470), input (or transmitted) to the second RF component (e.g., the second power amplifier (AMP_B)) through the second circuit (480), and input (or transmitted) to the third RF component (e.g., the transceiver (TRX)) through the third circuit (490).

[0060] As described above, the electronic device (300) (or power circuit (310)) uses a DC-DC converter (450) including a primary circuit (460) for converting an input voltage (455) and a secondary circuit for distributing an output voltage (465), thereby satisfying the insulation condition and reducing the size of the electronic device (300) (or power circuit (310)) and reducing the production cost.

[0061] Figure 5 shows an example of a graph showing the efficiency characteristics of a DC-DC converter.

[0062] In the graph (500) illustrated in Fig. 5, the X-axis represents the output power of the DC-DC converter, and the Y-axis represents the efficiency defined as the conversion ratio of the output power to the input power. More specifically, the first waveform (501) represents the efficiency characteristics of two DC-DC converters connected in parallel. In addition, the second waveform (502) represents the efficiency characteristics of one DC-DC converter.

[0063] In circuit design, a trade-off may occur between designing a single DC-DC converter structure and designing a parallel DC-DC converter structure. For example, when DC-DC converters are connected in parallel, the number of DC-DC converters increases, but the load on each DC-DC converter may be reduced by 1 / N. Here, N represents the number of DC-DC converters connected in parallel. Referring to the graph (500) of FIG. 5, in a light load region with low output power, parallel-connected DC-DC converters may provide lower efficiency than a single DC-DC converter due to the large base power for driving the DC-DC converter and the large switching loss consumed by the active components within the DC-DC converter. On the other hand, in a heavy load region with high output power, parallel-connected DC-DC converters may provide higher efficiency than a single DC-DC converter due to the small conduction loss generated by the load. The point where the above trade-off occurs may correspond to the point where the first waveform (501) and the second waveform (502) intersect. The above point may be referred to as an efficiency cross point. An area where an output power lower than the efficiency cross point is required may be referred to as a light load area, and an area where an output power higher than the efficiency cross point is required may be referred to as a medium load area.

[0064] A DC-DC converter may be required to have high efficiency across the entire load range. For example, an RU (or MMU) may be required to operate across the full load range for 24 hours, as shown in Table 1 below.

[0065] [Table 1]

[0066]

[0067] Referring to Table 1, for example, an RU (or MMU) may be required to operate in idle mode for 6 hours out of 24 hours. Additionally, an RU (or MMU) may be required to operate at 30% load for 10 hours out of 24 hours. Additionally, an RU (or MMU) may be required to operate at 50% load for 6 hours out of 24 hours. Additionally, an RU (or MMU) may be required to operate at 100% load for 2 hours out of 24 hours.

[0068] Therefore, in order to obtain high efficiency across the entire load range, the parallel-arranged DC-DC converters need to operate as a single DC-DC converter in the light load range and as parallel DC-DC converters in the medium load range. A circuit that operates as a single DC-DC converter in the light load range and as parallel DC-DC converters in the medium load range can be referred to as an IPM (intelligent power management) circuit for ES (energy saving).

[0069] The IPM circuit can operate to turn off one of the two DC-DC converters in a light load region and turn it on in a medium load region. The first DC-DC converter that is turned on in the full load region can be referred to as a master DC-DC converter. The second DC-DC converter that is turned off in the light load region and turned on in the medium load region can be referred to as a slave DC-DC converter. For example, the IPM circuit can operate to turn off the second DC-DC converter among the DC-DC converters arranged in parallel in the light load region and use only the first DC-DC converter. For example, the IPM circuit can operate to turn on the second DC-DC converter among the DC-DC converters arranged in parallel in the medium load region and use the first DC-DC converter and the second DC-DC converter together. The state of the IPM circuit in which the second DC-DC converter is turned off in the light load region may be referred to as IPM on. Additionally, the state of the IPM circuit in which the second DC-DC converter is turned on in the medium load region may be referred to as IPM off.

[0070] The IPM circuit can be in the IPM on state or the IPM off state by turning on or off the second DC-DC converter depending on the load condition of the circuit. However, during the process of turning on or off the second DC-DC converter, a current imbalance may occur in the DC-DC converters of the IPM circuit. For example, during the process of turning on or off the second DC-DC converter, an overcurrent may occur in the first DC-DC converter, and a reverse current may occur in the second DC-DC converter. Since the current imbalance causes an overcurrent or reverse current in each converter, the internal circuit of the DC-DC converter may be damaged or the efficiency characteristic of the entire IPM circuit may be reduced. Therefore, in order to improve the transient characteristic of the IPM circuit, a load-sharing function that prevents current imbalance between the DC-DC converters must be supported.

[0071] Fig. 6 illustrates an example of an electronic circuit for improving the efficiency characteristics of a DC-DC converter. The electronic circuit (600) of Fig. 6 may be an example of a circuit including the power circuit (310) and control circuit (320) of Fig. 3.

[0072] Referring to FIG. 6, the electronic circuit (600) may include DC-DC converters (601, 602) connected in parallel, a sensing circuit (603), a PWM circuit (604), a driving circuit (605), and an amplifier circuit (606). However, the circuit structure illustrated in FIG. 6 is merely an example, and the present disclosure is not limited thereto. For example, the sensing circuit (603) illustrated in FIG. 6 may be replaced with a higher-level system. Although FIG. 6 only illustrates a PWM circuit (604) and a driving circuit (605) for controlling the second DC-DC converter (602), this is merely for illustration, and the present disclosure is not limited thereto. For example, the electronic circuit illustrated in FIG. 6 may further include a PWM circuit and a driving circuit for controlling the first DC-DC converter (601). In this case, the PWM circuit and the driving circuit for controlling the first DC-DC converter (601) may be referred to as the first PWM circuit and the first driving circuit, respectively, and the PWM circuit (604) and the driving circuit (605) for controlling the second DC-DC converter (602) may be referred to as the second PWM circuit and the second driving circuit, respectively.

[0073] As described in FIG. 5, in a light load region, the use of the first DC-DC converter (601) can provide higher efficiency than the use of the DC-DC converters (601, 602) connected in parallel. Also, in a heavy load region, the use of the DC-DC converters (601, 602) connected in parallel can provide higher efficiency than the use of the first DC-DC converter (601). Therefore, the electronic circuit (600) may include a sensing circuit (603) to monitor a load state of the electronic circuit (600). For example, the sensing circuit (603) may generate a control signal based on an input signal of the DC-DC converters (601, 602) and a target load condition. The target load condition corresponds to an efficiency cross point illustrated in FIG. 5, which may be referred to as a critical point. The control signal is a clock signal and may represent either a first value or a second value. For example, the first value may represent a heavy load state in which the load of the electronic circuit (600) is above a threshold. For example, the second value may represent a light load state in which the load of the electronic circuit (600) is below a threshold. The sensing circuit (603) may provide the generated control signal to the driving circuit (604) and the PWM circuit (605).

[0074] The PWM circuit (604) may be configured to charge or discharge a capacitor connected to the PWM circuit (604) based on a control signal. For example, the PWM circuit (604) may identify whether the control signal has a first value or a second value indicating a load condition. For example, the PWM circuit (604) may be configured to discharge a capacitor connected to the PWM circuit (604) if the control signal indicates that a load of the electronic circuit (600) is below a threshold. For example, the PWM circuit (604) may be configured to charge a capacitor connected to the PWM circuit (604) if the control signal indicates that a load of the electronic circuit (600) is above a threshold. The voltage charged to the capacitor of the PWM circuit (604) may limit a duty cycle for generating the PWM signal. The duty cycle represents the percentage of time that the PWM signal is on within a specific period. For example, a PWM signal with a duty cycle of 60% may be kept on for 60% of the time and off for 40% of the time within a specific period. For example, the duty cycle may be limited within a range corresponding to the voltage charged to the capacitor of the PWM circuit (604). For example, if the voltage charged to the capacitor of the PWM circuit (604) is 0.5 V, the duty cycle of the PWM signal may be limited to a maximum of 40%.

[0075] The PWM circuit (604) can control the duty cycle of the PWM signal based on a gain for generating the PWM signal. The PWM circuit (604) can obtain a signal corresponding to a difference between an output voltage of the first DC-DC converter (601) and an output voltage of the second DC-DC converter (602) from the amplifier circuit (606). The PWM circuit (604) can determine a gain for generating the PWM signal based on the signal corresponding to the difference. The PWM circuit (605) can determine a voltage for generating the PWM signal based on the determined gain. The PWM circuit (604) can generate a PWM signal that is in an on state if the voltage for generating the PWM signal is equal to or greater than a reference voltage. For example, the PWM circuit (604) can generate a PWM signal that is in an off state if the voltage for generating the PWM signal is less than a reference voltage.

[0076] The driving circuit (605) can control the second DC-DC converter (602) to operate in an on state or an off state based on the control signal. For example, the driving circuit (605) can identify whether the control signal has a first value or a second value indicating a load state. For example, the first value of the control signal can indicate that the load of the electronic circuit (600) is a medium load state. For example, the second value of the control signal can indicate that the load of the electronic circuit (600) is a light load state. For example, when the control signal is identified as the first value, the driving circuit (605) can provide a PWM signal to at least one transistor in the second DC-DC converter (602). The second DC-DC converter (602) can be turned on because the PWM signal is provided. For example, the drive circuit (605) may not provide a PWM signal to at least one transistor within the second DC-DC converter (602) if the control signal is identified as the second value. The second DC-DC converter (602) may be turned off because the PWM signal is not provided.

[0077] Fig. 7a illustrates an example of a plurality of pins included in a PWM circuit. The PWM circuit (700) of Fig. 7a is an example of the PWM circuit (604) of Fig. 6. The PWM circuit (700) can generate and control a PWM signal. The PWM signal can be used to drive a DC-DC converter. The PWM signal can be a signal in which voltage or current is turned on and off for a certain period. The PWM signal can be expressed as a duty cycle. The duty cycle represents the ratio of time that the PWM signal is in an ON state within a specific period. For example, a PWM signal with a duty cycle of 60% can be maintained in an ON state for 60% of the time and in an OFF state for 40% of the time within a specific period. The PWM circuit (700) is a circuit that generates and controls a PWM signal, and may be referred to as a PWM IC (integrated circuit), a PWM controller, a PWM generator, or other terms having equivalent technical meanings.

[0078] Referring to FIG. 7A, the PWM circuit (700) may include a plurality of pins (701, 702, 703, 704, 705, 706, 707, 708, 709, 710). In FIG. 7A, the PWM circuit (500) is illustrated as including ten pins (701, 702, 703, 704, 705, 706, 707, 708, 709, 710), but the present disclosure is not limited thereto. For example, the PWM circuit (700) may include nine or fewer pins, or eleven or more pins. For example, the pins may be referred to as ports, nodes, nodes, or circuits. In addition, for example, the arrangement of pins included in the PWM circuit (700) may be changed.

[0079] For example, the PWM circuit (700) may include a pin (701) for gradually increasing the duty cycle of the PWM signal within a designated period. For example, when power is applied to the PWM circuit (700), the capacitor of the pin (501) may begin to be charged by a current source or an external circuit. The designated period is a time period during which the capacitor is charged from 0 V to a set voltage, which may be referred to as a soft start (SS) period. The voltage charged to the capacitor of the pin (501) in the SS period may limit the duty cycle of the PWM signal. For example, the voltage charged to the capacitor of the pin (501) may limit the maximum value of the duty cycle. In the SS period, limiting the duty cycle of the PWM signal according to the voltage charged to the capacitor of the pin (501) may be referred to as an SS function. The pin (501) may be referred to as a control pin, a duty pin, an SS pin, or an SS circuit.

[0080] For example, the PWM circuit (700) may include a pin (706) for controlling the duty cycle of the PWM signal. For example, the pin (706) may control the duty cycle of the PWM signal based on a gain for generating the PWM signal. The pin (706) may determine the gain for generating the PWM signal based on an error voltage. The error voltage may correspond to a difference between an output voltage of the first DC-DC converter (601) and an output voltage of the second DC-DC converter (602). The pin (706) may determine a voltage for generating the PWM signal based on the determined gain. The pin (706) may control the duty cycle of the PWM signal based on the voltage for generating the PWM signal. For example, the pin (706) may control the PWM circuit (700) to generate a PWM signal that is in an on state when the voltage for generating the PWM signal is equal to or higher than a reference voltage. For example, pin (706) may control the PWM circuit (700) to generate a PWM signal that is in an off state when the voltage for generating the PWM signal is less than the reference voltage. Pin (706) may be referred to as a compensation pin or compensation circuit.

[0081] For example, the PWM circuit (700) may include a pin (702) for adjusting a dead time between PWM signals (OUTA, OUTB) output from pins (708, 709), respectively. For example, the pin (702) may be referred to as an RTD (resistor timing device) pin or an RTD circuit. The PWM circuit (700) may include a pin (703) for sensing current to perform an OCP (over current protection) function. For example, the pin (703) may be referred to as a CS (current sense) pin or a CS circuit. The PWM circuit (700) may include a pin (704) for setting a frequency of a PWM signal. For example, the pin (704) may be referred to as a CT (capacitor timing) pin or a CT (capacitor timing) circuit. The PWM circuit (700) may include a pin (705) for monitoring and controlling an output voltage. For example, pin (705) may be referred to as an FB (feedback) pin or FB circuit. PWM circuit (700) may include pin (707) for common ground of the circuit. For example, pin (707) may be referred to as a ground (GND) pin or GND circuit. PWM circuit (700) may include pin (708) and pin (709) for outputting PWM signals with different phases. For example, pin (708) may be referred to as an output (OUT) A pin or OUT A circuit. For example, pin (709) may be referred to as an OUT B pin or OUT B circuit. PWM circuit (700) may include pin (710) for power supply of the circuit. For example, pin (710) may be referred to as a VDD pin or VDD circuit.

[0082] Fig. 7b illustrates an example of a plurality of pins included in a driving circuit. The driving circuit (720) of Fig. 7b is an example of the driving circuit (605) of Fig. 6. The driving circuit (720) is a circuit for driving a gate of a transistor. The driving circuit (720) is a circuit for driving a gate of a transistor and may be referred to as a FET (field effect transistor) driver, an FET circuit, a gate driver, or other terms having equivalent technical meanings.

[0083] Referring to FIG. 7B, the driving circuit (720) may include a plurality of pins (721, 722, 723, 724, 725, 726, 727, 728, 729, 730). In FIG. 7B, the driving circuit (720) is illustrated as including ten pins (721, 722, 723, 724, 725, 726, 727, 728, 729, 730), but the present disclosure is not limited thereto. For example, the driving circuit (720) may include nine or fewer pins, or eleven or more pins. For example, the pins may be referred to as ports, terminals, nodes, or circuits. In addition, the arrangement of pins included in the driving circuit (720) may be changed.

[0084] For example, the drive circuit (720) may include a pin (726) for controlling an enable (EN) operation of the drive circuit (720). For example, the pin (726) of the drive circuit (720) may control the second DC-DC converter (602) to operate in an on state or an off state based on a control signal. For example, the pin (726) of the drive circuit (720) may provide a PWM signal to at least one transistor within the second DC-DC converter (602) when a load of the electronic circuit is greater than or equal to a threshold. The second DC-DC converter (602) may be turned on based on the provided PWM signal. For example, the drive circuit (720) may not provide a PWM signal to at least one transistor within the second DC-DC converter (602) when a load of the electronic circuit is less than or equal to a threshold. The second DC-DC converter (602) may be turned off because the gate of at least one transistor within the second DC-DC converter (602) is not driven. For example, pin (726) may be referred to as an enable pin or an enable circuit.

[0085] The driving circuit (720) may include a pin (721) for supplying a bias power for driving an integrated circuit (IC). For example, the pin (721) may be referred to as a VDD pin or a VDD circuit. The driving circuit (720) may include a pin (722). For example, the pin (722) may be referred to as a not connected (NC) pin. The driving circuit (720) may include a pin (723) for generating a floating voltage of the second DC-DC converter (602). For example, the pin (723) may be referred to as a high side boost (HB) pin or an HB circuit. The driving circuit (720) may include a pin (724) for supplying a PWM signal to a high side FET of the second DC-DC converter (602). For example, the pin (724) may be referred to as a high side output (HO) pin or an HO circuit. The driving circuit (720) may include a pin (725) for sensing the source of the high side FET. For example, the pin (725) may be referred to as a HS (high side source) pin or HS circuit. The driving circuit (720) may include a pin (727) for obtaining a PWM signal of the high side FET. For example, the pin (727) of the driving circuit (720) may be connected to a pin (708) of the PWM circuit (700). However, the present disclosure is not limited thereto. For example, the pin (727) of the driving circuit (720) may be connected to a pin (709) of the PWM circuit (700). For example, the pin (727) may be referred to as a HI (high side input) pin or HI circuit. The driving circuit (720) may include a pin (728) for obtaining a PWM signal of the low side FET. For example, pin (728) of the driving circuit (720) may be connected to pin (709) of the PWM circuit (700). However, the present disclosure is not limited thereto.For example, pin (728) of the driving circuit (720) may be connected to pin (728) of the PWM circuit (700). For example, pin (728) may be referred to as a low side input (LI) pin or LI circuit. Driving circuit (720) may include pin (729). For example, pin (729) may be referred to as a VSS pin or VSS circuit. Driving circuit (720) may include pin (610) for supplying a PWM signal to a low side FET of the second DC-DC converter (602). For example, pin (610) may be referred to as a low side output (LO) pin or LO circuit.

[0086] Fig. 8 illustrates an example of an electronic circuit including a sensing circuit for sensing an input signal. The electronic circuit of Fig. 8 is an example of a circuit including a first DC-DC converter (601), a second DC-DC converter (602), and a sensing circuit (603) of Fig. 6.

[0087] As described in FIG. 5, in a light load region, the use of the first DC-DC converter (601) can provide higher efficiency than the use of DC-DC converters (601, 602) connected in parallel. Furthermore, in a heavy load region, the use of DC-DC converters (601, 602) connected in parallel can provide higher efficiency than the use of the first DC-DC converter (601). Therefore, the electronic circuit (800) may include a sensing circuit (603) for monitoring the load status of the electronic circuit (800).

[0088] Referring to FIG. 8, the electronic circuit (800) may include a first DC-DC converter (601), a second DC-DC converter (602), and a sensing circuit (603) to generate a control signal. The sensing circuit (603) may include a current transformer (CT) (802), an inverter (803), an operational amplifier (OP AMP) (808), and a plurality of resistors (804, 809, 810, 811). The control signal may be referred to as an intelligent power management enable (IPM_EN) signal. However, the sensing circuit (603) illustrated in FIG. 8 is merely an example, and the present disclosure is not limited thereto. For example, the sensing circuit (603) may refer to an analog circuit configured to compare an input signal with a target load condition (e.g., an efficiency crossover point) and generate a digital signal indicating one of two states.

[0089] For example, the sensing circuit (603) can sense an input signal of an input terminal (801) of parallel DC-DC converters (601, 602) using a current transformer (CT) (802). The sensing circuit (603) can convert the sensed input signal through a resistor (804) into a voltage of an input terminal (805) of an OP AMP (808). The converted voltage can be applied to a negative input terminal (805) of the OP AMP (808). The voltage of a positive input terminal (806) of the OP AMP (808) can correspond to a target load condition. The target load condition corresponds to an efficiency cross point illustrated in FIG. 5, which can be referred to as a critical point. The sensing circuit (603) can generate a control signal based on the voltage of the negative input terminal (805) and the voltage of the positive input terminal (806) using the OP AMP (808) (or a comparator). The control signal is a clock signal and can indicate a load state of the electronic circuit (800). For example, the control signal can indicate one of a first value or a second value. For example, the first value can indicate a heavy load state in which the load of the electronic circuit (800) is greater than or equal to a threshold. For example, the first value can indicate an IPM off state in which the second DC-DC converter (602) should be turned on. For example, the second value can indicate a light load state in which the load of the electronic circuit (800) is less than or equal to a threshold. For example, the second value can indicate an IPM on state in which the second DC-DC converter (602) should be turned off. The resistors (809, 810, 811) connected to the positive input terminal (806) of the OP AMP (808) can be arranged to have a hysteresis function to prevent the IPM function from malfunctioning due to noise from the power supply terminal.

[0090] For example, the electronic circuit (800) may not include a sensing circuit (603). A control signal indicating an IPM state may be generated based on input signals of DC-DC converters (601, 602) monitored by the system. The system may be implemented simply because it does not require a current transformer (CT) (802) and an OP AMP (808), but the real-time response characteristics may be lower than those of a sensing circuit, which is an analog circuit.

[0091] Fig. 9 illustrates an example of an electronic circuit including a PWM circuit and a driving circuit. The electronic circuit (900) of Fig. 9 is an example of a circuit including the second DC-DC converter (602), the PWM circuit (604), and the driving circuit (605) of Fig. 6.

[0092] The IPM circuit may cause overcurrent or reverse current in each DC-DC converter due to current imbalance during the process of switching from IPM-off to IPM-on. For example, when the IPM circuit switches from IPM-off to IPM-on, the second DC-DC converter (602) may be turned off. The output voltage of the second DC-DC converter (602) that switches to the off state may slowly decrease due to the soft stop function of the PWM circuit (604). Since the output voltage of the second DC-DC converter (602) slowly decreases, an overcurrent may occur in the first DC-DC converter (601) to compensate for the insufficient current. In addition, a reverse current may occur in the second DC-DC converter (602) due to the overcurrent in the first DC-DC converter (601). Current imbalance caused by overcurrent and reverse current can damage the internal circuits of the DC-DC converters (601, 602) or reduce the efficiency of the entire IPM circuit. Therefore, when the IPM circuit switches from IPM OFF to IPM ON, the second DC-DC converter (602) needs to be quickly turned off.

[0093] For example, in order to quickly turn off the second DC-DC converter (602), the enable circuit (726) of the driving circuit (605) may be connected to the transistor (901) for a control signal. The control signal may be a clock signal and may include information indicating a load state of the electronic circuit (900). The information indicating the load state may indicate one of a first value or a second value. For example, the first value may indicate a heavy load state in which the second DC-DC converter (602) should be turned on. For example, the second value may indicate a light load state in which the second DC-DC converter (602) should be turned off. The enable circuit (726) may control the second DC-DC converter (602) to operate in an on state or an off state based on the control signal. For example, the enable circuit (726) can identify whether the control signal has a first value or a second value indicating a load state. For example, if the enable circuit (726) is identified as the second value indicating a turn-off of the second DC-DC converter (602), the enable circuit (726) can control the drive circuit (605) not to provide a PWM signal to at least one transistor within the second DC-DC converter (602). For example, if the enable circuit (726) is identified as the first value indicating a turn-on of the second DC-DC converter (602), the enable circuit (726) can control the drive circuit (605) to provide a PWM signal to at least one transistor within the second DC-DC converter (602). The second DC-DC converter (602) can be turned off by the enable circuit (726) of the drive circuit (605) rather than by the PWM circuit (604). Therefore, the output voltage of the second DC-DC converter (602) may not be affected by the slow stop function of the PWM circuit (604). Accordingly, current imbalance that may occur during the process of the IPM circuit switching from IPM off to IPM on can be prevented.

[0094] As described above, the turn-on or turn-off of the second DC-DC converter (602) can be controlled by the enable circuit (726) of the drive circuit (605). Therefore, the PWM circuit (604) can perform PWM control based on the internal voltage even when the second DC-DC converter (602) is turned off. Due to the PWM control performed while the second DC-DC converter (602) is turned off, an inrush current can be generated when the second DC-DC converter (602) is turned on. The inrush current can cause an overcurrent or OCP (over current protection) in the first DC-DC converter (601) and can cause a reverse current in the second DC-DC converter (602). Current imbalance caused by overcurrent and reverse current may damage the internal circuits of the DC-DC converters (601, 602) or reduce the efficiency of the entire IPM circuit. Therefore, when the second DC-DC converter (602) is turned on from the off state, it is necessary to prevent a sharp transient of the second DC-DC converter (602).

[0095] For example, in order to prevent a sharp transient of the second DC-DC converter (602), a soft start (SS) circuit (701) of the PWM circuit (604) may be connected to a transistor (902) for a control signal. The SS circuit (701) may be configured to charge or discharge a capacitor of the SS circuit (701) based on the control signal. For example, the SS circuit (701) may identify whether the control signal has a first value or a second value indicating a load state. The second DC-DC converter (602) may obtain the second value indicating a turn-off of the second DC-DC converter (602). The SS circuit (701) may be configured to discharge the capacitor of the SS circuit (701) in response to the second value indicating a turn-off of the second DC-DC converter (602). In a state where the second DC-DC converter (602) is turned off, the SS circuit (701) can obtain a first value indicating the turn-on of the second DC-DC converter (602). The SS circuit (701) can be configured to charge a voltage to a discharged capacitor of the SS circuit (701) in response to the first value indicating the turn-on of the second DC-DC converter (602). The voltage charged to the SS circuit (701) can limit a duty cycle for generating a PWM signal. For example, the duty cycle can be limited within a range corresponding to the voltage charged to the capacitor of the SS circuit (701). For example, if the voltage charged to the capacitor of the SS circuit (701) is 0.5 V, the duty cycle of the PWM signal can be limited to a maximum of 40%. The time period required for the capacitor of the SS circuit (701) to be fully charged can be referred to as an SS period. When the second DC-DC converter (602) restarts, the duty cycle of the PWM signal is limited in the SS section, so that a sharp transient of the output voltage of the second DC-DC converter (602) can be prevented.

[0096] Fig. 10a illustrates an example of an electronic circuit including a PWM circuit. The electronic circuit (1000) of Fig. 10a is an example of a circuit including the first DC-DC converter (601), the second DC-DC converter (602), the PWM circuit (604), and the amplifier circuit (606) of Fig. 6.

[0097] Referring to FIG. 10A, an electronic circuit (1000) may include DC-DC converters (601, 602) connected in parallel, a PWM circuit (604), and an amplifier circuit (1006). The amplifier circuit (1006) of FIG. 10A is an example of the amplifier circuit (606) of FIG. 6. The amplifier circuit (1006) of FIG. 10A is merely an example, and the present disclosure is not limited thereto. For example, the amplifier circuit (1006) may be replaced with another circuit capable of performing an integration function for a voltage difference. An output terminal (1001) of a first DC-DC converter (601) may be connected to a negative input terminal of the amplifier circuit (1006). An output terminal (1002) of a second DC-DC converter (602) may be connected to a positive input terminal of the amplifier circuit (1006). The amplifier circuit (1006) can generate a signal corresponding to an error voltage between the output voltage of the output terminal (1002) of the second DC-DC converter (602) and the output terminal (1001) of the first DC-DC converter (601). The signal corresponding to the error voltage can be provided to the feedback circuit (705) by a superposition connection by the resistor (1007). The feedback circuit (705) can control the output voltage of the second DC-DC converter (602) based on negative feedback. Referring to FIG. 10A, the output terminal (1001) of the first DC-DC converter (601) and the output terminal (1002) of the second DC-DC converter (602) can be connected to one output terminal (1005) through resistors (1003, 1004).

[0098] In the IPM circuit where the second DC-DC converter (602) is turned on or off, voltage feedback using the feedback circuit (705) may cause current imbalance in the DC-DC converters (601, 602). For example, the turn-on or turn-off of the second DC-DC converter (602) may be controlled by the enable circuit (726) of the drive circuit (605). Therefore, in a state where the second DC-DC converter (602) is turned off, PWM control by the PWM circuit (604) may continue. Therefore, when the second DC-DC converter (602) is turned on, the accumulated feedback while the second DC-DC converter (602) is turned off is instantaneously added to the output of the second DC-DC converter (602), which may cause overcurrent or reverse current in the DC-DC converters (601, 602). As a result, the transient characteristics of the second DC-DC converter (602) may be degraded in the restart section of the IPM circuit, or a problem may occur in which the second DC-DC converter (602) does not power up.

[0099] Fig. 10B illustrates an example of an electronic circuit including a PWM circuit. The electronic circuit (1050) of Fig. 10B is an example of a circuit including the first DC-DC converter (601), the second DC-DC converter (602), the PWM circuit (604), and the amplifier circuit (606) of Fig. 6. Referring to Fig. 10B, the electronic circuit (1050) may include DC-DC converters (601, 602) connected in parallel, the PWM circuit (604), and the amplifier circuit (1006). The amplifier circuit (1006) of Fig. 10B is an example of the amplifier circuit (606) of Fig. 6. The amplifier circuit (1006) of Fig. 10B is merely an example, and the present disclosure is not limited thereto. For example, the amplifier circuit (1006) may be replaced with another circuit capable of performing an integration function on a voltage difference.

[0100] As described in FIG. 9, in order to prevent a sharp transient of the second DC-DC converter (606), the SS circuit (701) of the PWM circuit (604) may be connected to the transistor (902) for the control signal. The SS circuit (701) may limit the duty cycle of the PWM signal during the SS period. The SS period may correspond to the time period required for the capacitor of the SS circuit (701) to be fully charged. For example, if the voltage charged to the capacitor of the SS circuit (701) is 0.5 V, the duty cycle of the PWM signal may be limited to a maximum of 40%. During the process of restarting the second DC-DC converter (602), since the duty cycle of the PWM signal is limited by the capacitor voltage of the SS circuit (701), a delay may occur in regulating the output voltage of the second DC-DC converter (602) to the output voltage of the first DC-DC converter (601).

[0101] For example, in order to minimize the response speed delay of the IPM circuit according to the SS section, a compensation circuit (706) of the PWM circuit (604) may be used. Referring to FIG. 10B, the electronic circuit (1050) may include DC-DC converters (601, 602) connected in parallel, an amplifier circuit (1006), and a PWM circuit (604). The circuit structure illustrated in FIG. 10B is merely an example, and the present disclosure is not limited thereto. The PWM circuit (604) may control the duty cycle of the PWM signal based on the gain of the compensation circuit (706). For example, when the output voltage of the first DC-DC converter (601) is greater than the output voltage of the second DC-DC converter (602), the gain of the compensation circuit (706) for the second DC-DC converter (602) should be increased. Therefore, the positive input terminal of the amplifier circuit (1006) can be connected to the output terminal (1001) of the first DC-DC converter (601). In addition, the negative input terminal of the amplifier circuit (1006) can be connected to the output terminal (1002) of the second DC-DC converter (602). The amplifier circuit (1006) can generate a signal corresponding to the difference between the output voltages of the DC-DC converters (601, 602) connected in parallel. The output terminal of the amplifier circuit (1006) can be connected to the compensation circuit (706) of the PWM circuit (604) through the resistor (1007).

[0102] For example, the compensation circuit (706) of the PWM circuit (604) can control the duty cycle of the PWM signal. More specifically, the turn-on or turn-off of the second DC-DC converter (602) can be controlled by the enable circuit (726) of the drive circuit (605). Therefore, even if the second DC-DC converter (602) is in an off state, the internal voltage of the PWM circuit (604) can be maintained. Accordingly, the PWM circuit (604) can perform PWM control through the compensation circuit (706) even if the second DC-DC converter (602) is in an off state. For example, in the IPM on section where the second DC-DC converter (602) is turned off, the compensation circuit (706) can apply a signal (or compensation value) generated based on the difference between the output voltage of the first DC-DC converter (601) and the output voltage (e.g., 0 V) ​​of the second DC-DC converter (602) to the gain for generating a PWM signal of the compensation circuit (706). The compensation circuit (706) can determine the voltage of the compensation circuit (706) based on the gain. The compensation circuit (706) can control the duty cycle of the PWM signal based on the determined voltage of the compensation circuit (706) and the reference voltage. For example, the compensation circuit (706) can control the PWM circuit (604) to generate a PWM signal in an on state when the voltage of the compensation circuit (706) is equal to or higher than the reference voltage. For example, the compensation circuit (706) can control the PWM circuit (604) to generate a PWM signal in an off state when the voltage of the compensation circuit (706) is less than a reference voltage. The PWM circuit (604) can determine the gain of the compensation circuit (706) based on compensation accumulated in the IPM on period when the second DC-DC converter (602) is turned off. The PWM circuit (604) can generate the PWM signal based on the determined gain when the second DC-DC converter (602) is turned on.Therefore, the PWM circuit (604) can increase the duty cycle of the PWM signal without taking the time to integrate the difference between the output voltages of the DC-DC converters (601, 602) connected in parallel when the second DC-DC converter (602) is turned on. In addition, the PWM circuit (604) can minimize the response speed delay of the IPM circuit according to the SS period by increasing the duty cycle of the PWM signal based on the gain accumulated in the IPM on period when the second DC-DC converter (602) is turned on.

[0103] FIG. 11 illustrates an example of an electronic circuit including a sensing circuit, a PWM circuit, an amplifier circuit, and a driving circuit. The electronic circuit (1100) of FIG. 11 is an example of a circuit including a first DC-DC converter (601), a second DC-DC converter (602), a sensing circuit (603), a PWM circuit (604), a driving circuit (605), and an amplifier circuit (606) of FIG. 6. Referring to FIG. 11, the sensing circuit (603) may include a current transformer (CT) (802), an inverter, an OP AMP (808), and resistors, as illustrated in FIG. 8. However, the sensing circuit illustrated in FIG. 11 is merely an example, and the present disclosure is not limited thereto. The sensing circuit (603) may refer to an analog circuit configured to compare an input signal with a target load condition (e.g., an efficiency crossover point) and generate a digital signal indicating one of two states. Additionally, the sensing circuit (603) may be replaced with a system in an upper stage. In this case, a control signal indicating the load status of the electronic circuit (1100) may be generated based on the input signals of the DC-DC converters (601, 602) monitored by the system. For example, the amplifier circuit (1006) of FIG. 11 is an example of the amplifier circuit (606) of FIG. 6. The amplifier circuit (1006) of FIG. 11 is merely an example, and the present disclosure is not limited thereto. For example, the amplifier circuit (1006) may be replaced with another circuit capable of performing an integration function for a voltage difference.

[0104] For example, the CT (current transformer) (802) of the sensing circuit (603) can sense the input signal of the input terminal (801) of the DC-DC converters (601, 602) connected in parallel. The sensed input signal is a resistor (R gain) can be converted into the input voltage of the negative input terminal (805) of the OP AMP (808). The input voltage of the positive input terminal (808) of the OP AMP (808) can correspond to the target load condition. The target load condition corresponds to the efficiency cross point illustrated in FIG. 5, which can be referred to as a critical point. The OP AMP (808) can generate a control signal at the output terminal (807) based on the input voltage of the negative input terminal (805) and the input voltage of the positive input terminal (806). The resistors connected to the positive input terminal (806) of the OP AMP (808) can be arranged to have a hysteresis function to prevent the IPM function from malfunctioning due to noise of the power supply terminal.

[0105] For example, the control signal may be a clock signal and may indicate a load state of the electronic circuit (1100). For example, the control signal may indicate one of a first value or a second value. For example, the first value may indicate a heavy load state in which the load of the electronic circuit (1100) is greater than or equal to a threshold. For example, the first value may indicate an IPM off state in which the second DC-DC converter (602) should be turned on. For example, the second value may indicate a light load state in which the load of the electronic circuit (1100) is less than or equal to a threshold. For example, the second value may indicate an IPM on state in which the second DC-DC converter (602) should be turned off.

[0106] For example, the PWM circuit (604) may include a plurality of circuits. For example, the PWM circuit (604) may include a SS circuit (701), an RTD circuit (702), a CS circuit (703), a CT (capacitor timing) circuit (704), an FB circuit (705), a COMP circuit (706), a GND circuit (707), an OUT A circuit (708), an OUT B circuit (709), and a VDD circuit (710). The driving circuit (605) may include a plurality of circuits. For example, it may include a VDD circuit (721), an NC circuit (722), an HB circuit (723), an HO circuit (724), an HS circuit (725), an EN circuit (726), an HI circuit (727), an LI circuit (728), a VSS circuit (729), and an LO circuit (730). However, although the PWM circuit (604) and the driving circuit (605) illustrated in FIG. 11 are illustrated as including 10 circuits, the present disclosure is not limited thereto. For example, the PWM circuit (604) or the compensation circuit (605) may include 9 or fewer circuits, or 11 or more circuits.

[0107] For example, the SS circuit (701) of the PWM circuit (604) may be connected to the transistor (902) for the control signal. The OUT A circuit (708) of the PWM circuit (604) for supplying the PWM signal may be connected to the HI circuit (727) of the driving circuit (605). The OUT B circuit (709) of the PWM circuit (604) for supplying the PWM signal may be connected to the LI circuit (728) of the driving circuit (605). The EN circuit (726) of the driving circuit (605) for controlling the enable operation of the driving circuit (605) may be connected to the transistor (901) for the control signal. The HO circuit (724) of the driving circuit (605) for supplying the PWM signal may be connected to the gate of the high side transistor of the second DC-DC converter (602). The LO circuit (730) of the driving circuit (605) for supplying a PWM signal can be connected to the gate of the high side transistor of the second DC-DC converter (602).

[0108] For example, the positive input terminal of the amplifier circuit (1006) may be connected to the output terminal of the first DC-DC converter (601). The negative input terminal of the amplifier circuit (1006) may be connected to the output terminal (1002) of the second DC-DC converter (602). The negative input terminal of the amplifier circuit (1006) may be connected to the output terminal of the amplifier circuit (1006) through a capacitor. The amplifier circuit (1006) may generate a signal corresponding to the difference between the output voltages of the DC-DC converters (601, 602) connected in parallel. The output terminal of the amplifier circuit (1006) may be connected to the compensation circuit (706) of the PWM circuit (604) through a resistor (1007).

[0109] For example, the enable circuit (726) of the drive circuit (605) can be connected to the transistor (901) for the control signal. The enable circuit (726) can control the second DC-DC converter (602) to operate in an on state or an off state based on the control signal. For example, the enable circuit (726) can identify whether the control signal has a first value or a second value indicating a load state. For example, if the enable circuit (726) is identified as the first value indicating the turn-on of the second DC-DC converter (602), the enable circuit (726) can control the drive circuit (605) to provide a PWM signal to the transistors within the second DC-DC converter (602). For example, the enable circuit (726) can control the driving circuit (605) not to provide a PWM signal to the transistors within the second DC-DC converter (602) when the second value is identified as indicating the turn-off of the second DC-DC converter (602). By the control of the enable circuit (726), the second DC-DC converter (602) can enter an off state without delay. Therefore, a current imbalance that may occur due to a slow stop function of the PWM circuit (604) can be prevented.

[0110] For example, the SS circuit (701) of the PWM circuit (604) may be connected to the transistor (902) for the control signal. The SS circuit (701) may be configured to charge or discharge a capacitor of the SS circuit (701) based on the control signal. For example, the SS circuit (701) may identify whether the control signal has a first value or a second value indicating a load state. For example, the SS circuit (701) may be configured to discharge the voltage charged in the capacitor of the SS circuit (701) when the second value indicating the turn-off of the second DC-DC converter (602) is identified. Since the capacitor of the SS circuit (701) is discharged while the second DC-DC converter (602) is turned off, the SS function can be performed during a re-start process in which the second DC-DC converter (602) is turned on. For example, the SS circuit (701) may be configured to charge a voltage to a capacitor of the SS circuit (701) when the control signal identifies a first value indicating the turn-on of the second DC-DC converter (602). The SS circuit (501) may limit the duty cycle of the PWM signal until the capacitor is fully charged. Therefore, overcurrent or reverse current of the DC-DC converters (601, 602) due to a sharp transient of the output voltage of the second DC-DC converter (602) during the restart process may be prevented.

[0111] For example, the compensation circuit (706) of the PWM circuit (604) can control the duty of the PWM signal in order to minimize the response speed delay of the IPM circuit according to the SS section. More specifically, the turn-on or turn-off of the second DC-DC converter (602) can be controlled by the enable circuit (726) of the driving circuit (605). Therefore, even if the second DC-DC converter (602) is turned off, the PWM circuit (604) can perform PWM control by the internal voltage. For example, in the IPM on section in which the second DC-DC converter (602) is turned off, the compensation circuit (706) can determine the gain of the compensation circuit (706) based on a signal corresponding to the difference between the output voltage of the first DC-DC converter (601) and the output voltage (e.g., 0 V) ​​of the second DC-DC converter (602). The compensation circuit (706) can determine the voltage of the compensation circuit (706) based on the determined gain. The compensation circuit (706) can control the duty cycle of the PWM signal based on the determined voltage of the compensation circuit (706) and the reference voltage. For example, the compensation circuit (706) can control the PWM circuit (500) to generate a PWM signal that is in an on state when the voltage of the compensation circuit (706) is equal to or greater than the reference voltage. For example, the compensation circuit (706) can control the PWM circuit (604) to generate a PWM signal that is in an off state when the voltage of the compensation circuit (506) is less than the reference voltage. The PWM circuit (604) can determine the gain of the compensation circuit (706) through the compensation circuit (706) during the IPM on period in which the second DC-DC converter (602) is turned off. The PWM circuit (604) can generate a PWM signal based on the gain when the second DC-DC converter (602) is turned on.Therefore, the PWM circuit (604) can increase the duty cycle of the PWM signal without taking the time to integrate the difference between the output voltages of the parallel-connected DC-DC converters (601, 602) when the second DC-DC converter (602) is turned on. In addition, the PWM circuit (604) can minimize the response speed delay of the IPM circuit according to the SS section by increasing the duty cycle of the PWM signal through the compensation circuit (706).

[0112] For example, the IPM circuit can enter an IPM off state in which the second DC-DC converter (602) is turned on, to an IPM on state in which the second DC-DC converter (602) is turned off. More specifically, the sensing circuit (603) can sense an input signal of an input terminal (801) of DC-DC converters (601, 602) connected in parallel. The sensing circuit (603) can generate a control signal based on the sensed input signal and a target load condition. Here, the control signal can indicate the turn-off of the second DC-DC converter (602). The transistor (901) for the control signal can be connected to the enable circuit (726) of the drive circuit (605). The enable circuit (726) can control the drive circuit (605) not to provide a PWM signal to at least one transistor in the second DC-DC converter (602) based on the control signal. Due to the control of the enable circuit (726), the second DC-DC converter (602) can enter the off state without delay. Therefore, a current imbalance that may occur due to the slow stop function of the PWM circuit (604) can be prevented. The transistor (902) for the control signal can be connected to the SS circuit (701) of the PWM circuit (604). The SS circuit (701) can be configured to discharge the voltage charged in the capacitor of the SS circuit (701) based on the control signal. Since the voltage of the capacitor of the SS circuit (701) is discharged, the SS function of the SS circuit (701) can be performed when the second DC-DC converter (602) restarts. Since the turn-off of the second DC-DC converter (602) is controlled by the enable circuit (726) of the driving circuit (605), the PWM circuit (604) can perform PWM control by the internal voltage.The compensation circuit (706) can determine the gain of the compensation circuit (706) based on a signal corresponding to the difference between the output voltage of the first DC-DC converter (601) and the output voltage (e.g., 0 V) ​​of the second DC-DC converter (602). The compensation circuit (706) can determine the voltage of the compensation circuit (706) based on the determined gain. The compensation circuit (706) can control the duty cycle of the PWM signal based on the determined voltage of the compensation circuit (706) and the reference voltage. For example, the compensation circuit (706) can control the PWM circuit (604) to generate a PWM signal that is in an on state when the voltage of the compensation circuit (706) is equal to or greater than the reference voltage. For example, the compensation circuit (706) can control the PWM circuit (604) to generate a PWM signal that is in an off state when the voltage of the compensation circuit (706) is less than the reference voltage. In the IPM on period when the second DC-DC converter (602) is turned off, the gain of the compensation circuit (706) may increase depending on the voltage difference between the DC-DC converters (601, 602). However, the voltage for controlling the duty cycle of the PWM signal of the compensation circuit (706) may be related to the capacitor voltage of the SS circuit (701). Since the capacitor voltage of the SS circuit (701) is discharged in the IPM on period, the voltage for controlling the duty cycle of the PWM signal of the compensation circuit (706) may also have a low value. Therefore, in the IPM on period, the PWM circuit (604) may not output a PWM signal.

[0113] For example, the IPM circuit can restart from an IPM on state in which the second DC-DC converter (602) is turned off to an IPM off state in which the second DC-DC converter (602) is turned on. More specifically, the sensing circuit (603) can sense an input signal of an input terminal (801) of DC-DC converters (601, 602) connected in parallel. The sensing circuit (603) can generate a control signal based on the sensed input signal and a target load condition. Here, the control signal can indicate the turn-on of the second DC-DC converter (602). The transistor (901) for the control signal can be connected to an enable circuit (726) of the drive circuit (605). The enable circuit (726) can control the drive circuit (605) to provide a PWM signal to at least one transistor in the second DC-DC converter (602) based on the control signal. The transistor (902) for the control signal may be connected to the SS circuit (701) of the PWM circuit (604). The SS circuit (701) may be configured to charge the capacitor of the SS circuit (701) based on the control signal. The voltage charged to the capacitor of the SS circuit (701) may limit the duty cycle for generating the PWM signal. For example, the duty cycle may be limited in a range corresponding to the voltage charged to the capacitor of the SS circuit (701). For example, if the voltage charged to the capacitor of the SS circuit (701) is 0.5 V, the duty cycle of the PWM signal may be limited to a maximum of 40%. The time period required for the capacitor of the SS circuit (701) to be fully charged may be referred to as an SS period. When the second DC-DC converter (602) is restarted based on the control signal, the duty cycle of the PWM signal may be limited in the SS period. Therefore, overcurrent or reverse current of the DC-DC converters (601, 602) due to the sharp transient of the second DC-DC converter (602) in the SS section can be prevented.The compensation circuit (706) of the PWM circuit (604) can determine the gain of the compensation circuit (706) based on the compensation accumulated in the IPM on period when the second DC-DC converter (602) is turned off. The compensation circuit (706) can control the PWM circuit (604) to generate a PWM signal based on the determined gain when the second DC-DC converter (602) is turned on by the control signal. Therefore, the PWM circuit (604) can increase the duty cycle of the PWM signal without taking the time to integrate the difference between the output voltages of the DC-DC converters (601, 602) connected in parallel when the second DC-DC converter (602) is turned on. In addition, the PWM circuit (604) can minimize the response speed delay of the IPM circuit according to the SS section by increasing the duty cycle of the PWM signal based on the gain determined in the IPM on section when the second DC-DC converter (602) is turned on.

[0114] The electronic circuit and the electronic device including the same according to the present disclosure can enable control by the PWM circuit (604) in a turned-off state of the second DC-DC converter (602) by controlling the turn-on or turn-off of the second DC-DC converter (602) through the enable circuit (726). In addition, the electronic circuit and the device including the same according to the present disclosure can enable the SS function to be performed in the SS circuit (701) when the second DC-DC converter (602) is restarted by discharging the capacitor of the SS circuit (701) in the IPM on state. In addition, the electronic circuit and the electronic device including the same according to the present disclosure can minimize a response speed delay according to the SS section when the second DC-DC converter (602) is restarted by controlling the duty cycle of the PWM signal through the compensation circuit (706) of the PWM circuit (604) in the IPM on state.

[0115] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure pertains from the above description.

[0116] As described above, the electronic circuit may include a first direct current (DC)-DC converter having a first output terminal for generating a first output voltage for an input signal. The electronic circuit may include a second DC-DC converter having a second output terminal for generating a second output voltage for the input signal. The electronic circuit may include a pulse width modulation (PWM) circuit for controlling a duty cycle of a PWM signal for the second DC-DC converter. The electronic circuit may include a driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal. The electronic circuit may include an amplifier circuit having input terminals connected to the first output terminal and the second output terminal and an output terminal connected to a compensation circuit of the PWM circuit. The amplifier circuit may be configured to provide a signal corresponding to a difference between the first output voltage and the second output voltage to the compensation circuit.

[0117] For example, the electronic circuit may further include a sensing circuit including an output terminal for generating the control signal to monitor load information for the electronic circuit.

[0118] For example, the driving circuit may include an enable circuit connected to an output terminal of the sensing circuit. The enable circuit may control the driving circuit to provide the PWM signal to at least one transistor within the second DC-DC converter when the control signal indicates that the load of the electronic circuit is greater than or equal to a threshold. The enable circuit may control the driving circuit not to provide the PWM signal to at least one transistor within the second DC-DC converter when the control signal indicates that the load of the electronic circuit is less than a threshold.

[0119] For example, the PWM circuit may include a soft start (SS) circuit connected to an output terminal of the sensing circuit. The SS circuit may be configured to charge a capacitor of the SS circuit when the control signal indicates that the load of the electronic circuit is greater than a threshold point. The SS circuit may be configured to discharge a capacitor of the SS circuit when the control signal indicates that the load of the electronic circuit is less than a threshold point.

[0120] For example, the first output voltage of the first output terminal may be provided to a positive input terminal of the amplifier circuit. The second output voltage of the second output terminal may be provided to a negative input terminal of the amplifier circuit. The compensation circuit may be configured to increase a gain for generating the PWM signal when the signal indicates that the first output voltage is greater than or equal to the second output voltage. The compensation circuit may be configured to decrease the gain for generating the PWM signal when the signal indicates that the first output voltage is less than the second output voltage.

[0121] For example, the internal voltage of the PWM circuit can be maintained regardless of the control signal. While the second DC-DC converter is in the off state, the gain for generating the PWM signal can be increased.

[0122] For example, a first output terminal of the first DC-DC converter may be connected to a first sensing resistor. A second output terminal of the second DC-DC converter may be connected to a second sensing resistor. The first sensing resistor may be connected to the second sensing resistor.

[0123] As described above, the electronic device may include a first direct current (DC)-DC converter including a first output terminal for generating a first output voltage for an input signal. The electronic device may include a second DC-DC converter including a second output terminal for generating a second output voltage for the input signal. The electronic device may include an electronic component for obtaining the first output voltage and the second output voltage. The electronic device may include a pulse width modulation (PWM) circuit for controlling a duty cycle of a PWM signal for the second DC-DC converter. The electronic device may include a driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal. The electronic device may include an amplifier circuit including input terminals connected to the first output terminal and the second output terminal, and an output terminal connected to a compensation circuit of the PWM circuit. The above amplifier circuit may be configured to provide a signal corresponding to a difference between the first output voltage and the second output voltage to the compensation circuit.

[0124] For example, the electronic device may further include a sensing circuit including an output terminal for generating the control signal to monitor load information for an electronic circuit within the electronic device.

[0125] For example, the driving circuit may include an enable circuit connected to an output terminal of the sensing circuit. The enable circuit may control the driving circuit to provide the PWM signal to at least one transistor in the second DC-DC converter when the control signal indicates that the load of the electronic circuit is greater than or equal to a threshold point. The enable circuit may control the driving circuit not to provide the PWM signal to at least one transistor in the second DC-DC converter when the control signal indicates that the load of the electronic circuit is less than a threshold point.

[0126] For example, the PWM circuit may include a soft start (SS) circuit connected to an output terminal of the sensing circuit. The SS circuit may be configured to charge a capacitor of the SS circuit when the control signal indicates that the load of the electronic circuit is greater than a threshold point. The SS circuit may be configured to discharge a capacitor of the SS circuit when the control signal indicates that the load of the electronic circuit is less than a threshold point.

[0127] For example, the first output voltage of the first output terminal may be provided to a positive input terminal of the amplifier circuit. The second output voltage of the second output terminal may be provided to a negative input terminal of the amplifier circuit. The compensation circuit may be configured to increase a gain for generating the PWM signal when the signal indicates that the first output voltage is greater than or equal to the second output voltage. The compensation circuit may be configured to decrease a gain for generating the PWM signal when the signal indicates that the first output voltage is less than the second output voltage.

[0128] For example, the internal voltage of the PWM circuit can be maintained regardless of the control signal. While the second DC-DC converter is in the off state, the gain for generating the PWM signal can be increased.

[0129] For example, the electronic device may include a radio unit (RU) or a massive multiple input multiple output unit (MMU).

[0130] As described above, the electronic circuit may include a first direct current (DC)-DC converter having a first output terminal for generating a first output voltage for an input signal. The electronic circuit may include a second DC-DC converter having a second output terminal for generating a second output voltage for the input signal. The electronic circuit may include a PWM circuit for controlling a duty cycle of a PWM signal for the second DC-DC converter. The electronic circuit may include a driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal. The electronic circuit may include a sensing circuit having an output terminal for generating the control signal to monitor load information for the electronic circuit. The driving circuit may include an enable circuit connected to an output terminal of the sensing circuit. The enable circuit can control the driving circuit to provide the PWM signal to at least one transistor within the second DC-DC converter when the control signal indicates that the load of the electronic circuit is greater than or equal to a threshold. The enable circuit can control the driving circuit not to provide the PWM signal to at least one transistor within the second DC-DC converter when the control signal indicates that the load of the electronic circuit is less than a threshold.

[0131] For example, the electronic circuit may further include an amplifier circuit including input terminals connected to the first output terminal and the second output terminal and an output terminal connected to a compensation circuit of the PWM circuit. The amplifier circuit may be configured to provide a signal corresponding to a difference between the first output voltage and the second output voltage to the compensation circuit.

[0132] For example, the PWM circuit may include a soft start (SS) circuit connected to an output terminal of the sensing circuit. The SS circuit may be configured to charge a capacitor of the SS circuit when the control signal indicates that the load of the electronic circuit is greater than a threshold point. The SS circuit may be configured to discharge a capacitor of the SS circuit when the control signal indicates that the load of the electronic circuit is less than a threshold point.

[0133] For example, the first output voltage of the first output terminal may be provided to a positive input terminal of the amplifier circuit. The second output voltage of the second output terminal may be provided to a negative input terminal of the amplifier circuit. The compensation circuit may be configured to increase a gain for generating the PWM signal when the signal indicates that the first output voltage is greater than or equal to the second output voltage. The compensation circuit may be configured to decrease the gain for generating the PWM signal when the signal indicates that the first output voltage is less than the second output voltage.

[0134] For example, the internal voltage of the PWM circuit can be maintained regardless of the control signal. While the second DC-DC converter is in the off state, the gain for generating the PWM signal can be increased.

[0135] For example, a first output terminal of the first DC-DC converter may be connected to a first sensing resistor. A second output terminal of the second DC-DC converter may be connected to a second sensing resistor. The first sensing resistor may be connected to the second sensing resistor.

[0136] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0137] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured for execution by one or more processors in an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specifications of the present disclosure. The one or more programs may be provided as included in a computer program product. The computer program product may be traded between sellers and buyers as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read only memory (CD-ROM)) or an application store (e.g., Play Store). ™ ) or directly between two user devices (e.g., smart phones), online distribution (e.g., downloading or uploading). In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily created in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0138] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage devices, magnetic cassettes, or may be stored in memories formed by a combination of some or all of these. In addition, each configuration memory may include multiple copies.

[0139] Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device implementing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device implementing an embodiment of the present disclosure.

[0140] In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed singularly or plurally, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in plural may be composed of singular elements, or components expressed in singular may be composed of plural elements.

[0141] According to embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0142] Meanwhile, although the detailed description of the present disclosure has described specific embodiments, it is obvious that various modifications are possible within the scope of the present disclosure.

Claims

1. In electronic circuits, A first DC (direct current)-DC converter comprising a first output terminal for generating a first output voltage for an input signal; A second DC-DC converter including a second output terminal for generating a second output voltage for the input signal; A PWM circuit for controlling the duty cycle of a PWM (pulse width modulation) signal for the second DC-DC converter; A driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal; and An amplifier circuit including input terminals connected to the first output terminal and the second output terminal and an output terminal connected to a compensation circuit of the PWM circuit, The above amplifier circuit is configured to provide a signal corresponding to the difference between the first output voltage and the second output voltage to the compensation circuit. Electronic circuit.

2. In paragraph 1, Further comprising a sensing circuit including an output terminal for generating the control signal to monitor load information for the electronic circuit. Electronic circuit.

3. In paragraph 2, The above driving circuit includes an enable circuit connected to the output terminal of the above sensing circuit, When the control signal indicates that the load of the electronic circuit is above a threshold, the enable circuit controls the driving circuit to provide the PWM signal to at least one transistor in the second DC-DC converter, and If the control signal indicates that the load of the electronic circuit is below a threshold, the enable circuit controls the driving circuit not to provide the PWM signal to at least one transistor in the second DC-DC converter. Electronic circuit.

4. In paragraph 2, The above PWM circuit includes an SS (soft start) circuit connected to the output terminal of the above sensing circuit, When the control signal indicates that the load of the electronic circuit is above a threshold, the SS circuit is configured to charge the capacitor of the SS circuit, and If the control signal indicates that the load of the electronic circuit is below a critical point, the SS circuit is configured to discharge the capacitor of the SS circuit. Electronic circuit.

5. In paragraph 1, The first output voltage of the first output terminal is provided to the positive input terminal of the amplifier circuit, The second output voltage of the second output terminal is provided to the negative input terminal of the amplifier circuit, If the signal indicates that the first output voltage is greater than or equal to the second output voltage, the compensation circuit is configured to increase a gain for generating the PWM signal, and If the signal indicates that the first output voltage is less than the second output voltage, the compensation circuit is configured to reduce the gain for generating the PWM signal. Electronic circuit.

6. In paragraph 5, The internal voltage of the above PWM circuit is maintained regardless of the above control signal, While the second DC-DC converter is in the off state, the gain for generating the PWM signal is increased. Electronic circuit.

7. In paragraph 1, The first output terminal of the first DC-DC converter is connected to the first sensing resistor, The second output terminal of the second DC-DC converter is connected to the second sensing resistor, and The above first sensing resistor is connected to the above second sensing resistor, Electronic circuit.

8. In electronic devices, A first DC (direct current)-DC converter comprising a first output terminal for generating a first output voltage for an input signal; A second DC-DC converter including a second output terminal for generating a second output voltage for the input signal; An electronic component for obtaining the first output voltage and the second output voltage; A PWM circuit for controlling the duty cycle of a PWM (pulse width modulation) signal for the second DC-DC converter; A driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal; and An amplifier circuit including input terminals connected to the first output terminal and the second output terminal and an output terminal connected to a compensation circuit of the PWM circuit, The above amplifier circuit is configured to provide a signal corresponding to the difference between the first output voltage and the second output voltage to the compensation circuit. Electronic devices.

9. In paragraph 8, Further comprising a sensing circuit including an output terminal for generating the control signal to monitor load information for an electronic circuit within the electronic device. Electronic devices.

10. In paragraph 9, The above driving circuit includes an enable circuit connected to the output terminal of the above sensing circuit, When the control signal indicates that the load of the electronic circuit is greater than a threshold, the enable circuit controls the driving circuit to provide the PWM signal to at least one transistor in the second DC-DC converter, If the control signal indicates that the load of the electronic circuit is below a threshold, the enable circuit controls the driving circuit not to provide the PWM signal to at least one transistor in the second DC-DC converter. Electronic devices.

11. In paragraph 9, The above PWM circuit includes an SS (soft start) circuit connected to the output terminal of the above sensing circuit, When the control signal indicates that the load of the electronic circuit is above a threshold, the SS circuit is configured to charge the capacitor of the SS circuit, and When the control signal indicates that the load of the electronic circuit is below a threshold, the SS circuit is configured to discharge the capacitor of the SS circuit. Electronic devices.

12. In paragraph 8, The first output voltage of the first output terminal is provided to the positive input terminal of the amplifier circuit, The second output voltage of the second output terminal is provided to the negative input terminal of the amplifier circuit, If the signal indicates that the first output voltage is greater than or equal to the second output voltage, the compensation circuit is configured to increase a gain for generating the PWM signal, and If the signal indicates that the first output voltage is less than the second output voltage, the compensation circuit is configured to reduce a gain for generating the PWM signal. Electronic devices.

13. In paragraph 12, The internal voltage of the above PWM circuit is maintained regardless of the above control signal, While the second DC-DC converter is in the off state, the gain for generating the PWM signal is increased. Electronic devices.

14. In paragraph 8, The electronic device includes a RU (radio unit) or an MMU (massive multiple input multiple output unit). Electronic devices.

15. In electronic circuits, A first DC (direct current)-DC converter comprising a first output terminal for generating a first output voltage for an input signal; A second DC-DC converter including a second output terminal for generating a second output voltage for the input signal; A PWM circuit for controlling the duty cycle of a PWM (pulse width modulation) signal for the second DC-DC converter; A driving circuit for controlling the second DC-DC converter to operate in an ON state or an OFF state in response to a control signal corresponding to the input signal; and A sensing circuit including an output terminal for generating the control signal to monitor load information for the electronic circuit, The above driving circuit includes an enable circuit connected to the output terminal of the above sensing circuit, When the control signal indicates that the load of the electronic circuit is above a threshold, the enable circuit controls the driving circuit to provide the PWM signal to at least one transistor in the second DC-DC converter, and If the control signal indicates that the load of the electronic circuit is below a threshold, the enable circuit controls the driving circuit not to provide the PWM signal to at least one transistor in the second DC-DC converter. Electronic circuit.

Images