Field programmable gate array board and mezzanine board interface

Abstract

A circuit assembly, including a Field Programmable Gate Array (FPGA) board including a FPGA chip; a mezzanine board; a heat sink between the FPGA board and the mezzanine board; and a rigid mezzanine connection between the FPGA board and the mezzanine board, the rigid mezzanine connection extending through an opening in the heat sink.

Description

TITLE: Field Programmable Gate Array Board and Mezzanine Board InterfaceCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to United States Provisional Patent Application No. 63 / 669,268, filed July 10, 2024, the entirety of which is incorporated herein by reference.FIELD

[0002] The description relates generally to circuit assemblies, and in particular to a circuit assembly that includes an interface between a field programmable gate array board and a mezzanine board.BACKGROUND

[0003] The following is not an admission that anything discussed below is part of the prior art or part of the common general knowledge of a person skilled in the art.

[0004] Input / output connectors are used to connect Field Programmable Gate Array (FPGA) boards with external devices, such as mezzanine boards. Mezzanine connectors connecting FPGA boards and mezzanine boards are normally FMC and FMC+ connectors.SUMMARY

[0005] The following introduction is provided to introduce the reader to the more detailed discussion to follow. The introduction is not intended to limit or define any claimed or as yet unclaimed invention. One or more inventions may reside in any combination or sub-combination of the elements or process steps disclosed in any part of this document including its claims and figures.

[0006] In accordance with one aspect of this disclosure, which may be used alone or in combination with any other aspect, there is provided a circuit assembly with a Field Programmable Gate Array (FPGA) board connected to a mezzanine board by one or more rigid mezzanine connectors. A heat sink is provided between the FPGA board and the mezzanine board to facilitate heat management for the FPGA board. The FPGA board, heat sink, and mezzanineboard can be arranged to enable high-power circuitry to be implemented on the FPGA board in a compact package that fits within a standard slot while facilitating heat management for the FPGA board.

[0007] The rigid mezzanine connector can extend through an opening provided in the heat sink. The rigid mezzanine connector(s) can be shaped and positioned to facilitate airflow through the circuit assembly and thereby facilitate heat management. The rigid mezzanine connector(s) can also be implemented with a small footprint to minimize interference with airflow through the circuit assembly. This can further enhance cooling of the circuit assembly.

[0008] The heat sink and mezzanine board can be shaped so that the mezzanine board is located within a recess provided on the heat sink. This can provide a more compact circuit assembly package while still providing effective heat management for the FPGA board.

[0009] According to some aspects, there is provided a circuit assembly, comprising a Field Programmable Gate Array (FPGA) board including a FPGA chip; a mezzanine board; a heat sink between the FPGA board and the mezzanine board; and a rigid mezzanine connection between the FPGA board and the mezzanine board, the rigid mezzanine connection extending through an opening in the heat sink.

[0010] The opening can be an aperture through the heat sink.

[0011] The opening can be a notch in an edge of the heat sink.

[0012] The rigid mezzanine connection can be a high-density mezzanine card solid connector.

[0013] The high-density mezzanine card solid connector can have a high pin density allowing for a high-speed connection between the FPGA chip and the mezzanine card.

[0014] The mezzanine board can include a further connector communicatively coupled to the FPGA chip via the mezzanine connection.

[0015] The heatsink can have a plurality of generally parallel flow channels, the further connector can have a further connector heat sink comprising a plurality of further connector flow channels, and the plurality of further connector flow channels can extend generally parallel to the plurality of flow channels of the heatsink.

[0016] The further connector flow channels can be substantially aligned with the plurality of flow channels of the heatsink.

[0017] The rigid mezzanine connection can be adjacent a first lateral side of the FPGA chip and the circuit assembly can include a second rigid mezzanine connection between the FPGA board and the mezzanine board, the second rigid mezzanine connection adjacent a second lateral side of the FPGA chip opposite the first lateral side of the FPGA chip.

[0018] The rigid mezzanine connection and the second rigid mezzanine connection can each have a long dimension, and the rigid mezzanine connection and the second rigid mezzanine connection can be arranged with the long dimensions extending generally parallel to one another.

[0019] The rigid mezzanine connection has a long dimension and the heatsink has a plurality of generally parallel flow channels, and the rigid mezzanine connection is arranged with the long dimension extending generally parallel to the plurality of flow channels of the heatsink.

[0020] The heat sink can include a plurality of openings and the rigid mezzanine connection can be one of a plurality of rigid mezzanine connections, and each rigid mezzanine connection in the plurality of rigid mezzanine connections can extend through a corresponding opening in the plurality of openings in the heat sink.

[0021] The plurality of openings can include at least one aperture and at least one notch.

[0022] The opening can be a connection path cut into the heat sink.

[0023] The mezzanine board can be a first mezzanine board and the rigid mezzanine connection can be a first board rigid mezzanine connection, the assembly can further include a second mezzanine board and a second board rigid mezzanine connection between the FPGA board and the second mezzanine board, and the first mezzanine board and the second mezzanine board can be adjacent one another and can each overlie the FPGA board.

[0024] The FPGA board can be a first FPGA board, and the assembly can further include a second FPGA board and a third board rigid mezzanine connection between the second FPGA board and the first mezzanine board, the first FPGA board and the second FPGA board can be adjacent one another, and the first mezzanine board can overlie each of the first FPGA board and the second FPGA board.

[0025] The FPGA chip and the rigid mezzanine connection can be on the same face of the FPGA board.

[0026] The heat sink can have a recessed section and the mezzanine board can be nested within the recessed section.

[0027] The heat sink can have a non-recessed section having a first height and a combined height of the recessed section and the mezzanine board nested within the recessed section can be not greater than the first height.

[0028] The recessed section can overlie the FPGA chip.

[0029] A total combined height of the circuit assembly can be not greater than 39.04mm.

[0030] According to some aspects, there is provided a method of assembling a circuit assembly, comprising: receiving a Field Programmable Gate Array (FPGA) board including a FPGA chip, a heat sink, and a mezzanine board; arranging the heat sink between the FPGA board and the mezzanine board; and communicatively coupling the FPGA board to the mezzanine board through an opening in the heat sink.

[0031] According to some aspects, there is provided a circuit assembly, comprising: a Field Programmable Gate Array (FPGA) board including a FPGA chip; a mezzanine board; a heat sink interposed between the FPGA board and the mezzanine board, wherein the heat sink comprises a plurality of flow channels extending substantially in a longitudinal direction; and an elongated rigid connector extending between the FPGA board and the mezzanine board through an opening in the heat sink, wherein a long dimension of the elongated rigid connector extends substantially in the longitudinal direction.

[0032] The FPGA chip and the rigid mezzanine connection can be on the same face of the FPGA board.

[0033] The rigid connector can be adjacent a first lateral side of the FPGA chip and the circuit assembly can include a second rigid connector extending between the FPGA board and the mezzanine board through a second opening in the heat sink, the second rigid connector can be positioned adjacent to a second lateral side of the FPGA chip opposite the first lateral side of the FPGA chip.

[0034] A second long dimension of the second rigid connector can extend substantially in the longitudinal direction.

[0035] The heat sink can have a recessed section and the mezzanine board can be nested within the recessed section.

[0036] The heat sink can have a non-recessed section having a first height and a combined height of the recessed section and the mezzanine board nested within the recessed section can be not greater than the first height.

[0037] The recessed section can overlie the FPGA chip.

[0038] A total combined height of the circuit assembly can be not greater than 39.04mm.

[0039] It will be appreciated by a person skilled in the art that a system or method disclosed herein may embody any one or more of the featurescontained herein and that the features may be used in any particular combination or sub-combination.

[0040] These and other aspects and features of various examples will be described in greater detail below.BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings included herewith are for illustrating various examples of articles, methods, and apparatuses of the present specification and are not intended to limit the scope of what is taught in any way. In the drawings:

[0042] FIG. 1 is an exploded view of an example circuit assembly;

[0043] FIG. 2 is a top perspective view of a mezzanine board of the circuit assembly of FIG. 1 ;

[0044] FIG. 3 is a bottom perspective view of the mezzanine board of FIG. 2;

[0045] FIG. 4 is a top perspective view of a heatsink of the circuit assembly of FIG. 1 ;

[0046] FIG. 5 is a top perspective view of a Field Programmable Gate Array (FPGA) board of the circuit assembly of FIG. 1 ;

[0047] FIG. 6 is a bottom perspective view of the FPGA board of FIG. 5;

[0048] FIG. 7A is a schematic diagram of another example circuit assembly with a first staggered arrangement;

[0049] FIG. 7B is a schematic diagram of another example circuit assembly with a second staggered arrangement;

[0050] FIG. 7C is a schematic diagram of another example circuit assembly with a third staggered arrangement; and,

[0051] FIG. 8 is a flow chart of an example method of assembling a circuit assembly.DETAILED DESCRIPTION

[0052] Various apparatuses or processes will be described below to provide an example of an embodiment of each claimed invention. No exampledescribed below limits any claimed invention and any claimed invention may cover processes or apparatuses that differ from those described below. The claimed inventions are not limited to apparatuses or processes having all of the features of any one apparatus or process described below or to features common to multiple or all of the apparatuses or processes described below. It is possible that an apparatus or process described below is not an embodiment of any claimed invention. Any invention disclosed in an apparatus or process described below that is not claimed in this document may be the subject matter of another protective instrument, for example, a continuing patent application, and the applicants, inventors or owners do not intend to abandon, disclaim or dedicate to the public any such invention by its disclosure in this document.

[0053] Furthermore, it will be appreciated that for simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. It should be noted that the term “coupled” used herein indicates that two elements can be directly coupled to one another or coupled to one another through one or more intermediate elements.

[0054] It should be noted that terms of degree such as "substantially", "about" and "approximately" as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. These terms of degree may also be construed as including a deviation of the modified term if this deviation would not negate the meaning of the term it modifies.

[0055] Furthermore, any recitation of numerical ranges by endpoints herein includes all numbers and fractions subsumed within that range (e.g. 1 to 5 includes 1 , 1.5, 2, 2.75, 3, 3.90, 4, and 5). It is also to be understood that all numbers and fractions thereof are presumed to be modified by the term "about" which means a variation of up to a certain amount of the number to which reference is being made if the end result is not significantly changed.

[0056] The present disclosure relates generally to a circuit assembly containing an FPGA board. The circuit assembly can be shaped and sized tocomply with standard circuit assembly slot sizes (e.g. a standard PCIe slot) while providing effective heat management for the FPGA chip.

[0057] The circuit assemblies described herein generally include an FPGA board connected to a mezzanine board with a heat sink interposed between the FPGA board and the mezzanine board (i.e. physically separating the FPGA board and the mezzanine board). The FPGA board and mezzanine board can include mating rigid connectors that provide a communicative coupling between the FPGA chip and the mezzanine board. The rigid connectors can extend through an opening, such as an aperture or notch, in the heat sink. This can provide an effective coupling between the FPGA board and mezzanine board while still facilitating heat management across substantially the entire surface area of both the FPGA board and mezzanine board.

[0058] The rigid mezzanine connectors can be selected and arranged to reduce the interference with airflow (e.g., across an FPGA chip) and thereby facilitate heat management. The rigid mezzanine connectors can also help reduce space constrictions that result from the location and / or size of standard mezzanine connectors and / or further external connectors.

[0059] The rigid mezzanine connectors and the arrangement of the heat sink, FPGA board, and mezzanine board may effectively reduce interference with airflow through the circuit assembly while providing a circuit assembly that complies with standard limitations on board / package total size (e.g., a board must be within PCIe form factor, which is a limiting factor). For instance, the circuit assembly (including the FPGA board, mezzanine board, heat sink and cover / housing) can be sized to fit within a slot sized to conform to the PCIe dual slot standard (i.e. having a maximum circuit assembly height of no greater than 39.04mm / 1.537 inches).

[0060] Referring to Figure 1 , an example circuit assembly 100 is illustrated in an exploded view. The circuit assembly 100 includes a Field Programmable Gate Array (FPGA) board 102 containing an FPGA chip 104. The FPGA board 102 extends lengthwise from a first end 101 a to a second end101 b for a length 101 in a long dimension of the FPGA board 102 (see e.g. FIG. 5). The FPGA board 102 also extends laterally between a first lateral side 103a and a second lateral side 103b for a width 103 in a lateral dimension of the FPGA board 102.

[0061] As shown in the example of FIG. 1 , the chip 104 is provided on a first face 105 of the board 102. The example FPGA board 102 of Figure 1 includes one or more power connectors 129 (e.g., one or a plurality of power connectors). The power connectors 129 and the chip 104 may be on a common face of the board 102, such as face 105 in the example illustrated.

[0062] The assembly 100 also includes a mezzanine board 106. The mezzanine board 106 extends lengthwise from a first end 146a to a second end 146b for a length 146 in a long dimension of the mezzanine board 106 (see e.g. FIG. 2). The mezzanine board 106 also extends laterally between a first lateral side 144a and a second lateral side 144b for a width 144 in a lateral dimension of the mezzanine board 106.

[0063] In the example illustrated, the mezzanine board 106 overlies the FPGA board 102. Optionally, substantially the entire mezzanine board 106 overlies the FPGA board 102 as in the example illustrated.

[0064] As exemplified in Figure 1 , the FPGA board 102 can be at least as long and wide as the mezzanine board 106. Accordingly, substantially no part of the mezzanine board 106 overhangs the edge of the FPGA board 102. That is, the perimeter of the mezzanine board 106 (e.g. along the length dimension 146 and lateral dimension 144) may be contained within a projection of the perimeter of the FPGA board 102 (e.g. along the length dimension 101 and lateral dimension 103).

[0065] A face of the FPGA board 102 can be generally parallel to a face of the mezzanine board 106. For example, the first face 105 of the FPGA board 102 can be substantially parallel with the second face 124 of the mezzanine board 106 as shown in FIG. 1. Each of the FPGA board 102 and mezzanine board 106 can have a substantially planar board base. The planes defined bythe FPGA board 102 and mezzanine board 106 respectively can be substantially parallel within the circuit assembly 100.

[0066] The assembly 100 also includes a heat sink 120. As shown in the example of FIG. 1 , the heat sink 120 is interposed between the FPGA board 102 and the mezzanine board 106. The heat sink 120 may be arranged at any suitable position between the boards 102 and 106. In the example illustrated, the heat sink 120 is sized and positioned to align with, and overlie, the FPGA board 102.

[0067] The heat sink 120 can be shaped and sized to substantially separate the mezzanine board 106 from the FPGA board 106. That is, the heat sink 120 may separate (i.e. be interposed between) substantially the entirety of mezzanine board 106 overlying the FPGA board 102 (e.g. with the exception of openings 126 and / or mechanical connectors / mounts).

[0068] The heat sink 120 can be provided with a plurality of flow channels 134. The flow channels 134 can be arranged to allow air to flow through the heat sink 120 and thereby encourage heat transfer (i.e. cooling) of the components thermally coupled to the heat sink 120, such as the FPGA chip 104.

[0069] The flow channels can be shaped in any manner suitable to encourage air flow through the heat sink 120. In the example illustrated, the flow channels 134 extend generally linearly in the long dimension 123 of the heat sink 120. As illustrated, the flow channels 134 can extend substantially throughout the entire length 123 of the heat sink 120. When the circuit assembly 100 is inserted into a slot in operation, the end of the circuit assembly typically experiences greater airflow. Accordingly, flow channels 134 extending in the long dimension 123 can facilitate airflow through the heat sink 120.

[0070] The FPGA chip 104 is communicatively coupled to the mezzanine board 106 by a mezzanine connector 108. The mezzanine connector 108 can extend through an opening in the heat sink 120. This provides a short path length between the FPGA board 102 and mezzanine board 106 while stillallowing the heat sink 120 to extend over a substantial portion of the FPGA board 102.

[0071] The mezzanine connector 108 can be a rigid connector that, once connected, provides a fixed connection between the FPGA chip 104 and mezzanine board 106. This rigid, fixed connection can be contained entirely within the perimeter of the FPGA board 102 and mezzanine board 106. This ensures that the circuit assembly 100 can be inserted into a suitably sized slot within requiring any external connective components between the FPGA board 102 and mezzanine board 106 to be adjusted.

[0072] The connector 108 can be implemented by a rigid connector that provides the desired data connectivity for the FPGA chip 104. In the example of FIG. 1 , the mezzanine connector 108 is a high-density connector. The high- density connector can be adapted to deliver the data transfer requirements demanded of a mezzanine board connection between a mezzanine board and a FPGA chip.

[0073] The inventors discovered that many existing mezzanine connectors, such as FMC and FMC+ connectors are too bulky and have limited arrangement configurations. This interferes with airflow through a circuit assembly resulting in poor cooling. The connectors 108 can thus be selected to be small in size (i.e. have a limited footprint) to facilitate airflow and thereby improve heat management.

[0074] For example, the transverse dimension 136 of a connector 108 (Figures 2 and 3) may be less than 1 / 5th, less than 1 / 8th, or less than 1 / 10thof the width 144 of the board 106 (e.g., to facilitate airflow in a direction along the length 146). Referring to Figure 5, the long dimension 132 of a connector 108 may be at least 50% of the length 146’ of the chip, at least 75% of the length 146’ of the chip, or generally equal to the length 146’ of the chip 104. The transverse dimension 136 may be less than 1 / 5th, less than 1 / 8th, or less than 1 / 10thof the width 144’ of the chip 104.

[0075] In the example illustrated, the mezzanine connector 108 is a rigid connector. A rigid connector 108 often results in a more reliable assembly than a flexible connector. While flexible connectors may be arranged to go around the heatsink 120, they can be less reliable (e.g., prone to breakage). Routing the connector around the heatsink 120 (e.g., rather than through it) may also increase the latency due to the increased path length.

[0076] The example mezzanine connector 108 illustrated in Figure 1 is a high-density mezzanine card solid connector. The high-density mezzanine card solid connector has a high pin density allowing for a high-speed connection between an FPGA and a mezzanine card in a connector with a smaller form factor. The mezzanine connector 108 may be, for example, the ADM6 (male) and ADF6 (female) AcceleRate HD High-Density 4-Row Terminal and Socket connector made by Samtec™.

[0077] The mezzanine connector 108 can be provided by a pair of mating connection members. The mating connection members can include a first member 110 mounted to the mezzanine board 106 and a cooperating second member 112 mounted to the FPGA board 102. The cooperating first and second members 110 and 112 can be mating connectors such as socket and plug members. In the example of Figure 1 , the first member 110 is a socket member mounted to the mezzanine board 106 and the second member 112 is a plug member mounted to the FPGA board 102. In some examples, the second member of the mezzanine connection mounted to the FPGA board is the socket member and the first member mounted to the mezzanine board is the plug member. Optionally, the socket member is provided on the smaller board. Optionally, the more fragile connector can be provided on the cheaper board.

[0078] The mezzanine connector 108 is shown in expanded views in Figures 2, 3, and 5. A mezzanine connector 108 may be arranged in any suitable way.

[0079] Optionally, the mezzanine connector 108 can have an elongated shape with a long dimension 132 that is substantially greater than its lateral or transverse dimension 136. For example, the elongated shape of the mezzanine connector 108 may be at least 5 times as long along the long dimension 132 as wide along the lateral / transverse dimension 136.

[0080] Optionally, the long dimension 132 of the mezzanine connector 108 can be arranged generally parallel to flow channels 134 of the heat sink 106. Arranging the long dimension generally parallel to the flow channels 134 reduces the obstruction of fluid flow through the channels 134 when the connector 108 extends through the heat sink 120.

[0081] The example assembly 100 includes multiple mezzanine connectors 108 for improved connection, though some examples may include only a single mezzanine connector 108.

[0082] Multiple mezzanine connectors 108 may be arranged in any suitable pattern, such as adjacent one another or spaced apart. In some embodiments, multiple mezzanine connectors 108 are arranged with long dimensions 132 extending generally parallel to one another. Alternatively, two connectors could be arranged with the long dimensions extending at an angle to one another. Arranging connectors with the long dimensions extending at an angle to one another allows the connectors to be used to direct an airflow. For example, the connectors may be angled to direct airflow towards the most heat prone components (e.g., the FPCA chip). Alternatively, the connectors can be arranged in a parallel configuration to reduce obstruction to the air flow (e.g., angled connectors may increase backpressure which may reduce airflow).

[0083] The FPGA chip 104 can generate a great deal of heat. Accordingly, position of the FPGA chip 104 on the board 102 may be carefully selected to facilitate heat dissipation. At the same time, reducing latency between the FPGA chip 104 and the mezzanine board 106 is often an important operational factor. Thus, the circuit assembly 100 can be configured to reduce latency for the FPGA chip 104 while facilitating heat dissipation from the FPGA chip 104.

[0084] The example assembly 100 of Figure 1 includes a first mezzanine connector 108a adjacent to a first lateral side 114 of the FPGA chip 104 and a second mezzanine connector 108b adjacent to a second, opposite lateral side 116 of the FPGA chip 104. Positioning the mezzanine connector(s) 108 adjacent to the FPGA chip 104 can help reduce latency in data transmission between the chip 104 and mezzanine board 106. This may be particularly advantageous in combination with a rigid connector 108 that extends directly through the heat sink 120 to the mezzanine board 106.

[0085] The mezzanine connector 108 may be placed near the FPGA chip 104. Proximity to the FPGA chip 104 reduces the trace lengths needed to connect the chip 104 to the connector 108. The member of the connector 108 on the FPGA board 102 may be within 2 mm, 1 mm, or 0.5 mm of the FPGA chip 104. Optionally, the connector 108 is located as close to the FPGA chip as possible to reduce latency.

[0086] Optionally, the mezzanine connector 108 can be arranged with a long dimension 132 extending generally parallel to a lateral edge of the chip 104. This may encourage air to flow along the chip 104. The example assembly 100 shown in Figure 1 includes a first mezzanine connector 108a adjacent a first lateral side 103a of the FPGA board 102 and a second mezzanine connector 108b adjacent a second lateral side 103b of the FPGA board 102 opposite the first side 114.

[0087] Optionally, the mezzanine connector 108 can be arranged with a long dimension 132 extending generally parallel to a lateral edge of the board 102.

[0088] Optionally, a gap can be maintained between the connector 108 and the FPGA chip 104 (e.g., to allow for air flow and / or for ease of use or manufacturing). The gap may be at least 0.4 mm.

[0089] The mezzanine connector 108 can be provided on the same face 105 of the FPGA board 102 as the FPGA chip 104, e.g., as illustrated in Figure 1. Arranging the chip 104 and the connector 108 on a common face 105 of theFPGA board 102 may reduce latency. This may also allow the FPGA chip 104 to be maintained in close proximity to heat sink 120.

[0090] Alternatively, the FPGA chip 104 may be on an opposite face of the FPGA board 102 from the connector 108. Arranging the chip 104 and the connector 108 on opposite faces may, e.g., allow the face of the board 102 to which the connector 108 is attached to be arranged closer to the heatsink 120 and / or prevent the chip 104 from obstructing airflow through the heatsink 120.

[0091] Optionally, the mezzanine board 106 includes a further connector 128 to couple the FPGA chip to additional devices. The further connector 128 may provide an external connection to a device or component that is external to the circuit assembly 100. The further connector can be configured to connect to an additional device mounted to the mezzanine board and / or is provided to connect to external devices that are not part of the mezzanine board (e.g., input / output connectors). Accordingly, the further connector 128 may be arranged at an end of the mezzanine board, such as the first end 146a of the mezzanine board (see e.g. FIG. 2).

[0092] The further connector 128 may be any suitable connector for a given implementation of the circuit assembly 100. Optionally, the further connector 128 may include a heat sink of its own, such as a QSFP, SFP, etc. The further connector 128 may be, e.g., a QSFP DD connector 118. The QSFP DD connector 118 may connect to the additional devices through a network.

[0093] The external connector 128 (e.g. QSFP DD connector 118) can be positioned on the mezzanine board 106 (i.e. off the FPGA board 102) to separate the heat generation from the external connector QSFP DD connector 118 from the heat generation from the FPGA chip 104.

[0094] Optionally, the mezzanine board 106 includes more than one further connector. For example, the multiple further connectors of the mezzanine board 106 may include one or more further connectors to one or more additional devices mounted to the mezzanine board and / or one or more further connectors provided to connect to one or more external devices. Arranging thefurther connector on the mezzanine board 106 reduces space requirements for the FPGA board 102. This also removes cooling obstructions from the FPGA board 102.

[0095] The further connector can be connected to the FPGA chip 104 in any suitable way, and the connection between the further connector and the FPGA chip extends through the mezzanine connector 108. Optionally, the further connector can be connected to a pin of the FPGA chip 104 through a printed circuit board (PCB) trace (or traces) and the mezzanine connector 108.

[0096] As described herein above, the circuit assembly 100 of Figure 1 includes a heatsink 120 between the mezzanine board 106 and the FPGA board 102. Positioning the heat sink 120 between the mezzanine board 106 and the FPGA board 102 provides cooling for the FPGA board 102, including the chip 104. A first surface 122 (e.g., an upper surface) of the heat sink 120 is positioned facing the mezzanine board 106 and a second surface 124 (e.g., a lower surface) opposite the first surface 122 is positioned facing the FPGA board 102.

[0097] The heatsink 120 includes an opening 126 extends between the first surface 122 and the second surface 124. The opening 126 generally refers to a void section of the heat sink 120. The connector opening 126 is sized and shaped to allow the mezzanine connector 108 to extend therethrough. Optionally, a socket member and a plug member of a mezzanine connector mate through the connector opening 126. Extending the connectors through the heatsink 120 allows for a short and rigid connection between the FPGA board 102 and the mezzanine board 106.

[0098] The connector opening 126 may be an aperture (i.e., surrounded by the board 120) or a notch in the edge of the heatsink. An aperture connector opening is surrounded by the heatsink. A notch connector opening is only partially surrounded by the heatsink (e.g., at least 50% surrounded or at least 75% surrounded). The example heatsink 120 includes an aperture connector opening 126a and a notch connector opening 126b. The connector opening 126 may be formed in the heatsink in any suitable way. Optionally, theconnector opening 126 can be cut into the heatsink 120 after the heatsink 120 is formed.

[0099] In the example shown in FIGS. 1 and 4, the heatsink 120 has a first section 121 a and a second section 121 b. The second section 121 b is a recessed heat sink section that includes a recess 138 shaped to receive the mezzanine board 106 therein. The recessed heat sink section 121 b still has a heat sink portion with flow channels 134 interposed between the mezzanine board 106 and FPGA board 102 to facilitate cooling of the circuit assembly 100.

[0100] Positioning the mezzanine board 106 within a recess 138 of the heat sink 120 allows for the heatsink 120 to extend across a greater surface area of the FPGA board while maintaining the same overall height of the assembly 100. The first section 121a of the heat sink 120 can have a first section height 127 that is greater than the second section height 129. The first section height 127 may be substantially equal to a combined height of the second section 121 b and the mezzanine board 106 when assembled into the circuit assembly 100.

[0101] The circuit assembly 100 can be sized to conform with a standard slot size into which the circuit assembly may be inserted. For example, the circuit assembly 100 can have can be sized to fit within a slot sized to conform to the PCIe dual slot standard (i.e. having a maximum circuit assembly height of no greater than 39.04mm / 1.537 inches). That is, a combined height 159 of the FPGA board 102, mezzanine board 106 and heat sink 120 (as well as any covering or housing 130) may be no greater than 39.04mm / 1.537 inches.

[0102] As noted above, the mezzanine board 106 may include one or more further connectors 128 that may include separate heat sink regions. For example, the further connectors 128 may be provided with connector flow channels 140 formed by cooling fins 142.

[0103] Optionally, the flow channels 134 of the heat sink can be substantially aligned with flow channels 140 formed between cooling fins 142 on the further connector 128, e.g., on the QSFP DD Cage 118. Aligning flowchannels encourages airflow from one channel into another. That is, the flow channels 134 of the heat sink 120 may be aligned with the flow channels 140 of the further connector 128 so as to define a shared fluid flow channel that extends across the flow channels 134 on the first section 121a of the heat sink 120 and continues through the flow channels 140 of the further connector 128.

[0104] The flow channels 140 may be arranged on a face of the further connector 128 opposite to the face mounted to the board 102. Flow channels 140 on a face of the further connector 128 opposite the face mounted to the board 102 encourages cooling on opposite faces of the further connector 128, since the face mounted to the board 102 benefits from cooling through the heatsink 120.

[0105] The circuit assembly 100 can also include one or more additional components. For example, the circuit assembly 100 can include a housing or cover 130 overlying the further connector 128, the FPGA board 102, the heatsink 120, and / or the mezzanine board 106.

[0106] The use of smaller form-factor, solid mezzanine connectors allow the FPGA board 102 and the mezzanine board 106 to be connected directly through the heatsink 120.

[0107] As noted herein above, the mezzanine connector 108 and / or arrangement of heatsink 120 and board 102, 106 can be configured to support high data rates and low data trace lengths. The mezzanine connector 108 and / or arrangement of heatsink 120 and boards 102, 106 can support high density connectivity (i.e., a high number of pins in the connector). The mezzanine connector 108 and / or arrangement of heatsink 120 and boards 102, 106 can also support reduced connector sizes and more advantageous connector layouts as compared to existing solutions (e.g., which allows for better airflow and cooling properties to the FPGA chip).

[0108] Optionally, a mezzanine board may be connected to two or more FPGA boards. For example, the mezzanine board 106 of Figure 1 has two connectors 108a and 108b, and may be connected to a first FPGA board viaconnector 108a and to a second FPGA board via connector 108b. Accordingly, a mezzanine board 106 may be positioned partially overlying each of two or more FPGA boards 102. In some embodiments, boards are connected staggered with two or more FPGA boards connected to one or more mezzanine boards. Referring to Figure 7 A, illustrated is another circuit assembly 150 in which an example mezzanine board 106 overlies two FPGA boards 102 and is connected to one of the two FPGA boards 102 via one rigid connection 108 and to the other FPGA board 102 via another rigid connection 108. The pattern can be continued with further mezzanine boards and FPGA boards, and Figure 7A shows a staggered assembly of two mezzanine boards and two FPGA boards. It will be appreciated that more than two boards of one type may be connected each to a single board of another type, such as if four FPGA boards are each connected to the same mezzanine board (e.g., each overlying a corner of the mezzanine board). Each mezzanine board at least partially overlies each FPGA board to which it is connected to allow for a rigid connector between the two.

[0109] One or more heat sinks 120 can be positioned between the FPGA board(s) 102 and mezzanine board(s) 106 when arranged in a staggered configuration. The heat sink 120 may be arranged at any suitable position between the boards 102 and 106. For example, the heat sink 120 may be sized and positioned to align with the FPGA board 102, such as the example shown in Figure 7A. Figures 7B and 7C show alternative embodiments of circuit assemblies 152, 154, in which the heat sink 120 is sized and positioned to align with the mezzanine board 106 (Figure 7B) or sized and positioned to span multiple adjacent boards of one type (Figure 7C).

[0110] A staggered arrangement allows a mezzanine board to be designed to have its own functionality. For example, three FPGA boards may each be attached to a first mezzanine board having a first functionality and a second mezzanine board having a second, different functionality. A mezzanine board may provide any suitable functionality. For example, different functionalities for different mezzanine boards could be different network ports, gearboxes converting one protocol to another, boards interconnectfunctionality, cross-point chip, another smaller FPGA or a controller chip. In some embodiments, staggered mezzanine and FPGA boards is used to connect two FPGA boards, e.g., useful for tasks that require double FPGA resources.

[0111] Referring to Figure 8, an example method 200 is illustrated. Method 200 includes, at step 202, receiving a FPGA board which includes an FPGA chip (e.g., the board 102 including the chip 104 of Figure 1 ) and a mezzanine board (e.g., the mezzanine board 106 of Figure 1).

[0112] Method 200 includes, at step 204, assembling a circuit assembly (e.g., the circuit assembly 100 of Figure 1 ) with the FPGA board communicatively coupled to the mezzanine board.

[0113] In some examples, the FPGA board and the mezzanine board are assembled in any suitable way. In some examples, step 204 includes assembling the circuit assembly with a heatsink (e.g., heat sink 120) between the FPGA board and the mezzanine board. A mezzanine connector communicatively connecting the FPGA board and the mezzanine board may extend through an opening in the heatsink (e.g.., opening 126).

[0114] In some examples, any suitable mezzanine connection may be used to communicatively couple the FPGA board and the mezzanine board. In some examples, step 204 includes physically connecting a mezzanine connection by physically mating a plug member mounted to one of the mezzanine board and the FPGA board with a socket member mounted to the other of the mezzanine board and the FPGA board. In some examples, the mezzanine connection is a high-density mezzanine card solid connector.

[0115] It will be appreciated that numerous specific details are set forth in order to provide a thorough understanding of the example embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. Furthermore, this description and the drawings are not to be considered as limiting the scope of the embodiments described herein in anyway, but rather as describing the implementation of the various embodiments described herein.

[0116] As used herein, the wording “and / or” is intended to represent an inclusive - or. That is, “X and / or Y” is intended to mean X or Y or both, for example. As a further example, “X, Y, and / or Z” is intended to mean X or Y or Z or any combination thereof.

[0117] While the above description describes features of examples, it will be appreciated that some features and / or functions of the described examples are susceptible to modification without departing from the spirit and principles of operation of the described examples. For example, the various characteristics which are described by means of the represented examples or examples may be selectively combined with each other. Accordingly, what has been described above is intended to be illustrative of the claimed concept and non-limiting. It will be understood by persons skilled in the art that other variants and modifications may be made without departing from the scope of the invention as defined in the claims appended hereto. The scope of the claims should not be limited by the preferred examples and examples, but should be given the broadest interpretation consistent with the description as a whole.

Claims

CLAIMS:

1. A circuit assembly, comprising: a Field Programmable Gate Array (FPGA) board including a FPGA chip; a mezzanine board; a heat sink between the FPGA board and the mezzanine board; and a rigid mezzanine connection between the FPGA board and the mezzanine board, the rigid mezzanine connection extending through an opening in the heat sink.

2. The assembly of claim 1 , wherein the opening is an aperture through the heat sink.

3. The assembly of claim 1 , wherein the opening is a notch in an edge of the heat sink.

4. The assembly of any one of claims 1 to 3, wherein the rigid mezzanine connection is a high-density mezzanine card solid connector.

5. The assembly of claim 4, wherein the high-density mezzanine card solid connector has a high pin density allowing for a high-speed connection between the FPGA chip and the mezzanine card.

6. The assembly of any one of claims 1 to 5, wherein the mezzanine board includes a further connector communicatively coupled to the FPGA chip via the mezzanine connection.

7. The assembly of claim 6, wherein the heatsink has a plurality of generally parallel flow channels, the further connector has a further connector heat sink comprising a plurality of further connector flow channels, and the plurality offurther connector flow channels extend generally parallel to the plurality of flow channels of the heatsink.

8. The assembly of claim 7, wherein the further connector flow channels are substantially aligned with the plurality of flow channels of the heatsink.

9. The assembly of any one of claims 1 to 8, wherein the rigid mezzanine connection is adjacent a first lateral side of the FPGA chip and the circuit assembly includes a second rigid mezzanine connection between the FPGA board and the mezzanine board, the second rigid mezzanine connection adjacent a second lateral side of the FPGA chip opposite the first lateral side of the FPGA chip.

10. The assembly of claim 9, wherein the rigid mezzanine connection and the second rigid mezzanine connection each have a long dimension, and the rigid mezzanine connection and the second rigid mezzanine connection are arranged with the long dimensions extending generally parallel to one another.

11. The assembly of any one of claims 1 to 10, wherein the rigid mezzanine connection has a long dimension and the heatsink has a plurality of generally parallel flow channels, and the rigid mezzanine connection is arranged with the long dimension extending generally parallel to the plurality of flow channels of the heatsink.

12. The assembly of any one of claims 1 to 11 , wherein the heat sink comprises a plurality of openings and the rigid mezzanine connection is one of a plurality of rigid mezzanine connections, and each rigid mezzanine connection in the plurality of rigid mezzanine connections extends through a corresponding opening in the plurality of openings in the heat sink.

13. The assembly of claim 12, wherein the plurality of openings includes at least one aperture and at least one notch.

14. The assembly of any one of claims 1 to 13, wherein the opening is a connection path cut into the heat sink.

15. The assembly of any one of claims 1 to 14, wherein the mezzanine board is a first mezzanine board and the rigid mezzanine connection is a first board rigid mezzanine connection, the assembly further comprises a second mezzanine board and a second board rigid mezzanine connection between the FPGA board and the second mezzanine board, and the first mezzanine board and the second mezzanine board are adjacent one another and each overlies the FPGA board.

16. The assembly of claim 15, wherein the FPGA board is a first FPGA board, and the assembly further comprises a second FPGA board and a third board rigid mezzanine connection between the second FPGA board and the first mezzanine board, the first FPGA board and the second FPGA board are adjacent one another, and the first mezzanine board overlies each of the first FPGA board and the second FPGA board.

17. The assembly of any one of claims 1 to 16, wherein the FPGA chip and the rigid mezzanine connection are on the same face of the FPGA board.

18. The assembly of any one of claims 1 to 17, wherein the heat sink has a recessed section and the mezzanine board is nested within the recessed section.

19. The assembly of claim 18, wherein the heat sink has a non-recessed section having a first height and a combined height of the recessed section and the mezzanine board nested within the recessed section is not greater than the first height.

20. The assembly of any one of claims 18 and 19, wherein the recessed section overlies the FPGA chip.

21. The assembly of any one of claims 1 to 20, wherein a total combined height of the circuit assembly is not greater than 39.04mm.

22. A method of assembling a circuit assembly, comprising: receiving a Field Programmable Gate Array (FPGA) board including a FPGA chip, a heat sink, and a mezzanine board; arranging the heat sink between the FPGA board and the mezzanine board; and communicatively coupling the FPGA board to the mezzanine board through an opening in the heat sink.

23. A circuit assembly, comprising: a Field Programmable Gate Array (FPGA) board including a FPGA chip; a mezzanine board; a heat sink interposed between the FPGA board and the mezzanine board, wherein the heat sink comprises a plurality of flow channels extending substantially in a longitudinal direction; and an elongated rigid connector extending between the FPGA board and the mezzanine board through an opening in the heat sink, wherein a long dimension of the elongated rigid connector extends substantially in the longitudinal direction.

24. The assembly of claim 23, wherein the FPGA chip and the rigid mezzanine connection are on the same face of the FPGA board.

25. The assembly of any one of claims 23 and 24, wherein the rigid connector is adjacent a first lateral side of the FPGA chip and the circuit assembly includes a second rigid connector extending between the FPGA board and the mezzanine board through a second opening in the heat sink, the second rigid connector positioned adjacent to a second lateral side of the FPGA chip opposite the first lateral side of the FPGA chip.

26. The assembly of claim 25, wherein a second long dimension of the second rigid connector extends substantially in the longitudinal direction.

27. The assembly of any one of claims 23 to 26, wherein the heat sink has a recessed section and the mezzanine board is nested within the recessed section.

28. The assembly of claim 27, wherein the heat sink has a non-recessed section having a first height and a combined height of the recessed section and the mezzanine board nested within the recessed section is not greater than the first height.

29. The assembly of any one of claims 27 and 28, wherein the recessed section overlies the FPGA chip.

30. The assembly of any one of claims 23 to 29, wherein a total combined height of the circuit assembly is not greater than 39.04mm.

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