A touchless chip detection system

Abstract

This invention discloses a contactless chip testing system. The platform includes a PC, a data parsing / forwarding module, a source signal excitation module, a gating array, and a chip slot under test. The platform allows for simultaneous multi-selection via a PC's visual interface, enabling automated integrated testing of resistance, capacitance, package integrity, voltage, and overall power consumption between any chip pins. Compared to traditional mechanical probe-based contact testing systems, this invention is more compact. Furthermore, it employs an automatically gating physical path switching method, resulting in a higher switching rate and more efficient package testing.

Description

Technical Field

[0001] This invention relates to the fields of electronic technology and chip packaging and testing technology. Specifically, it relates to a probe-free chip packaging and testing system. Background Technology

[0002] Currently, integrated circuits are developing towards high performance and high integration, with the number of transistors integrated into a single device increasing and the size of the device decreasing. Chip packaging and testing is an essential step in the functional verification of chips before they leave the factory, used to determine whether the chip can function properly. Traditional chip packaging and testing technology uses a combination of manual and mechanical probes, testing by touching the corresponding pins of the chip. However, firstly, chip testing systems using mechanical probes are bulky and have a high barrier to entry; secondly, as the pin spacing of chips continues to shrink and the number of integrated pins increases, the precision testing work makes the point-contact testing method prone to problems such as accidental short circuits; and thirdly, each test of multiple pairs of pins requires repeated manual adjustment of the probe position, and the monotonous mechanical work can easily lead to oversights in the test. Summary of the Invention

[0003] The purpose of this invention is to provide a fully automated packaging and testing system for increasingly precise and miniaturized integrated circuit chips, aiming to:

[0004] (1) By using the circuit selection method, the preset test pin package can be arbitrarily selected and switched without additional operation, achieving higher test efficiency while being compact in size;

[0005] (2) Achieve integrated testing of multiple items, including resistance testing between arbitrary pins, capacitance testing between pins, package integrity testing between pins, logic voltage testing between pins, and chip power consumption testing.

[0006] (3) It can perform automated project testing based on user-defined test sequences.

[0007] The specific technical solution for achieving the objective of this invention is as follows:

[0008] A contactless chip testing system includes a PC, a data parsing / forwarding module, a source signal excitation module, a gating array, a signal source arbitration module, and a chip slot under test. The PC is connected to the data parsing / forwarding module, and the input operations of the PC are converted into corresponding test commands sent to the data parsing / forwarding module through a streaming instruction conversion algorithm.

[0009] The data parsing / forwarding module is connected to the PC, the source signal excitation module and the gating array. According to the instructions received by the PC, it activates the physical path and functional module in the gating array corresponding to the pin of the chip under test, and requests the signal source for testing from the source signal excitation module. At the same time, it corrects the test result and reports it to the PC.

[0010] The source signal excitation module is connected to the signal source arbitration module, and guides the signal quantity used for testing to the designated test position of the signal source arbitration module;

[0011] The gating array is connected to the data parsing / forwarding module and the chip slot under test, providing and maintaining the physical path for testing the chip slot under test, while uploading the test result value to the data parsing / forwarding module;

[0012] The signal source arbitration module is connected to the source signal excitation module and the gating array, and is used to receive the signal generated by the source signal excitation module, and output the excitation signal to the specified position of the gating array according to the signal source mixing algorithm;

[0013] The chip under test slot is connected to the gating array to load and unload the chip under test package, so that it can be connected to the circuit in the gating array.

[0014] The test calibration board is connected to the chip slot under test, and the nominal components on the test calibration board, such as fixed resistors and fixed capacitors, are used to calibrate the data error of the detection system.

[0015] The data parsing / forwarding module includes a respiratory detection module, an instruction parsing module, a control scheduling module, and a data reporting module;

[0016] The respiratory detection module is connected to a PC to receive communication establishment data from the PC and dynamically detect the connection status with the PC.

[0017] The instruction parsing module is connected to the PC and the control scheduling module to distinguish data packets from the PC, parse the test item information and test pin information in them, and inform the control scheduling module.

[0018] The control and scheduling module is connected to the instruction parsing module, the source signal excitation module, and the gating array. It is used to receive test information from the instruction parsing module, selectively activate the signal source in the source signal excitation module according to the test item information, and selectively connect the switch in the gating array according to the test pin information.

[0019] The data reporting module is connected to the PC and the gating array to receive the test data returned by the gating array, correct the data based on the calibration value, and return the results to the PC for display.

[0020] The source signal excitation module includes a feedback adjustment circuit, an adjustable compensation voltage source, an anti-temperature drift voltage source, an oscillation controller, and a high harmonic voltage-controlled temperature-compensated oscillator.

[0021] The feedback adjustment circuit is connected to the control scheduling module and the adjustable compensation voltage source. When the control scheduling module informs the source signal excitation module that the test item is a specified pin resistance test, a specified pin capacitance test, or a specified pin package integrity test, the adjustable compensation voltage source is adjusted to the specified voltage value according to the test information, and the feedback signal from the adjustable compensation voltage source is received at all times to keep the output of the adjustable compensation voltage source dynamically stable.

[0022] The adjustable compensation voltage source shown is connected to the feedback adjustment circuit and the signal source arbitration module. It adjusts the current voltage value output by the voltage source according to the preset selectable value and the signal of the self-feedback adjustment circuit, and sends the feedback information of the current voltage source to the feedback adjustment circuit to maintain the dynamic stability of the output and make the output more resistant to interference. At the same time, the output voltage signal is sent to the signal source arbitration module to arbitrate the excitation source.

[0023] The anti-temperature drift voltage source is connected to the control scheduling module and the signal source arbitration module. When the control scheduling module informs the source signal excitation module that the test item is the package integrity test between specified pins, the logic voltage test of specified pins, or the chip power consumption test, the precision constant voltage output is connected to the signal source arbitration module to arbitrate the excitation source according to the test information.

[0024] The oscillation controller is connected to the control scheduling module and the high harmonic voltage-controlled temperature compensated oscillator. When the control scheduling module informs the source signal excitation module of the test item, the high harmonic voltage-controlled temperature compensated oscillator is adjusted to the output waveform of the specified frequency according to the test information.

[0025] The high harmonic voltage-controlled temperature-compensated oscillator shown is connected to the oscillation controller and the signal source arbitration module. According to the signal from the oscillation controller, the current voltage source outputs a high-frequency, stable, and multi-waveform signal that can resist temperature deviation interference caused by long-term operation. The output voltage signal is then sent to the signal source arbitration module to arbitrate the excitation source.

[0026] The gating array includes an array scheduling module, a resistance acquisition module, a capacitance acquisition module, a package continuity determination module, a voltage acquisition module, and a current acquisition module.

[0027] The array scheduling module is connected to the control scheduling module, data reporting module, resistance acquisition module, capacitance acquisition module, package integrity judgment module, voltage acquisition module, current acquisition module and the chip under test slot. After receiving the test pin information from the control scheduling module, it opens the physical path to the corresponding pin in the chip under test slot, and selectively connects to the resistance acquisition module, capacitance acquisition module, package integrity judgment module, voltage acquisition module and current acquisition module according to the test item information for signal acquisition. At the same time, the acquired signal is transmitted back through the data reporting module.

[0028] The resistance acquisition module is connected to the array scheduling module and the signal source arbitration module. When the test items are the resistance test between specified pins and the capacitance test between specified pins, the corresponding physical quantities are acquired according to the physical path of the array scheduling module and the excitation signal provided by the signal source arbitration module, and converted into resistance values ​​through a measurement compensation algorithm.

[0029] The capacitance acquisition module is connected to the array scheduling module and the signal source arbitration module. When the test items are the resistance test between specified pins and the capacitance test between specified pins, the corresponding physical quantities are acquired according to the physical path of the array scheduling module and the excitation signal provided by the signal source arbitration module, and converted into capacitance values ​​through the measurement compensation algorithm.

[0030] The package integrity determination module is connected to the array scheduling module and the signal source arbitration module. When the test item is the package integrity between specified pins, the corresponding physical quantities are collected and converted into voltage-current scatter data according to the physical path of the array scheduling module and the excitation signal provided by the signal source arbitration module.

[0031] The voltage acquisition module is connected to the array scheduling module and the signal source arbitration module. When the test item is a logic voltage test of a specified pin, the corresponding physical quantity is acquired and converted into a voltage value according to the physical path of the array scheduling module and the excitation signal provided by the signal source arbitration module.

[0032] The current acquisition module is connected to the array scheduling module and the signal source arbitration module. When the test item is chip power consumption test, the corresponding physical quantity is acquired and converted into current value according to the physical path of the array scheduling module and the excitation signal provided by the signal source arbitration module.

[0033] The streaming instruction conversion algorithm, used to reduce the actual number of switching operations of the gating array and improve the system's lifespan, includes the following steps:

[0034] 1) Receive all test information selected by the user from the PC visual operation.

[0035] 2) If the test item is a specified pin resistance test, specified pin capacitance test, or specified pin package integrity test, then first construct an ordered instruction set with unidirectional hash table characteristics based on the test pin information. If the test item is a specified pin logic voltage test or chip power consumption test, only a general instruction set is constructed.

[0036] 3) Based on the instruction set, firstly, perform a depth-first traversal of the set and convert it into the platform's recognition format.

[0037] 4) Label the converted instructions with data according to the test items, integrate all the instruction sets into a data instruction stream, and send it to the data parsing / forwarding module.

[0038] The signal source mixing algorithm is used to combine and output excitation signals that conform to the various acquisition modules, thereby reducing system complexity. It includes the following steps:

[0039] 1) Monitor all excitation signal output paths from the source signal excitation module;

[0040] 2) If only the adjustable compensation voltage source and the high harmonic voltage-controlled temperature-compensated oscillator have output signals, then connect the output signals to the resistance acquisition module and the capacitance acquisition module.

[0041] 3) If only the adjustable compensation voltage source and the anti-temperature drift voltage source exist, and there is an output signal, then connect the output signal to the package integrity determination module.

[0042] 4) If only the temperature drift-resistant voltage source has an output signal, then connect the output to the voltage acquisition module and the current acquisition module.

[0043] 5) If any of the above conditions exist, report a signal source setting error to the system and wait for a reset and restart.

[0044] The measurement compensation algorithm, used to eliminate parasitic errors during the measurement process, includes the following steps:

[0045] 1) If the test item is a resistance test between specified pins or a capacitance test between specified pins, the array control module controls the switch array to connect the specified pins of the chip under test slot, the resistance acquisition module, and the capacitance acquisition module.

[0046] 2) If the test item is a specified pin resistance test, the resistance between the specified pins is acquired based on the built-in circuit of the resistance acquisition module and the resistance acquisition module, while the parasitic capacitance value is sampled by the parallel-connected capacitance acquisition module; if the test item is a specified pin capacitance test, the capacitance between the specified pins is acquired based on the capacitance acquisition module and the capacitance acquisition module, while the parasitic resistance value is sampled by the parallel-connected resistance acquisition module.

[0047] 3) After sampling, the data is uploaded to the data reporting module via the array control module. The data reporting module corrects the data based on the test items and sampled values ​​selected by the system to obtain the final test results.

[0048] The beneficial effects of this invention are:

[0049] (1) The present invention adjusts the chip packaging test conditions by using physical path selection, which has a fast switching speed and effectively improves test efficiency while ensuring test accuracy.

[0050] (2) This invention abandons the traditional mechanical probe and adopts an array switch, which reduces the size of the detection system and the threshold for use, making the overall detection system lighter while ensuring the integrity of the test.

[0051] (3) This invention allows for the selection of multiple test groups at once through visual operation, and can be automated by the platform. It is simple to operate and has a wide range of functions.

[0052] (4) The present invention uses an expandable chip socket, which can be compatible with chip testing with different pin counts and different package types, and will not perform destructive testing on the test chip.

[0053] (5) The present invention adopts a protective design, which can support continuous testing for a long time and the error caused by the system's own running time is small. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the structure of the present invention;

[0055] Figure 2 This is a schematic diagram illustrating the resistance test between specified chip pins in an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram illustrating the capacitance test between specified chip pins in an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram illustrating the packaging integrity test between specified chip pins in an embodiment of the present invention;

[0058] Figure 5 This is a schematic diagram illustrating the logic voltage test of a specified chip pin in an embodiment of the present invention;

[0059] Figure 6 This is a schematic diagram illustrating the power consumption test of a specified chip in an embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram of the streaming instruction conversion algorithm in an embodiment of the present invention;

[0061] Figure 8This is a schematic diagram of the signal source mixing algorithm in an embodiment of the present invention;

[0062] Figure 9 This is a schematic diagram of the measurement compensation algorithm in an embodiment of the present invention. Detailed Implementation

[0063] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0064] Example

[0065] See Figure 1 This embodiment includes a PC 1, a data parsing / forwarding module 2, a source signal excitation module 3, a gating array 4, a signal source arbitration module 5, a chip under test slot 6, and a test calibration board 7.

[0066] The PC 1 is connected to the data parsing / forwarding module 2;

[0067] The data parsing / forwarding module 2 is connected to the PC 1, the source signal excitation module 3, and the gating array 4.

[0068] The source signal excitation module 3 is connected to the signal source arbitration module 5;

[0069] The gating array 4 is connected to the data parsing / forwarding module 2 and the chip slot 6 under test;

[0070] The signal source arbitration module 5 is connected to the source signal excitation module 3 and the gating array 4;

[0071] The chip under test slot 6 is connected to the gating array 4.

[0072] See Figure 1 The data parsing / forwarding module 2 in this embodiment includes a breathing detection module 21, an instruction parsing module 22, a control scheduling module 23, and a data reporting module 24. The breathing detection module 2 receives communication establishment data from PC 1, dynamically detects the connection status with PC 1, and requests to establish a connection with PC 1 according to the USB standard specification when the connection is lost. The instruction parsing module 22 distinguishes between communication establishment data, data packets, or termination packets representing the end of a command from data packets from PC 1, discards all communication establishment data, and parses the test item information and test pin information of the data packets, informing the control scheduling module 23, and using the receipt of a termination packet as the end marker. The control scheduling module 23 receives test information from data packets from the instruction parsing module 22, and selectively activates the signal source in the source signal excitation module 3 according to the test item information, and selectively connects the connection relationships in the gating array 4 according to the test pin information. The data reporting module 24 receives the test data returned by the gating array 4, corrects the data based on the calibration value, and returns the results to PC 1 for display.

[0073] See Figure 1 In this embodiment, the source signal excitation module 3 includes a feedback adjustment circuit 31, an adjustable compensation voltage source 32, an anti-temperature drift voltage source 33, an oscillation controller 34, and a high-harmonic voltage-controlled temperature-compensated oscillator 35. When the control scheduling module 23 informs the source signal excitation module 3 that the test item is a specified pin-to-pin resistance test, a specified pin-to-pin capacitance test, or a specified pin-to-pin package integrity test, the feedback adjustment circuit 31 receives relevant enable information and generates excitation based on the required voltage value. It adjusts the adjustable compensation voltage source 32 to the specified voltage value and connects it to the signal source arbitration module 5 for arbitration of the excitation source. The adjustable compensation voltage source 32 outputs a voltage signal to the signal source arbitration module 5 and simultaneously outputs a feedback signal to the feedback adjustment circuit 31. When the feedback adjustment circuit 31 captures the feedback signal, it determines whether the output of the adjustable compensation voltage source 32 deviates from the normal output value and adjusts the excitation to maintain the dynamic stability of the signal source and enhance its anti-interference capability. When the control scheduling module 23 informs the source signal excitation module 3 that the test item is a specified pin package integrity test, a specified pin logic voltage test, or a chip power consumption test, the precision constant voltage output 33 is connected to the signal source arbitration module 5 to arbitrate the excitation source according to the test information. Because it has inherent temperature drift resistance, it can suppress error effects caused by heat generated during long-term system operation. When the control scheduling module 23 informs the source signal excitation module 3 that the test item is a specified pin resistance test or a specified pin capacitance test, the oscillation controller 34 receives the relevant enable information and, according to the test information, outputs a signal source of the specified frequency and shape from the high-harmonic voltage-controlled temperature-compensated oscillator 35, sending it to the signal source arbitration module 5 to arbitrate the excitation source.

[0074] See Figure 1The selection array 4 in this embodiment includes an array scheduling module 41, a resistance acquisition module 42, a capacitance acquisition module 43, a package continuity determination module 44, a voltage acquisition module 45, and a current acquisition module 46. After receiving the test pin information from the self-control scheduling module 23, the array scheduling module 41 opens the physical path to the relevant pins in the chip slot 6 under test, and selectively connects the resistance acquisition module 42, capacitance acquisition module 43, package integrity determination module 44, voltage acquisition module 45, and current acquisition module 46 to acquire signals according to the test item information. At the same time, the acquired signals are transmitted back through the data reporting module 23. When the test item is a resistance test between specified pins and a capacitance test between specified pins, the resistance acquisition module 42 acquires the corresponding physical quantity according to the physical path of the array scheduling module 41 and the excitation signal provided by the signal source arbitration module 5, and converts it into a resistance value through a measurement compensation algorithm. During inter-pin capacitance testing, based on the physical path of the array scheduling module 41 and the excitation signal provided by the signal source arbitration module 5, the capacitance acquisition module 43 acquires the corresponding physical quantity and converts it into capacitance value through a measurement compensation algorithm. When the test item is the package integrity between specified pins, based on the physical path of the array scheduling module 41 and the excitation signal provided by the signal source arbitration module 5, the package continuity judgment module acquisition module 44 acquires the corresponding physical quantity and converts it into voltage-current scatter data through calculation. When the test item is the logic voltage test of specified pins, based on the physical path of the array scheduling module 41 and the excitation signal provided by the signal source arbitration module 5, the voltage acquisition module 45 acquires the corresponding physical quantity and converts it into voltage value through calculation. When the test item is the chip power consumption test, based on the physical path of the array scheduling module 41 and the excitation signal provided by the signal source arbitration module 5, the current acquisition module 46 acquires the corresponding physical quantity and converts it into current value through calculation.

[0075] See Figure 2 Taking the resistance test between specified pins of a chip as an example, PC 1 first uses a streaming instruction conversion algorithm (see...) Figure 7 The command parsing module 22 sends a resistance test command between specified pins A and B. After parsing, the command sends information to the control scheduling module 23 indicating that the selected test item is resistance testing and the test pins are pins A and B. The control scheduling module 23, based on its internal lookup relationships, sends enable signals to the feedback adjustment circuit 31 and the oscillation controller 34 according to the test item. It also informs the feedback adjustment circuit 31 that the required voltage for testing and the oscillation controller 34 that the required signal is a high-frequency square wave signal, generated by the adjustable compensation voltage source 32 and the high-harmonic voltage-controlled temperature-compensated oscillator 35, and then connects to the signal source arbitration module 5. The signal source arbitration module 5 uses a signal source mixing algorithm (see [reference]). Figure 8The excitation signal is output to the resistance acquisition module 42 and the capacitance acquisition module 43; on the other hand, test information is sent to the array control module 41 to close the switch array, so that pins A and B of the chip under test slot 6 can only be connected to the resistance acquisition module 42 and the capacitance acquisition module 43, thus completing the connection of the physical path required for the test. According to the measurement compensation algorithm (see...) Figure 9 The internal resistance between pins A and B of the chip under test (TUT) slot 6 and the built-in circuit of the resistance acquisition circuit 42 form a complete acquisition circuit. The physical quantities are acquired by the resistance acquisition circuit 42 and the capacitance acquisition circuit 43 connected in parallel under the output excitation of the anti-temperature drift voltage source 33 and the high harmonic voltage-controlled temperature compensated oscillator 35. The resistance and parasitic capacitance values ​​between pins A and B are obtained. The measured data is transmitted back to the data reporting module 24 through the array control module 41. The data is then corrected in the data reporting module 24 to obtain the final accurate resistance value, which is then transmitted back to the PC 1 to display the final result.

[0076] See Figure 3 Taking the capacitance test between specified pins of a chip as an example, PC 1 first uses a streaming instruction conversion algorithm (see...) Figure 7 The command parsing module 22 sends a capacitance test command between specified pins A and B. After parsing, it sends the selected test item (capacity test) and the test pins (pins A and B) to the control scheduling module 23. The control scheduling module 23, based on its internal lookup relationships, sends enable signals to the feedback adjustment circuit 31 and the oscillation controller 34 according to the test item. It also informs the feedback adjustment circuit 31 that the required voltage for the test and the oscillation controller 34 that the required signal is a high-frequency square wave signal, generated by the adjustable compensation voltage source 32 and the high-harmonic voltage-controlled temperature-compensated oscillator 35, and then connects them to the signal source arbitration module 5. The signal source arbitration module 5 uses a signal source mixing algorithm (see [reference]). Figure 8 The excitation signal is output to the resistance acquisition module 42 and the capacitance acquisition module 43; on the other hand, test information is sent to the array control module 41 to close the switch array, so that pins A and B of the chip under test slot 6 can only be connected to the resistance acquisition module 42 and the capacitance acquisition module 43, thus completing the connection of the physical path required for the test. According to the measurement compensation algorithm (see...) Figure 9 The capacitance and resistance values ​​between pins A and B of the chip under test (TUT) are integrated into the capacitance acquisition circuit 43, forming a complete acquisition circuit. The capacitance acquisition circuit 43 and the resistance acquisition circuit 42 connected in parallel are used to acquire physical quantities under the excitation of the anti-temperature drift voltage source 33 and the high harmonic voltage-controlled temperature compensated oscillator 35. The capacitance and resistance values ​​between pins A and B, which contain parasitic parameters, are obtained. The measured data is transmitted back to the data reporting module 24 through the array control module 41. The data is then corrected in the data reporting module 24 to obtain the final accurate resistance value, which is then transmitted back to the PC 1 to display the final result.

[0077] See Figure 4 Taking the package integrity test between specified pins of a chip as an example, PC 1 first uses a streaming instruction conversion algorithm (see...) Figure 7 The instruction parsing module 22 sends a test instruction for the encapsulation integrity between specified pins A and B. After parsing, the instruction parsing module 22 sends the selected test item (encapsulation integrity test) and the test pins (pins A and B) to the control scheduling module 23. The control scheduling module 23, based on its internal lookup relationships, sends enable signals to the feedback adjustment circuit 31 and the anti-temperature drift voltage source 33 according to the test item. It also informs the feedback adjustment circuit 31 that the required test signal consists of several discrete voltage values, generated by the adjustable compensation voltage source 32. These values, along with the output of the anti-temperature drift voltage source 33, are connected to the signal source arbitration module 5. The signal source arbitration module 5 then uses a signal source mixing algorithm (see [reference]) to perform the test. Figure 8 The excitation signal is output to the package integrity judgment module 44; on the other hand, test information is sent to the array control module 41, and the switch array is closed so that pins A and B of the chip under test slot 6 can only be connected to the package integrity judgment module 44, thus completing the connection of the physical path required for the test. The internal ESD isolation characteristics of the pins A and B of the chip under test slot 6 and the circuit of the package integrity judgment module 44 form a complete acquisition circuit. The package integrity judgment module 44 performs physical quantity acquisition under the excitation of multiple excitation voltage values ​​of the adjustable compensation voltage source and the output excitation of the anti-temperature drift voltage source 33, and obtains a scatter plot of the voltage-current characteristic curve between pins A and B. The array control module 41 transmits the measured data back to the data reporting module 24, and performs numerical correction in the data reporting module 24 according to the data. Combined with the basic diode electrical characteristic curve, it determines whether there is package isolation between pins A and B, and transmits the result back to the PC 1 to display the final result.

[0078] See Figure 5 Taking the measurement of the logic voltage of a specific pin on a chip as an example, PC 1 first uses a streaming instruction conversion algorithm (see...) Figure 7 The instruction parsing module 22 sends a logic voltage test instruction to test all pins of the IC under test. The instruction includes characteristic constraints on the specified pins, such as input / output direction, input excitation signal, and whether measurement is required. After parsing, the instruction sends information to the control scheduling module 23 indicating that the selected test item is logic voltage test, that all pins are being tested, and the constraints on all pins. The control scheduling module 23, based on its internal lookup relationship, sends enable signals to the temperature drift-resistant voltage source 33 according to the test item, connecting the output of the temperature drift-resistant voltage source 33 to the signal source arbitration module 5. The signal source arbitration module 5 then uses a signal source mixing algorithm (see [reference]). Figure 8The excitation signal is output to the voltage acquisition module 45; on the other hand, test information is sent to the array control module 41, and the switch array is closed so that all pins of the chip under test slot 6 can only be connected to the voltage acquisition module 45, thus completing the connection of the physical path required for the test. The array control module 41 informs the voltage acquisition module 45 of all test sequences and the constraint relationship of each test on the pins. The voltage acquisition module adjusts the excitation of some pins, and at the same time acquires the voltage values ​​of pins A, B, C, etc. from the output of pins A, B, C, etc. of the chip under test slot 6. The array control module 41 transmits the measured data back to the data reporting module 24, and performs numerical correction on the data according to the data. It compares the constraint information of the test pins to determine whether the chip can meet the normal logic operation, and transmits the data back to the PC 1 to display the final result.

[0079] See Figure 6 Taking the measurement of chip power consumption as an example, PC 1 first uses a streaming instruction conversion algorithm (see...) Figure 7 The command to test the power consumption of the IC under test is sent to the command parsing module 22. After parsing, the command is sent to the control scheduling module 23, indicating that the selected test item is chip power consumption test, and the test pins are the VCC and GND pins of the chip. The control scheduling module 23, based on its internal lookup relationship, sends enable signals to the anti-temperature drift voltage source 33 according to the test item, and connects the output of the anti-temperature drift voltage source 33 to the signal source arbitration module 5. The signal source arbitration module 5 then uses a signal source mixing algorithm (see [reference]) to perform the test. Figure 8 The system determines the output and source of the signal and outputs the excitation signal to the voltage acquisition module 45. Simultaneously, it sends test information to the array control module 41, closing the switch array so that all pins of the chip under test slot 6 can only be connected to the current acquisition module 46, thus completing the physical path connection required for the test. A complete acquisition circuit is formed by the VCC and GND pins of the chip under test slot 6 and the circuit of the current acquisition module 46. The current acquisition module 46 acquires physical quantities under the excitation of the anti-temperature drift voltage source 33, obtaining the current value of the chip under the current operating conditions. The array control module 41 transmits the measured data back to the data reporting module 24, and performs numerical correction based on the data. The voltage output value of the anti-temperature drift voltage source, combined with the basic preset value, is converted into the chip's power consumption and transmitted back to the PC 1 to display the final result.

Claims

1. A contactless chip detection system, characterized in that, The system includes a PC (1), a data parsing / forwarding module (2), a source signal excitation module (3), a gating array (4), a signal source arbitration module (5), and a chip slot under test (6). The PC (1) is connected to the data parsing / forwarding module (2), and the input operation of the PC (1) is converted into the corresponding test command sent to the data parsing / forwarding module (2) through a streaming instruction conversion algorithm. The data parsing / forwarding module (2) is connected to the PC (1), the source signal excitation module (3) and the gating array (4). According to the instructions received by the PC (1), it activates the physical path and functional module corresponding to the pin of the chip under test in the gating array (4), and applies to the source signal excitation module (3) for a signal source for testing. At the same time, it corrects the test result and reports it to the PC (1). The source signal excitation module (3) is connected to the signal source arbitration module (5) to guide the signal quantity used for testing to the designated test position of the signal source arbitration module (5); The gating array (4) is connected to the data parsing / forwarding module (2) and the chip slot under test (6) to provide and maintain the physical path for testing the chip slot under test (6), and upload the test result value to the data parsing / forwarding module (2). The signal source arbitration module (5) is connected to the source signal excitation module (3) and the gating array (4) to receive the signal generated by the source signal excitation module (3) and output the excitation signal to the specified position of the gating array (4) according to the signal source mixing algorithm; The chip slot (6) under test is connected to the gating array (4) for loading and unloading the chip packaged under test, so that it is connected to the circuit in the gating array (4); wherein: The source signal excitation module (3) includes a feedback adjustment circuit (31), an adjustable compensation voltage source (32), an anti-temperature drift voltage source (33), an oscillation controller (34), and a high harmonic voltage-controlled temperature-compensated oscillator (35). The feedback adjustment circuit (31) is connected to the control scheduling module (23) and the adjustable compensation voltage source (32). When the control scheduling module (23) informs that the test item is a specified pin resistance test, a specified pin capacitance test, or a specified pin package integrity test, the adjustable compensation voltage source (32) is adjusted to the specified voltage value according to the test information content, and the feedback signal from the adjustable compensation voltage source (32) is received at all times to keep the output of the adjustable compensation voltage source (32) dynamically stable. The adjustable compensation voltage source (32) shown is connected to the feedback adjustment circuit (31) and the signal source arbitration module (5). It adjusts the voltage value of the current voltage source output according to the preset selectable value and the signal of the self-feedback adjustment circuit (31), and sends the feedback information of the current voltage source to the feedback adjustment circuit (31) to maintain the dynamic stability of the output and make the output more resistant to interference. At the same time, the output voltage signal is sent to the signal source arbitration module (5) to arbitrate the excitation source. The anti-temperature drift voltage source (33) is connected to the control scheduling module (23) and the signal source arbitration module (5). When the control scheduling module (23) informs that the test item is the package integrity test between specified pins, the logic voltage test of specified pins, or the chip power consumption test, the precision constant voltage output is connected to the signal source arbitration module (5) to arbitrate the excitation source according to the test information. The oscillation controller (34) is connected to the control scheduling module (23) and the high harmonic voltage-controlled temperature compensated oscillator (35). When the control scheduling module (23) informs that the test item is a specified pin resistance test or a specified pin capacitance test, the high harmonic voltage-controlled temperature compensated oscillator (35) is adjusted to the specified frequency output waveform according to the test information. The high harmonic voltage-controlled temperature-compensated oscillator (35) shown is connected to the oscillation controller (34) and the signal source arbitration module (5). According to the signal of the self-oscillation controller (34), the current voltage source outputs a high-frequency stable multi-waveform signal that can resist the interference of temperature deviation caused by long-term operation, and sends the output voltage signal to the signal source arbitration module (5) for arbitration of the excitation source.

2. The contactless chip detection system according to claim 1, characterized in that, It also includes a test calibration board (7), which is connected to the chip slot (6) under test. The nominal device on the test calibration board is used to calibrate the data error of the detection system.

3. The contactless chip detection system according to claim 1, characterized in that, The data parsing / forwarding module (2) includes a respiratory detection module (21), an instruction parsing module (22), a control scheduling module (23), and a data reporting module (24). The respiratory detection module (21) is connected to the PC (1) to receive communication establishment data from the PC (1) and dynamically detect the connection status with the PC (1); The instruction parsing module (22) is connected to the PC (1) and the control scheduling module (23) to distinguish data packets from the PC (1) and parse the test item information and test pin information therein, and inform the control scheduling module (23). The control and scheduling module (23) is connected to the instruction parsing module (22), the source signal excitation module (3) and the gating array (4) to receive test information from the instruction parsing module (22), and selectively activate the signal source in the source signal excitation module (3) according to the test item information, and selectively connect the switch connection in the gating array (4) according to the test pin information; The data reporting module (24) is connected to the PC (1) and the gating array (4) to receive the test data returned by the gating array (4), correct the data based on the calibration value, and return the data to the PC (1) to display the results.

4. The contactless chip detection system according to claim 1, characterized in that, The gating array (4) includes an array scheduling module (41), a resistance acquisition module (42), a capacitance acquisition module (43), a package continuity determination module (44), a voltage acquisition module (45), and a current acquisition module (46). The array scheduling module (41) is connected to the control scheduling module (23), the data reporting module (24), the resistance acquisition module (42), the capacitance acquisition module (43), the package integrity judgment module (44), the voltage acquisition module (45), the current acquisition module (46), and the chip slot under test (6). When it receives the test pin information from the control scheduling module (23), it opens the physical path to the corresponding pin in the chip slot under test (6). According to the test item information, it selectively connects to the resistance acquisition module (42), the capacitance acquisition module (43), the package integrity judgment module (44), the voltage acquisition module (45), and the current acquisition module (46) for signal acquisition. At the same time, it transmits the acquired signal back through the data reporting module (23). The resistance acquisition module (42) is connected to the array scheduling module (41) and the signal source arbitration module (5). When the test items are the resistance test between specified pins and the capacitance test between specified pins, the corresponding physical quantities are acquired according to the physical path of the array scheduling module (41) and the excitation signal provided by the signal source arbitration module (5), and converted into resistance values ​​through the measurement compensation algorithm. The capacitance acquisition module (43) is connected to the array scheduling module (41) and the signal source arbitration module (5). When the test items are the resistance test between specified pins and the capacitance test between specified pins, the corresponding physical quantities are acquired according to the physical path of the array scheduling module (41) and the excitation signal provided by the signal source arbitration module (5), and converted into capacitance values ​​through the measurement compensation algorithm. The package integrity determination module (44) is connected to the array scheduling module (41) and the signal source arbitration module (5). When the test item is the package integrity between specified pins, the corresponding physical quantity is collected and converted into voltage-current scatter data according to the physical path of the array scheduling module (41) and the excitation signal provided by the signal source arbitration module (5). The voltage acquisition module (45) is connected to the array scheduling module (41) and the signal source arbitration module (5). When the test item is the logic voltage test of a specified pin, the corresponding physical quantity is acquired and converted into a voltage value according to the physical path of the array scheduling module (41) and the excitation signal provided by the signal source arbitration module (5). The current acquisition module (46) is connected to the array scheduling module (41) and the signal source arbitration module (5). When the test item is chip power consumption test, the corresponding physical quantity is acquired and converted into current value according to the physical path of the array scheduling module (41) and the excitation signal provided by the signal source arbitration module (5).

5. The contactless chip detection system according to claim 1, characterized in that, The streaming instruction conversion algorithm, used to reduce the actual number of switching operations of the gating array and improve the system's lifespan, includes the following steps: 1) Receive all test information selected by the user from the PC (1) visualization operation; 2) If the test item is a specified pin resistance test, specified pin capacitance test, or specified pin package integrity test, then first construct an ordered instruction set with unidirectional hash table characteristics based on the test pin information; if the test item is a specified pin logic voltage test or chip power consumption test, only a general instruction set is constructed. 3) Based on the instruction set, firstly, perform a depth-first traversal of the set and convert it into the platform's recognition format; 4) Label the converted instructions with data according to the test items, and integrate all the instruction sets into a data instruction stream and send it to the data parsing / forwarding module (2).

6. The contactless chip detection system according to claim 1, characterized in that, The signal source mixing algorithm is used to combine and output excitation signals that conform to the various acquisition modules, thereby reducing system complexity. It includes the following steps: 1) Monitor all excitation signal output paths from the source signal excitation module (3); 2) If only the adjustable compensation voltage source (32) and the high harmonic voltage-controlled temperature-compensated oscillator (35) have output signals, then connect the output signals to the resistance acquisition module (42) and the capacitance acquisition module (43). 3) If only the adjustable compensation voltage source (32) and the temperature drift-resistant voltage source (33) exist and there is an output signal, then connect the output signal to the package integrity determination module (44). 4) If only the temperature drift-resistant voltage source (33) has an output signal, then connect the output to the voltage acquisition module (45) and the current acquisition module (46). 5) If any other situation exists besides the above, report a signal source setting error to the system and wait for a reset and restart.

7. The contactless chip detection system according to claim 4, characterized in that, The measurement compensation algorithm, used to eliminate parasitic errors during the measurement process, includes the following steps: 1) If the test item is a resistance test between specified pins or a capacitance test between specified pins, the array control module (41) controls the switch array to connect the specified pins of the chip slot (6) under test, the resistance acquisition module (42) and the capacitance acquisition module (43). 2) If the test item is a specified pin resistance test, the resistance between the specified pins is collected based on the built-in circuit of the resistance acquisition module (42) and the resistance acquisition module (42), and the parasitic capacitance value is sampled by the parallel-connected capacitance acquisition module (43); if the test item is a specified pin capacitance test, the capacitance between the specified pins is collected based on the built-in circuit of the capacitance acquisition module (43) and the capacitance acquisition module (43), and the parasitic capacitance value is sampled by the parallel-connected resistance acquisition module (43). 3) After sampling, the data is uploaded to the data reporting module (24) via the array control module (41). The data reporting module (24) corrects the data according to the test items and sampled values ​​selected by the system to obtain the final test results.

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