Super junction integration method and super junction integrated chip

Abstract

The invention discloses a super-junction integration method and a super-junction integrated chip, and belongs to the technical field of super-junction semiconductors, and the method comprises the steps: constructing a substrate layer; an integrated super-junction structure is formed on the substrate layer, the integrated super-junction structure defines an epitaxial layer and alternating P columns and N columns in the epitaxial layer, at least one isolation structure is arranged in the integrated super-junction structure, the isolation structure defines P beams, the P beams are located on the side, away from the substrate layer, in the epitaxial layer, and the bottoms of the P beams are connected with the corresponding P columns and N columns. The P beams and the P columns at the two sides enclose an isolation region at the top in the epitaxial layer; a super-junction MOS device and an isolation device are correspondingly formed on the integrated super-junction structure; the isolation region is constructed on the super junction structure and used for integrating the isolation device, the isolation device can be a low-voltage or medium-voltage control device, and integration of the super junction MOS chip and the control chip is achieved.

Description

Superjunction Integration Method and Superjunction Integrated Chip Technical Field

[0001] This application relates to the field of superjunction semiconductor technology, specifically to superjunction integration methods and superjunction integrated chips. Background Technology

[0002] Superjunction MOSFETs form multiple vertical PN junction structures by introducing alternating P-type and N-type regions within the drift region. This structure allows the device to maintain low on-resistance even at high voltages, thus improving energy efficiency. Compared to traditional MOSFETs, superjunction MOSFETs can significantly reduce on-resistance while maintaining high breakdown voltage, making them suitable for high-voltage, high-power applications. Currently, superjunction MOSFETs lack the technology to integrate other devices. For example, when superjunction MOSFETs are operating, external driver circuit chips are typically required for control. Currently, superjunction MOSFETs and low- or medium-voltage control chips operate independently. When these two independent devices are used together, the interconnections and parasitic parameters affect the switching speed and efficiency of the system. Furthermore, the combination of these two independent devices leads to irrational system reliability, a larger system size, and higher packaging costs.

[0003] Therefore, there is an urgent need to study superjunction integration technology for superjunction MOS devices. Summary of the Invention

[0004] The purpose of this application is to provide a superjunction integration method and a superjunction integrated chip. The main technical problem to be solved is that there is currently a lack of superjunction integration technology for superjunction MOS devices.

[0005] To achieve the above objectives, this application provides the following technical solution:

[0006] Superjunction integration methods, including,

[0007] Constructing the substrate layer;

[0008] Integrated superjunction structures are formed on the substrate.

[0009] The integrated superjunction structure defines an epitaxial layer and alternating P-pillars and N-pillars within the epitaxial layer. The integrated superjunction structure has at least one isolation structure, which defines a P-beam located inside the epitaxial layer on the side away from the substrate. The bottom of the P-beam connects to the corresponding P-pillar and N-pillar, and both ends extend to the two side P-pillars. The P-beam and the two side P-pillars form an isolation region at the top inside the epitaxial layer.

[0010] Superjunction MOS devices and isolation devices are formed on the integrated superjunction structure.

[0011] This application integrates a superjunction MOS chip and a control chip by constructing an isolation region on a superjunction structure. The isolation device can be a low-voltage or medium-voltage control device.

[0012] This application also discloses a superjunction integrated chip fabricated according to the superjunction integration method described above.

[0013] This application also discloses the application of the superjunction integrated chip described above in the fields of voltage conversion or power conversion.

[0014] Compared with the prior art, the advantages of this application are as follows:

[0015] This application provides a superjunction integration method and a superjunction integrated chip. By constructing an isolation region on the superjunction structure, an isolation device is integrated. This isolation device can be a low-voltage or medium-voltage control device, achieving the integration of the superjunction MOS chip and the control chip. Integrating multiple power devices and related control devices on the superjunction structure onto a single chip has the following advantages: Improved system performance: Integration reduces the number of interconnections and parasitic parameters between devices, improving the switching speed and efficiency of the system. Enhanced system reliability: The integrated design reduces external connections, lowers the probability of failure, and improves system reliability. Reduced system size: The integrated design significantly reduces the system size, facilitating miniaturization and lightweight design. Reduced cost: The integrated design reduces the number of devices and packaging costs, lowering the overall system cost. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 is a flowchart of the superjunction integration method.

[0018] Figure 2 is a schematic diagram of the integrated superjunction structure in the superjunction integration method.

[0019] Figure 3 is a schematic diagram of the forming of superjunction MOS devices and isolation devices in the superjunction integration method.

[0020] Figure 4 is a schematic diagram of the structure of the superjunction integrated chip in the superjunction integration method. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0023] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0024] It should also be understood that the terminology used in this embodiment description is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. As used in this embodiment description and the appended claims, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms. In the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application; the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; in the description of this application, "a plurality of" means two or more, unless otherwise expressly and specifically defined.

[0025] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] Please refer to Figures 1-4, the superjunction integration method includes,

[0027] Step 1: Construct substrate layer 100;

[0028] Step 2: Form an integrated superjunction structure 200 on the substrate.

[0029] The integrated superjunction structure 200 defines an epitaxial layer 201 and alternating P-pillars 202 and N-pillars 203 within the epitaxial layer 201. The integrated superjunction structure 200 has at least one isolation structure, which defines a P-beam 204. The P-beam 204 is located inside the epitaxial layer 201 on the side away from the substrate layer 100. The bottom of the P-beam 204 connects to the corresponding P-pillars 202 and N-pillars 203, and both ends extend to the two P-pillars 202 on both sides. The P-beam 204 and the two P-pillars 202 on both sides form an isolation region 205 at the top inside the epitaxial layer.

[0030] Step 3: Integrate the superjunction structure to form corresponding superjunction MOS devices and isolation devices.

[0031] In one exemplary embodiment, a method for forming an integrated superjunction structure on a substrate includes,

[0032] The integrated superjunction structure is formed by injection molding and / or by trench molding and epitaxial backfilling.

[0033] In one exemplary embodiment, the isolation device is a control device, which is a low-voltage and / or medium-voltage MOS device.

[0034] In an exemplary embodiment, the method for integrating a superjunction MOS device and an isolation device correspondingly formed on a superjunction structure includes,

[0035] The corresponding N-type and P-type impurities are injected to form the basic devices corresponding to the superjunction MOS device and the isolation device, and the device isolation is performed. The basic device includes a source, a drain and a gate.

[0036] In an exemplary embodiment, the method for integrating a superjunction MOS device and an isolation device correspondingly formed on a superjunction structure includes,

[0037] The integrated superjunction structure is divided into several regions, and corresponding basic devices are formed therefrom; the several regions include a terminal region, a superjunction MOS cell region, an NMOS region, an HVNMOS region, a PMOS region, an isolated HVNMOS region, an isolated HVPMOS region, and a cell region.

[0038] In one exemplary embodiment, the NMOS region and PMOS region correspond to the low-voltage region, and the operating voltage of the low-voltage region is below 10V; the HVNMOS region, the isolated HVNMOS region, and the isolated HVPMOS region correspond to the medium-voltage region, and the operating voltage of the medium-voltage region is 10V-100V; the superjunction MOS cell region corresponds to the high-voltage region, and the operating voltage of the high-voltage region is above 400V.

[0039] In an exemplary embodiment, the method for performing device isolation includes isolating various devices requiring isolation through PN junction isolation and field oxide isolation, and forming FOX field oxide, gate oxide, and gate polysilicon patterns.

[0040] In an exemplary embodiment, the method for integrating a superjunction MOS device and an isolation device on a superjunction structure further includes forming an ILD layer, a metal layer, and a passivation protection PA layer.

[0041] It should be noted that: the embodiments of this application construct an isolation region on the superjunction structure for integrating isolation devices. The isolation devices can be low-voltage or medium-voltage control devices, thereby realizing the integration of the superjunction MOS chip and the control chip; multiple power devices and related control devices on the superjunction structure are integrated onto a single chip.

[0042] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A superjunction integration method, characterized in that, The method includes: constructing a substrate layer; forming an integrated superjunction structure on the substrate layer, wherein the integrated superjunction structure defines an epitaxial layer and alternating P-pillars and N-pillars within the epitaxial layer; the integrated superjunction structure has at least one isolation structure; the isolation structure defines a P-beam located inside the epitaxial layer on the side away from the substrate layer; the bottom of the P-beam connects to the corresponding P-pillar and N-pillar, and both ends extend to the two side P-pillars; the P-beam and the two side P-pillars form an isolation region at the top within the epitaxial layer; and correspondingly forming a superjunction MOS device and an isolation device on the integrated superjunction structure.

2. The superjunction integration method according to claim 1, characterized in that, The method for forming an integrated superjunction structure on a substrate includes implantation mating epitaxial formation of the integrated superjunction structure and / or trench mating epitaxial backfill formation of the integrated superjunction structure.

3. The superjunction integration method according to claim 1, characterized in that, The isolation device is a control device, and the control device is a low-voltage and / or medium-voltage MOS device.

4. The superjunction integration method according to claim 1, characterized in that, The method for forming superjunction MOS devices and isolation devices on an integrated superjunction structure includes implanting corresponding N-type and P-type impurities, forming basic devices corresponding to the superjunction MOS devices and isolation devices, and performing device isolation. The basic devices include a source, a drain, and a gate.

5. The superjunction integration method according to claim 4, characterized in that, The method for forming superjunction MOS devices and isolation devices on an integrated superjunction structure includes dividing the integrated superjunction structure into several regions and forming corresponding basic devices; the several regions include a terminal region, a superjunction MOS cell region, an NMOS region, an HVNMOS region, a PMOS region, an isolation HVNMOS region, an isolation HVPMOS region, and a cell region.

6. The superjunction integration method according to claim 5, characterized in that, The NMOS and PMOS regions correspond to the low-voltage region, with an operating voltage below 10V; the HVNMOS, isolated HVNMOS, and isolated HVPMOS regions correspond to the medium-voltage region, with an operating voltage of 10V-100V; and the superjunction MOS cell region corresponds to the high-voltage region, with an operating voltage above 400V.

7. The superjunction integration method according to claim 4, characterized in that, The method for device isolation includes isolating various devices that require isolation through PN junction isolation and field oxide isolation, and forming FOX field oxide, gate oxide and gate polysilicon patterns.

8. The superjunction integration method according to claim 4, characterized in that, Methods for forming superjunction MOS devices and isolation devices on integrated superjunction structures also include forming ILD layers, metal layers, and passivation protection PA layers.

9. A superjunction integrated chip fabricated by the superjunction integration method according to any one of claims 1-8.

Images