Array substrate and driving method therefor, and display panel and display apparatus

Abstract

Provided in the present disclosure are an array substrate and a driving method therefor, and a display panel and a display apparatus. The array substrate comprises: a base substrate, which comprises a display area; a plurality of pixel electrodes, which are arranged in an array in the display area; a plurality of common electrodes, which comprise a plurality of hollowed-out structures located at some column gaps between the pixel electrodes; and a plurality of first gate lines, which extend at the column gaps where the plurality of hollowed-out structures are located, wherein the orthographic projections of the plurality of first gate lines on the base substrate overlap the orthographic projections of the plurality of hollowed-out structures on the base substrate.

Description

Array substrate, its driving method, display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410942106.7, filed on July 12, 2024, entitled "Array Substrate, Driving Method Thereof, Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, its driving method, a display panel, and a display device. Background Technology

[0004] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] The array substrate, its driving method, display panel, and display device disclosed herein are specifically described below:

[0006] On one hand, embodiments of this disclosure provide an array substrate, including:

[0007] A substrate, the substrate including a display area;

[0008] Multiple pixel electrodes are arranged in an array in the display area;

[0009] Multiple common electrodes, including multiple hollow structures located at the gaps between the pixel electrode columns;

[0010] Multiple first gate lines extend at the gaps between the columns containing the multiple hollow structures, and the orthographic projections of the multiple first gate lines on the substrate overlap with the orthographic projections of the multiple hollow structures on the substrate.

[0011] In some embodiments, the array substrate provided in this disclosure may further include multiple touch lines electrically connected to the multiple common electrodes. The extension direction of the touch lines is the same as the extension direction of the first gate lines. At the column gap between two adjacent pixel electrodes and at the row gap between two adjacent rows of pixel electrodes, the orthographic projections of the multiple touch lines on the substrate overlap with the orthographic projections of the multiple first gate lines on the substrate.

[0012] In some embodiments, in the array substrate provided in the present disclosure, at the column gap between two adjacent pixel electrodes, the orthographic projection of the touch line on the substrate covers the orthographic projection of the first gate line on the substrate, and the orthographic projection of the touch line on the substrate is located within the orthographic projection of the cutout structure on the substrate.

[0013] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transition electrodes, a first insulating layer, and a second insulating layer; wherein,

[0014] The plurality of transition electrodes are on the same layer as the plurality of pixel electrodes and are located on the side of the layer where the plurality of touch lines are located that is far away from the layer where the plurality of common electrodes are located;

[0015] The first insulating layer is located between the layer containing the plurality of touch lines and the layer containing the plurality of pixel electrodes;

[0016] The second insulating layer is located between the layer containing the multiple touch lines and the layer containing the multiple common electrodes;

[0017] The first insulating layer and the second insulating layer include a first via, the first via including a first sub-via and a second sub-via that are connected together, wherein the first sub-via penetrates the first insulating layer and overlaps with the touch line, and the second sub-via penetrates the first insulating layer and the second insulating layer and overlaps with the common electrode;

[0018] The adapter electrode is electrically connected to the touch line through the first sub-via, and the adapter electrode is electrically connected to the common electrode through the second sub-via.

[0019] In some embodiments, in the array substrate provided in the present disclosure, the touch line includes a main line located between two adjacent pixel electrodes and a first widened portion located between two adjacent rows of pixel electrodes;

[0020] The first widened portion is electrically connected to the adapter electrode at the first sub-via, and the first widened portion expands outward relative to the main line along the direction away from the second sub-via from the first sub-via.

[0021] In some embodiments, in the array substrate provided in the present disclosure, the touch line further includes a second widening portion, the second widening portion being located between two adjacent rows of pixel electrodes where the first widening portion is not provided, and the structure of the second widening portion being substantially the same as the structure of the first widening portion.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the layer containing the plurality of pixel electrodes is located between the layer containing the plurality of touch lines and the substrate, and the layer containing the plurality of common electrodes is located on the side of the layer containing the plurality of touch lines away from the substrate.

[0023] The array substrate further includes a second insulating layer located between the layer containing the plurality of touch lines and the layer containing the plurality of common electrodes. The second insulating layer includes a first via that overlaps with the touch lines and the common electrodes, and the touch lines are electrically connected to the common electrodes through the first via.

[0024] In some embodiments, the array substrate provided in the present disclosure further includes multiple data lines, which are alternately arranged with the first gate line at different column gaps of the pixel electrode;

[0025] At the column gaps of the pixel electrodes, the orthographic projection of the data line on the substrate lies within the orthographic projection of the common electrode on the substrate.

[0026] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of second gate lines, the second gate lines extending at the row gaps of the pixel electrodes, and the second gate lines including a third widening portion extending outward toward the column gaps of two adjacent pixel electrodes;

[0027] The first grid line includes a fourth widening portion that overlaps with the third widening portion;

[0028] The array substrate further includes a third insulating layer located between the layer containing the plurality of second gate lines and the layer containing the plurality of first gate lines. The third insulating layer includes a second via that overlaps with the third widening portion and the fourth widening portion. The third widening portion is electrically connected to the fourth widening portion through the second via.

[0029] In some embodiments, in the array substrate provided in the present disclosure, the second gate line further includes a fifth widening portion, the fifth widening portion and the third widening portion expanding outward to different column gaps, and the structure of the fifth widening portion is substantially the same as the structure of the third widening portion;

[0030] The first grid line also includes a sixth widening portion that overlaps with and is insulated from the fifth widening portion, and the structure of the sixth widening portion is substantially the same as that of the fourth widening portion.

[0031] In some embodiments, in the array substrate provided in the present disclosure, the same row gap of the pixel electrodes includes two second gate lines, one of which is electrically connected to the odd-numbered pixel electrode in the adjacent row, and the other of which is electrically connected to the even-numbered pixel electrode in the adjacent row.

[0032] In some embodiments, the array substrate provided in this disclosure further includes a non-display area located on at least one side of the display area;

[0033] The array substrate further includes a first control line, a first test line, multiple first transistors, a second control line, multiple second test lines, and multiple sets of second transistors located in the non-display area; wherein...

[0034] The gates of the plurality of first transistors are electrically connected to the first control line, the first terminals of the plurality of first transistors are electrically connected to the first test line, and the second terminals of different first transistors are electrically connected to different touch lines.

[0035] The multiple data lines are divided into multiple groups. The gates of all the second transistors are electrically connected to the second control line. The first terminals of different second transistors in a group are electrically connected to different second test lines. The second terminals of different second transistors in a group are electrically connected to different data lines in the group.

[0036] In some embodiments, in the array substrate provided in the present disclosure, the non-display area includes a first non-display area for bonding a driving circuit, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area;

[0037] The first control line is connected to the driving circuit from the second non-display area via two of the third non-display areas.

[0038] In some embodiments, in the array substrate provided in the present disclosure, the first control line is blank in the first non-display area, or the first control line surrounds the display area.

[0039] In some embodiments, in the array substrate provided in the present disclosure, the first detection line is located at least in the first non-display area and / or the second non-display area.

[0040] In some embodiments, in the array substrate provided in the present disclosure, the first detection line is connected from the second non-display area to the driving circuit via two third non-display areas.

[0041] In some embodiments, in the array substrate provided in the present disclosure, the first detection line is disposed in the blank area of ​​the first non-display area, or the first detection line surrounds the display area.

[0042] In some embodiments, the array substrate provided in this disclosure further includes a common electrode bus surrounding the display area and a common electrode lead located in the first non-display area, wherein the common electrode bus is electrically connected to the driving circuit through the common electrode lead;

[0043] The first detection line is located in the first non-display area and is electrically connected to the common electrode lead; and / or, the first detection line is located in the second non-display area and is electrically connected to the common electrode bus.

[0044] In some embodiments, in the array substrate provided in the present disclosure, the plurality of first transistors and the first detection line are simultaneously located in the first non-display area and / or the second non-display area.

[0045] On the other hand, embodiments of this disclosure provide a driving method for the above-mentioned array substrate, including:

[0046] During the display period, control all the touch lines to be connected to all the common electrodes;

[0047] During the touch control period, the different touch lines are controlled to operate independently, and the different common electrodes are controlled to operate independently.

[0048] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0049] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and the backlight module located on the light-incident side of the display panel. Attached Figure Description

[0050] Figure 1 is a schematic diagram of the structure of 2*6 sub-pixels in an array substrate provided in an embodiment of this disclosure;

[0051] Figure 2 is a schematic diagram of the cross-sectional structure along I-I' in Figure 1;

[0052] Figure 3 is a schematic diagram of the cross-sectional structure along II-II' in Figure 1;

[0053] Figure 4 is a schematic diagram of the structure of the layer where the second gate line is located in Figure 1;

[0054] Figure 5 is a schematic diagram of the active layer in Figure 1;

[0055] Figure 6 is a schematic diagram of the structure of the layer where the data line is located in Figure 1;

[0056] Figure 7 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 1;

[0057] Figure 8 is a schematic diagram of the structure of the layer where the touch line is located in Figure 1;

[0058] Figure 9 is a schematic diagram of the structure of the layer where the vias are located in Figure 1;

[0059] Figure 10 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 1;

[0060] Figure 11 is a schematic diagram of the structure of 2*6 sub-pixels in another array substrate provided in an embodiment of the present disclosure;

[0061] Figure 12 is a schematic diagram of the cross-sectional structure along III-III' in Figure 11;

[0062] Figure 13 is a schematic diagram of the cross-sectional structure along IV-IV' in Figure 11;

[0063] Figure 14 is a schematic diagram of the structure of the layer where the second gate line is located in Figure 11;

[0064] Figure 15 is a schematic diagram of the active layer in Figure 11;

[0065] Figure 16 is a schematic diagram of the structure of the layer where the data line is located in Figure 11;

[0066] Figure 17 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 11;

[0067] Figure 18 is a schematic diagram of the structure of the layer where the touch line is located in Figure 11;

[0068] Figure 19 is a schematic diagram of the structure of the layer where the vias are located in Figure 11;

[0069] Figure 20 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 11;

[0070] Figure 21 is an enlarged structural schematic diagram of region Z1 in Figure 1;

[0071] Figure 22 is a schematic diagram of the cross-sectional structure along line V-V' in Figure 21;

[0072] Figure 23 is an enlarged structural diagram of region Z2 in Figure 11;

[0073] Figure 24 is a schematic diagram of the cross-sectional structure along line VI-VI' in Figure 23;

[0074] Figure 25 is a schematic diagram of the cross-sectional structure along line VII-VII' in Figures 1 and 11;

[0075] Figure 26 is a schematic diagram of the structure of the region where the four common electrodes are located according to an embodiment of this disclosure;

[0076] Figure 27 is a schematic diagram of a structure for testing the data cable and touch cable separately according to an embodiment of this disclosure;

[0077] Figure 28 is a schematic diagram of another structure for testing the data cable and touch cable separately according to an embodiment of this disclosure;

[0078] Figure 29 is a structural schematic diagram of a touch line testing scheme provided in an embodiment of this disclosure;

[0079] Figure 30 is a schematic diagram of another structure of the touch line testing scheme provided in the embodiments of this disclosure;

[0080] Figure 31 is a schematic diagram of another structure of the touch line testing scheme provided in the embodiments of this disclosure;

[0081] Figure 32 is a schematic diagram of another structure of the touch line testing scheme provided in the embodiments of this disclosure;

[0082] Figure 33 is a schematic diagram of another structure of the touch line testing scheme provided in the embodiments of this disclosure;

[0083] Figure 34 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0084] Figure 35 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions, but are merely for illustrative purposes. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0086] Unless otherwise defined, the technical or scientific terms used herein should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0087] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0088] Due to the application scenarios, related automotive products require "elongated" displays with a relatively large aspect ratio (M:N). For "elongated" products, to enhance gate line driving, gate driver chips (gate ICs) or gate driver circuits (GOAs) can be set on both the left and right bezels to achieve simultaneous dual-sided driving. This results in relatively large left and right bezels.

[0089] To reduce the left and right bezels, the gate driver chip (IC) can be placed on the bottom bezel, and the horizontal (H-direction) gate lines can be connected to the gate driver chip (IC) via the vertical (V-direction) gate lines. However, since the vertical gate lines are covered with a common electrode made of indium tin oxide (IITO), during gate line scanning, both the H-direction and V-direction gate lines are turned on simultaneously. The overlap capacitance Cgc between the V-direction gate line and the common electrode pulls on the common voltage, affecting the pixel charging of the corresponding row, producing grayscale differences, and thus forming mura color blocks.

[0090] To at least improve the above-mentioned technical problems, this disclosure provides an array substrate. Figure 1 is a schematic diagram of the structure of 2*6 sub-pixels in an array substrate provided by this disclosure. Figure 2 is a schematic diagram of the cross-sectional structure along I-I' in Figure 1. Figure 3 is a schematic diagram of the cross-sectional structure along II-II' in Figure 1. Figures 4 to 10 are schematic diagrams of the structure of each film layer in Figure 1. Figure 11 is a schematic diagram of the structure of 2*6 sub-pixels in another array substrate provided by this disclosure. Figure 12 is a schematic diagram of the cross-sectional structure along III-III' in Figure 11. Figure 13 is a schematic diagram of the cross-sectional structure along IV-IV' in Figure 11. Figures 14 to 20 are schematic diagrams of the structure of each film layer in Figure 11.

[0091] In some embodiments, as shown in Figures 1, 3, 6, 7, 10, 11, 13, 16, 17, and 20, the array substrate provided in this disclosure embodiment may include:

[0092] The substrate 101 includes a display area AA, which includes a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, etc. In some embodiments, the substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, etc.

[0093] Multiple pixel electrodes 102 are arranged in an array in the display area AA. In some embodiments, the material of the pixel electrodes 102 may include transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO). Optionally, the pixel electrodes 102 may be slit electrodes as shown in FIG10 or block electrodes as shown in FIG17.

[0094] Multiple common electrodes 103 include multiple hollow structures 1031 located at the column gaps (e.g., the odd-numbered column gap or the even-numbered column gap) of the pixel electrodes 102; in some embodiments, the material of the common electrodes 103 may include transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO); optionally, the common electrodes 103 may be the block electrodes shown in FIG7 or the slit electrodes shown in FIG20.

[0095] Multiple first gate lines 104 extend at the column gaps of multiple cutout structures 1031, and the orthographic projections of the multiple first gate lines 104 on the substrate 101 overlap with the orthographic projections of the multiple cutout structures 1031 on the substrate 101. Optionally, at the column gaps between two pixel electrodes 102, the orthographic projections of the first gate lines 104 on the substrate 101 are located within the orthographic projections of the cutout structures 1031 on the substrate 101. In some embodiments, the first gate lines 104 may be located in the source / drain metal layer (SD). The material of the source / drain metal layer (SD) may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), and copper (Cu). The source / drain metal layer (SD) may be a single-layer structure or a stacked structure. For example, the source / drain metal layer (SD) may be a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0096] In the array substrate provided in the embodiments of this disclosure, the common electrode 103 of the first gate line 104 (equivalent to the V-direction gate line) is hollowed out, so that the overlap capacitance Cgc of the first gate line 104 and the common electrode 103 is small or even negligible, thereby effectively avoiding the pull of the overlap capacitance Cgc on the common voltage, thereby improving the mura defect.

[0097] Furthermore, since the data line 107 and the first gate line 104 are located in the odd-numbered column gaps and even-numbered column gaps of the pixel electrode 102, respectively, in related technologies, the hollow structure 1031 of the common electrode 103 exposes the data line 107 and the common electrode 103 covers the first gate line 104. In this disclosure, the hollow structure 1031 of the common electrode 103 exposes the first gate line 104 and the common electrode 103 covers the data line 107. In the actual process, it is only necessary to move the mask used to make the common electrode 103 along the row direction by the size of one pixel electrode 102 to change the hollow structure 1031 of the common electrode 103 from exposing the data line 107 to exposing the first gate line 104, and the common electrode 103 from covering the first gate line 104 to covering the data line 107. Therefore, it is not necessary to redevelop the mask of the common electrode 103, thus saving costs.

[0098] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 1, 3, 7 to 9, 11, 13, 18 to 20, may also include multiple touch lines 105, which are electrically connected to multiple common electrodes 103. This is equivalent to the common electrodes 103 of the present disclosure being reused as touch electrodes, avoiding the need for additional touch electrode layers and facilitating the design of thinner and lighter products.

[0099] In some embodiments, FIG21 is an enlarged structural schematic diagram of the Z1 region in FIG1, and FIG22 is a cross-sectional structural schematic diagram along the V-V' line in FIG21. As can be seen from FIG21 and FIG22, the array substrate provided in the embodiments of the present disclosure may further include: a plurality of transition electrodes 114, a first insulating layer 113 and a second insulating layer 106; wherein, the plurality of transition electrodes 114 may be on the same layer as the plurality of pixel electrodes 102 and located on the side of the layer where the plurality of touch lines 105 are located away from the layer where the plurality of common electrodes 103 are located. In other words, the present disclosure is applicable to ADS products where the pixel electrodes 102 are located on the top layer. Optionally, the first insulating layer 113 is located between the layer containing the multiple touch lines 105 and the layer containing the multiple pixel electrodes 102 (i.e., the layer containing the transition electrode 114); the second insulating layer 106 is located between the layer containing the multiple touch lines 105 and the layer containing the multiple common electrodes 103; the first insulating layer 113 and the second insulating layer 106 may include a first via V1, the first via V1 including a first sub-via V11 and a second sub-via V12 connected together, wherein the first sub-via V11 penetrates the first insulating layer 113 and overlaps with the touch lines 105, and the second sub-via V12 penetrates the first insulating layer 113 and the second insulating layer 106 and overlaps with the common electrode 103; the transition electrode 114 is electrically connected to the touch lines 105 through the first sub-via V11, and the transition electrode 114 is electrically connected to the common electrode 103 through the second sub-via V12, thus realizing the electrical connection between the touch lines 105 and the common electrode 103 through the transition electrode 114. Optionally, to save steps, the first sub-via V11 and the second sub-via V12 can be completed in one patterning process.

[0100] It should be noted that, in this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes. The specific pattern in the formed layer structure can be continuous or discontinuous; these specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0101] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1, FIG8 to 10, FIG21 and FIG22, the touch line 105 may include a main line 1051 located between two adjacent pixel electrodes 102 and a first widening portion 1052 located between two adjacent rows of pixel electrodes 102; wherein, the first widening portion 1052 is electrically connected to the adapter electrode 114 at the first sub-via V11, and the first widening portion 1052 expands outward relative to the main line 1051 along the direction away from the second sub-via V12 of the first sub-via V11, that is, the touch line 105 is widened on one side of the first sub-via V11 away from the second sub-via V12 to form the first widening portion 1052.

[0102] In some embodiments, as shown in FIG1, FIG8 to FIG10, in the array substrate provided in the embodiments of this disclosure, the touch line 105 may further include a second widening portion 1053. The second widening portion 1053 is located between two adjacent rows of pixel electrodes 102 where the first widening portion 1052 is not provided, and the structure of the second widening portion 1053 may be substantially the same as the structure of the first widening portion 1052. This arrangement can keep the pixel architecture consistent, which is beneficial to improving the display effect. Of course, in some embodiments, this disclosure may only provide the first widening portion 1052 that overlaps with the adapter electrode 114, without providing the second widening portion 1053.

[0103] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately the same" may be completely equivalent or may have some deviation (e.g., ±5% deviation). Therefore, as long as the relationship of "approximately the same" between related features meets the allowable error, it is within the protection scope of this disclosure.

[0104] In some embodiments, FIG23 is an enlarged structural schematic diagram of the Z2 region in FIG11, and FIG24 is a cross-sectional structural schematic diagram along line VI-VI' in FIG23. As can be seen from FIG23 and FIG24, the layer where the multiple pixel electrodes 102 are located can be located between the layer where the multiple touch lines 105 are located and the substrate 101, and the layer where the multiple common electrodes 103 are located can be located on the side of the layer where the multiple touch lines 105 are located away from the substrate 101. In other words, this disclosure is applicable to ADS products where the common electrodes 103 are located on the top layer. Optionally, a second insulating layer 106 can be provided between the layer where the multiple touch lines 105 are located and the layer where the multiple common electrodes 103 are located. The second insulating layer 106 includes a first via V1 that overlaps with the touch lines 105 and the common electrodes 103. The touch lines 105 are electrically connected to the common electrodes 103 through the first via V1. Referring to Figure 23, in order to facilitate the electrical connection between the touch line 105 and the common electrode 103, the touch line 105 and the common electrode 103 can be widened on both sides at the first via V1.

[0105] Referring to Figures 1, 3, 7 to 9, 11, 13, 18 to 24, in some embodiments, the extension direction of the touch line 105 is the same as the extension direction of the first gate line 104. At the column gap between two adjacent pixel electrodes 102 and the row gap between two adjacent rows of pixel electrodes 102, the orthographic projections of multiple touch lines 105 on the substrate 101 overlap with the orthographic projections of multiple first gate lines 104 on the substrate 101. Optionally, at the column gap between adjacent pixel electrodes 102, the orthographic projections of the touch lines 105 on the substrate 101 completely cover the orthographic projections of the first gate lines 104 on the substrate 101, and the orthographic projections of the touch lines 105 on the substrate 101 are located within the orthographic projection of the cutout structure 1031 on the substrate 101. At the row gap of the pixel electrode 102: the touch line 105 may partially cover the first gate line 104, as shown in FIG21; or, the touch line 105 may completely cover the first gate line 104, as shown in FIG23. In some embodiments, the touch line 105 may be located in the touch metal layer (TPM), and the material of the touch metal layer (TPM) may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), and copper (Cu). The touch metal layer (TPM) may be a single-layer structure or a multilayer structure, for example, the touch metal layer (TPM) may be a single-layer structure composed of a copper metal layer.

[0106] By setting a touch line 105 covered with a touch metal layer on the first gate line 104 instead of a common electrode 103, an overlapping capacitance Cgt exists between the first gate line 104 and the touch line 105. The overlapping capacitance Cgc between the first gate line 104 and the common electrode 103 can be ignored. Thus, during gate line scanning, the overlapping capacitance Cgt between the touch line 105 and the first gate line 104 causes fluctuations in the common signal. Since the metal resistance of the touch line 105 is small and the touch line 105 is directly connected to the driver chip (IC), the fluctuations caused by the overlapping capacitance Cgt on the common voltage signal on the touch line 105 can be dispersed more quickly, thereby effectively improving mura defects.

[0107] Furthermore, since the data line 107 and the first gate line 104 are located in the odd-numbered column gap and the even-numbered column gap of the pixel electrode 102, respectively, in related technologies, the touch line 105 covers the data line 107. In this disclosure, the touch line 105 covers the first gate line 104. In the actual process, it is only necessary to move the mask used to make the touch line 105 along the row direction by the size of one pixel electrode 102 to change the touch line 105 from covering the data line 107 to covering the first gate line 104. Therefore, there is no need to redevelop the mask for the touch line 105, thus saving costs.

[0108] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 1, 4, 6, 9, 11, 14, 16, 19, and 25, may further include multiple second gate lines 108. The second gate lines 108 extend at the row gaps of the pixel electrodes 102 and are electrically connected to the first gate lines 104. Optionally, the second gate lines 108 and the first gate lines 104 are electrically connected through a second via V2 penetrating the third insulating layer 109 between them. In some embodiments, two second gate lines 108 are included at the same row gap of the pixel electrodes 102. One second gate line 108 is electrically connected to the odd-numbered pixel electrode 102 in the adjacent row, and the other second gate line 108 is electrically connected to the even-numbered pixel electrode 102 in the adjacent row. This achieves a dual-gate pixel architecture, reducing the number of data lines 107, thereby reducing the number of source driver chips (Source ICs) and saving costs.

[0109] In some embodiments, in the array substrate provided in the present disclosure, FIG25 is a schematic cross-sectional view along line VII-VII' in FIG1 and FIG11. As shown in FIG1, 4, 6, 9, 11, 14, 16, 19 and 25, to enhance the electrical connection effect, the second gate line 108 includes a third widened portion 1081 that expands outward toward the column gap of two adjacent pixel electrodes 102; the first gate line 104 includes a fourth widened portion 1041 that overlaps with the third widened portion 1081; the second via V2 overlaps with the third widened portion 1081 and the fourth widened portion 1041, and the third widened portion 1081 is electrically connected to the fourth widened portion 1041 through the second via V2.

[0110] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1, 4, 6 and 9, the second gate line 108 may further include a fifth widening portion 1082, which expands outward from different column gaps with the third widening portion 1081, and the structure of the fifth widening portion 1082 is substantially the same as the structure of the third widening portion 1081; the first gate line 104 further includes a sixth widening portion 1042 that overlaps with and is insulated from the fifth widening portion 1082, and the structure of the sixth widening portion 1042 is substantially the same as the structure of the fourth widening portion 1041; this arrangement can keep the pixel architecture consistent, which is beneficial to improving the display effect. In some embodiments, in order to improve the pixel aperture ratio, the sixth widening portion 1042 may be located in the area where the fifth widening portion 1082 is located, and both the fifth widening portion 1082 and the sixth widening portion 1042 may overlap with the first widening portion 1052.

[0111] Figure 26 shows a schematic diagram of the structure of the region where the four common electrodes 103 (labeled as S_n, S_n-1, S_m, S_m-1 respectively) are located in this disclosure. The vertical wiring corresponding to G(N-1), G(N), G(N+1), G(M-1), G(M), and G(M+1) represents the first gate line 104, and the horizontal wiring represents the second gate line 108. The first gate line 104 and the second gate line 108 with the same label are electrically connected.

[0112] In the related technology, the data line 107 is covered by the touch line 105, and the first gate line 104 is covered by the common electrode 103. During gate line scanning, the first gate line 104 and the second gate line 108 with the same number are turned on at the same time. Because of the existence of the overlapping capacitance Cgc between the first gate line 104 and the common electrode 103, it pulls the common voltage signal on the common electrode 103, affecting the pixel charging of the corresponding row, producing grayscale differences, and thus forming mura color blocks.

[0113] The specific data simulation is shown in Table 1. In Table 1, H represents the horizontal direction, V represents the vertical direction, Sensor Total represents the total capacitance of a single common electrode 103, S2 to Gate represents the overlap capacitance Cgc of the common electrode 103 and the gate line (including the first gate line 104 and / or the second gate line 108), ΔV value represents the common voltage fluctuation value caused by the overlap capacitance Cgc, and grayscale difference represents the grayscale change value caused by the common voltage fluctuation.

[0114] As can be seen from Table 1 and Figure 26, when the G(N) gate line is turned on, the grayscale differences of the two common electrodes S_n and S_n-1, which overlap with the first gate line 104 marked by G(N), due to the overlap capacitance Cgc, are approximately 20.4 and 13.2, respectively; the grayscale differences of the two common electrodes S_m and S_m-1, which do not overlap with the first gate line 104 marked by G(N), due to the overlap capacitance Cgc, are approximately 7.2 and 0, respectively. This means that the grayscale difference between two adjacent columns (i.e., 20.4-7.2 and 13.2-0) is approximately 13, which shows obvious mura defects.

[0115] Table 1

[0116] In this disclosure, by using a touch line 105 to cover the first gate line 104 and a common electrode 103 to cover the data line 107, the capacitance between the first gate line 104 and the common electrode 103 is a lateral field capacitance rather than an overlapping capacitance Cgc. Specific data simulations are shown in Table 2. In Table 2, H represents the horizontal direction, V represents the vertical direction, Sensor Total represents the total capacitance of a single common electrode 103, S2 to Gate (H direction) represents the overlapping capacitance Cgc between the common electrode 103 and the second gate line 108, S2 to Gate (V direction) represents the lateral field capacitance between the common electrode 103 and the first gate line 104, ΔV value represents the common voltage fluctuation value caused by the overlapping capacitance Cgc and the lateral field capacitance, and grayscale difference represents the grayscale change value caused by the common voltage fluctuation.

[0117] Because the pixel charging occurs when the G(N) gate line is turned on, it only involves the two common electrodes S_n and S_m. The influence of the first gate line 104 marked by G(N) on the two common electrodes S_n-1 and S_m-1 can be ignored. Therefore, Table 2 only lists the relevant data for the two common electrodes S_n and S_m. Combining Table 2 and Figure 26, it can be seen that when the G(N) gate line is turned on, the grayscale difference of the S_n common electrode overlapping with the first gate line 104 marked by G(N) is approximately 14, and the grayscale difference of the S_m common electrode that does not overlap with the first gate line 104 marked by G(N) is approximately 7. This means that the grayscale difference between adjacent columns in this disclosure is approximately 14-7=7. Therefore, without considering the factor that the metal resistance of the touch line 105 is smaller than the ITO resistance of the common electrode 103, resulting in faster dissipation of the fluctuating signal, the grayscale difference caused only by the capacitance between the first gate line 104 and the common electrode 103 in the V direction is reduced from 13 in related technologies to 7, resulting in a very significant improvement.

[0118] Table 2

[0119] In some embodiments, as shown in Figures 1 to 6, 9 to 17, and 19, the array substrate may further include a transistor 110. The first electrode D of the transistor 110 is electrically connected to the pixel electrode 102, the second electrode S of the transistor 110 is integrally disposed with the data line 107, and the gate G of the transistor 110 is integrally disposed with the second gate line 108. Optionally, as shown in Figures 1 to 7, 11 to 16, and 20, in order to reduce the overlap capacitance between the common electrode 103 and the transistor 110, the common electrode 103 may be hollowed out at the transistor 110 to avoid the common electrode 103 and the transistor 110 from overlapping and forming overlap capacitance as much as possible.

[0120] Optionally, in the embodiments shown in Figures 1 to 10, 21 and 22, the layers from bottom to top are: substrate 101, the layer containing the second gate line 108, the layer containing the active layer A of the transistor 110, the third insulating layer 109, the layer containing the data line 107, the fourth insulating layer 111, the fifth insulating layer 112, the layer containing the common electrode 103, the second insulating layer 106, the layer containing the touch line 105, the first insulating layer 113, and the layer containing the pixel electrode 102. In this case, the first electrode D of the transistor 110 can be electrically connected to the pixel electrode 102 through a third via V3 that penetrates the first insulating layer 113, the second insulating layer 106, the fifth insulating layer 112 and the fourth insulating layer 111. In some embodiments, the second insulating layer 106, the fourth insulating layer 111 and the first insulating layer 113 can share the same mask for etching the first insulating layer 113. In this way, where the first insulating layer 113 is removed from the periphery, the fourth insulating layer 111 remains, thereby improving the corrosion resistance of the surrounding metal.

[0121] Optionally, in the embodiments shown in Figures 11 to 20, 23 and 24, from bottom to top, the layers are: substrate 101, layer containing the second gate line 108, layer containing the active layer A of transistor 110, third insulating layer 109, layer containing the data line 107, fourth insulating layer 111, fifth insulating layer 112, layer containing the pixel electrode 102, second insulating layer 106, layer containing the touch line 105, fifth insulating layer 112, and layer containing the common electrode 103. In this case, the first electrode D of transistor 110 can be electrically connected to pixel electrode 102 through a third via V3 that penetrates the fifth insulating layer 112 and the fourth insulating layer 111. In some embodiments, the fourth insulating layer 111 and the fifth insulating layer 112 can be etched using a mask of the fifth insulating layer 112. The pixel electrode 102 is directly electrically connected through a third via V3 penetrating the fourth insulating layer 111 and the fifth insulating layer 112, avoiding the need for a transfer electrode in the layer containing the common electrode 103, and a transfer hole connecting the pixel electrode 102 and the first electrode D of the transistor 110 respectively through the transfer electrode, which is beneficial for improving the aperture ratio. In addition, this disclosure may include dummy pixels, in which the pixel electrode 102 is electrically connected through a via penetrating the second insulating layer 106 and the first insulating layer 113. Based on this, to reduce the number of masking operations, the second insulating layer 106 and the first insulating layer 113 can be etched using a mask of the first insulating layer 113.

[0122] In some embodiments, the materials of the second insulating layer 106, the third insulating layer 109, the fourth insulating layer 111, and the first insulating layer 113 of this disclosure can be inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride; the material of the fifth insulating layer 112 can be organic insulating materials such as polyacrylic acid resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, and phenolic epoxy acrylic resin, and is not limited herein. The material of the active layer A of the transistor 110 can be semiconductor materials such as amorphous silicon, polycrystalline silicon, and indium gallium zinc oxide.

[0123] In some embodiments, as shown in FIG27 and FIG28, the array substrate 101 further includes a non-display area BB located on at least one side of the display area AA in the array substrate provided in the present disclosure embodiments; the array substrate may further include a first control line SW_Tx, a first test line Tcom, a plurality of first transistors T1, a second control line SW_D, a plurality of second test lines D1 to D12, and a plurality of sets of second transistors T2 located in the non-display area BB (FIG. 21 shows two sets of second transistors T2, and FIG. 22 shows one set of second transistors T2); wherein, the gates of the plurality of first transistors T1 are electrically connected to the first control line SW_Tx, and the plurality of first transistors T1 are electrically connected to the first control line SW_Tx. The first electrode of transistor T1 is electrically connected to the first test line Tcom, and the second electrodes of different first transistors T1 are electrically connected to different touch lines 105 (i.e., Tx_1, Tx_2, ..., Tx_m-1, Tx_m). Multiple data lines 107 are divided into multiple groups. The gates of all second transistors T2 are electrically connected to the second control line SW_D. The first electrodes of different second transistors T2 in a group are electrically connected to different second test lines D1 to D12. The second electrodes of different second transistors T2 in a group are electrically connected to different data lines 107 in the group (i.e., DL_1 to DL_6, or DL_n-5 to DL_n, or DL_1 to DL_12). It should be noted that this disclosure uses 6 data lines as a group (6D test) and 12 data lines as a group (12D test) as examples. In specific implementations, other numbers of data lines can also be used as a group (e.g., 2D test, 3D test, 9D test, etc.).

[0124] In this disclosure, the control (SW) signals for the touch line 105 and the data line 107 are independently separated, divided into a first control line SW_Tx and a second control line SW_D. During testing, both the first control line SW_Tx and the second control line SW_D are set high, and all first transistors T1 and second transistors T2 are turned on for in-plane (i.e., within the display area AA) detection. During normal display, the second control line SW_D is set low, the first control line SW_Tx is set high, the data lines 107 are independent of each other, and the touch line 105 is connected as a whole within the plane. Thus, when a row of second gate lines 108 is scanned, the pull of the common voltage by the first gate line 104 electrically connected to that second gate line 108 acts on the common electrode 103 throughout the entire plane, rather than being limited to the single common electrode 103 electrically connected to the touch line 105 above that first gate line 104, thereby reducing the fluctuation of the common voltage and improving mura defects. During touch operation, both the first control line SW_Tx and the second control line SW_D are set low, and all first transistors T1 and second transistors T2 are turned off to enable touch functionality.

[0125] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 29 to 33, the non-display area BB includes a first non-display area BB1 for bonding a driving circuit (IC or FPC), a second non-display area BB2 opposite to the first non-display area BB1, and two third non-display areas BB3 connecting the first non-display area BB1 and the second non-display area BB2; the first control line SW_Tx can be connected from the second non-display area BB2 through the two third non-display areas BB3 to the driving circuit (IC or FPC), and the driving circuit (IC or FPC) directly supplies power to the first control line SW_Tx. Optionally, as shown in Figures 29 and 32, the first control line SW_Tx can be left blank in the first non-display area BB1 (i.e., it does not exist), or, as shown in Figures 30, 31, and 33, the first control line SW_Tx can surround the display area AA.

[0126] Referring again to Figures 29 to 33, in this disclosure, the first detection line Tcom is located at least in the first non-display area BB1 and / or the second non-display area BB2. For example, in Figures 29 and 30, the first detection line Tcom is connected from the second non-display area BB2 through two third non-display areas BB3 to the driving circuit (IC or FPC), and the driving circuit (e.g., IC or FPC) directly supplies power to the first detection line Tcom. In some embodiments, as shown in Figures 29 and 30, the first detection line Tcom may or may not exist in the first non-display area BB1 (i.e., a blank setting), wherein when the first detection line Tcom exists in the first non-display area BB1, the first detection line Tcom surrounds the display area AA.

[0127] In some embodiments, as shown in Figures 31 to 33, the array substrate provided in this disclosure further includes a common electrode bus CB surrounding the display area AA and a common electrode lead com located in the first non-display area BB1. The common electrode bus CB is electrically connected to the driving circuit (IC or FPC) through the common electrode lead com. The first detection line Tcom is located in the first non-display area BB1 and is electrically connected to the common electrode lead com. And / or, the first detection line Tcom is located in the second non-display area BB2 and is electrically connected to the common electrode bus CB. In this way, the driving circuit (IC or FPC) can simultaneously power the common electrode bus CB and the first detection line Tcom through the common electrode lead com, saving the output pins of the driving circuit (IC or FPC).

[0128] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 29 to 33, a plurality of first transistors T1 can be located simultaneously in the first non-display area BB1 and / or the second non-display area BB2 along with the first detection line Tcom. In the embodiments shown in Figures 31 and 33, the first transistors T1 are simultaneously disposed in the first non-display area BB1 and the second non-display area BB2. During normal display, the first control line SW_Tx is high, and the first transistors T1 are turned on to connect the plurality of in-plane common electrodes 103 into a whole. Compared with the scheme where the first transistors T1 are only placed in the first non-display area BB1 or the second non-display area BB2, the common voltage signal is more uniform.

[0129] In some embodiments, in the array substrate provided in the present disclosure, the transistors can be P-type transistors or N-type transistors. The first terminal of the transistor can be the source and the second terminal can be the drain, or the first terminal of the transistor can be the drain and the second terminal can be the source; no limitation is made here. Additionally, the array substrate of the present disclosure may also include an alignment layer (PI) located on the top layer of the array substrate. Other essential components of the array substrate are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on the present disclosure.

[0130] Based on the same inventive concept, this disclosure also provides a driving method for the above-mentioned array substrate, which may include the following steps:

[0131] During the display period, control all touch lines to be connected to all common electrodes; optionally, by turning on all the first transistors, all touch lines are connected to all common electrodes to reduce fluctuations in the common voltage and improve mura defects.

[0132] During the touch period, different touch lines are controlled independently, and different common electrodes are also controlled independently. Optionally, by turning off all the first transistors, different touch lines are made independent, and correspondingly, the common electrodes electrically connected to different touch lines are also made independent, thereby realizing the touch function.

[0133] Based on the same inventive concept, this disclosure provides a display panel. Figure 34 is a schematic diagram of the structure of the display panel provided in this disclosure. As shown in Figure 34, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle of solving the problem by this display panel is similar to the principle of solving the problem by the array substrate described above, the implementation of this display panel can refer to the embodiment of the array substrate described above, and repeated details will not be described again.

[0134] In some embodiments, as shown in FIG34, the display panel provided in this disclosure may further include a liquid crystal layer 003 disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0135] Based on the same inventive concept, this disclosure provides a display device. Figure 35 is a schematic diagram of the structure of the display device provided in this disclosure. As shown in Figure 35, the display device of this disclosure includes the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0136] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0137] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0138] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0139] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area; Multiple pixel electrodes are arranged in an array in the display area; Multiple common electrodes, including multiple hollow structures located at the gaps between the pixel electrode columns; Multiple first gate lines extend at the gaps between the columns containing the multiple hollow structures, and the orthographic projections of the multiple first gate lines on the substrate overlap with the orthographic projections of the multiple hollow structures on the substrate.

2. The array substrate as claimed in claim 1, wherein, It also includes multiple touch lines electrically connected to the multiple common electrodes. The extension direction of the touch lines is the same as the extension direction of the first gate line. At the column gap between two adjacent pixel electrodes and at the row gap between two adjacent rows of pixel electrodes, the orthographic projection of the multiple touch lines on the substrate overlaps with the orthographic projection of the multiple first gate lines on the substrate.

3. The array substrate as described in claim 2, wherein, At the column gap between two adjacent pixel electrodes, the orthographic projection of the touch line on the substrate covers the orthographic projection of the first gate line on the substrate, and the orthographic projection of the touch line on the substrate is located within the orthographic projection of the cutout structure on the substrate.

4. The array substrate as described in claim 2 or 3, wherein, It also includes multiple adapter electrodes, a first insulating layer, and a second insulating layer; wherein, The plurality of transition electrodes are on the same layer as the plurality of pixel electrodes and are located on the side of the layer where the plurality of touch lines are located that is far away from the layer where the plurality of common electrodes are located; The first insulating layer is located between the layer containing the plurality of touch lines and the layer containing the plurality of pixel electrodes; The second insulating layer is located between the layer containing the multiple touch lines and the layer containing the multiple common electrodes; The first insulating layer and the second insulating layer include a first via, the first via including a first sub-via and a second sub-via that are connected together, wherein the first sub-via penetrates the first insulating layer and overlaps with the touch line, and the second sub-via penetrates the first insulating layer and the second insulating layer and overlaps with the common electrode; The adapter electrode is electrically connected to the touch line through the first sub-via, and the adapter electrode is electrically connected to the common electrode through the second sub-via.

5. The array substrate as claimed in claim 4, wherein, The touch line includes a main line located between two adjacent pixel electrodes and a first widened portion located between two adjacent rows of pixel electrodes; The first widened portion is electrically connected to the adapter electrode at the first sub-via, and the first widened portion expands outward relative to the main line along the direction away from the second sub-via from the first sub-via.

6. The array substrate as claimed in claim 5, wherein, The touch line also includes a second widening portion, which is located between two adjacent rows of pixel electrodes where the first widening portion is not provided, and the structure of the second widening portion is substantially the same as that of the first widening portion.

7. The array substrate as claimed in claim 2 or 3, wherein, The layer containing the plurality of pixel electrodes is located between the layer containing the plurality of touch lines and the substrate, and the layer containing the plurality of common electrodes is located on the side of the layer containing the plurality of touch lines away from the substrate. The array substrate further includes a second insulating layer located between the layer containing the plurality of touch lines and the layer containing the plurality of common electrodes. The second insulating layer includes a first via that overlaps with the touch lines and the common electrodes, and the touch lines are electrically connected to the common electrodes through the first via.

8. The array substrate according to any one of claims 1 to 7, wherein, It also includes multiple data lines, which are alternately arranged with the first gate line at different column gaps of the pixel electrode; At the column gaps of the pixel electrodes, the orthographic projection of the data line on the substrate lies within the orthographic projection of the common electrode on the substrate.

9. The array substrate according to any one of claims 1 to 8, wherein, It also includes multiple second gate lines that extend at the row gaps of the pixel electrodes, and the second gate lines include a third widening portion that extends outward toward the column gaps of two adjacent pixel electrodes; The first grid line includes a fourth widening portion that overlaps with the third widening portion; The array substrate further includes a third insulating layer located between the layer containing the plurality of second gate lines and the layer containing the plurality of first gate lines. The third insulating layer includes a second via that overlaps with the third widening portion and the fourth widening portion. The third widening portion is electrically connected to the fourth widening portion through the second via.

10. The array substrate as claimed in claim 9, wherein, The second gate line also includes a fifth widening portion, which expands outward from different column gaps as the third widening portion, and the structure of the fifth widening portion is substantially the same as that of the third widening portion; The first grid line also includes a sixth widening portion that overlaps with and is insulated from the fifth widening portion, and the structure of the sixth widening portion is substantially the same as that of the fourth widening portion.

11. The array substrate as claimed in claim 9 or 10, wherein, The pixel electrodes include two second gate lines at the same row gap, one of which is electrically connected to the odd-numbered pixel electrode in the adjacent row, and the other of which is electrically connected to the even-numbered pixel electrode in the adjacent row.

12. The array substrate according to any one of claims 1 to 11, wherein, The substrate further includes a non-display area located on at least one side of the display area; The array substrate further includes a first control line, a first test line, multiple first transistors, a second control line, multiple second test lines, and multiple sets of second transistors located in the non-display area; wherein... The gates of the plurality of first transistors are electrically connected to the first control line, the first terminals of the plurality of first transistors are electrically connected to the first test line, and the second terminals of different first transistors are electrically connected to different touch lines. The multiple data lines are divided into multiple groups. The gates of all the second transistors are electrically connected to the second control line. The first terminals of different second transistors in a group are electrically connected to different second test lines. The second terminals of different second transistors in a group are electrically connected to different data lines in the group.

13. The array substrate as claimed in claim 12, wherein, The non-display area includes a first non-display area for bonding the driving circuit, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; The first control line is connected to the driving circuit from the second non-display area via two of the third non-display areas.

14. The array substrate as claimed in claim 13, wherein, The first control line is set in the blank space of the first non-display area, or the first control line surrounds the display area.

15. The array substrate according to any one of claims 12 to 14, wherein, The first detection line is located at least in the first non-display area and / or the second non-display area.

16. The array substrate as claimed in claim 15, wherein, The first detection line is connected to the driving circuit from the second non-display area via two of the third non-display areas.

17. The array substrate as claimed in claim 16, wherein, The first detection line is set in the blank space of the first non-display area, or the first detection line surrounds the display area.

18. The array substrate as claimed in claim 15, wherein, It also includes a common electrode bus surrounding the display area and a common electrode lead located in the first non-display area, the common electrode bus being electrically connected to the driving circuit through the common electrode lead; The first detection line is located in the first non-display area and is electrically connected to the common electrode lead; and / or, the first detection line is located in the second non-display area and is electrically connected to the common electrode bus.

19. The array substrate according to any one of claims 12 to 18, wherein, The plurality of first transistors and the first detection line are simultaneously located in the first non-display area and / or the second non-display area.

20. A driving method for an array substrate as described in any one of claims 1 to 19, wherein, include: During the display period, control all the touch lines to be connected to all the common electrodes; During the touch control period, the different touch lines are controlled to operate independently, and the different common electrodes are controlled to operate independently.

21. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 19.

22. A display device, wherein, It includes the display panel as described in claim 21, and the backlight module located on the light-incident side of the display panel.

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