Display device, manufacturing method therefor and electronic device

Abstract

A display device and a manufacturing method therefor are provided. The display device according to one embodiment comprises: a substrate; a pixel electrode and a common electrode disposed to be spaced apart from each other on the substrate; and a light-emitting element which is disposed on the pixel electrode and the common electrode and which includes a first contact electrode and a second contact electrode, wherein the light-emitting element can include a first element rod, which is formed into a positive taper and includes a first semiconductor layer doped with a first conductive dopant and an active layer, and a second element rod, which is disposed on the first element rod, includes a second semiconductor layer doped with a second conductive dopant and has an incline angle greater than that of the first element rod.

Description

Display device, method for manufacturing the same and electronic device

[0001] The present invention relates to a display device, a method for manufacturing the same, and an electronic device.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting displays (LEDs).

[0003] The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, and an ultra-small light-emitting display device including a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the ultra-small light-emitting diode element is made of an inorganic material, it has the advantage of having a longer lifespan due to fewer deterioration issues compared to an organic light-emitting diode element.

[0004] The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that can increase light extraction efficiency and reduce power consumption.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate, a pixel electrode and a common electrode spaced apart from each other on the substrate, a light-emitting element disposed on the pixel electrode and the common electrode and including a first contact electrode and a second contact electrode, wherein the light-emitting element is formed in a regular tapered shape and includes a first semiconductor layer doped with a first conductive dopant and an active layer, and includes a first element rod and a second semiconductor layer disposed on the first element rod and doped with a second conductive dopant, and may include a second element rod having a greater inclination angle than the first element rod.

[0007] The first inclination angle formed by the inner surface of the first element load and one surface of the first semiconductor layer may be in the range of 20° to 65°, and the second inclination angle formed by the outer surface of the second element load and the outer surface of the first element load may be in the range of 110° to 155°.

[0008] The first element load may have a width that becomes narrower as it goes upward on the substrate, and the second element load may have the same width at the upper and lower portions.

[0009] The above display device may further include an undoped semiconductor on the second semiconductor layer.

[0010] The above undoped semiconductor may have a light extraction pattern.

[0011] The display device may further include an organic layer disposed on the lower surface of the light-emitting element on the pixel electrode and the common electrode, a first connection electrode connecting the pixel electrode and the first contact electrode, and a second connection electrode connecting the common electrode and the second contact electrode.

[0012] The display device may further include a connection electrode disposed between the first contact electrode and the pixel electrode, and between the second contact electrode and the common electrode.

[0013] The light emitting element further includes a conductive layer disposed on a lower surface of the first semiconductor layer, and a protective layer surrounding the conductive layer and the first semiconductor layer, the active layer, and the second semiconductor layer, wherein the first contact electrode is disposed on the protective film and is connected to the conductive layer that is exposed and not covered by the protective film, and the second contact electrode is disposed on the protective film and can be disposed in a hole penetrating the conductive layer, the first semiconductor layer, and the active layer.

[0014] The display device may further include a partition wall arranged to surround the light-emitting element and a reflective layer arranged on a side of the partition wall and a bottom of a space formed by the partition wall, and which does not come into contact with the pixel electrode and the common electrode.

[0015] The display device may further include a wavelength conversion layer disposed in a space formed by the partition wall.

[0016] The display device may include a substrate, a pixel electrode disposed on the substrate, a light-emitting element disposed on the pixel electrode and including a contact electrode, and a common electrode disposed on the light-emitting element, wherein the light-emitting element may include a first element rod formed in a regular tapered shape and including a first semiconductor layer doped with a first conductive dopant and an active layer, and a second semiconductor layer disposed on the first element rod and doped with a second conductive dopant, the second element rod having a greater inclination angle than the first element rod.

[0017] The first inclination angle formed by the inner surface of the first element load and one surface of the first semiconductor layer may be in the range of 20° to 65°, and the second inclination angle formed by the outer surface of the second element load and the outer surface of the first element load may be in the range of 110° to 155°.

[0018] The first element load may have a width that becomes narrower as it goes upward on the substrate, and the second element load may have the same width at the upper and lower portions.

[0019] The display device may further include an organic layer disposed between the pixel electrode and the light-emitting element and a connection electrode (BE) connecting the pixel electrode and the contact electrode.

[0020] The display device may further include a connection electrode disposed between the contact electrode and the pixel electrode.

[0021] The light emitting element (LE) further includes a conductive layer disposed on a lower surface of the first semiconductor layer and a protective film disposed on side surfaces of the conductive layer and side surfaces of the first semiconductor layer and the active layer, and the contact electrode is disposed on the protective film and can be connected to the conductive layer that is exposed and not covered by the protective film.

[0022] The display device may further include a partition wall arranged to surround the light-emitting element and a wavelength conversion layer arranged in a space formed by the partition wall.

[0023] The display device display method includes a step of forming a light-emitting element, and a step of transferring the light-emitting element onto a first substrate, wherein the step of forming the light-emitting element includes a step of forming an undoped semiconductor, a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer on a second substrate, a step of forming a double mask on the first semiconductor layer and performing a first etching, a step of performing a second etching according to an etching method different from the first etching, but continuing the second etching until the inner surface of the first semiconductor layer and the active layer have a first inclination angle, and the outer surface of the second semiconductor layer and the outer surface of the first semiconductor layer and the active layer have a second inclination angle, a step of forming a groove penetrating the conductive layer, the first semiconductor layer, and the active layer to expose the second semiconductor layer, a step of forming a protective layer surrounding the conductive layer, the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer, and a first contact electrode contacting the conductive layer on the protective layer, and a second contact electrode exposed by the groove. It may include a step of forming a second contact electrode that contacts the semiconductor layer.

[0024] The first inclination angle may be in a range of 20° to 65°, and the second inclination angle may be in a range of 110° to 155°.

[0025] The above first etching may be dry etching, and the above second etching may be wet etching.

[0026] An electronic device including a display device for displaying an image, the display device including a substrate, pixel electrodes and a common electrode spaced apart from each other on the substrate, a light-emitting element disposed on the pixel electrode and the common electrode and including a first contact electrode and a second contact electrode, the light-emitting element including a first semiconductor layer doped with a first conductive dopant and an active layer formed in a regular tapered shape, and including a first element rod and a second semiconductor layer disposed on the first element rod and doped with a second conductive dopant, the second element rod having a greater inclination angle than the first element rod.

[0027] Specific details of other embodiments are included in the detailed description and drawings.

[0028] According to the display device and its manufacturing method according to the embodiments, the amount of light emitted toward the lower side of the light-emitting element can be reduced, thereby improving reflectivity and light extraction efficiency. Accordingly, panel brightness can be increased and power consumption for the same brightness can be reduced.

[0029] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0030] Figure 1 is a perspective view showing a display device according to one embodiment.

[0031] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0032] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0033] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0034] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0035] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of Fig. 5.

[0036] Figure 7 is a cross-sectional view showing in detail an example of area A1 of Figure 6.

[0037] Fig. 8 is a drawing explaining the direction of propagation of light emitted from the light-emitting element of Fig. 7.

[0038] Figure 9 is a cross-sectional view showing another example of area A1 of Figure 6 in detail.

[0039] Fig. 10 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of Fig. 5.

[0040] Fig. 11 is a cross-sectional view showing in detail an example of area A of Fig. 10.

[0041] FIG. 12 is a layout diagram showing pixels of a display area according to one embodiment.

[0042] Fig. 13 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 12.

[0043] Figure 14 is a cross-sectional view showing in detail an example of area A2 of Figure 13.

[0044] Figure 15 is a cross-sectional view showing another example of area A2 of Figure 13 in detail.

[0045] Fig. 16 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0046] FIGS. 17 to 35 are exemplary drawings for explaining a method of manufacturing a display device according to one embodiment.

[0047] FIG. 36 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0048] FIGS. 37 and 38 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0049] FIG. 39 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment.

[0050] FIG. 40 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0051] FIG. 41 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0052] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0053] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0054] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0055] Specific embodiments are described below with reference to the attached drawings.

[0056] Figure 1 is a perspective view showing a display device according to one embodiment.

[0057] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc.

[0058] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, an ultra-small light-emitting diode is described as a light-emitting element below.

[0059] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0060] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel (100) may be formed to be flexible so as to be bent, curved, folded, or rolled.

[0061] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0062] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color, but the embodiments of the present specification are not limited thereto.

[0063] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit unit (250) may be disposed in the sub-area (SBA).

[0064] The display driving circuit unit (250) can generate signals and voltages for driving the display panel (100). The display driving circuit unit (250) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit unit (250) can be attached to the circuit board (300) using a COF (chip on film) method.

[0065] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit unit (250). The display panel (100) and the display driving circuit unit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0066] The power supply circuit (500) can generate multiple panel driving voltages according to an external power voltage. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF method.

[0067] Fig. 2 is a layout diagram showing a display device according to one embodiment. Fig. 2 illustrates that the sub-area (SBA) is unfolded rather than bent.

[0068] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0069] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0070] The display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of sub-pixels (SPX). A pixel (PX) may be defined as a sub-pixel group that is the smallest unit capable of expressing white gradation.

[0071] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0072] The first scan driver (SDC1) and the second scan driver (SDC2) may be positioned in the non-display area (NDA). The first scan driver (SDC1) may be positioned on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be positioned on the other side (e.g., the right side) of the display panel, but the embodiments of the present specification are not limited thereto.

[0073] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) can be electrically connected to the display driving circuit unit (250) via scan fan out lines. Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) can receive a scan control signal from the display driving circuit unit (250), generate scan signals according to the scan control signal, and output the scan signals to the scan lines.

[0074] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0075] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0076] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0077] The pad area (PA) is an area where pads (PD) and a display driving circuit (250) are arranged. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0078] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0079] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0080] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0081] A plurality of pixels (PX) can be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) can extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) can extend in the second direction (DR2) and be arranged in the first direction (DR1). The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of initialization scan lines (GIL), and a plurality of bias scan lines (GBL).

[0082] Each of the plurality of sub-pixels (SPX) may be connected to one of the plurality of write scan lines (GWLs), one of the plurality of initialization scan lines (GILs), one of the plurality of bias scan lines (GBLs), one of the plurality of emission control lines (ELs), and one of the plurality of data lines (DLs). Each of the plurality of sub-pixels (SPX) may be supplied with a data voltage of the data line (DL) according to a write scan signal of the write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0083] The non-display area (NDA) includes a first scan driver (SDC1), a second scan driver (SDC2), and a display driver circuit (250).

[0084] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a bias scan signal output unit (613), and an emission control signal output unit (614). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the bias scan signal output unit (613), and the emission control signal output unit (614) may receive a scan timing control signal (SCS) from a timing control circuit (251).

[0085] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (251) and sequentially output them to write scan lines (GWL).

[0086] The initialization scan signal output unit (612) can generate initialization scan signals according to a scan timing control signal (SCS) and sequentially output them to initialization scan lines (GIL).

[0087] The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL).

[0088] The light emission control signal output unit (614) can generate light emission control signals according to a scan timing control signal (SCS) and sequentially output them to light emission control lines (EL).

[0089] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0090] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the converted data voltages to the data lines (DL). In this case, the sub-pixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and the data voltages can be supplied to the selected sub-pixels (SPX).

[0091] The timing control circuit (251) can receive digital video data and timing signals from the outside. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and a data timing control signal (DCS) to the data driving circuit (252).

[0092] The power supply circuit (500) can generate a plurality of panel driving voltages according to a power voltage supplied from an external source. For example, the power supply circuit (500) can generate a first power voltage (VDD), a second power voltage (VSS), a third power voltage (VINT), and a fourth power voltage (VAINT) and supply them to the display panel (100).

[0093] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0094] Referring to FIG. 4, a sub-pixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), an emission line (EL), and a data line (DL). For example, the sub-pixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), an emission line (EL), and a data line (DL).

[0095] A sub-pixel (SPX) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor (C1), and a light-emitting element (LE). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0096] A driving transistor (DT) includes a gate electrode, a conductive layer, and a second electrode. The driving transistor (DT) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the conductive layer and the second electrode according to a data voltage applied to the gate electrode.

[0097] The light emitting element (LE) may be a micro light emitting diode.

[0098] The light emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light emitting element (LE) may be connected to the conductive layer of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to a second power line (VSL) to which a second power voltage is applied.

[0099] A capacitor (C1) is formed between the second electrode of the driving transistor (DT) and a first power line (VDL) to which a first power voltage is applied. The first power voltage may be a voltage of a higher level than the second power voltage. One electrode of the capacitor (C1) may be connected to the second electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0100] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0101] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, and ST6) are formed of p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively. One electrode of the third transistor (ST3) and one electrode of the fourth transistor (ST4) may be connected to an initialization voltage line (VIL).

[0102] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. The active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductors.

[0103] In this case, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) can be turned on when a scan signal of a gate high voltage is applied, and the third transistor (ST3) can be turned on when an initialization scan signal of a gate high voltage is applied. In contrast, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and therefore can be turned on when a scan signal of a gate low voltage and a light emission signal are applied.

[0104] Alternatively, the fourth transistor (ST4) may be formed as an n-type MOSFET, and thus, the active layer of each of the fourth transistors (ST4) may be formed of an oxide semiconductor. When the fourth transistor (ST4) is formed as an n-type MOSFET, it may be turned on when a scan signal of a gate high voltage is applied.

[0105] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed of an oxide semiconductor.

[0106] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0107] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three sub-pixels (SPX1, SPX2, SPX3), but the embodiment of the present specification is not limited thereto and may include four sub-pixels. When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), it may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3).

[0108] A plurality of pixels (PX) can be arranged in a matrix form. In each of the plurality of pixels (PX), a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0109] When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), the first sub-pixel (SPX1) can emit light of a first color, the second sub-pixel (SPX2) can emit light of a second color, and the third sub-pixel (SPX3) can emit light of a third color. Here, the light of the first color may be light in a blue wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a red wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of about 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of about 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of about 600 nm to 750 nm.

[0110] Alternatively, when each of the plurality of pixels (PX) includes four sub-pixels, the first sub-pixel may emit light of a first color, the second and fourth sub-pixels may emit light of a second color, and the third sub-pixel may emit light of a third color. Alternatively, the first sub-pixel may emit light of a first color, the second sub-pixel may emit light of a second color, the third sub-pixel may emit light of a third color, and the fourth sub-pixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0111] The first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). The second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). The third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LEs), and a third light conversion layer (QDL3).

[0112] In each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3), pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3) may be arranged in the second direction (DR2). Each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may have a rectangular planar shape, but the embodiment of the present specification is not limited thereto. The area of ​​the first pixel electrode (PXE1) may be the same as the area of ​​the first common electrode (CE1), the area of ​​the second pixel electrode (PXE2) may be the same as the area of ​​the second common electrode (CE2), and the area of ​​the third pixel electrode (PXE3) may be the same as the area of ​​the third common electrode (CE3), but the embodiment of the present specification is not limited thereto.

[0113] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1), and the area of ​​the second common electrode (CE2) may be larger than the area of ​​the first common electrode (CE1). In addition, since the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), whereas the first light conversion layer (QDL1) must convert the light, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3), and the area of ​​the first common electrode (CE1) may be larger than the area of ​​the third common electrode (CE3).

[0114] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a second electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0115] The first common electrode (CE1) may be connected to a second power line (VSL) to which a second driving voltage (VSS) is applied through a first common connection hole (CT4). The second common electrode (CE2) may be connected to the second power line (VSL) through a second common connection hole (CT5). The third common electrode (CE3) may be connected to the second power line (VSL) through a third common connection hole (CT6). Therefore, the second driving voltage (VSS) may be applied to each of the common electrodes (CE1, CE2, CE3). The pixel electrodes (PXE1, PXE2, PXE3) may be referred to as an anode electrode or a first electrode, and the common electrodes (CE1, CE2, CE3) may be referred to as a cathode electrode or a second electrode.

[0116] A plurality of light emitting elements (LEs) may be arranged on pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3). Each of the plurality of light emitting elements (LEs) may have a rectangular planar shape, but the embodiments of the present specification are not limited thereto. For example, each of the plurality of light emitting elements (LEs) may have a circular planar shape.

[0117] The first light conversion layer (QDL1) can completely overlap with the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0118] The second light conversion layer (QDL2) can completely overlap with the plurality of light emitting elements (LE) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LE) of the second sub-pixel (SPX2) into second light.

[0119] The light transmitting layer (TPL) can completely overlap with the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0120] When the light-emitting element (LE) of the first sub-pixel (SPX1) emits light of a first color, the light-emitting element (LE) of the second sub-pixel (SPX2) emits light of a second color, and the light-emitting element (LE) of the third sub-pixel (SPX3) emits light of a third color, the light conversion layers (QDL1, QDL2) and the light transmitting layer (TPL) may be omitted.

[0121] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of Fig. 5. Fig. 7 is a cross-sectional view showing in detail an example of area A1 of Fig. 6.

[0122] Referring to FIGS. 6 and 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0123] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film that protects the transistors and the light-emitting element layer of the thin film transistor layer (TFTL) from moisture penetrating through the substrate (SUB), which is vulnerable to moisture permeation. The barrier film (BR) may be composed of a plurality of inorganic films that are alternately laminated.

[0124] A thin film transistor (TFT1) may be arranged on the barrier film (BR). The thin film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) illustrated in FIG. 4. The thin film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0125] A first active layer (ACT1) of a thin film transistor (TFT1) may be disposed on the barrier film (BR). The first active layer (ACT1) of the thin film transistor (TFT1) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin film transistor (TFT1) may be formed of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0126] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region overlapping the first gate electrode (G1) in a third direction (DR3) that is a thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions in which ions are doped into a semiconductor material to have conductivity.

[0127] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), and the first drain region (D1) of the thin film transistor (TFT1) and on the barrier film (BR).

[0128] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) of a thin film transistor (TFT1) and a first capacitor electrode (CAE1). The first gate electrode (G1) may overlap the first active layer (ACT1) in the third direction (DR3). Although FIG. 6 illustrates that the first gate electrode (G1) and the first capacitor electrode (CAE1) are disposed apart from each other, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0129] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the thin film transistor (TFT1).

[0130] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed therebetween.

[0131] A first interlayer insulating film (141) may be placed on the second capacitor electrode (CAE2) and the second gate insulating film (132).

[0132] A first data metal layer may be disposed on a first interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D1) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the first interlayer insulating film (141).

[0133] A first planarization organic film (160) may be disposed on the first source connection electrode (PCE1) and the first interlayer insulating film (141) to planarize the step caused by the thin film transistor (TFT1).

[0134] A second data metal layer may be disposed on the first planarization organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) penetrating the first planarization organic film (160).

[0135] A second planarization organic film (180) may be placed on the second source connection electrode (PCE2) and the first planarization organic film (160).

[0136] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), the third gate insulating film (133), and the interlayer insulating film (141) are inorganic films, for example, silicon nitride (SiN). x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed.

[0137] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0138] The first planarization organic film (160) and the second planarization organic film (180) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0139] A light-emitting element layer may be arranged on the second planarizing organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), a common electrode (CE), and an organic layer (210).

[0140] A pixel electrode layer including pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) may be disposed on a second planarizing organic film (180).

[0141] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be connected to the second source connection electrode (PCE2) through a connection hole (CT1 / CT2 / CT3 in FIG. 5) penetrating the second planarization organic film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to the first source region (S1) or the first drain region (D1) of the thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin film transistor (TFT1) may be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0142] The common electrodes (CE1, CE2, and CE3) can be connected to a second power line (VSL in FIG. 4) to which a second driving voltage (VSS in FIG. 3) is applied through a common connection hole (CT4 / CT5 / CT6 in FIG. 5). The first electrode (CE1) can be connected to the second power line (VSL) through the first common connection hole (CT4). The second common electrode (CE2) can be connected to the second power line (VSL) through the second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power line (VSL) through the third common connection hole (CT6). Therefore, the second driving voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, and CE3).

[0143] The pixel electrode layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, in order to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu) having a low surface resistance.

[0144] An organic layer (210) may be disposed on each pixel electrode layer. For example, the organic layer (210) may cover at least a portion of the pixel electrodes (PXE1, PXE2, PXE3) and at least a portion of the common electrodes (CE1, CE2, CE3).

[0145] The organic layer (210) serves to temporarily fix or adhere the upper member (e.g., the light emitting element (LE)). For example, the organic layer (210) may be a film for temporarily adhering the upper member (e.g., the light emitting element (LE)) onto each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3). To facilitate the adhering, the thickness of the organic layer (210) may be greater than the thickness of each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3), and may be greater than the thickness of the contact electrode (CTE). The thickness of the organic layer (210) may be about 2 μm, but is not limited thereto.

[0146] In one embodiment, the organic layer (210) may be arranged in an island pattern shape in each sub-pixel (SPX1, SPX2, SPX3). For example, the organic layer (210) arranged in each sub-pixel (SPX1, SPX2, SPX3) may be arranged spaced apart from the organic layer (210) arranged in the adjacent sub-pixel (SPX1, SPX2, SPX3).

[0147] The organic layer (210) may be a photosensitive organic film such as a photoresist. Alternatively, the organic layer (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0148] A plurality of light emitting elements (LE) can be arranged on the organic layer (210). In FIGS. 6 and 7, the light emitting element (LE) is exemplified as a flip-type micro LED. The flip-type micro LED refers to an LED in which contact electrodes (CTE1, CTE2) are formed on one surface (e.g., the lower surface) of the light emitting element (LE).

[0149] Each of the plurality of light emitting elements (LEs) can be formed of an inorganic material such as gallium nitride (GaN).

[0150] Each of the plurality of light emitting elements (LEs) can be grown and formed on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light emitting elements (LEs) can be transferred onto the pixel electrode layer of the display panel (100) directly from the semiconductor substrate or via a transfer substrate. Alternatively, the plurality of light emitting elements (LEs) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS (Polydimethylsiloane) or silicone as a transfer substrate.

[0151] Although not shown in this specification, a reflective film may be disposed on the upper surface of the pixel electrode (PXE1) and the common electrode (CE1).

[0152] A reflective film can reflect light traveling downward from a light-emitting element (LE) and emit light to the upper surface of the light-emitting element (LE). Therefore, light loss from the light-emitting element (LE) can be reduced, and thus the light efficiency of the light-emitting element (LE) can be increased.

[0153] The reflective film can be formed as a single layer of a highly reflective metal, or as a multilayer, such as titanium (Ti) / aluminum (Al) / titanium (Ti) or ITO / aluminum (Al) / ITO.

[0154] The light emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (SEM3), a first contact electrode (CTE1), a second contact electrode (CTE2), and a protective film (INS).

[0155] The conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0156] The first semiconductor layer (SEM1) may be disposed on the conductive layer (E1). The first semiconductor layer (SEM1) may be formed of a semiconductor material layer doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like, for example, gallium nitride (GaN).

[0157] The active layer (MQW) can be disposed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0158] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately laminated. In this case, the well layers may be formed of indium gallium nitride (InGaN), and the barrier layer may be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments of the present specification are not limited thereto.

[0159] Alternatively, the active layer (MQW) may have a structure in which semiconductor materials having a large band gap energy and semiconductor materials having a small band gap energy are alternately laminated, or may include different group 3 to group 5 semiconductor materials depending on the wavelength of the emitted light.

[0160] For example, when the active layer (MQW) includes indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting element (LE) that emits the third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0161] A second semiconductor layer (SEM2) may be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductive dopant, such as silicon (Si), germanium (Ge), or tin (Sn), for example, gallium nitride (GaN).

[0162] The third semiconductor layer (SEM3) can be disposed on the second semiconductor layer (SEM2). The third semiconductor layer (SEM3)

[0163] The third semiconductor layer (SEM3) is a semiconductor material layer having an n-type dopant lower than a predetermined threshold value, and may be referred to as an undoped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN), having an n-type dopant lower than a predetermined threshold value.

[0164] The upper surface of the third semiconductor layer (SEM3) may have a light extraction pattern (LEP).

[0165] Light extraction patterns (LEPs) may be patterns for increasing the efficiency of light emitted from the upper surface of a light emitting element (LE). The light extraction patterns (LEPs) may be concave patterns formed in the shape of a hemisphere or a semi-ellipse. The light extraction patterns (LEPs) may be concave patterns having a cross-sectional shape of a semicircle or a semi-ellipse.

[0166] An electron blocking layer may be disposed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer may be omitted.

[0167] The superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN). The superlattice layer may be omitted.

[0168] The light emitting element (LE) can be divided into a conductive layer (E1), a first element load (LD1), a second element load (LD2), a first contact electrode (CTE1), and a second contact electrode (CTE2).

[0169] The first element load (LD1) may be arranged closer to the second planarization organic film (180) than the second element load (LD2). The first element load (LD1) has a tapered shape with a width that decreases toward the top. The first element load (LD1) may include a first semiconductor layer (SEM1) and an active layer (MQW). Therefore, in the first element load (LD1), the width of the first semiconductor layer (SEM1) is wider than the width of the active layer (MQW).

[0170] When the first element load (LD1) has a positive taper shape, the light extraction effect can be improved compared to a reverse taper shape.

[0171] For example, for convenience of explanation, the inner side of the first element load (LD1) is referred to as the first inner side (SS1) and the inner side of the second element load (LD2) is referred to as the second inner side (SS2). Meanwhile, the outer side of the first element load (LD1) is referred to as the first outer side (SO1) and the outer side of the second element load (LD2) is referred to as the second outer side (SO2).

[0172] The first element load (LD1) may have a first inclination angle (θ1) formed by the first inner surface (SS1) and one surface of the first semiconductor layer (SEM1) within a range of about 20° to 65°.

[0173] The second inclination angle (θ2) formed by the second outer surface (SO2) of the second element load (LD2) and the first outer surface (SO1) of the first element load (LD1) may be in the range of about 110° to 155°.

[0174] The second element load (LD2) is disposed on the first element load (LD1) and may have a side surface that is relatively vertical compared to the first element load (LD1). The second element load (LD2) may have a width of an upper surface and a width of a lower surface that are substantially the same. For example, the second semiconductor layer (SEM2) may have a cross-sectional shape that is substantially the same as a rectangle or square. The width of the third semiconductor layer (SEM3) of the second element load (LD2) is narrower than the width of the active layer (MQW).

[0175] The second element load (LD2) can secure the volume of the second semiconductor layer (SEM2) by forming a vertical side surface compared to the regular tapered shape, and can maximize the injection of electron carriers into the active layer (MQW). For example, when the second element load (LD2) is formed in the same regular tapered shape as the first element load (LD1), the width of the upper surface of the second semiconductor layer (SEM2) becomes narrower than the width of the lower surface, so that the volume of the second semiconductor layer (SEM2) is reduced.

[0176] The protective film (INS) may be a film for protecting the bottom and side surfaces of the light emitting element (LE). The protective film (INS) may be disposed on the bottom and side surfaces of the conductive layer (E1) and the side surfaces of a plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3). The protective film (INS) may be an inorganic film, for example, silicon nitride (SiN). x ), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed. It is preferable that the protective film (INS) be arranged from one end to the other end of the side of the light emitting element (LE), but it may be arranged to be spaced apart from one end due to process error.

[0177] A hole (LEH) can be formed to penetrate the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light emitting element (LE) and expose the second semiconductor layer (SEM2). The hole (LEH) may have a rectangular planar shape, but the embodiments of the present specification are not limited thereto. For example, the hole (LEH) may have a polygonal, circular, or elliptical planar shape such as a square.

[0178] Additionally, the protective film (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed without being covered by the protective film (INS).

[0179] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor layer (SEM1, MQW, SEM2, SEM3) and on at least one side and the lower surface of the conductive layer (E1). The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by the protective film (INS). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1).

[0180] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor layer (SEM1, MQW, SEM2, SEM3) and at least one side and the lower surface of the conductive layer (E1). At this time, the first contact electrode (CTE1) may be disposed on the first side of the semiconductor layer (SEM1, MQW, SEM2, SEM3) and the first side of the conductive layer (E1), while the second contact electrode (CTE2) may be disposed on the second side of the semiconductor layer (SEM1, MQW, SEM2, SEM3) and the second side of the conductive layer (E1).

[0181] The second contact electrode (CTE2) can be disposed on the passivation layer (INS) disposed in the hole (LEH) and the second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the passivation layer (INS). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0182] The first contact electrode (CTE1) and the second contact electrode (CTE2) may be disposed on at least a portion of the side surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2). The first contact electrode (CTE1) and the second contact electrode (CTE2) are spaced apart from the upper surface of the light emitting element (LE) in the third direction (DR3). For example, among the side surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3), at least an area adjacent to the upper surface of the third semiconductor layer (SEM3) may be exposed without being covered by the first contact electrode (CTE1) and the second contact electrode (CTE2). The first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed lower than at least one end of the passivation layer (INS).

[0183] The first contact electrode (CTE1) and the second contact electrode (CTE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0184] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may be disposed on three side surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3). For example, when the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3) include first to fourth side surfaces, the first contact electrode (CTE1) may be disposed on the first side surface, the second side surface, and the third side surface, and the second contact electrode (CTE2) may be disposed on the second side surface, the third side surface, and the fourth side surface.

[0185] The connecting electrodes (BE1, BE2) electrically connect the light emitting element (LE) and the pixel electrode layer.

[0186] In one embodiment, the first connection electrode (BE1) connects the first contact electrode (CTE1) of the light emitting element (LE) and the pixel electrode (PXE1 / PXE2 / PXE3).

[0187] The first connection electrode (BE1) may be disposed on the first contact electrode (CTE1) disposed on the side surface of the plurality of semiconductor layers (SEM1, MQW, SEM2), extend along the organic layer (210), and be disposed on the pixel electrode (PXE1 / PXE2 / PXE3). Accordingly, the first connection electrode (BE1) may connect the conductive layer (E1) of the light emitting element (LE) and the pixel electrode (PXE1 / PXE2 / PXE3).

[0188] The second connection electrode (BE2) connects the second contact electrode (CTE2) of the light emitting element (LE) and the common electrode (CE1 / CE2 / CE3). The second connection electrode (BE2) may be disposed on the second contact electrode (CTE2) disposed on the side of the plurality of semiconductor layers (SEM1, MQW, SEM2), extend along the organic layer (210), and be disposed on the common electrode (CE1 / CE2 / CE3). Accordingly, the second connection electrode (BE2) may connect the second semiconductor layer (SEM2) of the light emitting element (LE) and the common electrode (CE1 / CE2 / CE3).

[0189] The first connection electrode (BE1) and the second connection electrode (BE2) may be spaced apart from the upper surface of the semiconductor layers (SEM1, MQW, SEM2, SEM3) in the third direction (DR3). The first connection electrode (BE1) and the second connection electrode (BE2) may be formed lower than at least one end of the first contact electrode (CTE1) and the second contact electrode (CTE2). For example, the distance between the first connection electrode (BE1) and the upper surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3) may be greater than the distance between the first contact electrode (CTE1) and the upper surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3), and the distance between the second connection electrode (BE2) and the upper surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3) may be greater than the distance between the second contact electrode (CTE2) and the upper surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3). However, in one embodiment, as illustrated in FIG. 7, the first connection electrode (BE1) and the second connection electrode (BE2) may be formed at the same distance from the upper surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3) as the first contact electrode (CTE1) and the second contact electrode (CTE2).

[0190] The thickness of the first connection electrode (BE1) and the second connection electrode (BE2) may each be about 1000 Å, but is not limited thereto.

[0191] The first connecting electrode (BE1) and the second connecting electrode (BE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the second connecting electrode (BE2) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0192] A partition wall (BM) that divides each sub-pixel (SPX1, SPX2, SPX3) may be further arranged on the second flat organic film (180).

[0193] The bulkhead (BM) may also be called a light-shielding layer in that it includes a light-shielding material to prevent light from a light-emitting element (LE) of one sub-pixel from traveling to the neighboring sub-pixel.

[0194] The partition wall (BM) may be formed in a grid-like pattern across the entire display area (DA). The partition wall (BM) may not overlap with a plurality of light-emitting elements (LE) in the third direction (DR3). The partition wall (BM) may serve to provide a space for forming a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light transmitting layer (TPL). The partition wall (BM) may be formed of an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0195] In one embodiment, the partition wall (BM) is formed as a single layer, but this is not limited thereto. For example, the partition wall (BM) may be formed as a double layer. The partition wall (BM) may be formed as a double layer to secure sufficient space for forming the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0196] The barrier layer (BM) may include a light-blocking material as described above. For example, the barrier layer (BM) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0197] A reflective layer (RF) may be disposed inside a space formed by a barrier rib (BM). The reflective layer (RF) may be disposed on a side of the barrier rib (BM), a bottom surface between the barrier ribs (BM) and the barrier ribs (BM) that does not overlap with the pixel electrodes (PXE1, PXE2, PXE3), the common electrode (CE) and the light emitting element (LE). The reflective layer (RF) may include an opening formed in an area overlapping with the pixel electrodes (PXE1, PXE2, PXE3), the common electrode (CE) and the light emitting element (LE). The reflective layer (RF) may not be in contact with the pixel electrodes (PXE1, PXE2, PXE3) and the common electrode (CE) and may not be electrically connected to them.

[0198] Meanwhile, the second planarizing organic film (180) overlapping the pixel electrode layer (pixel electrodes (PXE1, PXE2, PXE3) and common electrode (CE)) may have an undercut shape positioned inward rather than on the side. By adopting this undercut shape, the reflective layer (RF) and the pixel electrode layer (pixel electrodes (PXE1, PXE2, PXE3) and common electrode (CE)) may be arranged on different layers and may not contact each other.

[0199] The reflection layer (RF) serves to reflect light traveling laterally in the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0200] The reflective layer (RF) may include a metallic material having a high light reflectivity. For example, the reflective layer (RF) may include aluminum or silver, or may include an alloy thereof.

[0201] In the first sub-pixel (SPX1), a first light conversion layer (QDL1) may be disposed between the partition walls (BM) and the partition walls (BM), in the second sub-pixel (SPX2), a second light conversion layer (QDL2) may be disposed between the partition walls (BM) and the partition walls (BM), and in the third sub-pixel (SPX3), a light transmitting layer (TPL) may be disposed between the partition walls (BM) and the partition walls (BM).

[0202] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band). The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band).

[0203] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band). It can include a second base resin (BRS2) and second wavelength conversion particles (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. The second wavelength conversion particles (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band).

[0204] The optically transparent layer (TPL) may include a light-transmitting organic material.

[0205] For example, the first base resin (BRS1), the second base resin (BRS2), and the light transmitting layer (TPL) may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0206] The capping layer (CAP) can be disposed on the barrier rib (BM), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0207] The capping layer (CAP) is an inorganic film, for example, silicon nitride (SiN). x), silicon oxide nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x ) can be formed. The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL) can be encapsulated by a capping layer (CAP).

[0208] A fourth organic film (213) may be disposed on the capping layer (CAP). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0209] The first color filter (CF1) arranged in the first sub-pixel (SPX1) can transmit the first light (light in the red wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel (SPX1) can emit the first light (light in the red wavelength band).

[0210] The second color filter (CF2) arranged in the second sub-pixel (SPX2) can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit the second light (light in the green wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the second sub-pixel (SPX2) can emit the second light (light in the green wavelength band).

[0211] The third color filter (CF3) arranged in the third sub-pixel (SPX3) can transmit the third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element (LE) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel (SPX3) can emit the third light (light in the blue wavelength band).

[0212] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap the partition wall (BM) in the third direction (DR3).

[0213] A fifth organic film (214) for planarization may be placed on a plurality of color filters (CF1, CF2, CF3).

[0214] The fourth organic film (213) and the fifth organic film (214) can be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0215] Fig. 8 is a drawing explaining the direction of propagation of light emitted from the light-emitting element of Fig. 7.

[0216] As illustrated in Fig. 8, in the case of a light-emitting element (LE) having a regular tapered shape, the light emitted from the lower surface of the light-emitting element (LE) may be relatively reduced and the reflectivity may be increased, compared to a light-emitting element (LE) having a reverse tapered shape, in the case of a first element load (LD1) including an active layer (MQW).

[0217] Accordingly, the display device according to one embodiment can increase the brightness of the display device when the same current as in the prior art is injected. Furthermore, the display device according to one embodiment can reduce power consumption compared to the same brightness as in the prior art.

[0218] Figure 9 is a cross-sectional view showing another example of area A1 of Figure 6 in detail.

[0219] The embodiment of Fig. 9 differs from the embodiment of Fig. 7 in that the light emitting element (LE) does not include a third semiconductor layer (SEM3). In Fig. 9, descriptions overlapping with the embodiments described with reference to Figs. 6 and 7 will not be repeated, and descriptions will be focused on differences from the embodiment of Fig. 7.

[0220] The light emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a first contact electrode (CTE1), a second contact electrode (CTE2), and a protective film (INS).

[0221] The first contact electrode (CTE1) and the second contact electrode (CTE2) are spaced apart from the upper surface of the light emitting element (LE) in the third direction (DR3). For example, among the side surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2), at least an area adjacent to the upper surface of the second semiconductor layer (SEM2) may be exposed without being covered by the first contact electrode (CTE1) and the second contact electrode (CTE2). The first contact electrode (CTE1) and the second contact electrode (CTE2) may be formed lower than at least one end of the passivation layer (INS).

[0222] Fig. 10 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of Fig. 5. Fig. 11 is a cross-sectional view showing in detail an example of area A2 of Fig. 10.

[0223] The embodiments of FIGS. 10 and 11 differ from the embodiments of FIGS. 6 and 7 in that no organic layer (210 in FIG. 7) is disposed between the light emitting element (LE) and the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3). In FIGS. 10 and 11, descriptions that overlap with the embodiments described with reference to FIGS. 6 and 7 will not be repeated, and descriptions will be focused on differences from the embodiments of FIGS. 6 and 7.

[0224] Referring to FIGS. 10 and 11, the light emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (SEM3), a first contact electrode (CTE1), a second contact electrode (CTE2), a first electrode (DE1), a second electrode (DE2), and a protective film (INS).

[0225] The first electrode (DE1) may be formed to be in direct contact with the first contact electrode (CTE1), and the second electrode (DE2) may be formed to be in direct contact with the second contact electrode (CTE2) in the hole (LEH). The first electrode (DE1) and the second electrode (DE2) protrude above the conductive layer (E1).

[0226] The first electrode (DE1) and the second electrode (DE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0227] In another embodiment, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be omitted. In this case, the first electrode (DE1) may directly contact the conductive layer (E1), and the second electrode (DE2) may directly contact the second semiconductor layer (SEM2) in the hole (LEH).

[0228] A first electrode (DE1) is disposed on pixel electrodes (PXE1, PXE2, PXE3), and a second electrode (DE2) is disposed on common electrodes (CE1, CE2, CE3). A first bonding electrode (BE1') may be disposed between the first electrode (DE1) and the pixel electrodes (PXE1, PXE2, PXE3). The first bonding electrode (BE1') may serve as a bonding metal for bonding the first electrode (DE1) and the pixel electrodes (PXE1, PXE2, PXE3). Similarly, a second bonding electrode (BE2') may be disposed between the second electrode (DE2) and the common electrodes (CE1, CE2, CE3), and may serve as a bonding metal for bonding the second electrode (DE2) and the common electrodes (CE1, CE2, CE3).

[0229] The first bonding electrode (BE1') and the second bonding electrode (BE2') may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the first bonding electrode (BE1') and the second bonding electrode (BE2') may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin.

[0230] FIG. 12 is a layout diagram showing pixels of a display area according to one embodiment.

[0231] The embodiment of FIG. 12 differs from the embodiment of FIG. 5 in that the light emitting elements (LEs) overlap the pixel electrodes (PXE1 / PXE2 / PXE3) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). In the embodiment of FIG. 12, descriptions overlapping with the embodiment of FIG. 5 are omitted.

[0232] Referring to FIG. 12, a first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). A second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). A third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LEs), and a light-transmitting layer (or third light conversion layer) (TPL).

[0233] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0234] For example, as shown in FIG. 12, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). In addition, since the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), whereas the first light conversion layer (QDL1) must convert the light, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0235] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a first electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0236] A plurality of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The same number of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3).

[0237] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1) and the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The area of ​​the first light conversion layer (QDL1) can be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0238] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2) and the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2) into second light.

[0239] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3) and the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0240] Fig. 13 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 12. Fig. 14 is a cross-sectional view showing in detail an example of area A2 of Fig. 13.

[0241] The embodiments of FIGS. 13 and 14 differ from the embodiment of FIG. 6 in that the light emitting elements (LE) are vertical type micro LEDs in which each of the plurality of light emitting elements (LE) extends in a third direction (DR3). The vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (SEM3) are sequentially arranged in the third direction (DR3), which is a vertical direction.

[0242] In the embodiments of FIGS. 13 and 14, descriptions that overlap with those of the embodiments of FIGS. 6 and 7 will not be repeated.

[0243] Referring to FIGS. 13 and 14, a pixel electrode layer may be disposed on the second planarizing organic film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3).

[0244] Although not shown in this specification, a reflective film may be disposed on the upper surfaces of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0245] A reflective film can reflect light traveling downward from a light-emitting element (LE) and emit light to the upper surface of the light-emitting element (LE). Therefore, light loss from the light-emitting element (LE) can be reduced, and thus the light efficiency of the light-emitting element (LE) can be increased.

[0246] An organic layer (210) is disposed on the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0247] A plurality of light emitting elements (LEs) may be arranged on an organic layer (210). In one embodiment, the organic layer (210) may be arranged in an island pattern shape in each sub-pixel (SPX1, SPX2, SPX3). For example, the organic layer (210) arranged in each sub-pixel (SPX1, SPX2, SPX3) may be arranged to be spaced apart from the organic layer (210) arranged in the adjacent sub-pixel (SPX1, SPX2, SPX3).

[0248] Each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of several to several hundred μm, respectively. For example, each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of approximately 100 μm or less, respectively.

[0249] The light emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (SEM3), a contact electrode (CTE), and a passivation layer (INS).

[0250] The light emitting element (LE) can be divided into a conductive layer (E1), a first element load (LD1), a second element load (LD2), and a contact electrode (CTE).

[0251] The first element load (LD1) may be arranged closer to the second planarization organic film (180) than the second element load (LD2). The first element load (LD1) has a tapered shape with a width that decreases toward the top. The first element load (LD1) may include a first semiconductor layer (SEM1) and an active layer (MQW). Therefore, in the first element load (LD1), the width of the first semiconductor layer (SEM1) is wider than the width of the active layer (MQW).

[0252] When the first element load (LD1) has a positive taper shape, the light extraction effect can be improved compared to a reverse taper shape.

[0253] For example, for convenience of explanation, the inner side of the first element load (LD1) is referred to as the first inner side (SS1) and the inner side of the second element load (LD2) is referred to as the second inner side (SS2). Meanwhile, the outer side of the first element load (LD1) is referred to as the first outer side (SO1) and the outer side of the second element load (LD2) is referred to as the second outer side (SO2).

[0254] The first element load (LD1) may have a first inclination angle (θ1) formed by the first inner surface (SS1) and one surface of the first semiconductor layer (SEM1) of about 20° to 65°.

[0255] The second outer surface (SO2) of the second element load (LD2) and the first outer surface (SO1) of the first element load (LD1) may have a second inclination angle (θ2) of about 110° to 155°.

[0256] The second element load (LD2) is disposed on the first element load (LD1) and may have a side surface that is relatively vertical compared to the first element load (LD1). The second element load (LD2) may have a width of an upper surface and a width of a lower surface that are substantially the same. For example, the second semiconductor layer (SEM2) may have a cross-sectional shape that is substantially the same as a rectangle or square. The width of the third semiconductor layer (SEM3) of the second element load (LD2) is narrower than the width of the active layer (MQW).

[0257] The second element load (LD2) can secure the volume of the second semiconductor layer (SEM2) by forming a vertical side surface compared to the regular tapered shape, and can maximize the injection of electron carriers into the active layer (MQW). For example, when the second element load (LD2) is formed in the same regular tapered shape as the first element load (LD1), the width of the upper surface of the second semiconductor layer (SEM2) becomes narrower than the width of the lower surface, so that the volume of the second semiconductor layer (SEM2) is reduced.

[0258] The protective film (INS) may be disposed on the side of the first semiconductor layer (SEM1), the side of the active layer (MQW), the side of the second semiconductor layer (SEM2), and the side of the third semiconductor layer (SEM3). The protective film (INS) may be a film for protecting the side of the light emitting element (LE). The protective film (INS) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon nitride oxide (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0259] A plurality of contact electrodes (CTE) may be disposed on the protective film (INS). Each of the plurality of contact electrodes (CTE) may be disposed between the organic layer (210) and the protective film (INS).

[0260] The protective layer (INS) has one or more openings exposing the conductive layer (E1). In one embodiment, the protective layer (INS) includes two openings.

[0261] Each of the plurality of contact electrodes (CTE) can be connected to an exposed conductive layer (E1) that is not covered by a protective film (INS).

[0262] A plurality of contact electrodes (CTEs) can be arranged on at least a portion of a side surface of a semiconductor layer (SEM1, MQW, SEM2, SEM3). Among the side surfaces of the semiconductor layers (SEM1, MQW, SEM2, SEM3), at least a region adjacent to a top surface of the semiconductor layer (SEM1, MQW, SEM2, SEM3) can be exposed without being covered by the contact electrodes (CTEs). For example, the contact electrodes (CTEs) are spaced apart from the top surfaces of the semiconductor layers (SEM1, MQW, SEM2, SEM3) in the third direction (DR3).

[0263] When a plurality of contact electrodes (CTEs) are formed of a metal having high reflectivity, light emitted from the active layer (MQW) of the light emitting element (LE) that propagates in the lateral direction of the light emitting element (LE) can be reflected by the plurality of contact electrodes (CTEs) and emitted to the upper surface of the light emitting element (LE). Therefore, since light loss of the light emitting element (LE) can be reduced, the light efficiency of the light emitting element (LE) can be increased. Therefore, in order to increase the light efficiency of the light emitting element (LE), it is preferable that each of the plurality of contact electrodes (CTEs) be arranged to cover most of the lateral surface of the semiconductor layers (SEM1, MQW, SEM2, SEM3).

[0264] The plurality of contact electrodes (CTEs) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the plurality of contact electrodes (CTEs) may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0265] The connecting electrode (BE) connects the contact electrode (CTE) of the light emitting element (LE) and the pixel electrode (PXE1 / PXE2 / PXE3).

[0266] In one embodiment, the connecting electrode (BE) is disposed on a contact electrode (CTE) disposed on a side surface of a plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3), extends along the organic layer (210), and can be in contact with the pixel electrode (PXE1 / PXE2 / PXE3). Accordingly, the connecting electrode (BE) can connect the conductive layer (E1) of the light emitting element (LE) and the pixel electrode (PXE1 / PXE2 / PXE3).

[0267] Among the side surfaces of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3), an area adjacent to the upper surface of the third semiconductor layer (SEM3) may be exposed without being covered by the connecting electrode (BE).

[0268] A first partition wall (BM1) and a second organic film (211) that divide each light-emitting area (EA1, EA2, EA3) may be further arranged on the second flattening organic film (180).

[0269] The first bulkhead (BM1) may not overlap with the plurality of light emitting elements (LE) in the third direction (DR3).

[0270] The first bulkhead (BM1) may be formed by negative photoresist and may have a reverse taper shape, but is not limited thereto.

[0271] A light-emitting element (LE) and a second organic film (211) may be placed within a space formed by the first partition wall (BM1). The second organic film (211) may be placed to cover a portion of a side surface of a plurality of light-emitting elements (LE). In addition, the second organic film (211) may be placed on a connection electrode (BE) and a protective film (INS).

[0272] The upper surface of each of the plurality of light-emitting elements (LE) may be exposed without being covered by the second organic film (211). The second organic film (211) is a layer for flattening the steps caused by the plurality of light-emitting elements (LE).

[0273] The second organic film (211) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0274] A common electrode (CE) may be disposed on the upper surface of each of the plurality of light emitting elements (LE) and the upper surface of the second organic film (211). The common electrode (CE) may be a common layer formed commonly on the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). The common electrode (CE) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0275] A second bulkhead (BM2) may be further arranged on the first bulkhead (BM1).

[0276] The second bulkhead (BM2) can serve to provide a space for forming the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0277] A reflective layer (RF) may be placed inside the space formed by the second bulkhead (BM2). The reflective layer (RF) may be placed on the side of the second bulkhead (BM2).

[0278] The capping layer (CAP) can be disposed on the second barrier rib (BM2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0279] A fourth organic film (213) may be disposed on the capping layer (CAP). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0280] Figure 15 is a cross-sectional view showing another example of area A2 of Figure 13 in detail.

[0281] The embodiment of FIG. 15 differs from the embodiment of FIG. 14 in that an organic layer (210 of FIG. 14) is not disposed between the light emitting element (LE) and the pixel electrodes (PXE1, PXE2, PXE3). In FIG. 15, descriptions overlapping with the embodiments described with reference to FIGS. 13 and 14 will not be repeated, and descriptions will be focused on differences from the embodiments of FIGS. 13 and 14.

[0282] Referring to FIG. 15, a bonding electrode (BE1') may be disposed between the light emitting element (LE) and the pixel electrodes (PXE1, PXE2, PXE3). The bonding electrode (BE1') may serve as a bonding metal for bonding the contact electrode (CTE) and the pixel electrodes (PXE1, PXE2, PXE3). The bonding electrode (BE1') may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the bonding electrode (BE1') may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin.

[0283] Fig. 16 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Figs. 17 to 35 are exemplary drawings for explaining a method for manufacturing a display device according to one embodiment. Figs. 20, 22, 24, and 26 are micrographs of a conductive layer and a plurality of semiconductor layers according to a manufacturing method according to one embodiment.

[0284] Hereinafter, a method for manufacturing a display device according to one embodiment will be described in detail by connecting FIG. 16 with FIG. 17 to FIG. 35. The method for manufacturing a display device described with reference to FIG. 16 to FIG. 35 may be a display device including a light-emitting element and a display panel described with reference to FIG. 5 to FIG. 7.

[0285] First, a plurality of semiconductor material layers (SEM3L, SEM2L, MQWL, SEM1L) and a conductive layer (E1L) are formed on a second substrate (SUB2). (S110 of Fig. 16)

[0286] First, a second substrate (SUB2) is prepared. The second substrate (SUB2) may be a sapphire substrate (Al2O3) or a transparent silicon wafer containing silicon. However, the present invention is not limited thereto, and in one embodiment, a case in which the second substrate (SUB2) is a sapphire substrate is exemplified and described.

[0287] A plurality of semiconductor material layers (SEM3L, SEM2L, SLTL, MQWL, EBLL, SEM1L) are formed on a second substrate (SUB2). The plurality of semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, a method for forming the semiconductor material layers may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and preferably, it can be formed by metal-organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0288] The precursor material for forming multiple semiconductor material layers is not particularly limited within a range that can be typically selected to form the target material. For example, the precursor material may be a metal precursor containing an alkyl group, such as a methyl group or an ethyl group. Examples thereof include, but are not limited to, compounds such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), and triethyl phosphate ((C2H5)3PO4).

[0289] Specifically, a third semiconductor material layer (SEM3L) is formed on a second substrate (SUB2). Although the drawing illustrates that the third semiconductor layer (SEM3) is laminated in one layer, the present invention is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer (SEM3L) may be arranged to reduce a difference in lattice constants between the second semiconductor material layer (SEM2L) and the second substrate (SUB2). For example, the third semiconductor material layer (SEM3L) may include an undoped semiconductor, and may be a material that is not doped as an n-type or p-type. In an exemplary embodiment, the third semiconductor material layer (SEM3L) may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0290] Using the method described above, a second semiconductor material layer (SEM2L), an active material layer (MQWL), and a first semiconductor material layer (SEM1L) are sequentially formed on a third semiconductor material layer (SEM3L).

[0291] Next, a conductive layer (E1L) is deposited on the semiconductor material layers (SEM3L, SEM2L, MQWL, SEM1L). The conductive layer (E1L) may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but is not limited thereto.

[0292] Second, a double mask is formed on the conductive layer (E1L) and primary etching is performed. (S120 of Figure 160) Primary etching can be performed by dry etching. When using a dry etching method, the etching gas may be chlorine (Cl2) or oxygen (O2) gas, but is not limited thereto.

[0293] Referring to FIG. 18, a hard mask material layer (HML) is formed on a conductive layer (E1L). The hard mask material layer (HML) may be formed of silicon oxide (SiOx). A patterned photoresist mask (PRM) is formed on the hard mask material layer (HML). Photoresist is a photosensitive material that is organically dissolved with a resin and a photosensitive agent. Therefore, the photoresist mask (PRM) is also formed of a photosensitive material.

[0294] Thereafter, the hard mask material layer (HML) is patterned through a dry etching process using the patterned photoresist mask (PRM) as a mask. The upper portion of the conductive layer (E1L) in an area that does not overlap with the patterned photoresist mask (PRM) may be exposed through the dry etching process. Then, the photoresist mask (PRM) pattern is removed by ashing. Thereafter, the conductive layer (E1L), the first semiconductor material layer (SEM1L), the active material layer (MQWL), and the second semiconductor material layer (SEM2) are etched using the patterned hard mask material layer (HML) as a mask.

[0295] Referring to FIGS. 19 and 20, the width of the plurality of semiconductor material layers may increase as they go downwards by dry etching. For example, the width of the first semiconductor layer (SEM1) may be narrower than the width of the active layer (MQW), and the width of the active layer (MQW) may be narrower than the width of the second semiconductor layer (SEM2). The third semiconductor layer (SEM3) may not be etched.

[0296] Meanwhile, dry etching uses highly reactive gases instead of liquid chemical solutions. As the etching depth increases during dry etching, the process time increases, and the plasma exposure time of the semiconductor material layer increases, potentially increasing damage to the active layer.

[0297] Third, secondary etching is performed using a hard mask. (S130 in Fig. 160) Secondary etching can be performed using wet etching.

[0298] Referring to FIGS. 21 and 22, when wet etching is performed using a hard mask, multiple semiconductor layers protruding outside the hard mask are etched, so that multiple semiconductor layers can be formed almost vertically.

[0299] Wet etching is a method of etching by causing a chemical reaction with the thin film material to be removed using a chemical solution. Since the thin film material is removed by a chemical reaction at the contact area, new chemical solution must continuously come into contact with the thin film surface for the chemical reaction to proceed smoothly on the surface. Wet etching has the advantage of very high selectivity because only substances that react chemically do not react. For example, the etching rate of the first semiconductor layer (SEM1) is lower than that of the active layer (MQW), and the etching rate of the second semiconductor layer (SEM2) is lower than that of the active layer (MQW). Therefore, because the etching rate of the second semiconductor layer (SEM2) is higher than that of the first semiconductor layer (SEM1), the etching amount of the second semiconductor layer (SEM2) becomes greater than that of the first semiconductor layer (SEM1) over time. For example, after a first period of time (e.g., 15 minutes) after the start of wet etching, the side surfaces of the plurality of semiconductor layers can be formed almost vertically, as shown in FIGS. 21 and 22. Thereafter, as a second period of time passes after the start of wet etching, the etching amount of the second semiconductor layer (SEM2) becomes greater than that of the first semiconductor layer (SEM1). For example, FIGS. 23 and 24 are shapes of the plurality of semiconductor layers (SEM1, MQW, SEM2, SEM3) after a third period of time (e.g., 30 minutes) after the start of wet etching, and FIGS. 25 and 26 are shapes of the plurality of semiconductor layers (SEM1, MQW, SEM2) after a fourth period of time (e.g., 150 minutes) after the start of wet etching.

[0300] In this way, each semiconductor layer can be formed at a desired inclination angle by adjusting the wetting time, etc.

[0301] Fourth, the first contact electrode (CTE1) and the second contact electrode (CTE2) are formed. (S140 of Fig. 160)

[0302] For example, referring to FIG. 27, a portion of the upper portion of the conductive layer (E1) is covered using a mask, and a hole (LEH) is formed in each of the light emitting elements (LE) where the mask is not placed, penetrating the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) to expose the second semiconductor layer (SEM2).

[0303] Next, referring to FIG. 28, a protective material layer (INSL) may be fully deposited on one surface of a semiconductor substrate (SSUB). The protective material layer (INSL) may be formed to cover one surface and side surfaces of the light-emitting elements (LE). The protective material layer (INSL) may be formed on one surface of the second substrate (SUB2) exposed between the light-emitting elements (LE).

[0304] Thereafter, the first mask may be used to form a portion of the hole (LEH) of each of the light emitting elements (LE). For example, the first mask may be used to form a portion of the hole (LEH) of each of the light emitting elements (LE) so as not to cover the protective material layer (INSL) disposed on the bottom surface of the hole (LEH) of each of the light emitting elements (LE).

[0305] In addition, when a large upper and lower voltage difference is formed in dry etching and the protective material layer (INSL) is etched, the etching gas proceeds in the third direction (DR3) and etches the protective material layer (INSL). As a result, the protective material layer (INSL) arranged on the sidewall of the hole (LEH) of each of the light-emitting elements (LE) can remain without being etched even if it is not protected by the first mask pattern. Accordingly, the protective material layer (INSL) arranged on the bottom surface of the hole (LEH) of each of the light-emitting elements (LE) is etched, and the second semiconductor material layer (SEML2) in the hole (LEH) of each of the light-emitting elements (LE) can be exposed without being covered by the protective material layer (INSL).

[0306] Then, the first mask can be removed by an ashing process.

[0307] Thereafter, etching is performed to expose a portion of the upper surface of the conductive layer (E1) and the inner bottom surface of the hole (LEH). Next, an electrode material layer is formed on the entire surface of the second substrate (SUB2) so as to cover all of the plurality of semiconductor layers (SEM1, MQW, SEM2) on the protective material layer (INSL). Thereafter, a portion of the electrode material layer is etched using a photoresist to form a first contact electrode (CTE1) and a second contact electrode (CTE2). The first contact electrode (CTE1) may contact the first conductive layer (E1), and the second contact electrode (CTE2) may contact the second semiconductor layer (SEM2).

[0308] Fifth, the light emitting element (LE) is transferred to the substrate (SUB). (S150 of Figure 160)

[0309] Referring to FIG. 29, a plurality of light-emitting elements (LE) of a second substrate (SUB2) are moved to a first adhesive layer (ADL1) disposed on a first transfer substrate (TSUB1).

[0310] The first transfer substrate (TSUB1) may be formed of a transparent material that allows light to pass through. For example, the first transfer substrate (TSUB1) may include a transparent polymer such as polyimide, polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesive layer (ADL1) disposed on one surface of the first transfer substrate (TSUB1) may include an adhesive material for adhering a plurality of light emitting elements (LE). For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0311] A first contact electrode (CTE1) and a second contact electrode (CTE2) of each of a plurality of light-emitting elements (LE) may be adhered to a first adhesive layer (ADL1) disposed on a first transfer substrate (TSUB1). Then, the plurality of light-emitting elements (LE) may be separated from the semiconductor substrate (SSUB) by a laser lift-off (LLO) process of irradiating a laser (Laser) onto the semiconductor substrate (SSUB). The laser may be a KrF excimer laser having a wavelength of approximately 248 nm, but the embodiments of the present specification are not limited thereto.

[0312] Referring to FIG. 30, a plurality of light-emitting elements (LE) of a first transfer substrate (TSUB1) are moved to a first laser separation layer (LLO1) arranged on a second transfer substrate (TSUB2).

[0313] The second transfer substrate (TSUB2) may be made of a transparent material that allows light to pass through. For example, the second transfer substrate (TSUB2) may include a transparent polymer such as polyimide, polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first laser separation layer (LLO1) disposed on the second transfer substrate (TSBU2) is a layer that can be separated by laser irradiation and may include, for example, a transparent polymer such as polyimide.

[0314] When heat is applied while one surface of each of the plurality of light-emitting elements (LE) is in contact with the first laser separation layer (LLO1), each of the plurality of light-emitting elements (LE) can be adhered or fixed to the first laser separation layer (LLO1), and the adhesive strength of the first adhesive layer (ADL1) is weakened, so that each of the plurality of light-emitting elements (LE) can be separated from the first adhesive layer (ADL1). One surface of each of the plurality of light-emitting elements (LE) can be the opposite surface of the other surface of each of the plurality of light-emitting elements (LE) on which the first adhesive electrode (CTE1) and the second adhesive electrode (CTE2) are arranged.

[0315] Next, an organic layer (210) is formed on a second planarized organic film (180) on which pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) are arranged, and then a second transfer substrate (TSUB2) is bonded so that a light emitting element (LE) is arranged on the organic layer (210).

[0316] When the organic layer (210) is a photosensitive organic film such as a photoresist, the organic layer (210) can be cured (soft baked) at a first temperature when forming the organic layer (210). Thereafter, after the light-emitting element (LE) is placed on the organic layer (210), the organic layer (210) can be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the embodiments of the present specification are not limited thereto. In addition, the process of completely curing the organic layer (210) at the second temperature may be performed for approximately 30 minutes.

[0317] Therefore, the bonding process using the organic layer (210) can bond the light emitting element (LE) to the substrate (SUB) at a relatively lower temperature and pressure compared to the eutectic bonding process.

[0318] Afterwards, the second transfer substrate (TSUB2) is separated from the plurality of light emitting elements (LE).

[0319] Afterwards, the second transfer substrate (TSUB2) is separated from the plurality of light emitting elements (LE).

[0320] Sixth, the following forms a bulkhead (BM) and connecting electrodes (BE1, BE2). (S160 in Fig. 16)

[0321] First, referring to FIG. 33, a barrier rib (BM) is formed on the second planarization organic film (180). For example, the barrier rib (BM) is formed on the second planarization organic film (180) using a negative photoresist. Since the negative photoresist dissolves in the portion that is not exposed to light, the barrier rib (BM) can be formed in a reverse taper shape with a width that becomes narrower as it goes downward.

[0322] Next, referring to FIG. 34, a reflective material layer is deposited on the entire surface of the substrate (SUB) on which the barrier rib (BM) is formed. The reflective material layer can be formed to cover both the barrier rib (BM) and the light-emitting element (LE). The reflective material layer is formed not only on the upper surface side surface of the barrier rib (BM), the upper surface and side surface of the light-emitting element (LE), but also on the floor between the light-emitting element (LE) and the barrier rib (BM).

[0323] The reflective material layer is formed on the upper surface and side surfaces of the barrier rib (BM), the upper surface and side surfaces of the light-emitting element (LE), and also on the bottom (the upper surface of the second planarizing organic film (180)) between the light-emitting element (LE) and the barrier rib (BM). The reflective material layer is arranged along the side surfaces of the light-emitting element (LE), the side surfaces of the organic layer (210), the first pixel electrode (PXE1), and the side surfaces of the second common electrode (CE1), but is disconnected by the undercut-shaped structure of the second planarizing organic film (180). Specifically, the reflective material layer arranged along the side surfaces of the light-emitting element (LE), the side surfaces of the organic layer (210), the first pixel electrode (PXE1), and the side surfaces of the first common electrode (CE1), and the reflective material layer arranged along the barrier rib (BM) are discontinuously arranged.

[0324] A portion of the reflective material layer, such as the upper surface of the barrier rib (BM), can be removed to form a reflective layer (RF), a first connection electrode (BE1), and a second connection electrode (BE2).

[0325] Seventh, a wavelength conversion layer, a light transmitting layer, and a color filter layer are formed sequentially. (S170 in Fig. 16)

[0326] Referring to FIG. 35, a first light conversion layer (QDL1) is formed in each of the first sub-pixels (SPX1), a second light conversion layer (QDL2) is formed in each of the second sub-pixels (SPX2), and a light transmitting layer (TPL) is formed in each of the third sub-pixels (SPX3). Then, a capping layer (CAP) is formed that covers the first light conversion layers (QDL1), the second light conversion layers (QDL2), and the light transmitting layers (TPL). Then, a second organic film (213) is formed on the capping layer (CAP).

[0327] Then, a first color filter (CF1) is formed on the second organic film (213) to overlap the first light conversion layers (QDL1) in the third direction (DR3), a second color filter (CF2) is formed to overlap the second light conversion layers (QDL2) in the third direction (DR3), and a third color filter (CF3) is formed to overlap the light transmitting layers (TPL) in the third direction (DR3). The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can all be formed in a region overlapping the partition wall (BM) in the third direction (DR3).

[0328] Then, a fifth organic film (214) is formed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3).

[0329] FIG. 36 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0330] Referring to FIG. 36, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0331] FIGS. 37 and 38 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0332] Referring to FIGS. 37 and 38, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0333] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2, descriptions of the first display device (10_2) and the second display device (10_3) are omitted.

[0334] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0335] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0336] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) via the connectors.

[0337] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0338] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for the user's left eye and a second eyepiece (1220) for the user's right eye. In FIGS. 37 and 38, the first eyepiece (1210) and the second eyepiece (1220) are separately arranged, but the embodiment of the present specification is not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0339] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0340] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1200) is implemented in a lightweight and compact form, the head-mounted display device (1000) may be equipped with a glasses frame as shown in FIG. 39 instead of the head-mounted band (800).

[0341] In addition, the head-mounted display device (1000) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0342] Fig. 39 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. Fig. 39 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0343] Referring to FIG. 39, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0344] In Fig. 39, it is exemplified that the virtual reality device (1000_3) is a glasses-type display device including glasses frame legs (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that illustrated in Fig. 39, and can be applied in various forms in various other electronic devices.

[0345] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye.

[0346] In FIG. 39, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0347] FIG. 40 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. FIG. 40 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0348] Referring to FIG. 40, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0349] FIG. 41 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0350] Referring to FIG. 41, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can view not only the image (IM) displayed on the display device (10_5), but also an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

[0351] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A pixel electrode and a common electrode spaced apart from each other on the substrate; A light emitting element is disposed on the pixel electrode and the common electrode, and includes a first contact electrode and a second contact electrode, The above light emitting element, A first semiconductor layer formed with a regular taper and doped with a first conductive dopant and an active layer, and a first element load; and A display device comprising a second semiconductor layer doped with a second conductive dopant and disposed on the first element load, and a second element load having a greater inclination angle than the first element load.

2. In paragraph 1, The first inclination angle formed by the inner surface of the first element load and one surface of the first semiconductor layer is within the range of 20° to 65°, A display device in which the second inclination angle formed by the outer surface of the second element load and the outer surface of the first element load is within a range of 110° to 155°.

3. In paragraph 1, A display device in which the first element load has a width that becomes narrower as it goes upward on the substrate, and the second element load has the same width at the upper and lower portions.

4. In paragraph 1, The second element load is a display device further including an undoped semiconductor on the second semiconductor layer.

5. In paragraph 4, The above undoped semiconductor is a display device having a light extraction pattern.

6. In paragraph 1, An organic layer disposed on the lower surface of the light-emitting element on the pixel electrode and the common electrode; and A display device further comprising a first connection electrode connecting the pixel electrode and the first contact electrode and a second connection electrode connecting the common electrode and the second contact electrode.

7. In paragraph 1, A display device further comprising a first connection electrode disposed between the first contact electrode and the pixel electrode, and a second connection electrode disposed between the second contact electrode and the common electrode.

8. In paragraph 1, The above light emitting element, A conductive layer disposed on the lower surface of the first semiconductor layer, and Further comprising a protective layer surrounding the conductive layer and the first semiconductor layer, the active layer and the second semiconductor layer, The first contact electrode is disposed on the protective layer and is connected to the conductive layer that is exposed and not covered by the protective layer, A display device in which the second contact electrode is disposed on a protective film and is disposed in a hole penetrating the conductive layer, the first semiconductor layer, and the active layer.

9. In paragraph 1, A partition wall arranged to surround the light emitting element; and A display device further comprising a reflective layer disposed on the side of the partition wall and on the bottom of the space formed by the partition wall, the reflective layer not in contact with the pixel electrode and the common electrode.

10. In paragraph 9, A display device further comprising a wavelength conversion layer disposed in a space formed by the above-mentioned partition wall.

11. Substrate; A pixel electrode disposed on the substrate; A light emitting element disposed on the pixel electrode and including a contact electrode; and including a common electrode disposed on the light emitting element, The above light emitting element, A first element load formed with a regular taper and including a first semiconductor layer doped with a first conductive dopant and an active layer; and A display device comprising a second semiconductor layer doped with a second conductive dopant and disposed on the first element load, and a second element load having a greater inclination angle than the first element load.

12. In paragraph 11, The first inclination angle formed by the inner surface of the first element load and one surface of the first semiconductor layer is within the range of 20° to 65°, A display device in which the second inclination angle formed by the outer surface of the second element load and the outer surface of the first element load is within a range of 110° to 155°.

13. In paragraph 11, A display device in which the first element load has a width that becomes narrower as it goes upward on the substrate, and the second element load has the same width at the upper and lower portions.

14. In paragraph 11, an organic layer disposed between the pixel electrode and the light-emitting element; and A display device further comprising a connecting electrode (BE) connecting the pixel electrode and the contact electrode.

15. In paragraph 11, A display device further comprising a connection electrode disposed between the contact electrode and the pixel electrode.

16. In paragraph 11, The above light emitting element, A conductive layer disposed on the lower surface of the first semiconductor layer; and Further comprising a protective film disposed on the side surfaces of the conductive layer and the side surfaces of the first semiconductor layer and the active layer, A display device in which the above contact electrode is disposed on the protective film and is connected to the conductive layer that is exposed and not covered by the protective film.

17. Step of forming a light-emitting element; and comprising a step of transferring the light-emitting element onto a first substrate, The step of forming the above light-emitting element is: A step of forming an undoped semiconductor, a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer on a second substrate; A step of forming a double mask on the first semiconductor layer and performing a first etching; A step of performing a second etching according to an etching method different from the first etching, but continuing the second etching until the inner surface of the first semiconductor layer and the active layer has a first inclination angle and the inclination angle formed by the outer surface of the second semiconductor layer and the outer surface of the first semiconductor layer and the active layer has a second inclination angle; A step of forming a groove that penetrates the conductive layer, the first semiconductor layer, and the active layer to expose the second semiconductor layer; A step of forming a protective layer surrounding the conductive layer, the first semiconductor layer, the active layer, the second semiconductor layer, and the third semiconductor layer; and A method for manufacturing a display device, comprising the step of forming a first contact electrode in contact with the conductive layer on the protective layer and a second contact electrode in contact with the second semiconductor layer exposed by the groove.

18. In paragraph 17, The first inclination angle is within the range of 20° to 65°, A method for manufacturing a display device, wherein the second inclination angle is within a range of 110° to 155°.

19. In paragraph 17, A method for manufacturing a display device, wherein the first etching is dry etching and the second etching is wet etching.

20. An electronic device including a display device that displays an image, The above display device, substrate; A pixel electrode and a common electrode spaced apart from each other on the substrate; A light emitting element is disposed on the pixel electrode and the common electrode, and includes a first contact electrode and a second contact electrode, The above light emitting element, A first semiconductor layer formed with a regular taper and doped with a first conductive dopant and an active layer, and a first element load; and An electronic device comprising a second semiconductor layer disposed on the first element load and doped with a second conductive dopant, and a second element load having a greater inclination angle than the first element load.

Images