Method for producing a semiconductor component, and semiconductor component

Abstract

The invention relates to a method for producing a gallium-nitride-based semiconductor component (100), in particular a transistor, comprising the following steps: providing a substrate and / or drain layer (11) and a layer which is applied to the substrate and / or drain layer (11), is doped in a first way and comprises a drift layer (12) that is doped in a first way; applying (210) a source layer (20), which comprises in particular magnesium, in a free region; forming a shielding region (13), which is doped in a second way, by means of diffusion from the source layer (20) such that, when viewed in a vertical direction, the shielding region is located at least partially at the level of a channel layer (14) and vertically below the free region, wherein, when viewed in the vertical direction, the channel layer is arranged between the source layer and the drift layer; and removing the source layer such that the free region can be used as a gate region. The invention also relates to a semiconductor component (100).

Description

[0001] Description

[0002] title

[0003] Method for manufacturing a semiconductor device and semiconductor device

[0004] The present invention relates to a method for manufacturing a semiconductor device and to such a semiconductor device, in particular a transistor, in particular a so-called JFET.

[0005] Background of the invention

[0006] Field-effect transistors, e.g., also known as field-effect transistors, are used in various fields.

[0007] JFETs (junction-FETs) are used. In this process, for example, a p-doped region acts as a gate and depletes the junction or JFET region.

[0008] Disclosure of the invention

[0009] According to the invention, methods for manufacturing a semiconductor device and a semiconductor device with the features of the independent claims are proposed. Advantageous embodiments are the subject of the dependent claims and the following description.

[0010] The invention relates to semiconductor devices, in particular field-effect transistors, especially JFETs, and their fabrication. Different types of doping are used in semiconductor materials, namely n-type and p-type doping, whereby different components can be doped differently. For the sake of clarity, field-effect transistors will be described below using a specific type of doping; n-type doping will be considered doping of the first kind, and p-type doping will be considered doping of the second kind. It should be understood, however, that n- and p-type doping can also be reversed, i.e., n-type doping could be doping of the second kind and p-type doping of the first kind.

[0011] Such a field-effect transistor typically comprises a substrate and / or drain layer, an n-doped drift layer, a channel layer (usually p-doped), and an n-doped source layer. The channel layer is arranged vertically between the source layer and the drift layer. The n-doped drift layer is deposited, for example, as an epitaxial layer on top of the substrate and / or drain layer.

[0012] Depending on the situation, the substrate and / or drain layer—at least in the final field-effect transistor—may comprise only the drain layer or both the substrate and drain layers. In the first case, however, the substrate and drain layers are still included in the manufacturing process, along with a buffer layer in between. This buffer layer is typically at least partially or completely removed in the final semiconductor device. This is because the buffer layer is insulating and would therefore prevent electrical contact between the n-doped drift layer and a drain connection. In the case of a homoepitaxial GaN substrate, the buffer layer can be omitted, and the conductive GaN substrate can remain in the device; thus, there are only substrate and drain layers. The channel layer can also be referred to as the JFET layer, JFET region, or junction layer, particularly in the case of so-called...JFETs (“Junction FET”) as will be explained in more detail later.

[0013] Furthermore, such a field-effect transistor has a p-doped shielding region (or several) that lies at least partially at the level of the channel layer in the vertical direction. This shielding region serves as a gate; therefore, it can also be referred to as a gate instead of a p-doped shielding region. The field-effect transistor then also has a (free) region that lies vertically above the shielding region; a gate electrode can be inserted into or applied to this region, thus making contact with the shielding region. The gate electrode is usually insulated from the source layer, for example, by means of an insulating layer. Furthermore, such a field-effect transistor has a source-contact material layer that borders the source layer. The gate electrode, however, is insulated from the source-contact material layer.Similarly, such a field-effect transistor has a drain-contact material layer that borders the substrate and / or drain layer. The source-contact material layer serves as the source electrode or connection, and conversely, the source-contact material layer serves as the source electrode or connection.

[0014] It should be noted that this type of field-effect transistor can have a large number of such free areas and gate electrodes. Between these free areas, so-called fins are formed, in which the aforementioned layers are located. This offers an advantage, as the vertical arrangement allows for many gate electrodes to be positioned side by side.

[0015] Such a field-effect transistor can be used alone or in combination with others, for example as a power switch. Preferred applications include, for example, in the electric powertrain of a vehicle, such as in a current converter (DC / DC converter, inverter), in chargers for electric vehicles, or in solar inverters.

[0016] Semiconductor devices such as field-effect transistors or transistors can generally be based on gallium nitride (GaN). This offers the possibility of realizing devices with lower on-resistance and simultaneously higher breakdown voltages than comparable devices based on, for example, silicon (Si) or silicon carbide (SiC). GaN transistors, or GaN-based transistors, can be used, for example, primarily as so-called high-electron mobility transistors (HEMTs), in which the current flows laterally at the substrate surface through a two-dimensional electron gas that forms the transistor channel. Such lateral devices can be fabricated by heteroepitaxy of the functional GaN layers on silicon wafers.However, for high breakdown voltage with low on-resistance per unit area, vertical components in which the current flows from the front of the substrate to the back of the substrate are more advantageous, both in terms of size and the electric field distribution inside the component.

[0017] For vertical devices, selectively p-doped regions or areas can be advantageous to reduce electric field peaks by means of p-shielding regions, thereby lowering the breakdown voltage of a device for the same epi-layer thickness. In addition to shielding implants, selective p-doping may be necessary for JFET regions, p-body regions, and p-contact regions.

[0018] The fabrication of selective p-GaN regions can be achieved via the implantation of magnesium or beryllium. Activation of these implantations is then typically carried out using temperatures in the range of 1250°C to 1400°C. This presents a technical challenge, particularly for epitaxy on foreign substrates such as silicon and sapphire, due to the differing CTE coefficients and the associated significant wafer deformation at high temperatures. With silicon and engineered poly-Al₂A₄ substrates, where silicon serves as the starting layer for epigrowth, additional defects can pose a problem, such as a temperature-sensitive area resulting from an exothermic reaction between gallium and silicon. In general, the GaN surface should be protected from degradation at temperatures above 850°C, making the activation of p-implantations technically complex even on native GaN substrates.

[0019] Against this background, it is now proposed to provide a p-doped shielding region in a gallium nitride-based semiconductor element. This shielding region is located at least partially at the level of the channel layer and vertically below the gate region. The free region lies laterally adjacent to the source layer. The shielding region is, or will be, diffused into the substrate. In particular, magnesium will diffuse into this substrate.

[0020] This enables the fabrication of GaN JFETs with selective p-type doping in the lateral direction (e.g., in the x-direction when the vertical direction is the z-direction). Particularly with epitaxy on foreign substrates, the activation of p-type implantations in the range of 1250°C to 1400°C, as mentioned, presents a technical challenge that complicates commercial manufacturing.

[0021] Magnesium diffusion is a method for creating p-doped regions limited in the x-direction or lateral direction within a transistor, specifically in a temperature range of 1100°C to 1300°C. This enables, in particular, the use of epitaxy on foreign substrates. However, diffusion can result in significant roughness at the interface between the magnesium film and gallium nitride, which can complicate its use, for example, in a transistor channel.

[0022] In contrast, p-doped regions produced by multiple epitaxial growth exhibit inhomogeneities in the dopant profile as well as on-wafer variation. This negatively impacts both the threshold voltage and the on-state performance. Additionally, their size is highly sensitive to the width of the JFET region. These disadvantages are eliminated by diffusion.

[0023] Not only does this enable the use of epitaxy on foreign substrates, but the control of the source layer through Mg diffusion also allows for high on-wafer homogeneity and dopant profile homogeneity (box profile) across the entire depth and width. This necessitates tighter manufacturing tolerances, thus enabling more aggressive designs (performance) and the fabrication of normally-off devices.

[0024] During production, the substrate and / or drain layer (possibly with buffer layer) and an n-doped layer applied to the substrate and / or drain layer, which includes an n-doped drift layer, are provided.

[0025] A source layer, primarily containing magnesium, is deposited in a free region. The p-doped shielding region (which, as mentioned, serves as a gate) is formed by diffusion from the source layer such that, in the vertical direction, the shielding region is at least partially at the level of a channel layer (depletion region) and vertically below the free region, with the channel layer being arranged vertically between the source layer and the drift layer. The source layer is subsequently removed, so that the free region can be used to connect a gate electrode to the shielding region. Thus, the gate and gate electrode can be configured such that the gate has a pn junction opposite the drift region or is separated by a pn junction.

[0026] This diffusion can occur at lower temperatures than those required for ion implantation, namely at temperatures between 1100 °C and 1300 °C and, in particular, with a relatively constant depth profile, also known as a box profile, with a concentration of, for example, 2e18 cm. A -3 to 3e18 cm A - 3.

[0027] Diffusion thus enables the fabrication of GaN-based semiconductor devices such as power transistors with p-shaped shielding or JFET regions, eliminating the need for an implantation process and its associated disadvantages due to high-temperature activation. This significantly simplifies the manufacturing process in some cases.

[0028] There are various embodiments for the fabrication process. In one embodiment, before the source layer is applied, the n-doped source layer and the free region are formed within the n-doped layer, such that the free region lies laterally adjacent to the source layer and borders the n-doped layer. After the source layer is applied, the channel layer is then formed, such that the channel layer is arranged vertically between the source layer and the drift layer, particularly by implantation. Furthermore, the p-doped shielding region is formed by diffusion from the source layer, such that the shielding region is located at least partially at the level of the channel layer and vertically below the free region.

[0029] In one embodiment, after the source layer is applied, the n-doped source layer is formed within the n-doped layer such that the free region lies laterally adjacent to the source layer and borders the n-doped layer. Furthermore, after the source layer is applied, the channel layer is formed such that the channel layer is arranged vertically between the source layer and the drift layer, particularly by means of implantation.

[0030] In one embodiment, before the source layer is applied, the n-doped source layer and the channel layer are formed within the n-doped layer such that the channel layer is arranged vertically between the source and drift layers. Laterally, the channel layer can be located between two shielding regions. Furthermore, before the source layer is applied, the free region is formed such that it lies laterally adjacent to the source layer and borders the n-doped layer, and, in particular, at least partially at the level of a portion of the n-doped layer in the vertical direction. After the source layer is applied, the p-doped shielding region is then formed by diffusion from the source layer, such that the shielding region lies at least partially at the level of the channel layer and vertically below the free region in the vertical direction.

[0031] In all variants, it can also be provided, for example, that a protective layer is formed on the source layer and the source layer, which is later removed. This serves to prevent magnesium from diffusing into the source layer and the underlying channel layer. Similarly, it can be provided, for example, that another protective layer is applied to the source layer before the source layer is applied. This additional protective layer prevents the source layer from being formed on top of the source layer and can be removed later.

[0032] In one embodiment, a nitrogen zone is formed before the application of the source layer, such that the nitrogen zone is located at least partially at the level of the channel layer and vertically below the free zone. The shielding zone is then formed within the nitrogen zone. This allows for more precise control of the thickness or, more generally, the dimensions of the shielding zone.

[0033] It is understood that further steps may be necessary for the final field-effect transistor, such as edge termination, contact path leads, and the like; standard methods can be used here.

[0034] Specific variants of the different embodiments and combinations thereof, as well as their various advantages, will be explained in more detail below with reference to the figures.

[0035] Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawing.

[0036] The invention is schematically illustrated in the drawing using exemplary embodiments and is described below with reference to the drawing.

[0037] Brief description of the drawings

[0038] Figure 1 schematically shows a field-effect transistor in one embodiment.

[0039] Figures 2 to 7 schematically show processes for manufacturing a field-effect transistor in various embodiments.

[0040] embodiment(s) of the invention

[0041] Figure 1 schematically depicts a field-effect transistor 100, or more generally, a semiconductor element, in one embodiment, particularly as a power transistor. The field-effect transistors are designed as so-called JFETs. Gallium nitride (GaN) is used as the semiconductor material on which the field-effect transistor is based. A cross-sectional view through the field-effect transistor is shown, with the z-direction being a vertical direction; the field-effect transistor has a greater extent in the xy-plane (the y-direction here lies into the plane of the drawing).

[0042] The following section describes the field-effect transistor with n-type doping (type I) and p-type doping (type II). As mentioned, the doping types can also be reversed.

[0043] The field-effect transistor 100 according to Figure 1 has an n-doped (or also lightly or (n-)-doped) drift layer 12, a channel layer (electron channel-forming layer) 14 – the JFET region – and an n-doped (or also highly or n+-doped) source layer 15. The channel layer 14 and the source layer 15 can be formed in particular in the (initially larger in the vertical direction) drift layer 12, as will be explained in more detail later.

[0044] The drift layer 12 is applied to the drain layer 11 of the field-effect transistor 100. The drain layer 11 can also include a substrate layer, e.g., a semiconductor substrate. However, the substrate layer and a buffer layer can be removed again during manufacturing if necessary.

[0045] The field-effect transistor 100 also has a drain contact material layer 10, e.g., a drain electrode, which here borders on or is connected to the drain layer 11 – but more generally, for example, also to a substrate layer. The field-effect transistor 100 also has a source contact material layer 16, e.g., a source electrode, which borders on or is connected to the source layer 16.

[0046] The field-effect transistor 100 also has a gate electrode 18, an insulating layer 17, a p-doped shielding region, and a gate 13. The insulating layer 17 isolates the gate electrode 18 from the source layer 15 and, if applicable, from the source contact material layer 16.

[0047] The gate electrode 18 and the insulating layer 17 are thus placed in a free area. It should be noted that two gate electrodes 18, insulating layers 17, and shielding areas 13 are shown here as examples, arranged in a mirror-symmetrical manner, with the source layer 15, the channel layer 14, and the source contact material layer 16 provided between them.

[0048] A conductive channel in channel layer 14 can be switched on or off by means of the gate electrode 18. When switched on, this channel allows current to flow from the source layer 15 to the drift layer 12. The voltage between the shielding region 13 and channel layer 14 influences the charge carrier density in channel layer 14.

[0049] Figures 2 to 7 schematically illustrate processes for manufacturing a field-effect transistor in various embodiments. Identical elements, components, or layers are designated with the same reference numerals as in Figure 1.

[0050] Figure 2 shows an embodiment of a manufacturing process. First, a substrate and / or drain layer and an n-doped layer applied to the substrate and / or drain layer are provided. The substrate and / or drain layer comprises a substrate layer 1, an n-doped drain layer 11, and a buffer layer 2 between them. The n-doped layer comprises the n-doped drift layer 12. It should be noted that, generally, for example, a large or thick n-doped drift layer 12 can be applied to the drain layer 11.

[0051] The buffer layer 2 is at least partially or completely removed for the final transistor; it is insulating and would prevent electrical contact with the drain layer 11 via a drain contact. However, in the case of epitaxial growth on a GaN substrate 1, the buffer layer 2 can be omitted, and the conductive GaN substrate 1 can remain in the transistor. For insulating foreign substrates 1, i.e., not GaN, the buffer layer 2 and the substrate or substrate layer 1 must be at least partially removed. In the case shown, in step 200, the source layer 15 is formed in this layer or the drift layer 12. Additionally, a mask, or more generally, another protective layer 23, is applied to the source layer 15. This creates a free region 202 laterally adjacent to the source layer 15, bordering the drift layer 12. This can be achieved, for example, by means of suitable structuring.As an example, a free area is created on both sides of the source layer 15.

[0052] In step 210, a magnesium-containing swelling layer 20 is applied in the open area. This swelling layer can consist of, for example, magnesium, an oxygen-free and silicon-free magnesium compound, or a magnesium compound with a thickness of 1 × 10⁻⁸ cm. -3 up to 1e22 cm -3 A doped PVD or CVD layer can be used. For example, an Al layer is preferred. x Gai. x An N-compound from CVD deposition, or an AIN-compound from PVD deposition. Similarly, other methods for moderating the amount of magnesium can be used to reduce the surface roughness of the subsequent p-doped shielding region 13.

[0053] In step 220, for example, the mask or further protective layer 23 is selectively removed using wet chemical methods. Additionally, an n-type implantation of the channel layer or the JFET region 14 is performed as an example. Here, the magnesium-containing swelling layer 20 is used as a mask. This ensures that the n-type implantation in the channel layer 14 of silicon or oxygen is self-aligned with the subsequent p-type region, and no misalignment occurs.

[0054] In step 230, a protective layer or cover layer 24 is formed on the source layer 15 and, in particular, also on the source layer 20. Here, the GaN surface of the source layer 15 can be described as being encapsulated with a cover layer.

[0055] In step 240, magnesium then diffuses into the drift layer 12 at a temperature between 1100°C and 1300°C. This creates the p-doped shielding regions 13. Simultaneously, the n-type dopants silicon or oxygen in the channel layer 14 are activated. With a typical n-type doping strength in the channel layer 14 of 1 e^18 cm, the resulting n-type doping concentration is approximately 1 e^18 cm. -3 The n-type channel layer 14 can be transformed at its edge into a p-region, a shielding region 13, by lateral diffusion. Depending on the doping concentration of the channel layer 14, the lateral overimplantation length from the p-type into the channel layer 14 is at most half the length of the vertical diffusion direction of a p-doped shielding region 13. The source layer 15, for example, has an n-type dopant concentration with Si of >3 e^19 cm³. -3 so that they are affected by magnesium diffusion with <1e19 cm -3 is not converted into a p-region at the edge.

[0056] In step 250, the encapsulation or protective layer 24 and the magnesium-containing swelling layer 20 are removed. After diffusion, the GaN surface of the shielding area 13 can be prepared for contact formation. This can include, for example, reducing the surface roughness by means of wet chemical treatment or atomic layer etching (ALE).

[0057] In step 260, the electrical component undergoes final processing. This includes, for example, adding the gate 18 or gate electrode, the source contact material or source electrode 16, and the insulating layer 17. Furthermore, the substrate layer 1 and the buffer layer 2, which may be an AIGaN buffer layer, are removed. Then, a drain contact material layer or drain electrode 10 is applied, which contacts the drain or n+ layer 11. Removing the substrate and buffer layers is necessary, for example, if the substrate layer is a foreign substrate.

[0058] Advantages of this variant include, for example, the self-aligned implantation of canal layer 14 to the diffused shielding area 13, which allows for precise adjustment of the doping. The resulting precise local demarcation between shielding area 13 and canal layer 14 enables higher doping in both shielding area 13 and canal layer 14, and thus a lower on-resistance in canal layer 14.

[0059] Magnesium diffusion also results in a highly reproducible Mg concentration within a box profile. In particular, lateral magnesium diffusion, and thus the width of the channel layer 14, can be controlled very precisely by diffusion. Similar to repeated epitaxial growth, homogeneity across the wafer is easily controlled. This is a particular advantage compared to epitaxially grown p-GaN, where variations of up to 30% across the wafer are common. The lower temperature budget of Mg diffusion compared to Mg implantation and the required activation allows the use of cost-effective foreign substrates compared to native GaN substrates. Magnesium diffusion improves the p-type contact formation between the gate electrode 18 and the shielding area 13.

[0060] Figure 3 shows an embodiment of a manufacturing process. In step 300, a substrate and / or drain layer and an n-doped layer applied to the substrate and / or drain layer are provided. The substrate and / or drain layer comprises a substrate layer 1, an n-doped drain layer 11, and a buffer layer 2 between them. The n-doped layer comprises the n-doped drift layer 12. It should be noted that, generally, for example, a large or thick n-doped drift layer 12 can be applied to the drain layer 11.

[0061] Unlike in Figure 2, the drift layer 12 (a GaN layer) is not structured. Instead, in step 310, the magnesium-containing swelling layer 20 is first applied as in step 210 according to Figure 2, specifically in free areas 302. This is followed by structuring.

[0062] In step 320, an n-type implantation of the channel layer 14 with oxygen or silicon is performed, as well as a combined n-type implantation of the source layer 15 with silicon, preferably with a doping concentration >3e19 cm -3 In this procedure, the magnesium-containing swelling layer 20 is used as a mask. This ensures that the n-type implantation in the silicon or oxygen canal layer 14 is self-aligned with the subsequent p-type region, and no adjustment offset occurs.

[0063] In step 330, a protective layer or cover layer 24 is formed on the source layer 15 and, in particular, also on the source layer 20. Here, the GaN surface of the source layer 15 can be described as being encapsulated with a cover layer.

[0064] In step 340, magnesium then diffuses into the drift layer 12 at a temperature between 1100°C and 1300°C. This creates the p-doped shielding regions 13. Simultaneously, the n-type dopants silicon or oxygen in the channel layer 14 are activated. With a typical n-type doping strength in the channel layer 14 of 1 e^18 cm, the resulting n-type doping concentration is approximately 1 e^18 cm. -3 The n-type channel layer 14 can be transformed at its edge into a p-region, a shielding region 13, by lateral diffusion. Depending on the doping concentration of the channel layer 14, the lateral overimplantation length from the p-type into the channel layer 14 is at most half the length of the vertical diffusion direction of a p-doped shielding region 13. The source layer 15, for example, has an n-type dopant concentration with Si of >3 e^19 cm³. -3 so that they are affected by magnesium diffusion with <1e19 cm -3 is not converted into a p-region at the edge.

[0065] In step 350, the encapsulation or protective layer 24 and the magnesium-containing swelling layer 20 are removed. After diffusion, the GaN surface of the shielding area 13 can be prepared for contact formation. This can include, for example, reducing the surface roughness by means of wet chemical treatment or atomic layer etching (ALE).

[0066] In step 360, as in step 260 according to Figure 2, the electrical component undergoes final processing. This includes, for example, the addition of the gate 18 or gate electrode, the source contact material or source electrode 16, and the insulating layer 17. Furthermore, the substrate layer 1 and the buffer layer 2, which may be an AIGaN buffer layer, are removed. Then, a drain contact material layer or drain electrode 10 is applied, which contacts the source layer 11. Removing the substrate and buffer layers is necessary, for example, if the substrate layer is a foreign substrate. Advantages of this approach include, for example, self-alignment of the channel layer 14 to the diffused shielding area 13, which allows for precise adjustment of the doping.The resulting precise local demarcation between shielding area 13 and channel layer 14 enables a higher doping concentration in shielding area 13 and channel layer 14, and thus a lower on-resistance in channel layer 14.

[0067] The GaN surface of the drift layer 12 does not need to be etched, allowing the p-type contact formation between the gate electrode 18 and the shielding area 13 to occur on an unetched GaN surface, significantly improving the contact resistance. Magnesium diffusion also results in a highly reproducible Mg concentration within a box profile. The lower temperature budget required for Mg diffusion compared to Mg implantation and the necessary activation allows the use of cost-effective foreign substrates compared to native GaN substrates. Magnesium diffusion further enhances the p-type contact formation between the gate electrode 18 and the shielding area 13.

[0068] Figure 4 shows an embodiment of a manufacturing process. First, a substrate and / or drain layer and an n-doped layer applied to the substrate and / or drain layer are provided. The substrate and / or drain layer comprises a substrate layer 1, an n-doped drain layer 11, and a buffer layer 2 between them. The n-doped layer comprises the n-doped drift layer 12. It should be noted that, generally, for example, a large or thick n-doped drift layer 12 can be applied to the drain layer 11.

[0069] In the case shown, in step 400, the source layer 15 is formed in this layer, or rather, in the drift layer 12. Additionally, a mask, or more generally, another protective layer 23, is applied to the source layer 15. A free area 402 is formed laterally next to the source layer 15, bordering the drift layer 12. This can be achieved, for example, by means of suitable structuring. As an example, a free area is formed on both sides of the source layer 15. Step 400 thus corresponds to step 200 according to Figure 2. In step 410, a nitrogen region 21 is formed such that the nitrogen region 21 is located at least partially at the level of the channel layer 14 and vertically below the free area 402. This can be achieved by means of implantation. This nitrogen region 21, or this implantation, controls the diffusion depth and the diffusion profile of the subsequently diffused shielding region 13.

[0070] The subsequent steps 420 to 470 then correspond to steps 210 to 260 according to Figure 2. In step 450, the magnesium is diffused into the drift layer 12, specifically into the nitrogen region 21 formed in the drift layer 12. This allows for improved control of the diffusion depth in the vertical and lateral directions due to the prior nitrogen implantation.

[0071] An additional advantage compared to the variant according to Figure 2 is therefore the sharper definition of the doping profiles in the shielding area 13 by more precise delimitation of the channel layer or the JFET area 14 to reduce the on-resistance.

[0072] Figure 5 shows an embodiment of a manufacturing process. In step 300, a substrate and / or drain layer and an n-doped layer applied to the substrate and / or drain layer are provided. The substrate and / or drain layer comprises a substrate layer 1, an n-doped drain layer 11, and a buffer layer 2 between them. The n-doped layer comprises the n-doped drift layer 12. It should be noted that, generally, for example, a large or thick n-doped drift layer 12 can be applied to the drain layer 11.

[0073] Furthermore, in step 500, a mask, or more generally, another protective layer 23, is applied to the drift layer 12. A free area 502 is formed laterally next to the mask 23, bordering the drift layer 12. This can be achieved, for example, by means of suitable structuring. As an example, a free area is formed on both sides of the source layer 15. Step 500 thus corresponds to step 300 according to Figure 3, except that the mask 23 is additionally applied. This mask is intended for subsequent nitrogen implantation.

[0074] In step 510, a nitrogen zone 21 is formed such that it is located at least partially at the level of the channel layer 14 and vertically below the free zone 502. This can be achieved by means of implantation. This nitrogen zone 21, or rather this implantation, controls the diffusion depth and the diffusion profile of the subsequently diffused shielding zone 13.

[0075] Steps 520 to 570 then correspond to steps 310 to 360 as shown in Figure 3. In step 530, however, the mask 23 is removed again before the implantation of the canal layer 14 takes place. In step 450, the magnesium is diffused into the drift layer 12, specifically into the nitrogen region 21 formed in the drift layer 12. This allows for improved control of the diffusion depth in both vertical and lateral directions due to the prior nitrogen implantation.

[0076] An additional advantage compared to the variant according to Figure 3 is therefore the sharper definition of the doping profiles in the shielding area 13 by more precise delimitation of the channel layer or the JFET area 14 to reduce the on-resistance.

[0077] Figure 6 shows an embodiment of a manufacturing process. First, in step 600, a substrate and / or drain layer and an n-doped layer applied to the substrate and / or drain layer are provided. The substrate and / or drain layer comprises a substrate layer 1, an n-doped drain layer 11, and a buffer layer 2 between them. The n-doped layer comprises the n-doped drift layer 12.

[0078] It should be mentioned that, generally, for example, a large or thick n-doped drift layer 12 is applied to the drain layer 11, with further layers then being formed in the thick drain layer 11, namely, for example, an epi-layer 12a, then a second epi-layer 12b, and then the source layer 15.

[0079] In the case shown, a mask, or more generally, an additional protective layer 23, is applied to the source layer 15. This creates a free area 602 laterally adjacent to the source layer 15, which—in the current phase—borders the source layer 15. This can be achieved, for example, by means of suitable structuring. As an example, a free area is created on both sides of the mask 23.

[0080] In step 610, the source layer 15 and the epi layer 12b are then structured using mask 23. The free area is thus deepened; in the current phase, it borders the epi layer 12a.

[0081] Optionally, in this step, the mask 23 can be trimmed isotropically using a dry chemical oxygen plasma process after etching.

[0082] This allows the n-type implantation in step 640 to be restricted at the edge of the epi-layers 12b and 12a, in order to make the separation of the JFET region from layers 14 and 14b to the shielding region 13 in the area of ​​p-over-implantation even more abrupt laterally. A lateral transition between the n- and p-type regions with full doping strength over a few nm can further improve the device performance.

[0083] In step 620, a magnesium-containing swelling layer 20 is applied, both in the open area and, in particular, on the further protective layer 23. The swelling layer can consist of, for example, magnesium, an oxygen-free and silicon-free magnesium compound, or a magnesium compound with a density of 1 × 10⁻⁸ cm. -3 up to 1e22 cm -3 A doped PVD or CVD layer can be used. For example, an Al layer is preferred. x Gai. xAn N-compound from CVD deposition, or an AIN compound from PVD deposition. Similarly, other methods can be used to moderate the amount of magnesium in order to reduce the surface roughness of the subsequent p-doped shielding region 13. In step 630, the mask 23 is selectively removed to reveal the magnesium-containing source layer 20.

[0084] In step 640, a self-aligned n-type implantation, masked by the source layer 20, takes place into the epi-layers 12a and 12b, e.g., using oxygen or silicon. Oxygen is preferred. Optionally, silicon can also be implanted into the source layer 15. After this step, the source layer 15, resulting from epi-growth and / or implantation, has a dopant concentration of preferably >3 e^19 cm³. -3 .

[0085] In step 650, a protective layer or cover layer 24 is formed on the source layer 15 and, in particular, also on the source layer 20. Here, the GaN surface of the source layer 15 can be described as being encapsulated with a cover layer.

[0086] In step 660, magnesium then diffuses into the drift layer 12 at a temperature between 1100°C and 1300°C. This creates the p-doped shielding regions 13. Simultaneously, the n-type dopants silicon or oxygen in the channel layer 14 are activated. With a typical n-type doping strength in the channel layer 14 of 1 e^18 cm, the resulting n-type doping concentration is approximately 1 e^18 cm. -3The n-type channel layer 14 can be transformed at its edge into a p-region, a shielding region 13, by lateral diffusion. Depending on the doping concentration of the channel layer 14, the lateral overimplantation length from the p-type into the channel layer 14 is at most half the length of the vertical diffusion direction of a p-doped shielding region 13. The source layer 15, for example, has an n-type dopant concentration with Si of >3 e^19 cm³. -3 so that they are affected by magnesium diffusion with <1e19 cm -3 is not converted into a p-region at the edge.

[0087] In step 670, the encapsulation or protective layer 24 and the magnesium-containing source layer 20 are removed. After diffusion, the GaN surface of the shielding area 13 can be prepared for contact formation. This can include, for example, reducing the surface roughness by means of wet chemical treatment or atomic layer etching (ALE). In step 680, as in step 260 according to Figure 2, the electrical component undergoes final processing. This includes, for example, adding the gate electrode 18, the source contact material or source electrode 16, and the insulating layer 17. Furthermore, the substrate layer 1 and the buffer layer 2, which is, for example, an Al-GaN buffer layer, are removed. Then, a drain contact material layer or drain electrode 10 is applied, which contacts the source layer 11. Removing the substrate and buffer layers is necessary, for example, if the substrate layer is a foreign substrate.

[0088] Advantages of this variant, particularly compared to the variant shown in Figure 2, include a longer junction or JFET region encompassing channel layers 14 and 14b (ultimately, both 14 and 14b are channel layers, with 14b being used here to illustrate the difference from, for example, Figure 2). This allows for better channel control with regard to setting the threshold voltage, Vth. In contrast to the variant shown in Figure 2, the junction or JFET region is extended by precisely the area of ​​region 14b. This allows Vth to be increased in the device. An n-type implantation can be omitted in this variant to save manufacturing effort, and the epi concentrations in layers 15, 12a, and 12b can be selected accordingly.

[0089] Figure 7 shows an embodiment of a manufacturing process. First, in step 700, a substrate and / or drain layer and an n-doped layer applied to the substrate and / or drain layer are provided. The substrate and / or drain layer comprises a substrate layer 1, an n-doped drain layer 11, and a buffer layer 2 between them. The n-doped layer comprises the n-doped drift layer 12.

[0090] It should be mentioned that, generally, for example, a large or thick n-doped drift layer 12 is applied to the drain layer 11, with further layers then formed within the thick drain layer 11, namely, for example, an epi-layer 12a, then a second epi-layer 12b, and finally the source layer 15. In the case shown, a mask, or more generally, another protective layer 23, is also applied to the source layer 15. A free region 702 is formed laterally next to the source layer 15, which—in the current phase—adjacent to the source layer 15. This can be achieved, for example, by means of suitable structuring. As an example, a free region is formed on both sides of the mask 23.

[0091] Step 710 corresponds to step 610 according to Figure 6, but additionally a nitrogen zone 21 is formed such that the nitrogen zone 21 is located at least partially at the level of the channel layer 14 and vertically below the free zone 402 in the vertical direction. This can be achieved by means of implantation. This nitrogen zone 21, or this implantation, controls the diffusion depth and the diffusion profile of the subsequently diffused shielding zone 13.

[0092] The subsequent steps 720 to 780 then correspond to steps 620 to 680 according to Figure 6. In step 760, the magnesium is diffused into the drift layer 12, specifically into the nitrogen region 21 formed in the drift layer 12. This allows for improved control of the diffusion depth in the vertical and lateral directions due to the prior nitrogen implantation.

[0093] An additional advantage compared to the variant shown in Figure 4 is that the longer junction or JFET region encompassing 14 and 14b allows for better channel control with regard to setting the threshold voltage, Vth. In contrast to the variant shown in Figure 2, the junction or JFET region is extended by precisely the region 14b. This allows Vth to be increased in the device.

[0094] The proposed diffusion of magnesium can be particularly well observed in a product, since diffusion results in a constant magnesium concentration profile down to a certain depth, whereas during implantation, the magnesium is implanted in several so-called shots, with each shot leaving an approximately Gaussian profile, which thus differs from the constant profile after diffusion.

Claims

Claims 1. Method for manufacturing a semiconductor device (100), in particular a transistor based on gallium nitride, comprising the following steps: Providing a substrate and / or drain layer (11) and a first-type doped layer applied to the substrate and / or drain layer (11), comprising a first-type doped drift layer (12), - Applying (210) a swelling layer (20) which in particular contains magnesium, in a free area (202), - Forming (240) a second type doped shielding region (13) by diffusion from the source layer (20) such that the shielding region is located at least partially at the level of a channel layer (14) and vertically below the free region (202) in the vertical direction, wherein the channel layer is arranged vertically between the source layer and the drift layer, and Removing (250) the source layer so that the free area can be used to contact a gate electrode (18) to the shielding area (13).

2. Method according to claim 1, further comprising, prior to applying the source layer: forming (410) a nitrogen region such that the nitrogen region is at least partially at the level of the channel layer and vertically below the free region in the vertical direction, wherein the shielding region is formed in the nitrogen region.

3. Method according to claim 1 or 2, further comprising, prior to application of the source layer: - Forming the first-type doped source layer (15) in the first-type doped layer, and the free region, such that the free region in a lateral direction next to the source layer (15) and bordering the first type doped layer, further encompassing, after application of the source layer: - Forming the canal layer such that the canal layer is arranged vertically between the source layer and the drift layer, in particular by means of implantation, - Formation of the second type doped shielding region by means of diffusion from the source layer, such that the shielding region is at least partially at the level of the channel layer and vertically below the free region in the vertical direction.

4. Method according to claim 1 or 2, further comprising, after application of the source layer: - Forming (200) the first-type doped source layer (15) in the first-type doped layer such that the free region (202) lies in a lateral direction next to the source layer (15) and borders the first-type doped layer (12), - Forming the canal layer such that the canal layer is arranged in a vertical direction between the source layer and the drift layer, in particular by means of implantation.

5. Method according to claim 1 or 2, further comprising, prior to application of the source layer: - Forming the first-type doped source layer (15) and the channel layer in the first-type doped layer, such that the channel layer is arranged vertically between the source layer and the drift layer, - Forming the free region such that the free region lies in the lateral direction next to the source layer (15) and borders the first-type doped layer, and in particular lies at least partially at the level of a part of the first-type doped layer in the vertical direction, further comprising, after application of the source layer: - Formation of the second-type doped shielding region by means of diffusion from the source layer, such that the shielding region is vertically The direction is at least partially at the level of the canal layer and vertically below the free area.

6. Method according to any of the preceding claims, further comprising, prior to application of the source layer: - Forming a protective layer (24) on the source layer and the source layer continuing to encompass, after forming the second type doped shielding area: Removing the protective layer 7. Method according to any of the preceding claims, further comprising, prior to application of the source layer: - Forming a further protective layer (23) on the source layer, continuing to cover, after application of the source layer: Removing the additional protective layer 8. A method according to any of the foregoing claims, further comprising: - Attaching a gate electrode (18) in the free area so that the gate electrode contacts the shielding area (13) and is insulated in particular from the drift layer (15).

9. Semiconductor device (100), in particular a transistor based on gallium nitride, the semiconductor device comprising: a substrate and / or drain layer (11), a first-type doped drift layer (12), a channel layer (14), and a first-type doped source layer (15), wherein the channel layer is arranged vertically between the source layer and the drift layer, the semiconductor device further comprising a free region located laterally next to the source layer (15), which is provided for contacting a gate electrode (18) to the shielding region (13), wherein the semiconductor device further comprises a second-type doped shielding region (13) located at least partially at the level of the channel layer in the vertical direction and vertically below the free area, wherein the shielding region is diffused in.

10. Semiconductor device according to claim 9, wherein the shielding area (13) is formed at least partially by diffused magnesium.

11. Semiconductor device according to claim 9 or 10, further comprising a drain contact material layer (10) adjacent to the substrate and / or drain layer (11).

12. Semiconductor device according to one of claims 9 to 11, which is designed according to a is produced according to one of the preceding claims.

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