Semiconductor optical element and semiconductor optical device

Abstract

The present invention is a semiconductor optical element (EL) comprising: a substrate (1); a laminate (2) in which a semiconductor layer (10), an active layer (20), and a semiconductor layer (30) are laminated in this order from the substrate (1) side; an exit surface (PL1) which is provided to one side surface of the laminate (2); a reflection surface (PL2) which is provided at another side surface of the laminate (2) so as to be opposite from the exit surface (PL1); a current control layer (3) which is provided on the laminate (2) and which renders at least the exit surface (PL1) side of the laminate (2) a current non-injection region (R1) that a current is not injected into; and a diffraction grating (GR) which is formed on the semiconductor layer (10) or the semiconductor layer (30) between the exit surface (PL1) and the reflection surface (PL2), wherein the diffraction grating (GR) is disposed in the current non-injection region (R1) in a plan view.

Description

Semiconductor optical element and semiconductor optical device

[0001] This application claims priority from Japanese Patent Application No. 2024-118779, filed on July 24, 2024, the contents of which are incorporated herein by reference.

[0002] A broad-area semiconductor laser (BA-LD: Broad-Area Laser Diode) is a semiconductor laser in which the width of the light-emitting region is expanded laterally, and is used as a variety of light sources that require high output. For example, broad-area semiconductor lasers are used as excitation light sources for solid-state lasers, fiber lasers, etc. It is desirable that the fluctuation of the oscillation wavelength of such broad-area semiconductor lasers used as excitation light sources be suppressed to 2 to 3 nm or less in order to improve or stabilize the excitation efficiency.

[0003] One method for controlling fluctuations in the oscillation wavelength is to use a periodic diffraction grating. Examples of periodic diffraction gratings include distributed Bragg reflectors (DBRs) and distributed feedback (DFBs). Much of the research into semiconductor lasers using such periodic diffraction gratings has been focused on semiconductor lasers for communication applications with relatively low output power, but in recent years, research has also begun to be conducted on high-output broad-area semiconductor lasers. Patent Document 1 listed below discloses a DBR laser that can improve beam quality during high-output operation.

[0004] It should be noted that high-power broad-area semiconductor lasers do not necessarily require strict wavelength control, unlike semiconductor lasers for communication applications. High-power broad-area semiconductor lasers allow multiple longitudinal modes within the range of the central wavelength, but differ from semiconductor lasers for communication applications in that the longitudinal modes are defined over a wide dynamic range from low to high power, and high reliability is required even at high power.

[0005] U.S. Patent No. 8,675,705

[0006] In recent years, semiconductor lasers for use as pump light sources have been required to have even higher output power. In the DBR laser disclosed in the above-mentioned Patent Document 1, a periodic diffraction grating is provided within the current injection stripe (i.e., the gain region). Such DBR lasers have a problem in that the crystal quality within the vertical structure is degraded, and the reliability of the semiconductor laser is reduced, compared to semiconductor lasers in which a periodic diffraction grating is not provided within the current injection stripe.

[0007] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor optical element and a semiconductor optical device that can improve reliability while suppressing fluctuations in oscillation wavelength.

[0008] In order to solve the above-mentioned problems, a first aspect of the present invention is a semiconductor optical element (EL) comprising: a substrate (1); a stack (2) in which, from the substrate side, a first conductivity type semiconductor layer (10), an active layer (20), and a second conductivity type semiconductor layer (30) are stacked; an emission surface (PL1) provided on one side of the stack; a reflection surface (PL2) provided on the other side of the stack so as to face the emission surface; a current control layer (3) provided on the stack and making at least the emission surface side of the stack a current non-injection region (R1) into which no current is injected; and a diffraction grating (GR) formed in the first conductivity type semiconductor layer or the second conductivity type semiconductor layer between the emission surface and the reflection surface, wherein the diffraction grating is arranged in the current non-injection region when viewed in a plan view.

[0009] In the semiconductor optical device according to the first aspect of the present invention, the diffraction grating formed in the first conductivity type semiconductor layer or the second conductivity type semiconductor layer of the laminate is arranged in a current non-injection region, which is a region into which no current is injected by a current limiting layer provided on the laminate, when viewed in a plan view, so that it is possible to improve reliability while suppressing fluctuations in the oscillation wavelength.

[0010] A second aspect of the present invention is a semiconductor optical device according to the first aspect of the present invention, wherein the laminate has a window region (W) formed therein that reduces the absorption rate of light generated in the active layer, the window region being located within the non-current injection region when viewed in a plan view, and the diffraction grating being located within the window region when viewed in a plan view.

[0011] A third aspect of the present invention is a semiconductor optical device according to the first or second aspect of the present invention, wherein the current control layer defines a region of the laminate adjacent to the non-current injection region as a current injection region (R0) into which current is injected, and the width of the current injection region in a second direction (Y direction) intersecting a first direction (X direction) in which the emission surface and the reflection surface face each other, when viewed in a plan view, becomes narrower as the width approaches the emission surface.

[0012] A fourth aspect of the present invention is the semiconductor optical device according to the third aspect of the present invention, wherein the width of the current injection region in the second direction is gradually narrowed toward the emission surface.

[0013] A fifth aspect of the present invention is a semiconductor optical device according to the third or fourth aspect of the present invention, wherein the non-current injection region is arranged to sandwich the current injection region, which has a narrowed width, in the second direction, and the diffraction grating is arranged to sandwich the current injection region, which has a narrowed width, in the second direction.

[0014] In a sixth aspect of the present invention, the coupling coefficient of the diffraction grating is κ [cm -1 ], and the length of the diffraction grating is L [cm -1 ], the semiconductor optical device according to any one of the first to fifth aspects of the present invention has κL in the range of 0.14 to 0.41.

[0015] A seventh aspect of the present invention is a semiconductor optical device according to the second aspect of the present invention, wherein the current control layer has a current non-injection region on the emitting surface side of the laminate as well as on the reflecting surface side of the laminate, and the window region is arranged within the current non-injection region on the emitting surface side of the laminate and within the current non-injection region on the reflecting surface side when viewed in a plan view.

[0016] An eighth aspect of the present invention is a semiconductor optical device (DV) comprising a thermally conductive submount (100) and a semiconductor optical element according to any one of the first to seventh aspects mounted on the submount via a thermally conductive metal bonding layer.

[0017] According to the present invention, it is possible to improve reliability while suppressing fluctuations in the oscillation wavelength.

[0018] FIG. 1 is a cross-sectional view showing a configuration of a main part of a semiconductor optical element according to a first embodiment of the present invention. FIG. 2 is a planar perspective view of the semiconductor optical element according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a specific configuration example of the semiconductor optical element according to the first embodiment of the present invention. FIG. 4 is a view for explaining a diffraction grating provided in the semiconductor optical element according to the first embodiment of the present invention. FIG. 5 is a view showing the relationship between the length of the diffraction grating and the coupling coefficient in the first embodiment of the present invention. FIG. 6 is a planar perspective view of a semiconductor optical element according to a second embodiment of the present invention. FIG. 7 is a planar perspective view of a semiconductor optical element according to a third embodiment of the present invention. FIG. 8 is a planar perspective view showing a modified example of the semiconductor optical element according to the third embodiment of the present invention. FIG. 9 is a planar perspective view showing a modified example of the semiconductor optical element according to the third embodiment of the present invention. FIG. 10 is a perspective view showing a modified example of the semiconductor optical element according to the third embodiment of the present invention.

[0019] Hereinafter, semiconductor optical elements and semiconductor optical devices according to embodiments of the present invention will be described in detail with reference to the drawings. In the drawings referred to below, the dimensions of each component are appropriately changed as necessary to facilitate understanding. In the following description, the positional relationships of each component will be described with reference to the XYZ Cartesian coordinate system (the origin position will be changed as necessary) shown in each drawing.

[0020] [First Embodiment] Fig. 1 is a cross-sectional view showing the main configuration of a semiconductor optical device according to a first embodiment of the present invention. Fig. 2 is a plan perspective view of the semiconductor optical device according to the first embodiment of the present invention. As shown in Fig. 1, the semiconductor optical device EL of this embodiment includes a substrate 1, a laminate 2 provided on the substrate 1, and a current control layer 3 provided on the laminate 2. In the XYZ orthogonal coordinate system in Fig. 1, the Z axis represents the stacking direction of the laminate 2, the X axis represents the emission direction of light emitted from the semiconductor optical device EL, and the Y axis represents a direction parallel to the interface between the substrate 1 and the laminate 2 and perpendicular to the X axis.

[0021] The substrate 1 is a semiconductor substrate of a first conductivity type. The stacked body 2 is formed by stacking, in this order from the substrate 1 side, a semiconductor layer 10 (first conductivity type semiconductor layer) which is a semiconductor layer of a first conductivity type, an active layer 20, and a semiconductor layer 30 (second conductivity type semiconductor layer) which is a semiconductor layer of a second conductivity type. One side surface (the surface on the +X side) of the stacked body 2 is an emission surface PL1 from which light generated in the active layer 20 is emitted, and the other side surface (the surface on the −X side) of the stacked body 2 is a reflection surface PL2 which reflects the light generated in the active layer 20.

[0022] As shown in Fig. 1, a diffraction grating GR constituting a DBR is formed in the semiconductor layer 10 of the laminate 2. The diffraction grating GR is formed along the X direction near the active layer 20 side on the +X side (the side of the output surface PL1) of the semiconductor layer 10, and forms a resonator together with the reflecting surface PL2. The length of the diffraction grating GR in the X direction is set taking into consideration the output of the semiconductor optical element EL, etc. Details of the length of the diffraction grating GR in the X direction will be described later. As shown in Fig. 2, the length of the diffraction grating GR in the Y direction is approximately the same as the length of the semiconductor optical element EL in the Y direction.

[0023] The diffraction grating GR is disposed in a non-current injection region R1 (details will be described later) when viewed in a plan view (when the semiconductor optical element EL is viewed from the +Z side). This is to improve the reliability of the semiconductor optical element EL compared to when the diffraction grating GR is formed in a region where current is injected. The diffraction grating GR may be formed in the semiconductor layer 30 instead of the semiconductor layer 10 of the stack 2.

[0024] Although details will be described later, it is preferable that the stack 2 has a window region W (see FIG. 3 ) formed therein that reduces the absorption rate of light generated in the active layer 20. The window region W is a region designed to have a larger energy band gap than regions other than the window region W (non-window regions). The window region W is, for example, arranged within the non-current injection region R1 when viewed in a planar view. When the window region W is arranged in this manner, it is preferable that the diffraction grating GR is arranged within the window region W when viewed in a planar view. The shape of the window region W when viewed in a planar view can be any shape. For example, the shape of the window region W when viewed in a planar view may be a shape that corresponds to the shape of the non-current injection region R1 when viewed in a planar view.

[0025] The current control layer 3 controls the current injected into the laminate 2. Specifically, the current control layer 3 controls the current so that a current is injected into the −X side (reflection surface PL2 side) of the laminate 2 and no current is injected into the +X side (exit surface PL1 side) of the laminate 2. In other words, the current control layer 3 defines the −X side (reflection surface PL2 side) of the laminate 2 as a current injection region R0 into which a current is injected, and defines the +X side (exit surface PL1 side) of the laminate 2 as a current non-injection region R1 into which no current is injected. By providing such a current control layer 3, as described above, the diffraction grating GR can be positioned within the current non-injection region R1 when viewed in a plan view.

[0026] The semiconductor optical element EL is, for example, a semiconductor laser element having an emission width in the Y direction of 75 μm or more, a cavity length of 3 mm or more, and capable of outputting laser light with an output of 10 W or more. Such a semiconductor optical element EL can also be called a broad-area semiconductor laser. As will be described in detail later, electrode layers 4 and 6 (see FIG. 3 ) are provided on the substrate 1 and current control layer 3 of the semiconductor optical element EL, respectively. For ease of understanding, this embodiment will be described taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type.

[0027] Fig. 3 is a cross-sectional view showing a specific example of the configuration of the semiconductor optical device according to the first embodiment of the present invention. In Fig. 3, components corresponding to those shown in Fig. 1 and Fig. 2 are denoted by the same reference numerals. The semiconductor optical device EL shown in Fig. 3 includes a substrate 1, a laminate 2, a current control layer 3, an electrode layer 4, an electrode layer 6, an antireflection coating 7, and an enhanced reflection coating 8.

[0028] The semiconductor layer 10 of the laminate 2 is formed by laminating, in order from the substrate 1 side, a buffer layer 11, a first cladding layer 12, a diffraction grating layer 13, a second cladding layer 14, and a waveguide layer 15. The active layer 20 of the laminate 2 generates light of a predetermined wavelength when a current is injected. The semiconductor layer 30 of the laminate 2 is formed by laminating, in order from the active layer 20 side, a waveguide layer 31 and a cladding layer 32.

[0029] The current control layer 3 is formed by laminating a block layer 41 and a contact layer 42 in this order from the semiconductor layer 30 side. The block layer 41 has a region 41a that passes current supplied via the contact layer 42 and a region 41b that blocks the current. The region 41b of the block layer 41 defines the +X side (emission surface PL1 side) and the −X side (reflection surface PL2 side) of the stack 2 as current non-injection regions R1, and the region 41b defines the region between the current non-injection regions R1 as current injection regions R0.

[0030] Window regions W are formed on the +X side (light output surface PL1 side) and the −X side (reflecting surface PL2 side) of the stacked body 2 and the current control layer 3. The window regions W are provided to reduce the absorption rate of light generated in the active layer 20. For example, when viewed in a plan view, the window regions W are arranged within the non-current injection region R1. Note that the window regions W on the −X side (reflecting surface PL2 side) of the stacked body 2 and the current control layer 3 can be omitted.

[0031] The electrode layer 4 is a p-side electrode layer of the semiconductor optical element EL and is formed on the contact layer 42 of the current control layer 3. The electrode layer 4 is, for example, a Ti / Au laminated film. The electrode layer 6 is an n-side electrode layer of the semiconductor optical element EL and is formed on the back surface (-Z side surface) of the substrate 1. The electrode layer 6 is, for example, a Ni / Ge / Au laminated film.

[0032] The anti-reflection coating 7 is a so-called AR (anti-reflective) coating and is formed on the output surface PL1, which is one side of the laminate 2. The enhanced reflection coating 8 is a so-called HR (high reflection) coating and is formed on the reflective surface PL2, which is the other side of the laminate 2. The reflectances of the anti-reflection coating 7 and the enhanced reflection coating 8 can be freely selected according to the design of the semiconductor optical element EL. For example, a low reflectance of approximately 0.1% can be achieved by using a single layer film of Al2O3, AlN, Si, SiO2, TiO2, etc., or a multilayer film combining two or more of these. Furthermore, a high reflectance approaching 100% can be achieved by stacking multiple pairs of two of these layers.

[0033] The semiconductor layer 10, the active layer 20, and the semiconductor layer 30 of the stacked body 2, and the block layer 41 and the contact layer 42 of the current control layer 3 can be formed by, for example, a metal organic chemical vapor deposition (MOCVD) method. In this case, the raw materials used may be selected appropriately from the group consisting of trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), arsine gas (AsH), halomethanes such as carbon bromide (CBr) or carbon chloride (CCl), diethylzinc (DEZ), monosilane (SiH), and the like, depending on the material constituting each layer.

[0034] The configuration of the semiconductor optical element EL shown in Fig. 3 will be described in detail below. The substrate 1, the laminated body 2, the current control layer 3, and the diffraction grating GR will be described in detail below in this order.

[0035] <Substrate 1> The substrate 1 includes a compound semiconductor and a dopant. Examples of the compound semiconductor include III-V group compound semiconductors such as GaAs and InP. Examples of the dopant include elements such as Si, Ge, Sn, S, Se, and Te. These elements can be used alone or in combination of two or more. The thickness of the substrate 1 is not particularly limited, but is, for example, about 250 to 450 μm.

[0036] <Stack 2> As described above, the stack 2 includes, for example, the semiconductor layer 10, the active layer 20, and the semiconductor layer 30. The stack 2 includes a compound semiconductor. Examples of the compound semiconductor include GaAs, AlGaAs, InGaAs, InGaAlAs, InP, GaInP, AlInP, AlGaInP, and InGaAsP.

[0037] <Semiconductor Layer 10> As described above, the semiconductor layer 10 includes, for example, a buffer layer 11, a first cladding layer 12, a diffraction grating layer 13, a second cladding layer 14, and a waveguide layer 15. The buffer layer 11 is a layer provided between the buffer layer 11 and the substrate 1 in order to form a high-quality semiconductor layer 10. The first cladding layer 12 is a layer for confining light generated in the active layer 20. The diffraction grating layer 13 is a layer in which a diffraction grating GR is formed. The diffraction grating layer 13 may have, for example, a superlattice structure in which different types of semiconductor compounds are alternately stacked. The second cladding layer 14, together with the first cladding layer 12, is a layer for confining light generated in the active layer 20. The waveguide layer 15, together with the active layer 20, is a layer through which light generated in the active layer 20 propagates.

[0038] The semiconductor layer 10 includes a compound semiconductor and a dopant. The compound semiconductor may be the same as or different from the compound semiconductor included in the substrate 1. For example, when the semiconductor layer 10 includes AlGaAs as the compound semiconductor, the Al composition is represented by x, and the composition ratio of Al to Ga is represented by x:(1-x). In this case, the waveguide layer 15 of the semiconductor layer 10 preferably has an Al composition x that satisfies, for example, 0.1≦x≦0.2.

[0039] The dopant may be the same as the dopant in the substrate 1. For example, the doping concentration of the waveguide layer 15 is 1×10 16 ~1 x 10 17 cm -3 The concentration is preferably in the range of 3×10 16 ~5 x 10 16 cm -3 It is more desirable that the concentration be in the range of .

[0040] The thicknesses of the first cladding layer 12, the second cladding layer 14, and the waveguide layer 15 are not particularly limited, but are preferably about 1 μm, for example. The doping concentration and thickness of the waveguide layer 15 are designed taking into consideration the balance between the resistance value of the semiconductor optical element EL and the reduction in light emission efficiency due to free carrier absorption.

[0041] <<Active Layer 20>> The active layer 20 has a band gap smaller than the band gaps of the semiconductor layer 10 and the semiconductor layer 30, and is a layer that generates light when a current is injected. The active layer 20 includes a compound semiconductor. The compound semiconductor is appropriately selected depending on the wavelength of the light to be emitted from the semiconductor optical element EL. Examples of the compound semiconductor include InGaAs, GaAs, InGaAlAs, AlGaInP, and InGaAsP.

[0042] The active layer 20 may be composed of, for example, a stack including a quantum well layer between two barrier layers. The two barrier layers on either side of the quantum well layer are layers including a compound semiconductor having a band gap larger than that of the quantum well layer. The barrier layers may further include a dopant. The barrier layers may be composed of a layer with a constant doping concentration, a graded layer in which the doping concentration changes with increasing distance from the quantum well layer, or a stack of these. Alternatively, the barrier layers may be composed of a layer with a constant composition of elements in the compound semiconductor, a graded layer in which the composition of elements in the compound semiconductor changes in the direction away from the quantum well layer, or a stack of these.

[0043] The thickness of the active layer 20 is not particularly limited, but is, for example, about 30 to 70 nm. The active layer 20 may also have a multiple quantum well structure in which quantum well layers and barrier layers are alternately stacked over multiple layers.

[0044] <<Semiconductor Layer 30>> The semiconductor layer 30 includes, for example, a waveguide layer 31 and a cladding layer 32, as described above. The waveguide layer 31 is a layer that, together with the active layer 20, propagates light generated in the active layer 20. The cladding layer 32 is a layer that confines the light generated in the active layer 20. In other words, the light generated in the active layer 20 propagates through the waveguide layer 31, the waveguide layer 15 of the semiconductor layer 10, and the active layer 20 while being confined by the cladding layer 32 and the second cladding layer 14 and first cladding layer 12 of the semiconductor layer 10.

[0045] The semiconductor layer 30 includes a compound semiconductor and a dopant. The compound semiconductor may be the same as or different from the compound semiconductor included in the substrate 1 or the semiconductor layer 10. For example, when the semiconductor layer 30 includes AlGaAs as the compound semiconductor, it is desirable that the waveguide layer 31 of the semiconductor layer 30 has a doping ratio of 0.1≦x≦0.2. The dopant may be, for example, an element such as C. The doping concentration of the waveguide layer 31 may be the same as or different from the doping concentration of the waveguide layer 15 in the semiconductor layer 10. For example, the doping concentration of the waveguide layer 31 may be 1×10 16 ~1 x 10 17 cm -3 The concentration is preferably in the range of 3×10 16 ~5 x 10 16 cm -3 It is more desirable that the concentration be in the range of .

[0046] The thickness of the waveguide layer 31 may be the same as or different from the thickness of the waveguide layer 15 in the semiconductor layer 10. The thickness of the cladding layer 32 may be the same as or different from the thickness of the first cladding layer 12 in the semiconductor layer 10. The thicknesses of the waveguide layer 31 and the cladding layer 32 are not particularly limited, but are preferably about 1 μm, for example.

[0047] <Current Control Layer 3> As described above, the current control layer 3 includes, for example, a block layer 41 and a contact layer 42. The block layer 41 allows current to be injected into the current injection region R0 and prevents current from being injected into the current non-injection region R1. The contact layer 42 ensures that contact with the electrode layer 4 is ohmic contact.

[0048] The block layer 41 and the contact layer 42 contain a compound semiconductor and a dopant. The compound semiconductor may be the same as or different from the compound semiconductor contained in the substrate 1, the semiconductor layer 10, or the semiconductor layer 30. Here, the dopant used in the region 41a of the block layer 41 may be the same as the dopant used in the semiconductor layer 30, and the dopant used in the region 41b of the block layer 41 may be the same as the dopant used in the substrate 1 or the semiconductor layer 10. This is because the region 41b of the block layer 41 needs to block current. The dopant used in the contact layer 42 may be the same as the dopant used in the semiconductor layer 30.

[0049] The current control layer 3 is preferably a so-called SAS (Self Aligned Structure). The SAS structure is a structure in which a contact layer 42 is formed on a block layer 41 having an etched region 41a, and the etched region 41a is buried with the contact layer 42. In this SAS structure, current is injected into the stack 2 via the region 41a of the block layer 41 in which the contact layer 42 is buried.

[0050] <Diffraction Grating GR> Fig. 4 is a diagram for explaining the diffraction grating provided in the semiconductor optical device according to the first embodiment of the present invention. Fig. 4 is an enlarged view of a portion of the diffraction grating GR shown in Fig. 3. Although Figs. 1 and 3 show the diffraction grating GR schematically, as shown in Fig. 4, the diffraction grating GR has a structure in which convex portions and concave portions are formed alternately along the X direction.

[0051] As shown in Figure 4, the period of the diffraction grating GR is p, the height of the convex portions is h1, the height of the concave portions is h2, and the formation position of the diffraction grating GR (depth position in the direction from the interface between the second cladding layer 14 and the waveguide layer 15 toward the substrate 1) is d. As the diffraction grating GR of this embodiment, for example, one can be used in which the period p is 290 μm, the height h1 of the convex portions is 100 μm, the height h2 of the concave portions is 30 nm, and the formation position d of the diffraction grating GR is 500 nm. Furthermore, the ratio of the convex portions in one period of the diffraction grating GR (duty ratio) is 25%, and the order of the period p is second order. This is because if the order of the period p were first order, the length of the period p would be too short, making it difficult to form the diffraction grating GR.

[0052] As described above, the length of the diffraction grating GR in the X direction is set in consideration of the output of the semiconductor optical element EL, etc. Here, in order to make the output of the laser light emitted from the semiconductor optical element EL 10 W or more, it is preferable that the length of the diffraction grating GR in the X direction be, for example, about 200 to 1000 μm.

[0053] 5 is a diagram showing the relationship between the length of the diffraction grating and the coupling coefficient in the first embodiment of the present invention. The horizontal axis of the graph shown in FIG. 5 represents the length of the diffraction grating, and the vertical axis represents the coupling coefficient κ of the diffraction grating. Here, the diffraction grating layer 13 is assumed to be n-type AlGaAs or a superlattice structure in which n-type GaAs and n-type AlGaAs are alternately stacked, and the diffraction grating GR has the structure described with reference to FIG. 4 . The thickness of the n-type GaAs and n-type AlGaAs forming the superlattice structure is, for example, 2.5 nm.

[0054] 5, "Al=0.2" indicates a simulation result when the diffraction grating layer 13 is made of n-type AlGaAs with an Al composition x of 0.2. "Al=0.315×10 pairs" indicates a simulation result when the diffraction grating layer 13 has a superlattice structure in which 10 pairs of n-type GaAs and n-type AlGaAs with an Al composition x of 0.315 are stacked.

[0055] Furthermore, "Al = 0.5 (InGaP)" indicates a simulation result when the diffraction grating layer 13 is made of n-type AlGaAs with an Al composition x of 0.5. InGaP has a refractive index equivalent to that of n-type AlGaAs with an Al composition x of 0.5, and therefore the above description is used. "Al = 0.5 x 20 pairs" indicates a simulation result when the diffraction grating layer 13 has a superlattice structure in which 20 pairs of n-type GaAs and n-type AlGaAs with an Al composition x of 0.5 are stacked.

[0056] Referring to FIG. 5, when the Al composition x of the n-type AlGaAs that forms the diffraction grating layer 13 is "0.2", the coupling coefficient of the diffraction grating GR is about 8.2 cm -1 When the Al composition x of n-type AlGaAs forming the superlattice structure of the diffraction grating layer 13 is "0.315", the coupling coefficient of the diffraction grating GR is about 6.1 cm -1 When the Al composition x of the n-type AlGaAs that forms the diffraction grating layer 13 is "0.5", the coupling coefficient of the diffraction grating GR is about 4.5 cm -1 When the Al composition x of n-type AlGaAs forming the superlattice structure of the diffraction grating layer 13 is "0.5", the coupling coefficient of the diffraction grating GR is about 3.8 cm -1 becomes.

[0057] When the Al composition x of the n-type AlGaAs that forms the diffraction grating layer 13 is "0.2," the reflectivity of the diffraction grating GR is 2% when the length of the diffraction grating GR is 173.9 μm, and the reflectivity of the diffraction grating GR is 15% when the length of the diffraction grating GR is approximately 500 μm. When the Al composition x of the n-type AlGaAs that forms the superlattice structure of the diffraction grating layer 13 is "0.315," the reflectivity of the diffraction grating GR is 2% when the length of the diffraction grating GR is approximately 230 μm, and the reflectivity of the diffraction grating GR is 15% when the length of the diffraction grating GR is approximately 670 μm. When the Al composition x of the n-type AlGaAs that forms the diffraction grating layer 13 is "0.5," the reflectivity of the diffraction grating GR is 2% when the length of the diffraction grating GR is approximately 320 μm, and the reflectivity of the diffraction grating GR is 15% when the length of the diffraction grating GR is approximately 890 μm. When the Al composition x of the n-type AlGaAs that forms the superlattice structure of the diffraction grating layer 13 is "0.5," the reflectivity of the diffraction grating GR is 2% when the length of the diffraction grating GR is approximately 390 μm, and the reflectivity of the diffraction grating GR is 15% when the length of the diffraction grating GR is 1109.3 μm.

[0058] The dashed line in Fig. 5 indicates the product (κL) of the coupling coefficient κ of the diffraction grating GR and the length L of the diffraction grating GR. Fig. 5 shows κL when the reflectance of the diffraction grating GR is 2% and κL when the reflectance of the diffraction grating GR is 15%. The value of κL when the reflectance of the diffraction grating GR is 2% is 0.14, and the value of κL when the reflectance of the diffraction grating GR is 15% is 0.41.

[0059] Here, in order to obtain an output of about 10 W from the semiconductor optical element EL, the reflectivity of the diffraction grating GR needs to be about 2 to 15%. From the results shown in Fig. 5, in order to obtain a semiconductor optical element EL capable of outputting laser light with an output of 10 W or more, the length of the diffraction grating GR is preferably 173.9 to 1109.3 µm (about 200 to 1000 µm). In other words, in order to obtain a semiconductor optical element EL capable of outputting laser light with an output of 10 W or more, the value of the product (κL) of the diffraction grating GR and the length L is preferably 0.14 to 0.41.

[0060] As mentioned above, the diffraction grating GR is preferably disposed within the non-current injection region R1 in plan view. The non-current injection region R1 does not affect the output characteristics and wavelength fluctuation suppression characteristics of the semiconductor optical element EL. Therefore, it is desirable that the length of the portion of the non-current injection region R1 in the X direction where the diffraction grating GR is not formed in plan view (the length corresponding to the lengths Δ1 and Δ2 shown in FIG. 2 ) is as short as possible. For example, the length Δ1 between the current injection region R0 and the diffraction grating GR shown in FIG. 2 is preferably approximately 35 μm in consideration of the reliability of the output surface PL1, and the length Δ2 between the diffraction grating GR and the output surface PL1 is preferably approximately 15 μm in consideration of manufacturing errors of the diffraction grating GR. When the length Δ1 is 35 μm and the length Δ2 is 15 μm, and the length of the diffraction grating GR in the X direction is set to 200 to 1000 μm, the length of the non-current injection region R1 occupied by the diffraction grating GR is 80 to 95.2%.

[0061] As described above, in this embodiment, the diffraction grating GR is formed in the semiconductor layer 10 or the semiconductor layer 30 between the emission surface PL1 and the reflection surface PL2 of the stacked body 2 in which the semiconductor layer 10, the active layer 20, and the semiconductor layer 30 are stacked. When viewed in a plan view, the diffraction grating GR is disposed in the current non-injection region R1, which is a region into which no current is injected by the current control layer 3. As a result, in this embodiment, the crystal quality of the current injection region R0 is not degraded as in the conventional case. Therefore, in this embodiment, the diffraction grating GR can suppress fluctuations in the oscillation wavelength while improving reliability.

[0062] Furthermore, in this embodiment, at least a portion of the non-current injection region R1 is made into a window region W that reduces the absorption rate of light generated in the active layer 20, and a diffraction grating GR is formed within the window region W. As a result, even if a deterioration in crystal quality occurs due to the formation of the diffraction grating GR, localized heat generation due to light absorption within the window region W is suppressed, thereby making it possible to suppress deterioration and destruction of the crystal structure.

[0063] Second Embodiment Fig. 6 is a planar perspective view of a semiconductor optical device according to a second embodiment of the present invention. In Fig. 6, the same components as those shown in Fig. 2 are designated by the same reference numerals. The semiconductor optical device EL of this embodiment is basically similar in configuration to the semiconductor optical device EL shown in the first embodiment. However, the semiconductor optical device EL of this embodiment differs from the semiconductor optical device EL shown in the first embodiment in the configurations of the current injection region R0, the current non-injection region R1, and the diffraction grating GR in plan view. The configuration of the window region W in plan view is also different, but in this embodiment, for ease of explanation, the configuration of the window region W in plan view will be the same as the configuration of the current non-injection region R1 in plan view.

[0064] 2, the semiconductor optical element EL of the first embodiment has a configuration in which the current injection region R0 and the current non-injection region R1 are separated in the X direction. In contrast, in the semiconductor optical element EL of this embodiment, the current injection region R0 is shaped to protrude in the +X direction, and the current injection region R0 and the current non-injection region R1 are partially overlapped in the X direction.

[0065] Specifically, the current injection region R0 in this embodiment has a configuration in which a narrow region (hereinafter referred to as the narrow region) that protrudes in the +X direction from the end on the +X side is added, and the current non-injection region R1 sandwiches the narrow region in the Y direction. Moreover, the diffraction grating GR provided in the current non-injection region R1 is also formed to sandwich the narrow region of the current injection region R0 in the Y direction when viewed in a plan view.

[0066] The diffraction grating GR is formed in this manner in order to eliminate higher-order modes and stabilize the transverse mode (mode in the Y direction) at the emission surface PL1. That is, in a high-power broad area semiconductor laser, the width of the light-emitting region in the transverse direction (Y direction) is as wide as several tens to several hundreds of μm, and therefore a large number of different transverse modes exist. In particular, the existence of high-order transverse modes, known as higher-order modes, is a factor in degrading the beam quality of a broad area semiconductor laser. In this embodiment, the higher-order modes are eliminated by the diffraction grating GR, which is formed to sandwich the narrow region of the current injection region R0 in the Y direction when viewed in a plan view.

[0067] As described above, in this embodiment, the diffraction grating GR is formed in a plan view so as to sandwich the narrow region of the current injection region R0 in the Y direction. Therefore, the laser light guided in the X direction through the current injection region R0 in a plan view is scattered in the Y direction in the region where the diffraction grating GR is formed. This makes it possible to eliminate higher-order modes that occur during high-power operation, stabilize the transverse mode (mode in the Y direction) at the output surface PL1, and improve beam quality.

[0068] In the semiconductor optical element EL of this embodiment, similarly to the semiconductor optical element EL of the first embodiment, the diffraction grating GR is arranged, in plan view, in a current non-injection region R1 (window region W) that is a region into which no current is injected by the current control layer 3. Therefore, also in this embodiment, the diffraction grating GR can suppress fluctuations in the oscillation wavelength while improving reliability and suppressing deterioration and destruction of the crystal structure.

[0069] Third Embodiment Fig. 7 is a planar perspective view of a semiconductor optical device according to a third embodiment of the present invention. In Fig. 7, the same components as those shown in Figs. 2 and 6 are designated by the same reference numerals. The semiconductor optical device EL of this embodiment is basically similar in configuration to the semiconductor optical devices EL shown in the first and second embodiments. However, the semiconductor optical device EL of this embodiment differs from the semiconductor optical devices EL shown in the first and second embodiments in the configurations of the current injection region R0, the current non-injection region R1, and the diffraction grating GR in a planar view. The configuration of the window region W in a planar view is also different, but in this embodiment, for ease of explanation, the configuration of the window region W in a planar view will be the same as the configuration of the current non-injection region R1 in a planar view.

[0070] In the semiconductor optical element EL of this embodiment, as in the semiconductor optical element EL of the second embodiment, the current injection region R0 is shaped to protrude in the +X direction, and the current injection region R0 and the non-current injection region R1 partially overlap in the X direction. However, whereas the semiconductor optical element EL of the second embodiment has a constant Y-direction width of the narrow region protruding in the +X direction from the X-side end, in the semiconductor optical element EL of this embodiment, the Y-direction width of the narrow region gradually narrows as it progresses in the +X direction. Note that, as in the second embodiment, the narrow region is sandwiched between the non-current injection regions R1 in the Y direction.

[0071] In the semiconductor optical element EL illustrated in Fig. 7, the length of the narrow region in the X direction is shorter than that of the second embodiment. Therefore, the diffraction grating GR provided in the non-current injection region R1 can be of the form shown in Fig. 6 or the form shown in Fig. 2. The form shown in Fig. 6 is a form in which the narrow region of the current injection region R0 is sandwiched in the Y direction. The form shown in Fig. 2 is a form in which the length in the Y direction is approximately the same as the maximum width in the Y direction of the current injection region R0. It should be noted that the semiconductor optical element EL of this embodiment is not limited to one in which the length in the X direction of the narrow region is shorter than that of the second embodiment.

[0072] As described above, in this embodiment, similarly to the second embodiment, the diffraction grating GR is formed in a plan view so as to sandwich the narrow region of the current injection region R0 in the Y direction. Therefore, similarly to the second embodiment, it is possible to eliminate higher-order modes that occur during high-output operation, stabilize the transverse mode (mode in the Y direction) at the output surface PL1, and improve beam quality.

[0073] In this embodiment, the width of the narrow region in the Y direction narrows stepwise as it progresses in the +X direction, which causes the higher-order modes of the guided light to be scattered stepwise along the X direction, thereby making it possible to further stabilize the transverse mode (mode in the Y direction) at the output surface PL1 compared to the first and second embodiments and improving the beam quality.

[0074] In addition, in this embodiment, since the diffraction grating GR having the configuration shown in Fig. 2 is provided, fluctuations in the oscillation wavelength can be suppressed. That is, in this embodiment, in addition to suppressing higher-order modes, the effect of wavelength fixation can be obtained.

[0075] In the semiconductor optical element EL of this embodiment, similarly to the semiconductor optical elements EL of the first and second embodiments, the diffraction grating GR is arranged, in plan view, in a current non-injection region R1 (window region W) that is a region into which no current is injected by the current control layer 3. Therefore, also in this embodiment, the diffraction grating GR can suppress fluctuations in the oscillation wavelength, improve reliability, and suppress deterioration and destruction of the crystal structure.

[0076] 8A to 8D are planar perspective views showing modified examples of the semiconductor optical device according to the third embodiment of the present invention. In FIGS. 8A to 8D, the same components as those shown in FIG. 7 are denoted by the same reference numerals. In this modified example, the shape of the narrow region of the current injection region R0 is changed. Although not shown in FIGS. 8A to 8D, the shapes of the non-current injection region R1 (window region W) and the diffraction grating GR also change depending on the shape of the narrow region in plan view.

[0077] As shown in Figures 8A to 8D, the number of steps in the narrow region may be any. Furthermore, the steps in the narrow region may be equally spaced or unequally spaced. Specifically, the length of each step in the narrow region in the X direction may be the same (equally spaced) or different (unequally spaced), as shown in Figures 8A and 8B. Similarly, although not shown, the rate of change in the width of each step in the narrow region in the Y direction may be the same (equally spaced) or different (unequally spaced). However, considering the purpose of scattering higher-order modes in stages, it is preferable that the narrow region narrows in width in the Y direction at equal intervals.

[0078] In the third embodiment, the narrow region of the current injection region R0 has a width that changes stepwise in the Y direction. However, the narrow region of the current injection region R0 may have a width that changes continuously in the Y direction. For example, the narrow region of the current injection region R0 may have a tapered shape in which the width in the Y direction changes gradually (continuously) as it progresses in the +X direction.

[0079] 9 is a perspective view showing a semiconductor optical device according to one embodiment of the present invention. As shown in FIG. 9, the semiconductor optical device DV of this embodiment includes a thermally conductive submount 100 and a semiconductor optical element EL according to any one of the first to third embodiments described above. In the semiconductor optical device DV, the semiconductor optical element EL is mounted on the submount 100 via a thermally conductive metal bonding layer (not shown).

[0080] Specifically, the submount 100 has a positive electrode 101 and a negative electrode 102 on its upper surface. The semiconductor optical element EL is mounted on the positive electrode 101 so that the electrode layer 4 shown in FIG. 3 is electrically connected to the positive electrode 101. The semiconductor optical element EL is also electrically connected by a wire 110 to the electrode layer 6 shown in FIG. 3 and the negative electrode 102. Therefore, by supplying an appropriate current between the positive electrode 101 and the negative electrode 102, laser light is emitted from the emission surface PL1 of the semiconductor optical element EL mounted on the submount 100.

[0081] It should be noted that the semiconductor optical element and semiconductor optical device of the present invention are not limited to the above-described embodiments, nor are they limited to the above-described modifications. In other words, the present invention can be freely modified within the scope of the present invention. For example, in the above-described embodiments and specific configuration examples, the stacked structure of the semiconductor optical element has been mainly described, but structures other than the stacked structure are optional.

[0082] 1...substrate, 2...laminated body, 3...current control layer, 10...semiconductor layer, 20...active layer, 30...semiconductor layer, 100...submount, DV...semiconductor optical device, EL...semiconductor optical element, GR...diffraction grating, PL1...emission surface, PL2...reflection surface, R0...current injection region, R1...current non-injection region

Claims

1. A semiconductor optical device comprising: a substrate; a stacked body in which, from the substrate side, a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are stacked; an emission surface provided on one side of the stacked body; a reflection surface provided on the other side of the stacked body so as to face the emission surface; a current control layer provided on the stacked body, which makes at least the emission surface side of the stacked body a current non-injection region into which no current is injected; and a diffraction grating formed in the first conductivity type semiconductor layer or the second conductivity type semiconductor layer between the emission surface and the reflection surface, wherein the diffraction grating is located within the current non-injection region when viewed in a plan view.

2. The semiconductor optical device according to claim 1, wherein the laminate has a window region formed therein that reduces the absorption rate of light generated in the active layer, the window region being located within the non-current injection region when viewed in a plan view, and the diffraction grating being located within the window region when viewed in a plan view.

3. The semiconductor optical device according to claim 1 or 2, wherein the current control layer defines a current injection region into which current is injected in an area adjacent to the non-current injection region of the laminate, and the width of the current injection region in a second direction intersecting with a first direction in which the emission surface and the reflection surface face each other, when viewed in a plan view, becomes narrower as it approaches the emission surface.

4. The semiconductor optical device according to claim 3, wherein the width of said current injection region in said second direction is gradually narrowed toward said light output surface.

5. A semiconductor optical device according to claim 3 or 4, wherein the non-current injection region is arranged to sandwich the current injection region, the width of which has been reduced, in the second direction, and the diffraction grating is arranged to sandwich the current injection region, the width of which has been reduced, in the second direction.

6. The coupling coefficient of the diffraction grating is κ [cm -1 ], and the length of the diffraction grating is L [cm -1 6. The semiconductor optical device according to claim 1, wherein κL is in the range of 0.14 to 0.41, where κL is the refractive index of the semiconductor optical fiber.

7. The semiconductor optical device according to claim 2, wherein the current control layer has a current non-injection region on the reflecting surface side of the laminate in addition to the light emitting surface side of the laminate, and the window region is disposed within the current non-injection region on the light emitting surface side of the laminate and within the current non-injection region on the reflecting surface side when viewed in a plan view.

8. A semiconductor optical device comprising: a thermally conductive submount; and a semiconductor optical element according to any one of claims 1 to 7 mounted on the submount via a thermally conductive metal bonding layer.

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