Systems and methods for current / voltage controlled neuromorphic computing in artificially created nanoscopic magnetic honeycomb lattice

Abstract

A computing element is provided. The computing element includes a) an artificial lattice comprising a multiplicity of connecting elements separated by pores; b) a plurality of input channels attached to the artificial lattice each configured to provide at least one of an electrical current and voltage to the artificial lattice; c) a plurality of readout channels attached to the artificial lattice, wherein each readout channel of the plurality of readout channels is connected to a common ground; and d) one or more sensing elements positioned at least one of perpendicular and along to the plurality of input channels and attached to the artificial lattice, wherein the one or more sensing elements configured to read a readout to create an output.

Description

SYSTEMS AND METHODS FOR CURRENT / VOLT AGE CONTROLLED NEUROMORPHIC COMPUTING IN ARTIFICIALLY CREATED NANOSCOPIC MAGNETIC HONEYCOMB LATTICECROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Application No. 63 / 675,158, filed July 24, 2024, which is hereby incorporated by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH & DEVELOPMENT

[0002] This invention was made with governl9ment support under DE- SC0014461 awarded by the U.S. Department of Energy. The government has certain rights in the invention.FIELD

[0003] The field of the invention relates generally to a neurom orphic computer, and more specifically, to systems and methods for current / voltage controlled neuromorphic computing in an artificially created nanoscopic magnetic honeycomb lattice.BACKGROUND

[0004] Neuromorphic computing is turning out to be the game changer in modem times. However, the much of the current research for developing the hardware for neuromorphic computation mostly relies on semiconductor-based transistor or oxide materials, such as in memristors. These both have limitations in terms of power usage, speed, or reproducibility. Some have demonstrated the possibility of neuromorphic computing using two-dimensional nanostructured magnets using the magnetic field as the read and / or write method.

[0005] Nanoscopic magnetic honeycomb lattice, for example artificial spin ice (ASI) as in square, pinwheel, and honeycomb lattice systems, has emerged as a niche venue to develop the reservoir or neuromorphic computing platform. It stems from the factthat an ASI with N elements can exhibit 2n different magnetization patterns, thus acting as a vast reservoir to process information. The nodes or vertices in artificial spin ice, such as honeycomb lattice, are known to exhibit emergent magnetic charges that relax by emitting or absorbing magnetic charge defect or effective magnetic monopoles. The magnetic charges interacting via Coulomb’s interaction give rise to collective response, which resembles artificial neural network. However, the dipolar interaction (Coulomb’s term), which is long range in nature but weak, leads to non-electrically tunable ‘athermal’ character in artificial spin ice system with large magnetic element (~ micrometer).

[0006] To probe the non-linearity in readouts, researchers have used magnetic field application, often in the form of cycles of count m, to induce a particular magnetization pattern in the system that can be read using a variety of techniques. It includes ferromagnetic resonance (FMR) spectra, Hall resistance, and magnetic force microscopy (among others).

[0007] The readout data is trained using machine learning for neuromorphic computing. The method to obtain readout data or, the use of cycles of magnetic field application for input are not practical for device development or prototypes. Also, those honeycomb lattices are made of large size nanoelements (typical length varying between 100 nm to several micrometer) that may be arranged in connected or disconnected configuration. Those samples are mostly created using electron-beam lithography, which is also very costly. However, there is a need to find new methodologies to address these challenges.

[0008] This background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.BRIEF DESCRIPTION

[0009] In one aspect, a computing element is provided. The computing element includes a) an artificial lattice comprising a multiplicity of connecting elements separated by pores; b) a plurality of input channels attached to the artificial lattice eachconfigured to provide at least one of an electrical current and voltage to the artificial lattice; c) a plurality of readout channels attached to the artificial lattice, wherein each readout channel of the plurality of readout channels is connected to a common ground; and d) one or more sensing elements positioned at least one of perpendicular and along to the plurality of input channels and attached to the artificial lattice, wherein the one or more sensing elements configured to read a readout to create an output. The computing element may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0010] In another aspect, at least one processor and at least one memory device are provided to be in communication with the chip, made of artificial lattice. The processor is programmed to: a) receive signals from one or more sensing elements attached to an artificial lattice comprising a multiplicity of connecting elements separated by pores; b) analyze the signals to determine a readout from the artificial lattice, wherein the signals are electrical signals measured by the one or more sensing elements; and c) analyze a database of signals and readouts to determine an input to the artificial lattice corresponding to a readout. The computer device may have additional, less, or alternate functionalities, including those discussed elsewhere herein.

[0011] Various refinements exist of the features noted in relation to the above-mentioned aspects. Further features may also be incorporated in the above-mentioned aspects as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to any of the illustrated embodiments may be incorporated into any of the above-described aspects, alone or in any combination.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The Figures described below depict various aspects of the systems and methods disclosed. It should be understood that each Figure depicts an embodiment of a particular aspect of the disclosed systems and methods, and that each of the Figures is intended to accord with a possible embodiment thereof. Further, wherever possible, the following description refers to the reference numerals included in the following Figures, in which features depicted in multiple Figures are designated with consistent reference numerals. There are shown in the drawings arrangements presently discussed, it beingunderstood, however, that the present embodiments are not limited to the precise arrangements.

[0013] Figure 1 A shows an example honeycomb lattice based on an atomic force micrograph in accordance with at least one embodiment.

[0014] Figure IB illustrates another example honeycomb lattice shown via a scanning electron micrograph, in accordance with at least one embodiment.

[0015] Figures 2A-2C illustrate different views of a quasi-particle of a magnitude two arbitrary units as it traverses the lattice via relaxation between vertices, in accordance with at least one embodiment.

[0016] Figure 2D illustrates a neutron scattering measurement, confirming the quasi-particle dynamics at very fast relaxation rate in accordance with at least one embodiment.

[0017] Figure 3 illustrates an analogy between a neural network and the honeycomb lattice.

[0018] Figure 4 illustrates a simplified view of an example honeycomb lattice.

[0019] Figure 5 illustrates a schematic depiction of current flow along a honeycomb lattice element.

[0020] Figure 6 illustrates an exemplary schematic of an example chip for a neuromorphic computer in accordance with at least one embodiment.

[0021] Figures 7A and 7B each illustrate different example designs of printed circuit boards that are used for neuromorphic applications.

[0022] Figure 8 illustrates a graph of readouts from the example chip shown in Figure 6.

[0023] Figures 9 A and 9B illustrate short-term and fading memory in the chip shown in Figure 6.

[0024] Figure 10A illustrates binary encoding of a MNIST standard dataset to the chip shown in Figure 6 in accordance with at least one embodiment.

[0025] Figure 10B illustrates a confusion matrix of the classification accuracy for MNIST standard dataset based on the chip readouts for the binary encoding shown in Figure 10 A.

[0026] Figure 11 illustrates a graph of normalized readout data from the chip shown in Figure 6 and predicted behavior for Mackey-Glass chaotic time-series.

[0027] Corresponding reference characters indicate corresponding parts throughout the drawings.DETAILED DESCRIPTION

[0028] The field of the invention relates generally to a neuromorphic computer, and more specifically, to systems and methods for current / voltage controlled neuromorphic computing in an artificially created nanoscopic magnetic honeycomb lattice (without any magnetic field application).

[0029] As used herein reservoir computing is a framework for computation derived from recurrent neural network theory that maps input signals into higher dimensional computational spaces through the dynamics of a fixed, non-linear system called a reservoir. After the input signal is fed into the reservoir, which is treated as a "black box," a readout mechanism is utilized to read the state of the reservoir. The readout data is then fed to a machine learning model to obtain the neuromorphic output. The first key benefit of this framework is that training is performed only at the readout stage. The second key benefit is that both the logic operation and the memory storage can be performed in the same system, thus removing the Von Neumann bottleneck, and reducing the computational cost. Another major advantage of the presented system is the much smaller energy consumption, which is the need of the hour.

[0030] For the purposes of this discussion, “readout” and “output” are two different things in the context of a neuromorphic chip. The readout is the data that is measured after sending the input signal to the honeycomb lattice. Output is obtained from the weighted treatment of the readout data that are used for Al tasks.

[0031] The 'reservoir' in reservoir computing is the internal structure of the computer, and must have two properties: it is made up of individual, non-linear units, and it is capable of storing information at short time scale. The non-linearity describes the collective non-linear response of the reservoir to set of inputs, which is what allows reservoir computers to solve complex problems. Reservoirs are able to store information for short time, where the previous input affects the next response. The change in response of the individual element of the reservoir due to the past input action allows both spatial and temporal correlation between input information, which is eventually exploited for to complete specific training task.

[0032] The readout is sent to the neural network layer that performs a weighted linear transformation on the readout of the reservoir. The weights of the readout layer are trained by analyzing the spatiotemporal patterns of the reservoir after excitation by known inputs, and by utilizing a training method such as a linear regression or a Ridge regression. As its implementation depends on spatiotemporal reservoir patterns, the details of training methods are tailored to each type of reservoir.

[0033] As used herein, neuromorphic computing is an approach to computing that is inspired by the structure and function of the human brain. A neuromorphic computer / chip is any device that uses physical artificial neurons to do computations. In recent times, the term neuromorphic has been used to describe analog, digital, mixed-mode analog / digital VLSI, and software systems that implement models of neural systems (for perception, motor control, or multisensory integration). The implementation of neuromorphic computing on the hardware level can be realized by oxide-based memristors, spintronic memories, threshold switches, transistors, among others. Training software-based neuromorphic systems of spiking neural networks can be achieved using error backpropagation.

[0034] A key aspect of neuromorphic engineering is understanding how the morphology of individual neurons, circuits, applications, and overall architectures creates desirable computations, affects how information is represented, influences robustness to damage, incorporates learning and development, adapts to local change (plasticity), and facilitates evolutionary change.

[0035] Scientists have been searching for new venues to address the challenges of power usage, speed, or reproducibility in reservoir or neuromorphic computing. In the exemplary embodiment, artificially created magnetic honeycomb lattice can be a suitable candidate in this regard.

[0036] The herein described neuromorphic device is very different from transistor-based neuromorphic devices, such as Intel’s Loihi2, that rely on the extensive training of synapses for Al (artificial intelligence) tasks. In the present device, the synapse’s weights are automatically controlled by the lattice itself during the input encoding process. More specifically, the system doesn’t control the synapse weight (that are billion in numbers in a one sq. inch size specimen) or doesn’t train them. Instead, the present technique relies on the training of the readout data to generate the outputs for the Al tasks.

[0037] The present systems use a large throughput nanoscopic magnetic honeycomb lattice of ultra-small (~ 11 nm in length, ~ 4 nm in width, 5-10 nm in thickness) permalloy (Ni0.81Fe0.19) connecting element. The macroscopic size of honeycomb lattice specimen can vary between few micrometer to full 4-inch diameter silicon wafer. The present disclosure describes the creation of magnetic honeycomb lattice made of ultra-small magnetic element, as well as the large throughput size of the macroscopic specimen. This disclosure describes the method to create and use the large throughput artificial honeycomb lattice of nanoscopic elements.

[0038] The methods recited herein may be replicated to create a plethora of magnetic and non-magnetic lattices of the same size and microscopic detail of different materials, e.g., cobalt, hard ferromagnetic elements (such as FePt, FePd), Sn, Pb as well as other soft magnetic materials. Accordingly, one having skill in the art would understand that the systems and methods described herein may be used in the nanoengineering method to create artificial permalloy honeycomb lattices out of other materials.

[0039] The methods described herein can also be used to create magnetic lattices of smaller as well as larger element sizes (with typical length varying between 5 nm to 100 nm) by selecting diblock copolymer of different molecular weights to generate the hexagonal template of varying diameters and periodicities or, using alumina (A12O3) template (with typical element length of 40-50 nm and higher).

[0040] In the example embodiment, the honeycomb lattice is a reservoir which processes input signals and provides readout. By adding electrical wiring and a microprocessor to send / receive the signals / readouts, the honeycomb lattice becomes a neuromorphic chip. Therefor the reservoir is the processor if the neuromorphic chip. Accordingly, the systems and methods described herein provide for a neuromorphic chip based on the honeycomb lattice reservoir.

[0041] The systems described herein describe an innovative data encoding and on-chip readout scheme to perform variety of Al (artificial intelligence) tasks, e.g., pattern recognition, speech and video recognition, chaotic time-series prediction etc. Furthermore, the systems described herein provide for an information encoding and electrical readout scheme, as described herein.

[0042] In the example embodiment, the system encodes information encoding via the parallel injection of input currents / voltages that directly correspond to the pixel intensity of the encoded object. In this disclosure, this methodology is called a “temperature encoding” method. The system performs electrical readouts (voltage / current) on-chip via sensing at multiple locations in perpendicular, as well as along, configuration to the input current / voltage application directions. The system performs information encoding using the “temperature encoding” method and on-chip readout via sensing at multiple locations perpendicular to the input current / voltage application direction can be applied to any physical system for the neuromorphic hardware development purpose. In particular, the information encoding and readout methodology in regard to application in nanoscopic magnetic lattice, can be used irrespective of the motif, e.g., honeycomb, triangular, square, hexagonal and all others.

[0043] In the example embodiment, the readouts are fed to a logistic regression or neural network to generate outputs for the Al tasks. To improve the accuracy in pattern recognition and other Al tasks, the system uses a novel and innovative scheme of adjusting the readouts by using multiple combinations of sensing voltages on the chip. The modified readouts undergo the logistic regression or weight optimization via few layers of artificial neural networks to generate the final outputs for the Al tasks.

[0044] While there are neuromorphic chip designs based on magnetic materials, these are significantly different from the systems and methods described herein.For example, the systems and methods described herein do not use any magnetic tunnel junction or domain wall track that require magnetic field application. In the present case, the system and methods use the seamless design of magnetic honeycomb lattice to generate the readout without any magnetic field application. Also, the present systems and methods do not employ numerical method to adjust the synapse function. In the present case, the synapse is automatically adjusted by the magnetic lattice itself.

[0045] The present systems and methods use a honeycomb lattice spin ice system to create a reservoir. Second, the present systems and methods use electrical inputs (current / voltage) to write the information and electrical output to read the data. This is in contrast to systems that use magnetic field or FMR (Ferromagnetic resonance) techniques to write or read the data.

[0046] The present systems and methods take advantage of the fact that as the size of the constituting element reduces to the nanoscopic level, the exchange interaction becomes prominent and affects the intrinsic spin dynamics. Similarly, the nature of local magnetic correlation deviates from the truly Coulombic origin. Consequently, such magnetic systems can exhibit complex nonlinear local interaction and faster dynamics. The two properties, nonlinearity and fast dynamics, are highly desirable for the development of robust neuromorphic computer for edge computing of complex task.

[0047] In the approach described herein — instead of using magnetic field, the system uses electronic industry standard electrical inputs (current or volage) to probe the collective magnetic response in the artificial honeycomb lattice of ultra-small nanoscopic magnetic (permalloy) element with connected topography.

[0048] Figure 1 A shows an example honeycomb lattice based on an atomic force micrograph in accordance with at least one embodiment. Figure IB illustrates another example honeycomb lattice shown via a scanning electron micrograph, in accordance with at least one embodiment. The microscopic images of the artificially created lattice are shown here in Figures 1 A and lb. The ultra-small element size reduces the inter-elemental magnetic dipolar interaction energy to a modest 30-45 K, thus allowing the use of one or more soft tuning parameters (such as electrical current) to alter the magnetic state locally and temporally. The use of electrical tuning parameter was not possible in large element size (500 nm or longer) magnetic honeycomb lattice, created using electron-beam lithographytechnique, as the inter-elemental dipolar interaction energy is much larger, to the tune of 10,000 K. Those systems (magnetic lattices) are ‘athermal.’ Hence, they cannot be used for electrical manipulation of the underlying magnetic states. Thus, the physical size of ultrasmall connecting element in the magnetic honeycomb lattice plays crucial role in the design of electrically tunable neuromorphic device in this system.

[0049] Figures 2A-2C illustrate different views of a quasi-particle of a magnitude two arbitrary units as it traverses the lattice via relaxation between vertices, in accordance with at least one embodiment. More specifically, item 2Q is a quasi-particle of magnitude 2 arbitrary units that traverses the lattice via relaxation between vertices. Figure 2D illustrates a neutron scattering measurement, confirming the quasi-particle dynamics at very fast relaxation rate in accordance with at least one embodiment. The neutron scattering measurement illustrates that the relaxation rate of the quasi-particle is very high, in the order of 20 picoseconds (ps).

[0050] The second important requirement for the neuromorphic application is fast processing speed of information. The artificial honeycomb lattice of single domain size nanoscopic permalloy element, with typical length of ~ 11 nm (nanometer), is shown to exhibit very fast dynamics at ~ 20 - 50 ps time scale due to magnetic charge defect quasiparticle’s relaxation as illustrated in Figures 2A-2D. Additionally, the small dipolar interaction energy due to small element size, ~ 30 - 45 K, causes self-propelled dynamics even at low temperature without the application of any external stimuli, such as magnetic field. This is in strong contrast to the large element size ASI system where magnetic field application is necessary to spur magnetic charge defect’s mediated dynamics. The small interaction energy in the herein described system renders a highly versatile platform using modest tuning parameter, such as current to alter the static and dynamic correlation between magnetic charges. This provides the advantage of this unique capability to create an energyefficient neuromorphic computer in the 2D magnetic lattice.

[0051] Figure 3 illustrates an analogy between a neural network and the of the honeycomb lattice 300. The neural network 305 could be biological or artificial. The quasi-particle dynamics act as synapse and the connecting elements of the honeycomb lattice provide the synaptic pathways between neurons at the vertices. Each node of the honeycomb lattice acts as a neuron, as shown in Figure 3. Since there are over a billion nodes andconnecting elements in 1 sq. inch size artificial honeycomb lattice specimen, the system manifests a very high density of neurons and synapses that can be useful to carryout complex machine learning tasks. This is further illustrated in Figure 4.

[0052] Figure 4 illustrates a simplified view of an example honeycomb lattice. Each vertex of the honeycomb lattice, shown by number 1 or 3, acts as a neuron. The neuron releases synapses in the form of quasi-particle, shown by black ball carrying number 2, that traverses between the neurons (vertices) along the honeycomb element. So, the honeycomb element provides the synaptic pathways. Thus, this system has a unique advantage over the transistor-based neuromorphic devices that require the packing of a very large number of transistors to achieve high density of neuron and synapse counts.

[0053] The synaptic activity can be controlled / tuned by electric current or voltage application due to the small dipolar interaction energy between nearest neighboring elements. The system uses this property to create a new neuromorphic device, which uses a combination of simultaneous multiple current biased states to access the unique reservoir states that can be used for machine learning. Unlike the application of single current input, which can follow the path-like electrical transport and drift diffusion model due to the scattering from magnetic charge at the vertices in a honeycomb network, multiple inputs alter the static and dynamic correlation between magnetic charges due to the collective interference effect. There is a graphical depiction of this effect in Figure 5. Subsequently, a new electrical transport pattern or mechanism arises. Further details about the device design, electrical measurement readouts and machine learning methods, used to perform the pattern recognition tasks, are discussed below.

[0054] Figure 5 illustrates a schematic depiction of current flow along a honeycomb lattice element. Figure 5 shows a schematic depiction of current flow along the honeycomb element via graph theory. Electric inputs e.g., a set of currents or voltages are fed on the left side at selective spots, shown by the dots. After the input, the current combination propagates towards right, forming a wave type pattern.

[0055] Details of the nanofabrication method and the electrical measurement scheme to generate readouts for neuromorphic device application are discussed below.

[0056] The magnetic honeycomb lattice can be created via this nanoengineering methodology. First, an artificial honeycomb lattice of ultra-small nanoscopic magnetic element with connected topography is created. The typical element size of the honeycomb lattice is ~ 11 nm (length), 4 nm width, 5-10 nm thickness. In one embodiment, permalloy magnet (Ni0.81Fe0.19) may be used to create the magnetic honeycomb, one having ordinary skill in the art would understand that other materials can be utilized to create the artificial honeycomb lattice. Examples of materials include, but are not limited to, different magnetic or non-magnetic elements, such as cobalt (Co), hard ferromagnetic elements (such as FePt, FePd), tin (Sn), lead (Pb), as well as other soft magnetic materials and varying element sizes. Details of the nanoengineering methods are discussed below.

[0057] Fabrication of artificial honeycomb lattice involves the synthesis of porous hexagonal diblock template on top of a silicon substrate, calibrated reactive ion etching (RIE) using CF4 gas to transfer the hexagonal pattern to the underlying silicon substrate and the deposition of magnetic material (permalloy) on top of the uniformly rotating substrate in near-parallel configuration (~ 2° - 3°) to achieve the two-dimensional character of the system. In one example embodiment, the fabrication process utilizes diblock copolymer polystyrene(PS)-b-poly-4-vinyl pyridine (P4VP) of molecular weight ~ 20K Dalton with the volume fraction of 70% PS and 30% P4VP. The self-assembly of diblock copolymer is driven by microphase separation arising from the immiscibility of the polymer blocks. A microphase separated diblock copolymer film can take various forms from spherical to cylindrical to lamellar, depending upon the volume fraction of each block. At this volume fraction, the diblock copolymer tends to self-assemble, under right condition, in a hexagonal cylindrical structure of P4VP in the matrix of polystyrene (PS). A 0.5% PS-b- P4VP copolymer solution in toluene can be spin casted onto cleaned silicon wafers at 2500 rpm for 30 s and placed in vacuum for 12 hours to dry. The samples are then solvent annealed at 25o C for 12 hours in a mixture of THF / toluene (80:20 v / v) environment. The process results in the self-assembly of P4VP cylinders in a hexagonal pattern within a PS matrix. The average diameter of a P4VP cylinder is ~12 nm and the center-to-center distance between two cylinders is ~28 nm. Submerging the samples in ethanol for 20 minutes releases the P4VP cylinders yielding a porous hexagonal template. The diblock template is used as a mask to transfer the topographical pattern to the underlying silicon or silicon nitridesubstrate. The top surface of the reactively etched silicon substrate resembles a honeycomb lattice pattern of connecting elements, with typical length of ~ 11 nm. This property is exploited to create metallic honeycomb lattice by depositing permalloy, Ni0.81Fe0.19, in near parallel configuration in an electron-beam evaporation. For this purpose, a new sample holder was designed and setup inside the e-beam chamber. The substrate was rotated uniformly about its axis during the deposition to create uniformity. This allowed evaporated permalloy to coat the top surface of the honeycomb only, producing the desired magnetic honeycomb lattice with a typical element size of ~ 11 nm (length) x 4 nm (width). Artificial lattice of different thicknesses are created by depositing permalloy material of varying thicknesses, ranging from 5 nm to 10 nm. Atomic force micrograph (AFM) and field emission scanning electron micrograph (FESEM) of a typical honeycomb lattice are shown in Figure 1. The average roughness in the thickness of a honeycomb element is about 0.5 nm or less. Each honeycomb unit is about 30 nm wide.

[0058] Figure 6 illustrates an exemplary schematic of an example chip 600 for a neuromorphic computer in accordance with at least one embodiment. The schematic shows that N input channels 605 (either current or voltage) can be applied in parallel to a honeycomb lattice 602. The readout voltage 610 (can also be resistance or readout current) is measured perpendicular or along to the input current / voltage direction. For N physical inputs 605, the chip 600 can have a total of 2ndigital inputs. Thus, the system can measure the same number, 2n, of readouts. This chip 600 can then be used for Neuromorphic Computation as described herein.

[0059] The system uses an electrical measurement scheme to obtain readouts for ML (machine learning) outputs. For the purposes of this discussion, “readout” and “output” are two different things in the context of neuromorphic chip 600. The readout is the data that is measured after sending the input signal to the honeycomb lattice 602. Output is obtained from the weighted treatment of the readout data that are used for Al tasks.

[0060] The system uses a unique and novel method to inject a multitude of inputs 605 and obtain the corresponding readouts in the honeycomb reservoir. The system uses a combination of simultaneous small voltages (~ 0.1 V - 5 V) or current applications to probe the multitude of magnetic states, as shown in Figure 6. In the schematic figures, the current / voltage input channels 605 are fed to the rectangular specimen from left and exits onthe right. All channels on the right 615 are connected to a common ground. The readouts are obtained at multiple locations, which are perpendicular or along to the current / voltage input direction.

[0061] In the example embodiment, the honeycomb lattice 602 is a reservoir which processes input signals and provides readout. By adding electrical wiring and a microprocessor to send / receive the signals / readouts, the honeycomb lattice 602 becomes a neuromorphic chip 600. Therefor the reservoir is the processor if the neuromorphic chip 600. Accordingly, the systems and methods described herein provide for a neuromorphic chip 600 based on the honeycomb lattice reservoir 602.

[0062] Figures 7A and 7B each illustrate different example designs of printed circuit boards that are used for neuromorphic applications. Figures 7A and 7B illustrate 12 input configurations with different electrical readout configurations of the chip 600 (shown in Figure 6). The seamless design allows to increase or decrease the number of inputs, as needed, to the chip. For example, the chip can have 9 or even 16 inputs for different applications. The multiple input configuration is utilized to generate large number of electrical readouts via Binary combinations of voltage or current. For example, the 12-input configurations can have current combinations like 011000111010 or 110001110111. There are 4096 such possible binary combinations in the 12-input configuration. Each of the current combination generates a distinct readout voltage, signifying the very large number of magnetic configurations in artificial honeycomb lattice 602 (shown in Figure 6) that can be either inferred or tuned by electrical input. The mechanism of interaction between electron’s spin in electrical current and the magnetic configuration in honeycomb lattice 602 plays important role in this.

[0063] Figure 8 illustrates a graph of readouts from the example chip 600 (shown in Figure 6). In Figure 8, the readouts are for 512 combinations of input currents / voltages in 9-input configuration. Different current combinations result in distinct readout voltages. A high degree of distinction between the readout voltages are very desirable for training and testing of the neuromorphic computation. Additionally, the number of combinations can be easily extended to 64,000 by creating 16-input configuration in the chip 600.

[0064] Figures 9 A and 9B illustrate short-term and fading memory in the chip 600 (shown in Figure 6). For Figure 9A, three random sequences are encoded using a 300 ns pulse without any time delay between the random series. The figure shows different readouts. In Figure 9B, the same random sequences are run again but with a time difference of 20 microseconds between them, then the readouts look similar in each case. These Figures show that the chip 600 retains the memory for a short time and that when a time lag is applied, then the chip 600 relaxes back to its original state, thus the memory fades.

[0065] The chip 600 can be used for neuromorphic computing. One of the key criteria of a neuromorphic chip is to exhibit short-term or fading memory over a short time duration after the neuron activation (either via spiking or electrical stimulation). The chip 600, made of permalloy honeycomb lattice 602 (shown in Figure 6) with parallel current / voltage inputs, depicts that. When randomly selected sequences without any time delay between them are run on the chip 600. The randomly selected sequences basically refer to no orderly encoding of 300 nano-second pulse inputs e.g. 1, 2, 3 etc. in terms of binary combinations (1 would correspond to 000000000001, 2 would correspond to 000000000010 etc.). An example of random selection can be 12, 4096, 255 etc. As shown in Figure 9A, all three sets of readouts (generated by three randomly selected sequences, instead of orderly sequences), are different from each other. On the other hand, if a time delay of, say 10 micro-seconds, is introduced between the same randomly selected series with 300 nano-second pulse inputs, then all three sets of readouts are more of less same, as shown in Figure 9B. This shows that the chip 600 has a short-term memory of the order of micro-seconds. In other words, when the 300 nano-second pulse inputs are encoded without time delay, then the system already remembers the previous encoding when responding to the next input encoding. Hence, the readouts are different from each other as the random nature of input encoding affects the intrinsic magnetic state of the honeycomb material. But when subjected to a short-time delay between the pulsed inputs, the honeycomb lattice 602 relaxes back to the original state before responding to the next input. Thus, the chip 600 exhibits the short-term memory which fades over a time scale of few microseconds.

[0066] The chip 600 can be used for pattern recognition and time-series prediction. Information is encoded to the sample through the chip’s channels, as shown in Figure 6. Each channel is digital and can take only two values (e.g., 1 and 0). For a chip 600 with N input channels 605, this gives 2Nset of combinations that can be used as inputs.Thus, a simple way to encode information is to use their binary representation. In a standard dataset, such as MNIST, pixels store values that range from 0 to 255. So, the first channel 605 would correspond to the first least significant bit of the pixel’s value, the second channel 605 would correspond to the second least significant bit of the pixel’s value, and so on.

[0067] The voltage is probed with respect to the ground at various location on the surface of the sample to determine the magnetic “state” which corresponds to both the history of the past inputs as well as the current combination. By using the simplest preprocessing method for a NxN image (e.g. , flatting the image and passing pixels sequentially), the system obtains N2number of voltages, where each measurement corresponds to a particular pixel. Since there are multiple voltage probes on the chip 600 (given by number M), the total number of readouts is MxN2. Finally, the system converts the readout matrix to a 1 -dimensional vector that is passed to a Logistic regression model or neural network. To improve the accuracy in prediction, the system further implements block sequencing methods. In that scheme, the pixels in the standard dataset image are grouped into small blocks (e.g., 3 by 3 or 4 by 4 regions) before fed into the chip. This improved the accuracy score compared to using rows or columns.

[0068] After grouping the data into blocks, the system inputs each pixel to the chip 600 using a novel method, called thermometer encoding of input. Thermometer encoding maps an integer to a sequence of 1’ s. The larger the value, the longer the sequence of 1’ s. The advantage of using this type of encoding is that the transition between one integer to another is smoother (For example, if using 12 channels to encode a value between 0 and 255, 25 would be converted to 000000000001, 45 to 000000000011, 145 as 000001111111, etc.

[0069] The principle is simple. One must first decide the maximum integer that needs to be encoded, as well as the number of channels. Then, the system gets a set of thresholds. If there are N channels, the system uses N thresholds. The value of each threshold is calculated using the following equation:

[0070] Figure 10A illustrates binary encoding of a MNIST standard dataset to the chip 600 (shown in Figure 6) in accordance with at least one embodiment. Morespecifically, a binary encoding of a handwritten digit 1 from the MNIST dataset (Modified National Institute of Standards and Technology). Figure 10B illustrates a confusion matrix of the classification accuracy for MNIST standard dataset based on the chip readouts for the binary encoding shown in Figure 10 A. The confusion matrix in 10B shows -92% in the classification of the MNIST dataset by the chip 600.

[0071] The MNIST data set consists of 60,000 low resolution images of hand-written digits from 0-9. So, each digit has 6,000 images. Each image consists of 28x28 pixels. Similarly, the Fashion-MNIST dataset consists of 60,000 low resolution images of fashion items e.g., pants, hats, shirts, etc. Both MNIST and Fashion-MNIST are greyscale images with 28x28 pixels. Each pixel can have a value between 0 to 255.

[0072] The chip 600 performs really well against MNIST and Fashion- MNIST dataset classification. The chip 600 obtains an accuracy of 92% and 88% in the classification of MNIST and Fashion-MNIST datasets, respectively. The encoding of MNIST data and confusion matrix are shown in Figures 10A and 10B, respectively. In both cases, the system cam either use logistic regression or neural network with very few layers. The accuracy remains similar in both cases (logistic regression or neural network) or a little bit better by using two or three layers of neural networks. This provides the proof of concept of the use of the systems and methods described herein for use as neuromorphic hardware.

[0073] To test image MNIST dataset classification, the system used the following procedures. First, each image (originally 28x28 pixels) was reduced to a smaller binary format, then broken down into segments. Second, each segment is converted into a 12-bit binary sequence, which is sent to the chip 600 in a time-multiplexed fashion — one segment at a time. Third, for each segment, the readout voltage of the chip 600 is recorded. This process results in a feature vector composed of all readout voltages over the time series of the input. And fourth, the readout data is fed to a logistic regression model for training and classification of the 10 MNIST digit classes. This setup allows the magnetic device to act as a temporal processor of spatial image information, exploiting short-term memory and interference effects to enrich the representation. Temperature encoding works in similar fashion and yields similar accuracy.

[0074] Figure 11 illustrates a graph of normalized readout data from the chip 600 (shown in Figure 6) and predicted behavior for Mackey-Glass chaotic time-series.More specifically, Figure 11 illustrates a Mackey-Glass time series, Mackey-Glass is a chaotic time-series constructed from the following differential equation:where x(t) is the variable of interest (time series), T is the time delay (controlling the level of chaos, and ft, y, and n are parameters defining the dynamics of the system.By taking advantage of the high-nonlinearity as well as the short-term memory behavior exhibited by the chip, it can predict the next value in the sequence of the chaotic time-series following a training. For this task, the thermometer encoding performs much better than direct binary mapping. So, after converting the time-series to “thermometer” values, the system passes them sequentially and measure the voltage for each of them. The result is a N by M matrix, where N is the number of sequential values, and M is the number of voltage probes. This matrix can be flattened and passed to a Linear Regression model to make a prediction for the next value. The longer the sequence, the better the model performs. The system obtains very high accuracy, ranging from 95% to 98% (depending on the prior input history), in the Mackey-Glass test on the chip 600 as shown in Figure 11. It further confirms the neuromorphic capability of the chip 600.ADDITIONAL CONSIDERATIONS

[0075] Example embodiments of honeycomb lattice systems and methods are described above in detail. The systems and methods are not limited to the specific embodiments described herein, but rather, components of the system and methods may be used independently and separately from other components described herein. For example, the honeycomb lattices described herein may be used with other honeycomb lattices to generate algebraic logic units.

[0076] As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to “example” or “one example” of the present disclosure are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features. Further, to the extent that terms “includes,” “including,” “has,” “contains,” and variants thereof are usedherein, such terms are intended to be inclusive in a manner similar to the term “comprises” as an open transition word without precluding any additional or other elements.

[0077] Furthermore, as used herein, the term “real-time” refers to at least one of the time of occurrence of the associated events, the time of measurement and collection of predetermined data, the time to process the data, and the time of a system response to the events and the environment. In the examples described herein, these activities and events occur substantially instantaneously.

[0078] The patent claims at the end of this document are not intended to be construed under 35 U.S.C. § 112(f) unless traditional means-plus-function language is expressly recited, such as “means for” or “step for” language being expressly recited in the claim(s).

[0079] This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.

Claims

WHAT IS CLAIMED IS:

1. A computing element comprising: an artificial lattice comprising a multiplicity of connecting elements separated by pores; a plurality of input channels attached to the artificial lattice each configured to provide at least one of an electrical current and voltage to the artificial lattice; a plurality of readout channels attached to the artificial lattice, wherein each readout channel of the plurality of readout channels is connected to a common ground; and one or more sensing elements positioned at least one of perpendicular and along to the plurality of input channels and attached to the artificial lattice, wherein the one or more sensing elements configured to read a readout to create an output.

2. The computing element of Claim 1, wherein the readout is at least one of a voltage, a current, and a resistance.

3. The computing element of Claim 1, wherein the artificial lattice is a honeycomb lattice, wherein the multiplicity of connecting elements separated by hexagonal cylindrical pores.

4. The computing element of Claim 1, wherein artificial lattice is comprised of connecting elements, wherein a length of the connecting element is 11 nm in length, wherein a width is 4 nm, and wherein a thickness is between 5 and 10 nm.

5. The computing element of Claim 4, wherein the connecting elements is made of an alloy, permalloy of Nio.8iFeo.19.

6. The computing element of Claim 1, wherein a number of the plurality of input channels is equal to or larger than a number of the plurality of readout channels.

7. The computing element of Claim 1 further comprising a microprocessor device in communication with the one or more sensing elements, wherein the microprocessor device is configured to send electrical signals for different settings of the plurality of input channels.

8. The computing element of Claim 7, wherein the microprocessor is further configured to collect the readout voltages / currents / resistances based on the one or more sensing elements and use machine learning to generate outputs.

9. The computing element of Claim 1, wherein a plurality of sensing locations are positioned at a plurality of locations on the artificial lattice.

10. The computing element of Claim 1, wherein the artificial lattice is magnetic.

11. The computing element of Claim 1, wherein the artificial lattice is non-magnetic.

12. The computing element of Claim 1, wherein the computing element retains information for a period of time after activation.

13. The computing element of Claim 1, wherein the computing element is used as a neuromorphic chip.

14. The computing element of Claim 1, wherein for N input channels provides 2Ndigital inputs and 2Nreadouts.

15. A computer device comprising at least one processor in communication with at least one memory device, wherein the at least one processor is programmed to: receive signals from one or more sensing elements attached to an artificial lattice comprising a multiplicity of connecting elements separated by pores; analyze the signals to determine a readout from the artificial lattice, wherein the signals are electrical signals measured by the one or more sensing elements; and analyze a database of signals and readouts to determine an input to the artificial lattice corresponding to a readout.

16. The computer device of Claim 15, wherein the at least one processor is further programmed to:receive a plurality of electrical readouts from the artificial lattice corresponding to a plurality of electrical inputs into a plurality of input channels attached to the artificial lattice; determine correlations between each of the plurality of electrical readouts and each of the plurality of inputs; and generate a database of signals based on the plurality of inputs, the plurality of electrical readouts, and the plurality of correlations.

17. The computer device of Claim 16, wherein the at least one processor is further programmed to use machine learning to determine outputs based on the readouts from one or more sensing elements.

18. The computer device of Claim 16, wherein for N input channels provides 2Nanalog inputs and 2Nreadouts.

19. The computer device of Claim 15, wherein the readout is at least one of a voltage, a current, and a resistance.

20. The computer device of Claim 15, wherein a plurality of input channels are attached to the artificial lattice and each configured to provide a current to the artificial lattice.

21. The computer device of Claim 20, wherein the one or more sensing elements are positioned perpendicular to the plurality of input channels and attached to the artificial lattice, wherein the one or more sensing elements configured to read a readout voltage.

22. The computer device of Claim 15, wherein the artificial lattice is a honeycomb lattice, wherein the multiplicity of connecting elements separated by hexagonal cylindrical pores.

23. The computer device of Claim 15, wherein artificial lattice is comprised of connecting elements, wherein a length of the connecting element is 11 nm in length, wherein a width is 4 nm, and wherein a thickness is between 5 and 10 nm.

24. The computer device of Claim 21, wherein the connecting elements is made of an alloy, permalloy of Nio.8iFeo.19.

25. The computer device of Claim 15, wherein the artificial lattice retains information for a period of time after activation.

26. The computer device of Claim 15, wherein the artificial lattice is used as a neuromorphic chip.

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