Neuromorphic chip compiling method and compiling system

Abstract

Disclosed are a neuromorphic chip compiling method and compiling system. The compiling method comprises: acquiring a pre-trained model and a data set of a neuromorphic application; generating an initial neuromorphic chip architecture and a network spiking input; performing an optimization and adjustment operation, performing simulation, and evaluating performance; and determining whether an optimization objective is satisfied, and performing loop optimization until an optimal neuromorphic chip architecture is obtained. In the method, by means of iterative optimization and effective evaluation, an optimal neuromorphic chip architecture is efficiently explored in a vast design space, thereby improving design quality and efficiency. The present application further provides a corresponding compiling system, comprising a generator, a simulator, and a compiler, thereby achieving automated compilation and deployment, and providing support for the design of large-scale multi-core neuromorphic chips.

Description

Compilation methods and compilation systems for neuromorphic chips Technical Field

[0001] This application relates to the field of computer technology, and in particular to compilation methods and compilation systems for neuromorphic chips. Background Technology

[0002] In recent years, with the rapid development of artificial intelligence technology, neuromorphic computing, which simulates the structure and function of the human brain, has attracted much attention. As the core of neuromorphic computing, neuromorphic chips have shown great potential in achieving high-energy-efficiency and low-latency intelligent computing. Especially in resource-constrained scenarios requiring real-time response, neuromorphic chips have broad application prospects.

[0003] Neuromorphic chips are commonly used to implement spiking neural networks (SNNs), which are artificial neural network models that more closely resemble the working principles of biological nervous systems. Compared to traditional artificial neural networks, SNNs have significant advantages in information processing and energy efficiency. However, efficiently deploying SNN algorithms on neuromorphic chips faces numerous challenges.

[0004] In particular, with the increasing scale of applications, the design space of neuromorphic chips has expanded dramatically. Traditional manual design methods are struggling to cope with such a vast design space and cannot effectively explore and optimize chip architecture. Neuromorphic compilation and optimization techniques are gradually becoming a bottleneck hindering the wider development and application of neuromorphic chips. Summary of the Invention

[0005] This application proposes a compilation method and system for neuromorphic chips to achieve automated deployment of complex, large-scale neuromorphic applications and multi-objective optimization of neuromorphic chip architecture.

[0006] According to one embodiment of this application, a method for compiling a neuromorphic chip is proposed, comprising: acquiring a pre-trained model and a dataset for a neuromorphic application; generating an initial neuromorphic chip architecture for the neuromorphic application based on the pre-trained model, and generating network impulse input based on the dataset; performing optimization and adjustment operations on the initial neuromorphic chip architecture; applying the network impulse input to the neuromorphic chip architecture and performing simulation to obtain simulation results; evaluating the performance of the neuromorphic chip architecture based on the simulation results and generating an evaluation index value; if the evaluation index value does not meet a preset optimization target, repeating the optimization and adjustment, the simulation, and the evaluation steps until the obtained evaluation index value meets the optimization target; and outputting a neuromorphic chip architecture that meets the optimization target for deployment.

[0007] In some possible implementations, generating an initial neuromorphic chip architecture for the neuromorphic application based on the pre-trained model includes: dividing the neurons in the pre-trained model into multiple partitions according to a preset partitioning strategy; and mapping the multiple partitions to the processing units of the neuromorphic chip architecture according to a preset mapping strategy.

[0008] In some possible implementations, the method further includes at least one of the following: setting the partitioning strategy based on the pre-trained model, application scenario, and hardware platform, wherein the partitioning strategy includes a weighted combination of one or more of the following strategies: minimum number of partitions strategy, balanced number of partitions strategy, minimum global communication traffic between partitions strategy, balanced global and local communication traffic between partitions strategy, independent partitioning strategy for a single network layer, mixed partitioning strategy for multiple network layers, and balanced number of neurons within a partition strategy; or setting the mapping strategy based on the pre-trained model, application scenario, and hardware platform, wherein the mapping strategy includes a weighted combination of one or more of the following strategies: minimum communication traffic strategy, communication load balancing strategy, shortest critical path strategy, minimum peak power consumption strategy, minimum average power consumption strategy, deadlock avoidance strategy, and critical link aging delay strategy.

[0009] In some possible implementations, the method further includes: validating the generated network pulse input, wherein the validation includes one or more of the following: format checking, used to verify whether the format of the data in the network pulse input conforms to a predefined standard; time consistency checking, used to ensure that the timestamps of the pulse sequence in the network pulse input are correct and ordered; frequency analysis, used to verify whether the pulse frequency in the network pulse input is within the expected range; statistical characteristic analysis, used to check whether the pulse distribution in the network pulse input conforms to the expected statistical characteristics; encoding consistency checking, used to ensure that the pulse encoding method in the network pulse input is consistent with the requirements of the pre-trained model; or network structure consistency checking, used to ensure that the network structure in the network pulse input is consistent with the structure of the pre-trained model.

[0010] In some possible implementations, the method further includes: determining the optimization adjustment operation based on a top-level control optimization strategy, wherein the top-level control optimization strategy includes at least one of the following: a nonlinear optimization method, a heuristic search method, a reinforcement learning method, a deep learning method, or a large language model method.

[0011] In some possible implementations, the optimization and adjustment operations include performing one or more of the following sequentially in a set order: adjusting the partitioning of neurons in the pre-trained model between partitions; adjusting the mapping position of partitions to the processing units of the initial neuromorphic chip architecture; adjusting the routing and topology strategies of the on-chip network in the initial neuromorphic chip architecture; balancing the communication load of the on-chip network in the initial neuromorphic chip architecture; and adjusting the communication arbitration priority of the on-chip network in the initial neuromorphic chip architecture.

[0012] In some possible implementations, the evaluation metric values ​​include a weighted average of one or more of the following: power consumption, inference / training speed, or chip area.

[0013] In some possible implementations, the neuromorphic application is an application of a spiking neural network.

[0014] According to one embodiment of this application, a brain-inspired chip compilation system is also proposed, comprising: a generator, configured to receive a pre-trained model and a dataset, generate an initial brain-inspired chip architecture for the brain-inspired application based on the pre-trained model, and generate network impulse inputs based on the dataset; a simulator, configured to receive the brain-inspired chip architecture and the network impulse inputs, and perform simulation by applying the network impulse inputs to the brain-inspired chip architecture to obtain simulation results; and a compiler, configured to receive the simulation results, evaluate the performance of the brain-inspired chip architecture based on the simulation results, generate evaluation index values, output brain-inspired chip architectures whose evaluation index values ​​meet a preset optimization objective as the optimal brain-inspired chip architecture, perform optimization adjustment operations on brain-inspired chip architectures whose evaluation index values ​​do not meet the optimization objective, and output the optimized brain-inspired chip architectures to the simulator for further simulation.

[0015] In some possible implementations, the generator includes: an architecture generation module, configured to divide neurons in the pre-trained model into multiple partitions according to a preset partitioning strategy, and to map the multiple partitions to the processing units of the neuromorphic chip architecture according to a preset mapping strategy; and an input generation module, configured to generate network impulse inputs based on the dataset.

[0016] In some possible implementations, the compiler includes: an evaluator for evaluating the performance of the neuromorphic chip architecture based on the simulation results and generating evaluation index values; an optimizer for performing optimization adjustments on the neuromorphic chip architecture and outputting the optimized neuromorphic chip architecture to the simulator; and a controller for determining whether the evaluation index values ​​meet the optimization objective, controlling the optimizer to perform optimization adjustments on neuromorphic chip architectures whose evaluation index values ​​do not meet the optimization objective, and outputting neuromorphic chip architectures whose evaluation index values ​​meet the optimization objective as the optimal neuromorphic chip architecture.

[0017] In some possible implementations, the optimization and adjustment operations include performing one or more of the following in a predetermined order: adjusting the partitioning of neurons in the pre-trained model between partitions; adjusting the mapping position of partitions to the processing units of the initial neuromorphic chip architecture; adjusting the routing and topology strategies of the on-chip network in the initial neuromorphic chip architecture; balancing the communication load of the on-chip network in the initial neuromorphic chip architecture; or adjusting the communication arbitration priority of the on-chip network in the initial neuromorphic chip architecture.

[0018] In some possible implementations, the controller employs a top-level control optimization strategy to determine the optimization adjustment operation, the top-level control optimization strategy including at least one of the following: nonlinear optimization method, heuristic search method, reinforcement learning method, deep learning method, and large language model method.

[0019] In some possible implementations, the generator, the compiler, and the simulator are deployed on three different computing platforms.

[0020] The neuromorphic chip compilation method and compilation system proposed in this application have the following significant advantages:

[0021] First, by automatically compiling and deploying complex neuromorphic applications onto neuromorphic chips, deployment efficiency and flexibility are significantly improved. The process of converting pre-trained models to chip architecture is handled automatically, effectively reducing the need for manual intervention and enabling rapid deployment even for complex, large-scale neuromorphic applications. Second, by employing iterative optimization methods, combined with simulation evaluation and various optimization operations, the system can effectively explore a vast design space to find the optimal neuromorphic chip architecture that meets specific application requirements. This not only improves the quality of chip design but also significantly shortens the design cycle. Furthermore, by introducing evaluation metrics and optimization objectives, comprehensive optimization of neuromorphic chip performance is achieved, allowing the final chip architecture to better balance various performance indicators and adapt to the needs of different application scenarios. In addition, the automation and scalability of the technical solution in this application provide strong support for the design of large-scale multi-core neuromorphic chips, contributing to the application and development of neuromorphic computing technology in a wider range of fields. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0023] Figure 1 shows a flowchart of a method for compiling a neuromorphic chip according to an embodiment of this application.

[0024] Figure 2 shows a structural block diagram of a compilation system for a neuromorphic chip according to an exemplary embodiment of this application.

[0025] Figure 3 shows a structural block diagram of a compilation system for a neuromorphic chip according to an exemplary embodiment of this application. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0027] The embodiments of this application can be applied to computer systems / servers that can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with computer systems / servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems, etc.

[0028] Computer systems / servers can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are performed by remote processing devices linked through a communication network. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0029] One aspect of this application provides a method for compiling a neuromorphic chip. This method can effectively and automatically compile and deploy complex neuromorphic applications onto the neuromorphic chip, and achieve multi-objective optimization of the chip architecture during the compilation process. The technical solution of this application will be described in detail below with reference to specific embodiments.

[0030] Figure 1 shows a flowchart of a method for compiling a neuromorphic chip according to an embodiment of this application. As shown in the figure, the method includes steps 1 to 6.

[0031] Step 1: Obtain the pre-trained model and dataset for the neuromorphic application.

[0032] In one embodiment of this application, the neuromorphic application is the implementation of spiking neural networks (SNNs). SNNs are artificial neural network models that more closely resemble the working principles of biological nervous systems, offering significant advantages in information processing and energy efficiency.

[0033] The process of obtaining a pre-trained model includes importing the network checkpoint file (ckpt) of the spiking neural network. The ckpt file contains all the parameter states of the SNN at a specific training stage, serving as a snapshot of the network during training. By reading the ckpt file, key information such as the network weights can be extracted. This information defines the strength of connections between neurons and the overall structure of the network, which can be used for subsequent architecture generation and optimization.

[0034] Simultaneously, a task dataset corresponding to the SNN model can be obtained. The dataset typically contains input data for a specific task (such as image classification, speech recognition, etc.). Those skilled in the art will understand that the selection of the dataset should match the task type of the pre-trained model to ensure that the subsequently generated network impulse inputs accurately reflect the actual application scenario.

[0035] Step 2: Generate an initial neuromorphic chip architecture based on the pre-trained model, and generate network pulse input based on the dataset.

[0036] This step consists of two main parts: generating the initial neuromorphic chip architecture and generating network impulse inputs.

[0037] According to one embodiment of this application, generating an initial neuromorphic chip architecture based on a pre-trained model mainly includes the following two sub-steps: dividing the neurons in the pre-trained model into multiple partitions according to a preset partitioning strategy; and mapping the multiple partitions to the processing units of the neuromorphic chip architecture according to a preset mapping strategy.

[0038] Setting a partitioning strategy can comprehensively consider the characteristics of the pre-trained model, the target application scenario, and the hardware platform. The partitioning strategy adopted in the implementation of this application can include one or a weighted combination of the following strategies: a minimum number of partitions strategy, primarily aimed at reducing communication overhead, suitable for scenarios with high communication costs; a balanced number of partitions strategy, used to ensure uniform distribution of computational load, suitable for hardware platforms with strong parallel computing capabilities; a minimum global communication traffic strategy between partitions, primarily aimed at reducing cross-partition communication and improving overall efficiency; a balanced global and local communication traffic strategy within partitions, primarily aimed at seeking a balance between global and local communication, suitable for complex network structures; a single network layer independent partitioning strategy, used to ensure that the network structure layers of neuromorphic applications are divided into the same partition, suitable for large and complex network structures to improve architecture performance; a multi-network layer hybrid partitioning strategy, used to allow multiple network structure layers of neuromorphic applications to be mixed and divided into the same partition, suitable for small and medium-sized network structures to improve resource utilization efficiency; and a balanced number of neurons within a partition strategy, primarily aimed at isomorphizing each partition and balancing the resource utilization and performance of each partition.

[0039] Those skilled in the art will understand that these strategies can be used individually or in combination through weighted synthesis to suit different needs.

[0040] For example, consider deploying a pre-trained SNN model for image classification onto a neuromorphic chip with 16 processing elements (PEs). This SNN model contains one input layer, two hidden layers, and one output layer, totaling 10,000 neurons. According to this application, considering the application scenario and hardware platform, the following partitioning strategies can be set: Balanced partition number strategy (weight 0.4); Minimum global communication traffic between partitions strategy (weight 0.4); Minimum partition number strategy (weight 0.2).

[0041] Based on the above partitioning strategy, the network can be partitioned as follows: First, the network is initially divided into 16 partitions, each containing approximately 625 neurons, to satisfy the partition number balance strategy. Then, the connections between neurons are analyzed, and tightly connected neurons are organized within the same partition as much as possible to reduce inter-partition communication. For example, the neurons in the input layer might be mainly distributed to the first few partitions, the neurons in the hidden layer to be dispersed in the middle partitions, and the neurons in the output layer to be concentrated in the last few partitions, thus satisfying the strategy of minimizing global communication traffic between partitions. Finally, it may be found that some partitions have very few neurons, in which case these partitions can be merged into adjacent partitions, ultimately resulting in 14 partitions instead of 16, which to some extent satisfies the partition number minimization strategy without significantly affecting the balance.

[0042] The mapping strategy setting in the second sub-step can also comprehensively consider the pre-trained model, application scenario, and hardware platform. The mapping strategy adopted in the implementation of this application may include one or a weighted combination of the following strategies: a minimum communication traffic strategy, mainly aimed at reducing data transmission between processing units; a communication load balancing strategy, mainly aimed at ensuring a relatively balanced communication burden among processing units; a shortest critical path strategy, mainly aimed at optimizing critical computation paths and improving overall response speed; a minimum peak power consumption strategy and a minimum average power consumption strategy, mainly aimed at considering energy consumption factors and suitable for power-sensitive scenarios; a deadlock avoidance strategy, mainly aimed at ensuring the stable operation of the compilation system; and a critical link aging delay strategy, mainly aimed at considering hardware lifespan and improving the long-term reliability of the compilation system.

[0043] Those skilled in the art will understand that these mapping strategies can also be used individually or in combination through weighted synthesis.

[0044] Continuing with the examples above, let's illustrate mapping strategies. For instance, you could set the following mapping strategies: Minimum communication traffic strategy (weight 0.5); Load balancing strategy (weight 0.3); Minimum power consumption strategy (weight 0.2).

[0045] Based on the above mapping strategy, the following mapping results can be obtained: First, frequently communicating partitions are mapped to physically adjacent PEs. For example, partitions containing input layer neurons may be mapped to PEs near the chip edge because these partitions need to directly receive external input. Then, considering the computational load of each partition (e.g., which can be determined by the number of neurons and activation frequency), high-load partitions and low-load partitions are mapped to PEs alternately to achieve load balancing. Finally, considering the power consumption characteristics of some PEs (e.g., PEs in the chip center may be easier to dissipate heat), highly active partitions are mapped to these PEs to optimize overall power consumption.

[0046] The above mapping strategy minimizes communication while also considering load balancing and power consumption optimization.

[0047] Another key part of this step—generating network impulse input based on the dataset—is the process of converting regular input data into impulse sequences that can be processed by the SNN. This process typically involves specific encoding schemes, such as frequency encoding or time encoding.

[0048] According to this application, after generating network pulse input, a series of checks can be performed to ensure the quality and validity of the generated pulse input. The checks employed in the implementation of this application may include one or more of the following: format check: verifying whether the format of the pulse input data conforms to a predefined standard; time consistency check: ensuring that the timestamps of the pulse sequence are correct and ordered; frequency analysis: verifying whether the pulse frequency is within the expected range; statistical characteristic analysis: checking whether the pulse distribution conforms to the expected statistical characteristics; encoding consistency check: ensuring that the pulse encoding method is consistent with the requirements of the pre-trained model; and network structure consistency check, used to ensure that the network structure is consistent with the structure of the pre-trained model.

[0049] By verifying the network impulse input, it is ensured that the generated network impulse input can accurately reflect the characteristics of the original dataset and is compatible with the pre-trained model and the obtained neuromorphic chip architecture.

[0050] Step 3: Perform optimization and adjustment operations on the currently obtained neuromorphic chip architecture.

[0051] After the initial neuromorphic chip architecture is generated, it can be optimized and adjusted to further improve performance, reduce power consumption, and optimize resource utilization. The optimization and adjustment operation is one of the core steps in the compilation method proposed in this application. It automatically improves the neuromorphic chip architecture through a series of operations, making it better suited to the target application and hardware platform.

[0052] According to some implementations, the optimization and adjustment operations include performing one or more of the following in a set order: adjusting the division of neurons between partitions; adjusting the mapping position of partitions to the processing units of the neuromorphic chip architecture; adjusting the routing and topology strategies of the on-chip network in the neuromorphic chip architecture; balancing the communication load of the on-chip network in the neuromorphic chip architecture; and adjusting the communication arbitration priority of the on-chip network in the neuromorphic chip architecture.

[0053] Adjusting the partitioning of neurons between partitions can be used to re-evaluate and refine the initial partitioning results. For example, it might be found that communication overhead between some partitions is too high. In this case, one could try reassigning neurons that communicate frequently to the same partition, or splitting overloaded partitions into multiple smaller partitions.

[0054] Adjusting the mapping of partitions to the processing units of the neuromorphic chip architecture is used to rearrange the distribution of partitions across physical processing units. For example, if some processing units are found to be underutilized or overutilized, the partition mapping can be readjusted to achieve better load balancing.

[0055] The performance of Network-on-Chip (NoC) has a significant impact on the overall system efficiency. By adjusting the routing and topology strategies of the Network-on-Chip in a neuromorphic chip architecture, the routing algorithm of data packets can be changed, or the topology of the NoC can be adjusted to reduce communication latency and improve throughput.

[0056] Balancing the communication load of on-chip networks in neuromorphic chip architectures can help avoid network congestion and hotspots. For example, partitions with high communication demand can be reallocated, or data flow patterns can be adjusted to distribute the communication load.

[0057] Adjusting the communication arbitration priority of the on-chip network in the neuromorphic chip architecture can optimize the allocation of network resources. For example, higher transmission priority can be assigned to packets on the critical path to reduce overall latency.

[0058] The optimization process is typically managed by a controller within the compiler. The controller can employ a top-level control optimization strategy to determine how to execute the aforementioned optimization operations. The top-level control optimization strategy employed according to the embodiments of this application may include one or more of the following methods used alone or in combination: nonlinear optimization methods, heuristic search methods, reinforcement learning methods, deep learning methods, and large language model methods.

[0059] Nonlinear optimization methods are mainly used to handle complex, nonlinear optimization problems.

[0060] Heuristic search methods, such as simulated annealing and genetic algorithms, are used to quickly find approximate optimal solutions in large-scale search spaces.

[0061] Reinforcement learning methods are used to learn optimal policies through interaction with the environment, and are particularly suitable for dynamically changing optimization problems.

[0062] Deep learning methods refer to the use of neural networks to learn complex optimization strategies.

[0063] The large language model approach refers to using the reasoning capabilities of large-scale language models to guide optimization decisions.

[0064] These methods can be used individually or in combination. For example, reinforcement learning can be used to control the overall optimization process while heuristic search methods are applied to specific optimization operations.

[0065] The process of controller management and optimization adjustment operations is illustrated using reinforcement learning as an example. In this example, the controller can act as an agent in reinforcement learning, the current architecture state and evaluation metric value constitute the environment state, the selection of optimization operations is regarded as an action, and the degree of improvement in the evaluation metric value can be used as a reward signal.

[0066] In this way, the controller can learn more effective optimization strategies and make smarter decisions during the optimization process.

[0067] By optimizing and adjusting the operation, the neuromorphic chip architecture has been improved, providing an optimized architecture for subsequent simulation and evaluation, which is very helpful in finding a solution closer to the optimal solution in a huge design space.

[0068] Step 4: Apply the network pulse input to the optimized neuromorphic chip architecture, perform simulation and obtain simulation results, evaluate the performance of the optimized neuromorphic chip architecture based on the simulation results, and generate evaluation index values.

[0069] Before starting the simulation, you can prepare the neuromorphic architecture configuration file and the corresponding network impulse input required for the simulation process.

[0070] Specifically, a configuration file describing the neuromorphic chip architecture, optimized and adjusted in step 3, can be generated, containing information such as neuron distribution, connection topology, and processing unit configuration. During the iteration process, the network input pulse data generated in step 2 can remain largely unchanged, but it may be necessary to make minor format adjustments or reorganizations of the network input pulses according to the current optimized and adjusted neuromorphic chip architecture to ensure better adaptation to the new architecture.

[0071] The simulation process can be performed in a simulator. The simulator can receive the neuromorphic architecture configuration file and the corresponding network impulse input, and perform system-level simulation to simulate the overall behavior of the neuromorphic chip architecture, including neuronal activation, synaptic transmission, and on-chip network communication, and then output the simulation results.

[0072] During the simulation, the processing of network pulse inputs on the neuromorphic chip architecture is simulated, and various related data are recorded.

[0073] After the simulation is complete, the simulator will output a series of raw simulation result data. This data may include, but is not limited to: the activation mode of each neuron, the timing information of synaptic transmission, the activity of the processing unit, the communication mode and load of the on-chip network, etc.

[0074] The simulation results are passed to the evaluator module in the compiler. The evaluator analyzes the data and assesses the performance of the neuromorphic chip architecture, for example, to obtain hardware power consumption per kilowatt-hour (PPA) evaluation metrics. In some implementations, the evaluation metrics may include a combined weighted value of one or more of the following: power consumption, inference / training speed, and chip area.

[0075] Power consumption can include static power consumption and dynamic power consumption, which reflects the energy efficiency of the architecture; inference / training speed (Performance) is used to indicate how fast the architecture processes input data, usually measured in the number of inferences / trainings per second; chip area (Area) reflects the resource utilization of the architecture and potential manufacturing costs.

[0076] Step 5: Determine whether the evaluation index value meets the preset optimization target. If the evaluation index value does not meet the optimization target, return to step 3 and repeat the optimization adjustment, simulation, evaluation and judgment steps until the optimal neuromorphic chip architecture in which the evaluation index value meets the optimization target is obtained.

[0077] Step 5 is the core control link of the entire compilation and optimization process. By judging whether the evaluation index value meets the preset optimization target, it is determined whether the optimization and adjustment process for the neuromorphic chip architecture needs to continue or has already achieved the expected optimization target.

[0078] The controller module in the compiler can receive an evaluation metric value from the evaluator. In one example, this metric value combines factors such as power consumption, speed, and area. The controller can then compare this metric value with a preset optimization target.

[0079] The optimization objectives may vary depending on the application scenario. For example, in resource-constrained scenarios, the focus may be on minimizing power consumption; in scenarios with high real-time processing requirements, the focus may be on improving speed; and in cost-sensitive applications, the focus may be on optimizing area. Multiple optimization objectives can be set simultaneously (e.g., two). If each optimization objective is met, the current neuromorphic chip architecture is determined to meet the preset optimization objectives.

[0080] The controller can make decisions based on the judgment results. If the evaluation index value meets the preset optimization goal, the optimization process ends and the current neuromorphic chip architecture is considered to be the optimal neuromorphic chip architecture. If the evaluation index value does not meet the preset optimization goal, the controller will instruct to return to step 3 and continue the iteration of optimization and adjustment.

[0081] When further optimization and adjustment are needed, steps 3 to 5 above can be repeated. Specifically, step 3 is executed to perform a new round of optimization and adjustment operations on the current neuromorphic chip architecture; step 4 is executed to perform simulation on the adjusted architecture, evaluate its performance and generate evaluation index values; then step 5 is executed again to determine whether the evaluation index values ​​meet the preset optimization goals.

[0082] The above iterative optimization process will be repeated continuously until a neuromorphic chip architecture whose evaluation index value meets the optimization goal is found, or the preset maximum number of iterations is reached.

[0083] In this application, by continuously improving the neuromorphic chip architecture until the optimal solution that meets the specific application requirements is found, the compilation system is allowed to effectively explore in a large design space, and finally obtain a high-performance neuromorphic chip architecture that meets the expectations in terms of power consumption, speed and area.

[0084] Step 6: Output the optimal neuromorphic chip architecture for deployment.

[0085] The output of the optimal neuromorphic chip architecture can include the neuron distribution, processing unit configuration, on-chip network topology, memory allocation, timing information, etc.

[0086] In some implementations, multiple optimal neuromorphic chip architectures that meet the optimization objective can be output as candidates for selection and deployment by the target neuromorphic chip. For example, the optimal neuromorphic chip architecture with the highest and second-highest accuracy that meets the optimization objective can be output as a candidate architecture for the target neuromorphic chip, thereby increasing the flexibility of the final selection.

[0087] The compiler can send the optimal neuromorphic chip architecture to the target neuromorphic chip through a suitable communication interface.

[0088] In some examples, after receiving the optimal neuromorphic chip architecture, the neuromorphic chip can initiate the optimal neuromorphic chip architecture parsing, configure the chip's various components according to the parsed content, and initialize the chip state, thereby transforming the neuromorphic chip architecture generated and compiled and optimized according to this application from theoretical design into a practically usable hardware configuration.

[0089] The neuromorphic chip compilation method proposed in this embodiment enables the automated compilation and deployment of complex, large-scale neuromorphic applications onto neuromorphic chips, significantly improving deployment efficiency and flexibility. By employing an iterative optimization approach, combined with simulation evaluation and various optimization operations, this method can effectively explore a vast design space to find the optimal neuromorphic chip architecture that meets specific application requirements. This method not only improves the quality of chip design but also significantly shortens the design cycle. Furthermore, by introducing specific evaluation metrics and optimization objectives, such as power consumption, inference / training speed, and chip area, comprehensive optimization of neuromorphic chip performance is achieved, enabling the final chip architecture to better adapt to the needs of different application scenarios. Moreover, the automation and scalability of this neuromorphic chip compilation method provide strong support for the design of large-scale multi-core neuromorphic chips, contributing to the application and development of neuromorphic computing technology in a wider range of fields.

[0090] Another aspect of this application provides a compilation system for a neuromorphic chip. Figure 2 shows a structural block diagram of a compilation system for a neuromorphic chip according to an exemplary embodiment of this application. As shown, the compilation system includes a generator, a simulator, and a compiler.

[0091] The generator is used to receive a pre-trained model (e.g., a pre-trained SNN model) and a dataset, generate an initial neuromorphic chip architecture based on the pre-trained model, and generate network spike inputs based on the dataset.

[0092] In some implementations, the generator may include: an architecture generation module for generating an initial neuromorphic chip architecture based on a pre-trained model, including dividing neurons in the pre-trained model into multiple partitions according to a preset partitioning strategy, and mapping the multiple partitions to processing units of the neuromorphic chip architecture according to a preset mapping strategy; and an input generation module for generating network impulse inputs based on a dataset.

[0093] In the schematic diagram shown in Figure 2, the initial neuromorphic chip architecture generated by the generator is directly output to the simulator. In other embodiments, the initial neuromorphic chip architecture generated by the generator can be sent to the compiler for optimization and adjustment before being sent to the simulator for simulation. These embodiments are all within the protection scope of this application.

[0094] As shown in Figure 2, the simulator is used to receive neuromorphic chip architecture and network pulse input, perform simulation on the received neuromorphic chip architecture, and output the simulation results to the compiler.

[0095] The compiler receives the simulation results, evaluates the performance of the neuromorphic chip architecture based on the simulation results, generates evaluation index values, outputs the neuromorphic chip architecture whose evaluation index values ​​meet the preset optimization target as the optimal neuromorphic chip architecture, performs optimization adjustment operations on the neuromorphic chip architecture whose evaluation index values ​​do not meet the optimization target, and outputs the optimized neuromorphic chip architecture to the simulator for further simulation.

[0096] In the embodiment shown in Figure 2, the compiler may include an evaluator, an optimizer, and a controller.

[0097] The evaluator is used to assess the performance of the neuromorphic chip architecture based on the simulation results and generate evaluation index values.

[0098] The controller determines whether the evaluation metric value meets the optimization objective, controls the optimizer to perform optimization adjustments on neuromorphic chip architectures whose evaluation metric values ​​do not meet the optimization objective, and outputs neuromorphic chip architectures whose evaluation metric values ​​meet the optimization objective as the optimal neuromorphic chip architecture. In the embodiment shown in Figure 2, the controller determines that the evaluation metric value meets the optimization objective only if it simultaneously meets both optimization objective 1 and optimization objective 2. In the embodiment shown in Figure 2, the compiler outputs two optimal neuromorphic chip architectures—a first candidate architecture and a second candidate architecture—to increase the selectivity and flexibility of the final deployment.

[0099] In some implementations, the controller employs a top-level control optimization strategy to control the optimization adjustment operation. The top-level control optimization strategy may include one or more of the following methods used alone or in combination: nonlinear optimization method, heuristic search method, reinforcement learning method, deep learning method, and large language model method.

[0100] The optimizer performs optimization adjustments on the neuromorphic chip architecture based on the control of the controller, generating an optimized neuromorphic chip architecture and outputting it to the simulator. In some embodiments, the optimization adjustments include performing one or more of the following in a predetermined order: adjusting the partitioning of neurons between partitions; adjusting the mapping positions of partitions to processing units in the neuromorphic chip architecture; adjusting the routing and topology strategies of the on-chip networks in the neuromorphic chip architecture; balancing the communication load of the on-chip networks in the neuromorphic chip architecture; and adjusting the communication arbitration priority of the on-chip networks in the neuromorphic chip architecture.

[0101] For other details and advantages of this embodiment, please refer to the above description of the compilation method for neuromorphic chips, which will not be repeated here.

[0102] Figure 3 shows a structural block diagram of a compilation system for a neuromorphic chip according to an exemplary embodiment of this application. As shown in Figure 3, the generator, the compiler, and the simulator are deployed on three different computing platforms. These different computing platforms can be different nodes of a cloud computing platform, different parallel computing units, or different physical servers, etc.

[0103] By running the generator, compiler, and simulator on different computing platforms, it is possible to run different components simultaneously, improve the overall processing speed, and facilitate the flexible allocation of computing resources according to the needs of each component. It is also beneficial to expand the processing capabilities of each component and achieve fault isolation, thereby improving the efficiency, reliability, and scalability of the entire compilation system.

[0104] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the data processing device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0105] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0106] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.

[0107] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0108] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0109] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the protection scope of one or more embodiments of this specification.

Claims

1. A method for compiling a neuromorphic chip, characterized in that, include: Obtain pre-trained models and datasets for brain-like applications; Based on the pre-trained model, an initial neuromorphic chip architecture is generated for the neuromorphic application, and network impulse input is generated based on the dataset; Optimization and adjustment operations are performed on the neuromorphic chip architecture; The network pulse input is applied to the neuromorphic chip architecture, and simulation is performed to obtain simulation results. The performance of the neuromorphic chip architecture is evaluated based on the simulation results, and evaluation index values ​​are generated. If the evaluation index value does not meet the preset optimization target, the optimization adjustment, simulation, and evaluation steps are repeated until the obtained evaluation index value meets the optimization target. Output a neuromorphic chip architecture that meets the optimization objectives for deployment.

2. The method according to claim 1, characterized in that, Based on the pre-trained model, an initial neuromorphic chip architecture is generated for the neuromorphic application, including: According to a preset partitioning strategy, the neurons in the pre-trained model are divided into multiple partitions; According to a preset mapping strategy, the multiple partitions are mapped to the processing units of the neuromorphic chip architecture.

3. The method according to claim 2, characterized in that, The method further includes at least one of the following: Based on the pre-trained model, application scenario, and hardware platform, the partitioning strategy is set, which includes one or a weighted combination of the following strategies: minimum number of partitions, balanced number of partitions, minimum global communication traffic between partitions, balanced global and local communication traffic between partitions, independent partitioning strategy for a single network layer, hybrid partitioning strategy for multiple network layers, and balanced number of neurons within a partition; or The mapping strategy is set based on the pre-trained model, application scenario, and hardware platform. The mapping strategy includes one or more of the following strategies in a weighted combination: minimum communication traffic strategy, communication load balancing strategy, shortest critical path strategy, minimum peak power consumption strategy, minimum average power consumption strategy, deadlock avoidance strategy, and critical link aging delay strategy.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: The generated network pulse input is verified. The verification includes one or more of the following: Format checking is used to verify whether the format of the data in the network pulse input conforms to a predefined standard; A time consistency check is used to ensure that the timestamps of the pulse sequence in the network pulse input are correct and ordered; Frequency analysis is used to verify whether the pulse frequency in the network pulse input is within the expected range; Statistical characteristic analysis is used to check whether the pulse distribution in the network pulse input conforms to the expected statistical characteristics; A code consistency check is used to ensure that the pulse coding scheme in the network pulse input is consistent with the requirements of the pre-trained model; or A network structure consistency check is used to ensure that the network structure of the network impulse input is consistent with the structure of the pre-trained model.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The optimization and adjustment operations are determined based on the top-level control optimization strategy. The top-level control optimization strategy includes at least one of the following: Nonlinear optimization methods Heuristic search methods Reinforcement learning methods Deep learning methods, or Large language model approach.

6. The method according to any one of claims 2-5, characterized in that, The optimization and adjustment operations include performing one or more of the following sequentially in a set order: Adjust the partitioning of neurons in the pre-trained model; Adjust the mapping position of the partition to the processing unit of the initial neuromorphic chip architecture; Adjust the routing and topology strategies of the on-chip network in the initial neuromorphic chip architecture; Balance the communication load of the on-chip network in the initial neuromorphic chip architecture; Adjust the communication arbitration priority of the on-chip network in the initial neuromorphic chip architecture.

7. The method according to any one of claims 1-6, characterized in that, The evaluation index value includes one or more of the following weighted values: Power consumption Inference / training speed, or Chip area.

8. The method according to any one of claims 1-7, characterized in that, The neuromorphic application mentioned above refers to the application of spiking neural networks.

9. A compilation system for a neuromorphic chip, characterized in that, include: A generator is used to receive a pre-trained model and a dataset, generate an initial neuromorphic chip architecture for the neuromorphic application based on the pre-trained model, and generate network impulse inputs based on the dataset; A simulator is used to receive the neuromorphic chip architecture and the network pulse input, and to perform simulation by applying the network pulse input to the neuromorphic chip architecture to obtain simulation results; The compiler is used to receive the simulation results, evaluate the performance of the neuromorphic chip architecture based on the simulation results, generate evaluation index values, output the neuromorphic chip architecture whose evaluation index values ​​meet the preset optimization target as the optimal neuromorphic chip architecture, perform optimization adjustment operations on the neuromorphic chip architecture whose evaluation index values ​​do not meet the optimization target, and output the optimized neuromorphic chip architecture to the simulator for further simulation.

10. The system according to claim 9, characterized in that, The generator includes: An architecture generation module is used to divide the neurons in the pre-trained model into multiple partitions according to a preset partitioning strategy, and to map the multiple partitions to the processing units of the neuromorphic chip architecture according to a preset mapping strategy. An input generation module is used to generate network pulse inputs based on the dataset.

11. The system according to claim 9 or 10, characterized in that, The compiler includes: An evaluator is used to assess the performance of the neuromorphic chip architecture based on the simulation results and generate evaluation index values. An optimizer is used to perform optimization and adjustment operations on the neuromorphic chip architecture and output the optimized and adjusted neuromorphic chip architecture to the simulator; The controller is used to determine whether the evaluation index value meets the optimization objective, control the optimizer to perform optimization adjustment operations on the neuromorphic chip architecture whose evaluation index value does not meet the optimization objective, and output the neuromorphic chip architecture whose evaluation index value meets the optimization objective as the optimal neuromorphic chip architecture.

12. The system according to claim 10 or 11, characterized in that, The optimization and adjustment operations include performing one or more of the following sequentially in a set order: Adjust the partitioning of neurons in the pre-trained model; Adjust the mapping position of the partition to the processing unit of the initial neuromorphic chip architecture; Adjust the routing and topology strategies of the on-chip network in the initial neuromorphic chip architecture; Balance the communication load of the on-chip network in the initial neuromorphic chip architecture; or Adjust the communication arbitration priority of the on-chip network in the initial neuromorphic chip architecture.

13. The system according to claim 11, characterized in that, The controller uses a top-level control optimization strategy to determine the optimization adjustment operation. The top-level control optimization strategy includes at least one of the following: nonlinear optimization method, heuristic search method, reinforcement learning method, deep learning method, or large language model method.

14. The system according to any one of claims 10-13, characterized in that, The generator, the compiler, and the simulator are deployed on three different computing platforms.

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