Display panel and electronic device comprising same

Abstract

The objective of the present invention is to provide a display panel capable of displaying a high-quality image, and an electronic device comprising same, the display panel comprising: first transistors disposed adjacent to each other in a first direction; and a silicon semiconductor layer, which has a main part extending in the first direction and an extension part extending in a second direction intersecting the first direction, wherein, in a planar view, the extension part is interposed between the first transistors.

Description

Display panel and electronic device having the same

[0001] Embodiments of the present invention relate to a display panel and an electronic device having the same, and more particularly, to a display panel capable of displaying high-quality images and an electronic device having the same.

[0002] Display panels are used in a variety of electronic devices. To display high-quality images with higher resolution, pixel sizes are shrinking, necessitating the placement of various electronic components in a narrow area.

[0003] Conventional display panels and electronic devices equipped with them have a problem in that they cannot display high-quality images due to interference between various electronic elements placed in a narrow area.

[0004] The present invention aims to address various issues, including those described above, by providing a display panel capable of displaying high-quality images and an electronic device comprising the same. However, these tasks are exemplary and should not be construed as limiting the scope of the present invention.

[0005] According to one aspect of the present invention, a display panel is provided, which includes first transistors arranged adjacently along a first direction, a main portion extending along the first direction, and an extension portion extending in a second direction intersecting the first direction, and a silicon semiconductor layer in which the extension portion is interposed between the first transistors in a plan view.

[0006] Each of the above first transistors may have a first semiconductor layer and a first gate electrode positioned on the first semiconductor layer and overlapping the first semiconductor layer.

[0007] The above first semiconductor layer may include an oxide semiconductor.

[0008] A gate insulating layer covering the silicon semiconductor layer may be further provided, and the first semiconductor layer may be positioned on top of the insulating layer.

[0009] Capacitor electrodes may be further provided between the gate insulating layer and the first semiconductor layer and spaced apart from each other to correspond to the first transistors.

[0010] In the plan view, the extension portion may be interposed between the capacitor electrodes.

[0011] The end of the extension portion in the second direction may coincide with the end of the portion adjacent to the extension portion of each of the capacitor electrodes in the second direction.

[0012] Shielding layers may be further provided between the capacitor electrodes and the first transistors.

[0013] Each of the above shield layers can be electrically connected to a corresponding one of the above capacitor electrodes.

[0014] The device further comprises second transistors corresponding to the first transistors and data lines corresponding to the second transistors, each of the second transistors having one end electrically connected to a corresponding one of the data lines and the other end electrically connected to a first gate electrode of a corresponding one of the first transistors, and a second semiconductor layer of each of the second transistors may be positioned on the same layer as a first semiconductor layer of each of the first transistors.

[0015] A driving voltage line electrically connected to the above silicon semiconductor layer may be further provided.

[0016] The above driving voltage line may be located on the upper portion of the silicon semiconductor layer.

[0017] The light emitting control transistors are further provided, including a portion of the main portion located on one side of the extension portion and a portion of the main portion located on the other side, and each of the light emitting control transistors can be electrically connected to a corresponding one of the first transistors.

[0018] Each of the two ends of the main section may further be provided with connection electrodes electrically connecting the corresponding one of the first transistors.

[0019] According to one aspect of the present invention, an electronic device is provided, comprising a display panel and a lower cover having an opening forming an exterior and exposing a portion of the display panel, wherein the display panel comprises first transistors arranged adjacently along a first direction, a main portion extending along the first direction, and an extension portion extending in a second direction intersecting the first direction, the extension portion having a silicon semiconductor layer interposed between the first transistors in a plan view.

[0020] Each of the above first transistors may have a first semiconductor layer and a first gate electrode positioned on the first semiconductor layer and overlapping the first semiconductor layer.

[0021] The above first semiconductor layer may include an oxide semiconductor.

[0022] The device may further include a gate insulating layer covering the silicon semiconductor layer, the first semiconductor layer being positioned on the insulating layer, and capacitor electrodes interposed between the gate insulating layer and the first semiconductor layer and spaced apart from each other to correspond to the first transistors.

[0023] In the plan view, the extension portion may be interposed between the capacitor electrodes.

[0024] A driving voltage line electrically connected to the above silicon semiconductor layer may be further provided.

[0025] Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for carrying out the invention.

[0026] According to one embodiment of the present invention, as described above, a display panel capable of displaying high-quality images and an electronic device including the same can be implemented. Of course, the scope of the present invention is not limited by these effects.

[0027] FIG. 1 is a block diagram schematically illustrating an electronic device according to one embodiment of the present invention.

[0028] FIG. 2 is a schematic diagram schematically illustrating electronic devices according to embodiments of the present invention.

[0029] FIG. 3 is a schematic diagram schematically illustrating a case where electronic devices according to embodiments of the present invention are wearable electronic devices.

[0030] FIG. 4 is a schematic diagram schematically illustrating a case where an electronic device according to an embodiment of the present invention is an electronic device for a vehicle.

[0031] FIG. 5 is a plan view schematically illustrating a display module according to one embodiment of the present invention.

[0032] Figure 6 is a side view schematically illustrating the display module of Figure 5.

[0033] Fig. 7 is a plan view schematically illustrating the display module of Fig. 5.

[0034] Figure 8 is a conceptual diagram schematically enlarged to illustrate part A of the display module of Figure 7.

[0035] FIG. 9 is a conceptual diagram schematically enlarged to illustrate a portion of a display panel according to one embodiment of the present invention.

[0036] Fig. 10 is an equivalent circuit diagram of one pixel arranged in the display area of ​​the display module of Fig. 7.

[0037] Fig. 11 is a layout diagram schematically showing the locations of transistors, capacitors, etc. in pixels arranged in the display area of ​​the display module of Fig. 7.

[0038] Figures 12 to 20 are schematic layout diagrams showing components such as transistors and capacitors of the display panel illustrated in Figure 11 in layers.

[0039] Fig. 21 is a schematic diagram illustrating pixel electrodes of the display panel illustrated in Fig. 11.

[0040] Fig. 22 is a cross-sectional view schematically illustrating a cross-section taken along line B-B' of Fig. 11.

[0041] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals, and redundant descriptions thereof will be omitted.

[0043] In the following examples, when various components such as layers, films, regions, and plates are said to be "on" other components, this includes not only cases where they are "directly on" other components, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and therefore, the present invention is not necessarily limited to what is shown.

[0044] In the following examples, the x-axis, y-axis, and z-axis are not limited to three axes on an orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0045] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0046] In the following examples, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0047] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. And, “at least one of A and B” refers to the case where it is A, or B, or both A and B.

[0048] In the following examples, when it is said that a film, region, or component is connected, it includes not only cases where the films, regions, or components are directly connected, but also cases where other films, regions, or components are interposed between the films, regions, or components and thus indirectly connected. For example, when it is said in this specification that a film, region, or component is electrically connected, it includes not only cases where the films, regions, or components are directly electrically connected, but also cases where other films, regions, or components are interposed between them and thus indirectly electrically connected.

[0049] Fig. 1 is a block diagram schematically illustrating an electronic device (1) according to one embodiment of the present invention. The electronic device (1) according to the present embodiment may be a display device, and may further include modules having additional functions in addition to the display module (11).

[0050] As illustrated in FIG. 1, the electronic device (1) according to the present embodiment may include a display module (11), a processor (51), a memory (52), a power module (54), an input module (55), an output module (56), and a communication module (57).

[0051] The display module (11) may include a display panel (10, see FIG. 5) as described below. For example, the display module (11) may include a display panel (10) and a data driver (20, see FIG. 5) mounted thereon. The display panel (10) will be described below.

[0052] The processor (51) can control most of the components of the electronic device (1). For example, the processor (51) can output digital video data to the display module (11) so that the display module (11) can display an image, and can receive input data from the input module (55) and cause the electronic device (1) to perform a function according to the data. The processor (51) can include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0053] If necessary, the processor (51) may be divided into two or more from a functional or structural perspective. For example, the processor (51) may include a main processor in the form of a first driving chip including a central processing unit, and an auxiliary processor in the form of a second driving chip that is part of the display module (11). The auxiliary processor in the form of a second driving chip may include a controller that receives an image signal from the main processor and processes the image signal so as to conform to the interface specifications of the display panel (10) included in the display module (11).

[0054] The memory (52) may include at least one of non-volatile memory and volatile memory. The memory (52) may store data information required for the operation of the processor (51) or the display module (11). When the processor (51) executes an application stored in the memory (52), a data signal and / or an input control signal for an image is transmitted to the display module (11), and the display module (11) may process the received signal to output image information.

[0055] The power module (54) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate power required for the operation of the electronic device (1). Power conversion by the power conversion module may include DC-DC conversion, AC-DC conversion, or DC-AC conversion. Of course, the present invention is not limited thereto.

[0056] The input module (55) can provide input information to the processor (51) and / or the display module (11). The input module (55) can include various sensor modules as well as physical buttons, a keyboard, and a microphone. Examples of the sensor modules include a touch sensor, a pressure sensor, a distance sensor, a position sensor, a digitizer, a motion recognition sensor, a camera sensor, a light receiving sensor, a photoelectric conversion sensor, and / or a temperature sensor. In addition, the sensor module can include a biosensor such as a blood pressure sensor, a blood sugar sensor, an electrocardiogram sensor, and / or a heart rate sensor.

[0057] The output module (56) can receive information other than the image transmitted from the processor (51) and provide it to the user. The output module (56) may include, for example, an acoustic module, a haptic module, and / or a light-emitting module. In addition, the output module (56) may include a functional module unique to the electronic device (1), such as a cooling module of a refrigerator.

[0058] For reference, the display module (11) can also be in charge of an output function. For example, the display panel (10) included in the display module (11) can display (output) information processed in the electronic device (1). For example, the display panel (10) can display execution screen information of an application running in the electronic device (1), display a UI (User Interface) according to the execution screen information, or display GUI (Graphical User Interface) information. The display panel (10) can include a display layer that displays an image and a touch screen layer that detects a user's touch input. Accordingly, the display panel (10) can function as a part of an input module (55) that provides an input interface between the electronic device (1) and the user, and at the same time, function as a part of an output module (56) that provides an output interface between the electronic device (1) and the user.

[0059] The communication module (57) is a module responsible for transmitting and receiving information between the electronic device (1) and an external device, and may include a receiving unit and a transmitting unit. The communication module (57) may include various wireless communication modules such as a mobile communication module, a broadcast receiving module, a wireless Internet module, a short-range communication module, a Wi-Fi module, and / or a Bluetooth module, or various wired communication modules.

[0060] The electronic device (1) illustrated in FIG. 1 is exemplary, and may not include a communication module (57), for example, in the case of a display device that does not have a communication function. In addition, for example, when the electronic device (1) includes a display device, at least one of the components of the electronic device (1) described above may be included in the display device. In addition, some of the individual modules functionally included in one module may be included in the display device, and other parts may be included in the electronic device (1) separately from the display device. For example, the display device may include a display module (11), and the processor (51), the memory (52), and the power module (54) may be components of the electronic device (1) rather than the display device. Alternatively, various modifications are possible, such as the display device including the display module (11) and the power module (54), and the power module (54) may supply power to components such as the processor (51) and the memory (52) of the electronic device (1).

[0061] FIG. 2 is a schematic diagram schematically illustrating electronic devices (1) according to embodiments of the present invention. FIG. 2 illustrates a smartphone (1_1a), a tablet PC (1_1b), a laptop (1_1c), a TV (1_1d), and a desk monitor (1_1e) as examples of the electronic devices (1). The electronic device (1) may include a display panel and a lower cover having an opening that forms the exterior of the electronic device (1) and exposes a portion of the display panel.

[0062] A smartphone (1_1a) may include a processor (51), a memory (52), a power module (54), and a display module (11), as well as an input module (55) such as a touch sensor, a communication module (57), etc. The smartphone (1_1a) may process information received through the communication module (57) or other input modules and display the information through the display module (11).

[0063] In the case of a tablet PC (1_1b), a laptop (1_1c), a TV (1_1d) and / or a desk monitor (1_1e), similarly to a smartphone (1_1a), it may include a display module (11) and an input module (55), and in some cases, a communication module (57).

[0064] FIG. 3 is a schematic diagram schematically illustrating a case where electronic devices (1) according to embodiments of the present invention are wearable electronic devices. FIG. 3 illustrates smart glasses (1_2a), a head-mounted display (1_2b), and a smart watch (1_2c) as examples of electronic devices (1).

[0065] Smart glasses (1_2a) and head-mounted displays (1_2b) may include a display module (11) that displays images and a reflector that reflects such images and presents them to the user's eyes. Users can experience virtual reality or augmented reality using these electronic devices (1).

[0066] The smart watch (1_2c) includes a biometric sensor as an input module (55) and can provide biometric information recognized by the biometric sensor to the user through a display module (11).

[0067] FIG. 4 is a schematic diagram schematically illustrating a case where an electronic device (1) according to an embodiment of the present invention is a vehicle electronic device (1_3). As illustrated in FIG. 4, the vehicle electronic device (1_3) may be included in an instrument panel or center fascia of a vehicle, or may be a CID (Center Information Display) placed on a dashboard of a vehicle, or a room mirror display replacing a side mirror.

[0068] Of course, the electronic device (1) of the present invention is not limited to the above-described ones. For example, the electronic device (1) according to one embodiment of the present invention may include not only devices that mainly feature displays, such as billboards, electronic display boards, and / or game consoles, but also various home appliances that display information through a display module (11), such as refrigerators, washing machines, dryers, air conditioners, and / or robot vacuum cleaners. In addition, if the display module (11) has a function of transmitting light, the electronic device (1) may be a smart window or a transparent display device that displays a background and a display image together. Of course, the electronic device (1) of the present invention is not limited to these, and any electronic device (1) that includes a display panel (10) described below may be said to fall within the scope of the present invention.

[0069] FIG. 5 is a plan view schematically illustrating a display module (11) including a display panel (10) according to one embodiment of the present invention, and FIG. 6 is a side view schematically illustrating the display module (11) of FIG. 5. The electronic device (1) described above may include a display module (11) such as that illustrated in FIGS. 5 and 6.

[0070] The display panel (10) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged. The display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. In Fig. 5, the display area (DA) is illustrated as having a roughly rectangular shape with rounded corners.

[0071] The peripheral area (PA) may be located outside the display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) arranged to surround at least a portion of the display area (DA), and a second peripheral area (PA2) located at the lower end of the display area (DA) and extending in a first direction (x-axis direction). A width of the second peripheral area (PA2) in the first direction (x-axis direction) may be narrower than a width of the display area (DA). This structure allows at least a portion of the second peripheral area (PA2) to be easily bent.

[0072] The shape of the plane of the display panel (10) illustrated in FIG. 5 may be substantially the same as the shape of the substrate (100, see FIG. 7) included in the display panel (10). When the display panel (10) includes a display area (DA) and a peripheral area (PA) outside the display area (DA), it can be said that the substrate (100) includes the display area (DA) and a peripheral area (PA) outside the display area (DA). Hereinafter, for convenience, the substrate (100) is described as having the display area (DA) and the peripheral area (PA).

[0073] The display panel (10) may include a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) spaced apart from the main region (MR) with the bending region (BR) therebetween. The main region (MR) may be arranged on one side of the bending region (BR), and the sub-region (SR) may be arranged on the other side of the bending region (BR). The display panel (10) may be bent in the bending region (BR) as illustrated in FIG. 6, and at least a portion of the sub-region (SR) may overlap the main region (MR) when viewed in a third direction (z-axis direction).

[0074] Although Fig. 6 illustrates a bending of the display panel (10), the present invention is not limited thereto. For example, the display panel (10) may be a foldable display panel, in which case the display panel (10) may be bent within the display area (DA) about a bending axis crossing the display area (DA). Of course, if necessary, the display panel (10) may not be bent. The sub-area (SR) may be a non-display area.

[0075] A data driver (20) may be placed in a sub-region (SR) of a display panel (10) including a display module (11). The data driver (20) may be placed in the display panel (10) in the form of an integrated circuit (IC). For example, the data driver (20) may be a data driving integrated circuit that generates a data signal.

[0076] A display circuit board (30) may be attached to an end of the sub-region (SR) of the display panel (10). That is, if necessary, the display module (11) may include such a display circuit board (30). The display circuit board (30) may be electrically connected to a data driver (20) or the like through a pad of the sub-region (SR) of the display panel (10).

[0077] Fig. 7 is a plan view schematically illustrating the display module (11) of Fig. 5. As illustrated in Fig. 7, the display panel (10) included in the display module (11) may include a substrate (100). Various components constituting the display panel (10) may be arranged on the substrate (100).

[0078] The substrate (100) may include glass, ceramic, metal, or polymer resin. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) may have a multilayer structure including two layers including such polymer resins and an inorganic layer interposed between the layers. Alternatively, the substrate (100) may have a structure in which layers including such polymer resins and inorganic layers are alternately laminated. The inorganic layer may include, for example, silicon oxide, silicon nitride or silicon oxynitride.

[0079] Pixels are arranged in a display area (DA), and the display area (DA) can provide an image using light emitted from the pixels. Each pixel can include a light-emitting diode (LED), and the light-emitting diode (LED) can be electrically connected to a pixel circuit (PC). The pixel circuit (PC) and the light-emitting diode (LED) can be arranged in the display area (DA). In Fig. 7, for convenience, the pixel circuit (PC) and the light-emitting diode (LED) are illustrated as being positioned side by side, but in reality, the pixel circuit (PC) and the light-emitting diode (LED) can overlap at least partly. For example, the light-emitting diode (LED) can be arranged on the pixel circuit (PC).

[0080] A gate driving circuit, a pad (14), a first power supply wiring (15), and a second power supply wiring (16) may be arranged in the peripheral area (PA). The gate driving circuit may include, for example, a first scan driving circuit (12a), a second scan driving circuit (12b), and / or a light emission control driving circuit (13).

[0081] The first scan driving circuit (12a) can provide a scan signal to the pixel circuit (PC) through the gate line (SL). The second scan driving circuit (12b) can be arranged on the opposite side of the first scan driving circuit (12a) with the display area (DA) interposed therebetween. Some of the pixel circuits (PC) arranged in the display area (DA) can be electrically connected to the first scan driving circuit (12a), and the rest can be connected to the second scan driving circuit (12b). Of course, the second scan driving circuit (12b) can be omitted in some cases.

[0082] The light emission control driving circuit (13) may be arranged on one side of the display area (DA) like the first scan driving circuit (12a). The light emission control driving circuit (13) may provide a light emission control signal to the pixel (P) through the light emission control line (EL). In Fig. 7, the light emission control driving circuit (13) is illustrated as being arranged only on one side of the display area (DA), but the present invention is not limited thereto. For example, the display panel (10) may have light emission control driving circuits (13) arranged on one side and the other side of the display area (DA). Alternatively, the first scan driving circuit (12a) may be arranged on one side of the display area (DA), and the light emission control driving circuit (13) may be arranged on the other side.

[0083] The pad (14) may be placed in the second peripheral area (PA2) of the substrate (100). The pad (14) is exposed without being covered by an insulating layer, and may be electrically connected to the display circuit board (30). The pad (34) of the display circuit board (30) may be electrically connected to the pad (14) of the display panel (10).

[0084] The display circuit board (30) transmits a signal or power from the control unit to the display panel (10). The control signal generated by the control unit can be transmitted to each gate driving circuit through the display circuit board (30). In addition, the control unit can provide a first power voltage (ELVDD) and a second power voltage (ELVSS) to the first power supply wire (15) and the second power supply wire (16). The first power voltage (ELVDD, hereinafter referred to as driving voltage) is provided to each pixel circuit (PC) through a driving voltage line (PL) connected to the first power supply wire (15), and the second power voltage (ELVSS, hereinafter referred to as common voltage) can be provided to a common electrode of a light emitting diode (LED) connected to the second power supply wire (16). The first power supply wire (15) can extend in a first direction (x-axis direction). The second power supply wiring (16) has a loop shape with one side open, so that it can partially surround the display area (DA).

[0085] The data signal of the data driver (20) can be transmitted to the pixel circuit (PC) through the data line (DL) electrically connected to the input line (IL) via the input line (IL).

[0086] Fig. 8 is a conceptual diagram schematically enlarging part A of the display module (11) of Fig. 7. As illustrated in Fig. 8, a data line (DL) extending along the second direction (y-axis direction) is arranged in the display area (DA), and an input line (IL) is arranged in the peripheral area (PA). The input line (IL) can transmit a data signal of the data driver (20) to the data line (DL). In FIG. 8, for convenience of illustration, the data lines (DL) include a first data line (DL1), a second data line (DL2), a third data line (DL3), a fourth data line (DL4), a fifth data line (DL5), and a sixth data line (DL6), and the input lines (IL) include a first input line (IL1), a second input line (IL2), a third input line (IL3), a fourth input line (IL4), a fifth input line (IL5), and a sixth input line (IL6). However, the number of data lines (DL) and the number of input lines (IL) may be varied.

[0087] Some of the data lines (DL) may be directly connected to the corresponding input lines (IL), while other of the data lines (DL) may be electrically connected to the corresponding input lines (IL) via data transfer lines (DTL).

[0088] The first data line (DL1), the third data line (DL3), and the fifth data line (DL5) can receive data signals from the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). The first data line (DL1), the third data line (DL3), and the fifth data line (DL5) can be electrically connected to the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). Each of the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) can be integral with a corresponding one of the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). Alternatively, each of the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) may be electrically connected to a corresponding one of the first input line (IL1), the third input line (IL3), and the fifth input line (IL5) through the first contact hole (CNT1), as illustrated in FIG. 8.

[0089] The second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) can be electrically connected to the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) through the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3). That is, the second input line (IL2) can be electrically connected to the second data line (DL2) through the first data transmission line (DTL1), the fourth input line (IL4) can be electrically connected to the fourth data line (DL4) through the second data transmission line (DTL2), and the sixth input line (IL6) can be electrically connected to the sixth data line (DL6) through the third data transmission line (DTL3).

[0090] Most of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) may be located within the display area (DA). One end of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) may be electrically connected to a corresponding one of the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) through a second contact hole (CNT2). The other end of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) may be electrically connected to a corresponding one of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) through a third contact hole (CNT3). For reference, in Fig. 8, the second contact hole (CNT2) and the third contact hole (CNT3) are illustrated as being located in the peripheral area (PA), but the present invention is not limited thereto. For example, the second contact hole (CNT2) and / or the third contact hole (CNT3) may be located within the display area (DA).

[0091] The first data transmission line (DTL1) may include a first horizontal connection line (DHL1), a first vertical connection line (DVL1), and a first additional vertical connection line (DVL1'), the second data transmission line (DTL2) may include a second horizontal connection line (DHL2), a second vertical connection line (DVL2), and a second additional vertical connection line (DVL2'), and the third data transmission line (DTL3) may include a third horizontal connection line (DHL3), a third vertical connection line (DVL3), and a third additional vertical connection line (DVL3'). The first horizontal connection line (DHL1), the second horizontal connection line (DHL2), and the third horizontal connection line (DHL3) may extend approximately in the first direction (x-axis direction). The first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3') extend approximately in the second direction (y-axis direction) and can be substantially parallel to the data line (DL).

[0092] Each of the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) is electrically connected to a corresponding one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), and the third vertical connection line (DVL3) through a second contact hole (CNT2), and each of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) can be electrically connected to a corresponding one of the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3') through a third contact hole (CNT3). Each of the first horizontal connecting line (DHL1), the second horizontal connecting line (DHL2), and the third horizontal connecting line (DHL3) is electrically connected to a corresponding one of the first vertical connecting line (DVL1), the second vertical connecting line (DVL2), and the third vertical connecting line (DVL3) through the first connecting contact hole (DHL-CNT1), and can be electrically connected to a corresponding one of the first additional vertical connecting line (DVL1'), the second additional vertical connecting line (DVL2'), and the third additional vertical connecting line (DVL3') through the second connecting contact hole (DHL-CNT2).

[0093] The first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3') may be arranged on the same first layer, and the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), and the third horizontal connection line (DHL3) may be arranged on a second layer different from the first layer. For reference, when certain components are arranged on the same layer, it means that the components can be formed simultaneously with the same material through the same mask process.

[0094] In FIG. 8, as described above, the first data transmission line (DTL1) includes a first horizontal connection line (DHL1), a first vertical connection line (DVL1), and a first additional vertical connection line (DVL1'), the second data transmission line (DTL2) includes a second horizontal connection line (DHL2), a second vertical connection line (DVL2), and a second additional vertical connection line (DVL2'), and the third data transmission line (DTL3) includes a third horizontal connection line (DHL3), a third vertical connection line (DVL3), and a third additional vertical connection line (DVL3'). However, the present invention is not limited thereto.

[0095] For example, as illustrated in FIG. 9, which is a conceptual diagram schematically enlarged to illustrate a portion of a display module (11) according to one embodiment of the present invention, a first data transmission line (DTL1) may include a first horizontal connection line (DHL1) and a first vertical connection line (DVL1), a second data transmission line (DTL2) may include a second horizontal connection line (DHL2) and a second vertical connection line (DVL2), and a third data transmission line (DTL3) may include a third horizontal connection line (DHL3) and a third vertical connection line (DVL3). In this case, each of the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), and the third horizontal connection line (DHL3) may be electrically connected to a corresponding one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), and the third vertical connection line (DVL3) through the first connection contact hole (DHL-CNT1), and may be electrically connected to a corresponding one of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) through the second connection contact hole (DHL-CNT2).

[0096] FIG. 10 is an equivalent circuit diagram of a pixel arranged in a display area (DA) of a display panel (10) included in a display module (11) of FIG. 7. As illustrated in FIG. 10, a pixel circuit (PC) connected to a light-emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. For example, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), a storage capacitor (Cst), and a hold capacitor (Chd).

[0097] The first transistor (T1) is a driving transistor that outputs a driving current corresponding to a data signal, and the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be switching transistors that transmit signals through on / off. The first terminal (first electrode) of each of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be either a source region or a drain region, and the second terminal (second electrode) may be the other one.

[0098] At least one of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) may be a PMOS (p-channel MOSFET), and the others may be NMOS (n-channel MOSFETs). For example, the fifth transistor (T5) may be a PMOS, and the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the sixth transistor (T6), and the seventh transistor (T7) may be NMOS. Alternatively, the fifth transistor (T5) and the sixth transistor (T6) may be PMOS, and the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) may be NMOS. Alternatively, all transistors may be NMOS or all transistors may be PMOS.

[0099] At least one of the transistors may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and the rest may be transistors having oxide semiconductor layers. For example, the fifth transistor (T5) may include a semiconductor layer made of polycrystalline silicon having high reliability, and each of the remaining transistors may include an oxide semiconductor layer having the characteristics of high carrier mobility and low leakage current. Hereinafter, a case will be described where the fifth transistor (T5) is a PMOS including a silicon semiconductor layer, and the remaining transistors are NMOS including oxide semiconductor layers.

[0100] The pixel circuit (PC) may be electrically connected to gate lines that transmit signals to the gate electrodes of each of the transistors. For example, the pixel circuit (PC) may be connected to a scan line (GWL) that transmits a scan signal (GW), a first reference gate line (GRL) that transmits a first reference signal (GR), a second reference gate line (GCL) that transmits a second reference signal (GC), a first emission control line (EML) that transmits a first emission control signal (EM), a second emission control line (EMBL) that transmits a second emission control signal (EMB), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel circuit (PC) may be connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (VREF), and an initialization voltage line (VL) that transmits an initialization voltage (VINT).

[0101] A first transistor (T1), which is a driving transistor, may be electrically connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a first gate electrode (G1) connected to the first node (N1), a first terminal electrically connected to the driving voltage line (PL), and a second terminal connected to a second node (N2). The first terminal may be a drain region (D) and the second terminal may be a source region (S). The first terminal of the first transistor (T1) may be electrically connected to the driving voltage line (PL) via a fifth transistor (T5), and the second terminal of the first transistor (T1) may be electrically connected to a pixel electrode of a light-emitting diode (LED) via a sixth transistor (T6). The first transistor (T1) can receive a data signal (DATA) according to the switching operation of the second transistor (T2) and control the amount of driving current (Id) flowing to the light-emitting diode (LED).

[0102] A second transistor (T2), which is a data write transistor, may be electrically connected between a data line (DL) and a first node (N1). The second transistor (T2) may include a gate electrode connected to a scan line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) is turned on by a scan signal (GW) transmitted to the scan line (GWL), electrically connecting the data line (DL) and the first node (N1), and transmitting a data signal (DATA) from the data line (DL) to the first node (N1).

[0103] A third transistor (T3), which is a first initialization transistor, may be electrically connected between a first node (N1) and a reference voltage line (VRL). The third transistor (T3) may include a gate electrode connected to the first reference gate line (GRL), a first terminal connected to the first node (N1), and a second terminal connected to the reference voltage line (VRL). The third transistor (T3) may be turned on by a first reference signal (GR) transmitted to the first reference gate line (GRL), and may transmit a reference voltage (VREF) from the reference voltage line (VRL) to the first node (N1).

[0104] The fourth transistor (T4), which is a second initialization transistor, may be electrically connected between the first transistor (T1) and the initialization voltage line (VL). Specifically, the fourth transistor (T4) may be electrically connected between the sixth transistor (T6) described below and the initialization voltage line (VL). The fourth transistor (T4) may include a gate electrode connected to the first emission control line (EML), a first terminal connected to the second terminal of the sixth transistor (T6) and a light-emitting diode (LED), and a second terminal connected to the initialization voltage line (VL). The fourth transistor (T4) may be turned on by the first emission control signal (EM) transmitted to the first emission control line (EML), and may transmit the initialization voltage (VINT) from the initialization voltage line (VL) to the pixel electrode of the light-emitting diode (LED). That is, the fourth transistor (T4) can initialize the potential of the pixel electrode of the light-emitting diode (LED) to the initialization voltage (VINT).

[0105] A fifth transistor (T5), which is a light-emitting control transistor, may be electrically connected between a driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate electrode connected to the first light-emitting control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a first light-emitting control signal (EM) from the first light-emitting control line (EML).

[0106] A sixth transistor (T6), which is a motion control transistor, may be connected between the first transistor (T1) and a light emitting diode (LED). The sixth transistor (T6) may include a gate electrode connected to a second light emitting control line (EMBL), a first terminal connected to a second node (N2), and a second terminal connected to the light emitting diode (LED). The sixth transistor (T6) may be turned on by a second light emitting control signal (EMB) from the second light emitting control line (EMBL), thereby electrically connecting the second node (N2) and a pixel electrode of the light emitting diode (LED).

[0107] For reference, in Fig. 10, the fifth transistor (T5) is illustrated as operating in response to the first emission control signal (EM) and the sixth transistor (T6) is illustrated as operating in response to the second emission control signal (EMB), but the present invention is not limited thereto. For example, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to the same emission control signal.

[0108] For reference, the first reference signal (GR) can be substantially synchronized with the scan signal (GW) of the pixel circuit (PC) located in the previous row. The second reference signal (GC) described below can also be substantially synchronized with the scan signal (GW) of the pixel circuit (PC) located in the previous row, or can be substantially synchronized with the scan signal (GW) or the first reference signal (GR) of the pixel circuit (PC) located in the next row.

[0109] The storage capacitor (Cst) may be electrically connected between the first node (N1) and the second node (N2). That is, the pixel circuit (PC) included in the display panel according to the present embodiment may be a source follower type circuit in which the storage capacitor (Cst) is connected between the first node (N1) and the second node (N2). The first storage electrode (CEs1) of the storage capacitor (Cst) may be connected to the first node (N1), and the second storage electrode (CEs2) may be connected to the second node (N2). The electrodes constituting the capacitor may be referred to as capacitor electrodes. The storage capacitor (Cst) may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0110] A hold capacitor (Chd) may be connected between the seventh transistor (T7) and the second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be electrically connected to the second node (N2), and a second hold electrode (CEh2) may be electrically connected to a reference voltage line (VRL) via the seventh transistor (T7). The hold capacitor (Chd) may allow the voltage of the second node (N2) of the first transistor (T1) to remain constant and not fluctuate when a peripheral signal fluctuates.

[0111] A seventh transistor (T7), which is a third initialization transistor, may be electrically connected between a second hold electrode (CEh2) of a hold capacitor (Chd) and a reference voltage line (VRL). The seventh transistor (T7) may include a gate electrode connected to a second reference gate line (GCL), a first terminal connected to the second hold electrode (CEh2) of the hold capacitor (Chd), and a second terminal connected to the reference voltage line (VRL). The seventh transistor (T7) may be turned on by a second reference signal (GC) transmitted to the second reference gate line (GCL), and may transmit a reference voltage (VREF) from the reference voltage line (VRL) to the second hold electrode (CEh2) of the hold capacitor (Chd).

[0112] A light emitting diode (LED) includes a pixel electrode electrically connected to a second node (N2) via a sixth transistor (T6) and a common electrode above the pixel electrode, and the common electrode can be supplied with a common voltage (ELVSS). The common electrode can be integral with a plurality of light emitting diodes (LEDs).

[0113] Although the pixel circuit (PC) in FIG. 10 is illustrated as including seven transistors and two capacitors, the present invention is not limited thereto. For example, the pixel circuit (PC) may include five transistors and two capacitors. It may also include six transistors and one or two capacitors.

[0114] FIG. 11 is a layout diagram schematically showing the positions of transistors, capacitors, etc., in pixels arranged in the display area of ​​the display panel (10) included in the display module (11) of FIG. 7. For convenience of explanation, FIG. 11 illustrates two pixel circuits, for example, a first pixel circuit (PC1) and a second pixel circuit (PC2), arranged in the same row along the first direction (x-axis direction). However, the present invention is not limited thereto. In addition, although FIG. 11 illustrates the first pixel circuit (PC1) and the second pixel circuit (PC2) as being approximately mirror-symmetrical with respect to an imaginary line (IML) extending in the second direction (y-axis direction) between them, the present invention is not limited thereto. The display panel (10) may include a plurality of pixel circuits arranged to form rows in the first direction (x-axis direction) and columns in the second direction (y-axis direction).

[0115] As illustrated in FIG. 11, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include transistors and capacitors. For example, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include the first transistor (T1) to the seventh transistor (T7), the storage capacitor (Cst), and the hold capacitor (Chd) described above with reference to FIG. 10. That is, considering the first pixel circuit (PC1) and the second pixel circuit (PC2), two first transistors (T1) may be arranged adjacent to each other along the first direction (x-axis direction).

[0116] Gate lines electrically connected to the first pixel circuit (PC1) and the second pixel circuit (PC2), such as the scan line (GWL), the first reference gate line (GRL), the second reference gate line (GCL), the first emission control line (EML), and the second emission control line (EMBL), may extend approximately in the first direction (x-axis direction). In addition, a horizontal connection line (DHL, see FIG. 19) may also extend approximately in the first direction (x-axis direction).

[0117] The first pixel circuit (PC1) may be electrically connected to a data line (DL) passing through the first pixel circuit (PC1), and the second pixel circuit (PC2) may be electrically connected to a data line (DL) passing through the second pixel circuit (PC2). The data line (DL) may extend approximately along the second direction (y-axis direction). The data line (DL) electrically connected to the first pixel circuit (PC1) and the data line (DL) electrically connected to the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned virtual line (IML).

[0118] The first pixel circuit (PC1) may be electrically connected to a voltage line passing through the first pixel circuit (PC1), such as a reference voltage line (VRL) and an initialization voltage line (VL). The second pixel circuit (PC2) may be electrically connected to a voltage line passing through the second pixel circuit (PC2), such as a reference voltage line (VRL) and an initialization voltage line (VL). The reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the first pixel circuit (PC1) may be symmetrical with respect to the reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the second pixel circuit (PC2) with respect to the aforementioned imaginary line (IML). The reference voltage line (VRL) and the initialization voltage line (VL) may each extend approximately along the second direction (y-axis direction). For convenience, the initialization voltage line (VL) passing through the first pixel circuit (PC1) may be referred to as the first initialization voltage line, and the initialization voltage line (VL) passing through the second pixel circuit (PC2) may be referred to as the second initialization voltage line. That is, the first initialization voltage lines and the second initialization voltage lines extending in the second direction (y-axis direction) may be arranged alternately along the first direction (x-axis direction).

[0119] The vertical connection line (DVL) may also extend along the second direction (y-axis direction). The vertical connection line (DVL) may correspond to a portion of the data transmission line (DTL) described with reference to FIG. 8 or FIG. 9, for example, any one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3'). In this case, the vertical connection line (DVL) may be electrically connected to a data line (DL) of a pixel circuit arranged in a different column from the first pixel circuit (PC1) and the second pixel circuit (PC2) illustrated in FIG. 11, so as to transmit a data signal to pixel circuits arranged in a different column. Alternatively, if the first pixel circuit (PC1) or the second pixel circuit (PC2) is not located near a corner of the display area (DA) as shown in FIG. 8 or FIG. 9, but rather in the center of the display area (DA), the vertical connection line (DVL) may be a dummy line to which no electrical signal is applied, or may be a dummy line to which a constant electrical signal is applied as needed.

[0120] For reference, the horizontal connection line (DHL) to be described later may correspond to a part of the data transmission line (DTL) described with reference to FIG. 8 or FIG. 9, for example, one of the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), or the third horizontal connection line (DHL3). In this case, the horizontal connection line (DHL) is electrically connected to the data line (DL) of the pixel circuit arranged in a different column from the first pixel circuit (PC1) and the second pixel circuit (PC2) illustrated in FIG. 11, together with the vertical connection line (DVL), so as to transmit a data signal to the pixel circuits arranged in a different column. Alternatively, if the first pixel circuit (PC1) or the second pixel circuit (PC2) is not located near a corner of the display area (DA) as shown in FIG. 8 or FIG. 9, but rather in the center of the display area (DA), the horizontal connection line (DHL) may be a dummy line to which no electrical signal is applied, or may be a dummy line to which a constant electrical signal is applied as needed.

[0121] Figures 12 to 20 are layout diagrams schematically illustrating components such as transistors and capacitors of the display panel (10) illustrated in Figure 11, layer by layer. Figure 21 is a layout diagram schematically illustrating pixel electrodes of the display panel (10) illustrated in Figure 11. And Figure 22 is a cross-sectional view schematically illustrating a cross-section taken along the line B-B' of Figures 11 to 21.

[0122] For convenience of explanation, the first pixel circuit (PC1) is described as being located in the i-th row and j-th column, and the second pixel circuit (PC2) is described as being located in the i-th row and j+1-th column.

[0123] The display panel (10) may include a circuit layer including transistors and capacitors arranged on a substrate (100), and a display element layer arranged on the circuit layer and including a light-emitting diode (LED). The circuit layer may include the transistors and capacitors described above with reference to FIGS. 10 and 11.

[0124] As illustrated in Fig. 12, a lower metal layer (1010) may be disposed on a substrate (100). The lower metal layer (1010) may include a first portion (1011) extending along a second direction (y-axis direction), and a second portion (1012) and a third portion (1013) connected to the first portion (1011) and extending approximately along the first direction (x-axis direction).

[0125] The first part (1011) of the lower metal layer (1010) may be positioned on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second part (1012) and the third part (1013) of the lower metal layer (1010) may be positioned on opposite sides with the first part (1011) therebetween. The second part (1012) and the third part (1013) may extend overall along the first direction (e.g., the x-direction), but may be locally bent. The lower metal layer (1010) may include a metallic material. Specifically, the lower metal layer (1010) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the lower metal layer (1010) may have a single-layer structure including molybdenum, a double-layer structure in which a molybdenum layer and a titanium layer are stacked, or a triple-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0126] The lower metal layer (1010) may have a voltage level of a constant voltage. For example, the lower metal layer (1010) may have the same voltage level as the driving voltage line (PL) described above with reference to FIG. 10. That is, the driving voltage (ELVDD) may be applied to the lower metal layer (1010). To this end, the lower metal layer (1010) may be electrically connected to a portion of the driving voltage line (PL) or the first power supply line (15), for example, in the peripheral area (PA). The lower metal layer (1010) may at least partially shield light traveling to the fifth semiconductor layer (A5) of the fifth transistor (T5) and protect the fifth transistor (T5) from electrostatic discharge (ESD).

[0127] A buffer layer (101) may be disposed on the lower metal layer (1010) to cover the lower metal layer (1010). The buffer layer (101) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. This buffer layer (101) may have a single-layer structure or a multi-layer structure.

[0128] A silicon semiconductor layer (1110) as illustrated in Fig. 13 may be placed on the buffer layer (101). The silicon semiconductor layer (1110) may include silicon, for example, polysilicon.

[0129] As illustrated in FIG. 13, the silicon semiconductor layer (1110) may have an isolated shape. In addition, the silicon semiconductor layer (1110) may have a main portion (MP) having a shape extending approximately along a first direction (x-axis direction) and an extension portion (ETP) having a shape extending in a second direction (y-axis direction) intersecting the first direction. The main portion (MP) and the extension portion (ETP) may be integral. The main portion (MP) of the silicon semiconductor layer (1110) may intersect with an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). In addition, the extension portion (ETP) of the silicon semiconductor layer (1110) may overlap with an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2) in a plan view. In the plan view, this extension (ETP) may be located between the first transistor (T1) of the first pixel circuit (PC1) and the second transistor (T2) of the second pixel circuit (PC2). This silicon semiconductor layer (1110) may include a fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). In other words, the fifth semiconductor layer (A5) of the first pixel circuit (PC1) and the fifth semiconductor layer (A5) of the second pixel circuit (PC2) may be integral.

[0130] If the silicon semiconductor layer (1110) has only the main portion (MP) and does not have the extension portion (ETP), the area occupied by the silicon semiconductor layer (1110) in the area of ​​the first pixel circuit (PC1) and the area of ​​the second pixel circuit (PC2) becomes very small. In this case, in order to form the main portion (MP), a layer including a silicon semiconductor material is formed on approximately the entire surface of the substrate (100) and the process of patterning it using a photoresist or the like, since the amount of photoresist removed is large, it takes a lot of time, and a defect may occur in which the main portion (MP) is not formed in the intended shape. However, in the case of the display panel (10) according to the present embodiment and the electronic device (1) having the same, since the silicon semiconductor layer (1110) has not only the main portion (MP) but also the extension portion (ETP), the area occupied by the silicon semiconductor layer (1110) in the area of ​​the first pixel circuit (PC1) and the area of ​​the second pixel circuit (PC2) can be increased. Accordingly, the occurrence of defects during the manufacturing process can be effectively prevented or minimized.

[0131] The silicon semiconductor layer (1110) may overlap with the lower metal layer (1010). For example, the main portion (MP) of the silicon semiconductor layer (1110) may roughly overlap with the third portion (1013) of the lower metal layer (1010), and the extension portion (ETP) of the silicon semiconductor layer (1110) may overlap with the first portion (1011) of the lower metal layer (1010). Accordingly, the fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may overlap with the third portion (1013) of the lower metal layer (1010).

[0132] A first gate insulating layer (103) may be disposed on the silicon semiconductor layer (1110) to cover the silicon semiconductor layer (1110). The first gate insulating layer (103) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. This first gate insulating layer (103) may have a single-layer structure or a multi-layer structure.

[0133] A first gate layer (1200) as illustrated in FIG. 14 may be arranged on the first gate insulating layer (103). For reference, in FIG. 14, the first gate layer (1200) is illustrated as overlapping with the underlying silicon semiconductor layer (1110) for convenience. In FIG. 14, the first gate layer (1200) is illustrated as including a first emission control line (EML), a first conductive layer (1210), a second conductive layer (1220), a third conductive layer (1230), and a fourth conductive layer (1240). The first emission control line (EML), the first conductive layer (1210), the second conductive layer (1220), the third conductive layer (1230), and the fourth conductive layer (1240) of the first pixel circuit (PC1), and the first emission control line (EML), the first conductive layer (1210), the second conductive layer (1220), the third conductive layer (1230), and the fourth conductive layer (1240) of the second pixel circuit (PC2) may be approximately symmetrical with respect to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0134] As illustrated in FIG. 14, the first emission control line (EML), the first conductive layer (1210), the second conductive layer (1220), the third conductive layer (1230), and the fourth conductive layer (1240) can be arranged spaced apart from each other. The first emission control line (EML), the first conductive layer (1210), the second conductive layer (1220), the third conductive layer (1230), and the fourth conductive layer (1240) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. The components included in the first gate layer (1200) may be formed simultaneously with the same material, and thus may have the same layer structure.

[0135] The first emission control line (EML) can extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The first emission control line (EML) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0136] The first emission control line (EML) may include a fifth gate electrode (G5) of each of the fifth transistors (T5) of the first pixel circuit (PC1) and the second pixel circuit (PC2). A portion of the first emission control line (EML) may protrude to overlap with a fifth semiconductor layer (A5) of the fifth transistor (T5), and the protruding portion of the first emission control line (EML) may correspond to the fifth gate electrode (G5) of the fifth transistor (T5). The fifth semiconductor layer (A5) of the fifth transistor (T5) may include a channel region (C5) overlapping with the fifth gate electrode (G5), and conductive regions (S5, D5) disposed on both sides of the channel region (C5) and being conductive by being doped with impurities or subjected to plasma treatment. One of the conductive regions (S5, D5) may be a source region, and the other may be a drain region. The source region and drain region may correspond to the source electrode and the drain electrode, respectively. The positions of the source region and drain region may be swapped depending on the properties of the transistor.

[0137] The first conductive layer (1210) has an isolated shape, but the first conductive layers (1210) of two adjacent pixel circuits may be integral with each other. For example, as illustrated in FIG. 14, the first conductive layer (1210) belonging to the first pixel circuit (PC1) may be integral with the first conductive layer (1210) of the pixel circuit located in the -x direction, that is, the pixel circuit located in the j-1th column, and the first conductive layer (1210) belonging to the second pixel circuit (PC2) may be integral with the first conductive layer (1210) of the pixel circuit located in the +x direction, that is, the pixel circuit located in the j+2th column. The second conductive layer (1220) and the third conductive layer (1230) may each have an isolated shape. The fourth conductive layer (1240) also has an isolated shape, but may be integral with the first pixel circuit (PC1) and the pixel circuit located in the j-1th column, and may also be integral with the second pixel circuit (PC2) and the pixel circuit located in the j+2th column. In the first pixel circuit (PC1) and the second pixel circuit (PC2), the first conductive layer (1210), the second conductive layer (1220), the third conductive layer (1230), and the fourth conductive layer (1240) may be symmetrical with respect to the aforementioned virtual line (IML).

[0138] The first conductive layer (1210) may overlap with the third semiconductor layer (A3, see FIG. 17) described later. This first conductive layer (1210) may at least partially shield light traveling to the third semiconductor layer (A3) of the third transistor (T3) and may protect the third transistor (T3) from electrostatic discharge (ESD).

[0139] The second conductive layer (1220) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) has an isolated shape and may be positioned adjacent to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive layer (1220) may be a second hold electrode (CEh2) of a hold capacitor (Chd).

[0140] The third conductive layer (1230) located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be a first storage electrode (CEs1) of the storage capacitor (Cst).

[0141] A second gate insulating layer (105) may be arranged to cover the first gate layer (1200). The second gate insulating layer (105) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second gate insulating layer (105) may have a single-layer structure or a multi-layer structure. If necessary, the second gate insulating layer (105) may include a different material from the first gate insulating layer (103). For example, the first gate insulating layer (103) may include silicon oxide, and the second gate insulating layer (105) may include silicon nitride.

[0142] A second gate layer (1300) as illustrated in FIG. 15 may be disposed on the second gate insulating layer (105). In FIG. 15, the second gate layer (1300) is illustrated as including a fifth conductive layer (1310) and a sixth conductive layer (1320). The fifth conductive layer (1310) and the sixth conductive layer (1320) of the first pixel circuit (PC1) and the fifth conductive layer (1310) and the sixth conductive layer (1320) of the second pixel circuit (PC2) may be approximately symmetrical with respect to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0143] As illustrated in FIG. 15, the fifth conductive layer (1310) and the sixth conductive layer (1320) may be spaced apart from each other. The fifth conductive layer (1310) and the sixth conductive layer (1320) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. The components included in the second gate layer (1300) may be simultaneously formed of the same material, and thus may have the same layer structure.

[0144] The fifth conductive layer (1310) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fifth conductive layer (1310) disposed in the first pixel circuit (PC1) and the fifth conductive layer (1310) disposed in the second pixel circuit (PC2) may be spaced apart from each other and may be substantially symmetrical with respect to the aforementioned virtual line (IML). The extension portion (ETP) of the silicon semiconductor layer (1110) may be located between the fifth conductive layer (1310) disposed in the first pixel circuit (PC1) and the fifth conductive layer (1310) disposed in the second pixel circuit (PC2) in a plan view. The fifth conductive layer (1310) of the first pixel circuit (PC1) may overlap the second conductive layer (1220) and the third conductive layer (1230) of the first pixel circuit (PC1) located below. This fifth conductive layer (1310) may be a first hold electrode (CEh1) of the hold capacitor (Chd) and a second storage electrode (CEs2) of the storage capacitor (Cst). That is, the first hold electrode (CEh1) of the hold capacitor (Chd) and the second storage electrode (CEs2) of the storage capacitor (Cst) may be integral. Accordingly, the second conductive layer (1220) and the fifth conductive layer (1310) may form the hold capacitor (Chd), and the third conductive layer (1230) and the fifth conductive layer (1310) may form the storage capacitor (Cst).

[0145] The sixth conductive layer (1320) disposed on each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may also have an isolated shape. The sixth conductive layer (1320) may overlap with the second semiconductor layer (A2, see FIG. 17) described below. The sixth conductive layer (1320) may at least partially shield light traveling to the second semiconductor layer (A2) of the second transistor (T2) and may protect the second transistor (T2) from electrostatic discharge (ESD).

[0146] A first interlayer insulating layer (107) may be arranged to cover the second gate layer (1300). The first interlayer insulating layer (107) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The first interlayer insulating layer (107) may have a single-layer structure or a multi-layer structure. For example, the first interlayer insulating layer (107) may have a stacked structure of a layer including silicon oxide and a layer including silicon nitride.

[0147] An intermediate conductive layer (1400) as illustrated in FIG. 16 may be disposed on the first interlayer insulating layer (107). FIG. 16 illustrates that the intermediate conductive layer (1400) includes a shield layer (1410). The shield layer (1410) of the first pixel circuit (PC1) and the shield layer (1410) of the second pixel circuit (PC2) may be approximately symmetrical with respect to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0148] The shield layer (1410) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. For example, the shield layer (1410) may have a single-layer structure including molybdenum or titanium.

[0149] The shield layer (1410) disposed on each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The shield layer (1410) may overlap with the first semiconductor layer (A1, see FIG. 17) described below. The shield layer (1410) may at least partially block light traveling to the first semiconductor layer (A1) of the first transistor (T1) and protect the first transistor (T1) from electrostatic discharge (ESD). The shield layer (1410) may be connected to the fifth conductive layer (1310) through a contact hole (1410CT) formed in the first interlayer insulating layer (107) therebelow. Accordingly, the shield layer (1410) can have the same potential as the fifth conductive layer (1310), which is the first hold electrode (CEh1) of the hold capacitor (Chd) and the second storage electrode (CEs2) of the storage capacitor (Cst).

[0150] A second interlayer insulating layer (108) may be arranged to cover the intermediate conductive layer (1400). The second interlayer insulating layer (108) may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second interlayer insulating layer (108) may have a single-layer structure or a multi-layer structure. For example, the second interlayer insulating layer (108) may have a laminated structure of a layer including silicon oxide and a layer including silicon nitride.

[0151] A semiconductor layer (1500) as illustrated in FIG. 17 may be disposed on the second interlayer insulating layer (108). The semiconductor layer (1500) may include an oxide semiconductor. The oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO). Fig. 17 illustrates that a semiconductor layer (1500) includes a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), a third oxide semiconductor pattern (1530), and a fourth oxide semiconductor pattern (1540). As illustrated in Fig. 17, the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be arranged to be spaced apart from each other.

[0152] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The first oxide semiconductor pattern (1510) may include a first semiconductor layer (A1), a fourth semiconductor layer (A4), and a sixth semiconductor layer (A6). That is, the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the first pixel circuit (PC1) may be integral, and the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the second pixel circuit (PC2) may be integral. This first oxide semiconductor pattern (1510) may have a shape that is folded several times.

[0153] The first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) included in the first oxide semiconductor pattern (1510) may overlap with the first gate electrode (1610), the seventh conductive layer (1620), and the second emission control line (EMBL), which will be described later with reference to FIG. 18. That is, the portion of the first oxide semiconductor pattern (1510) that overlaps with the first gate electrode (1610) may be the first semiconductor layer (A1), the portion of the first oxide semiconductor pattern (1510) that overlaps with the seventh conductive layer (1620) may be the fourth semiconductor layer (A4), and the portion of the first oxide semiconductor pattern (1510) that overlaps with the second emission control line (EMBL) may be the sixth semiconductor layer (A6).

[0154] For reference, in the plan view, the shape of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the shape of the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be different from each other. The first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) may be arranged in the same row as the first pixel circuit (PC), but may extend in the direction of the pixel circuit of the adjacent column, for example, the pixel circuit arranged in the i-th row and the j-1-th column, so as to be integral with the first oxide semiconductor pattern of the pixel circuit arranged in the j-1-th column. In contrast, the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may have an isolated shape. Of course, if necessary, the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) may also have an isolated shape. In this case, the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be approximately symmetrical with respect to the imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0155] The second oxide semiconductor pattern (1520) arranged in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape, but may be integral with two adjacent pixel circuits. For example, as illustrated in FIG. 17, the second oxide semiconductor pattern (1520) belonging to the first pixel circuit (PC1) may be integral with the second oxide semiconductor pattern (1520) of the pixel circuit located in the -x direction, that is, the pixel circuit located in the j-1th column, and the second oxide semiconductor pattern (1520) belonging to the second pixel circuit (PC2) may be integral with the second oxide semiconductor pattern (1520) of the pixel circuit located in the +x direction, that is, the pixel circuit located in the j+2th column. The second oxide semiconductor pattern (1520) of the first pixel circuit (PC1) and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) may be approximately symmetrical with respect to the aforementioned virtual line (IML).

[0156] The second oxide semiconductor pattern (1520) may include a second semiconductor layer (A2) of the second transistor (T2) and a third semiconductor layer (A3) of the third transistor (T3). That is, the second semiconductor layer (A2) of the second transistor (T2) and the third semiconductor layer (A3) of the third transistor (T3) may be connected integrally. The second semiconductor layer (A2) and the third semiconductor layer (A3) included in the second oxide semiconductor pattern (1520) may overlap with a first reference gate line (GRL) of a scan line (GWL) described later with reference to FIG. 18. That is, the portion overlapping with the scan line (GWL) of the second oxide semiconductor pattern (1520) may be the second semiconductor layer (A2), and the portion overlapping with the first reference gate line (GRL) of the second oxide semiconductor pattern (1520) may be the third semiconductor layer (A3).

[0157] The third oxide semiconductor pattern (1530) arranged in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape, but may be integral with two adjacent pixel circuits. For example, as illustrated in FIG. 17, the third oxide semiconductor pattern (1530) belonging to the first pixel circuit (PC1) may be integral with the third oxide semiconductor pattern (1530) of the pixel circuit located in the -x direction, that is, the pixel circuit located in the j-1th column, and the third oxide semiconductor pattern (1530) belonging to the second pixel circuit (PC2) may be integral with the third oxide semiconductor pattern (1530) of the pixel circuit located in the +x direction, that is, the pixel circuit located in the j+2th column. The third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be approximately symmetrical with respect to the aforementioned virtual line (IML).

[0158] The third oxide semiconductor pattern (1530) may include a seventh semiconductor layer (A7) of a seventh transistor (T7). The seventh semiconductor layer (A7) included in the third oxide semiconductor pattern (1530) may overlap with a second reference gate line (GCL) which will be described later with reference to FIG. 18. That is, the portion of the third oxide semiconductor pattern (1530) that overlaps with the second reference gate line (GCL) may be the seventh semiconductor layer (A7).

[0159] The fourth oxide semiconductor pattern (1540) may be arranged on the first pixel circuit (PC1). The fourth oxide semiconductor pattern (1540) may be arranged at a position corresponding to one end of the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2), and may correspond to a type of dummy electrode.

[0160] Each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may include at least a partially conductive region. For example, at least a portion of each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be subjected to a treatment such as doping or plasma treatment, so that the portion thus treated may have conductivity.

[0161] A third gate insulating layer (109) may be arranged to cover the semiconductor layer (1500). This may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. This second gate insulating layer (105) may have a single-layer structure or a multi-layer structure.

[0162] A third gate layer (1600) as illustrated in FIG. 18 may be arranged on the third gate insulating layer (109). In FIG. 18, for convenience, the third gate layer (1600) is illustrated as overlapping the semiconductor layer (1500) therebelow. In FIG. 18, the third gate layer (1600) is illustrated as including a first gate electrode (1610), a seventh conductive layer (1620), an eighth conductive layer (1630), a first reference gate line (GRL), a scan line (GWL), a second reference gate line (GCL), a second emission control line (EMBL), and an auxiliary power line (1640). These components in the first pixel circuit (PC1) and these components in the second pixel circuit (PC2) may be approximately symmetrical with respect to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0163] The first gate electrode (1610), the seventh conductive layer (1620), the eighth conductive layer (1630), the first reference gate line (GRL), the scan line (GWL), the second reference gate line (GCL), and the auxiliary power line (1640) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. The components included in the third gate layer (1600) may be formed simultaneously with the same material, and thus may have the same layer structure.

[0164] The first gate electrode (1610) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) has an isolated shape and may be the gate electrode of the first transistor (T1). The portion overlapping the first gate electrode (1610) of the first oxide semiconductor pattern (1510) becomes a channel region (C1), and both sides of the channel region (C1) may be conductive regions (S1, D1) doped with impurities or processed with plasma to be conductive. One of the conductive regions (S1, D1) may be a source region and the other may be a drain region. The source region and the drain region may correspond to the source electrode and the drain electrode. Of course, the positions of the source region and the drain region may be switched depending on the properties of the transistor.

[0165] The seventh conductive layer (1620) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape, but may be integral with two adjacent pixel circuits. For example, as illustrated in FIG. 18, the seventh conductive layer (1620) belonging to the first pixel circuit (PC1) may be integral with the seventh conductive layer (1620) of the pixel circuit located in the -x direction, that is, the pixel circuit located in the j-1th column, and the seventh conductive layer (1620) belonging to the second pixel circuit (PC2) may be integral with the seventh conductive layer (1620) of the pixel circuit located in the +x direction, that is, the pixel circuit located in the j+2th column.

[0166] The seventh conductive layer (1620) may be a gate electrode of the fourth transistor (T4). A part of the seventh conductive layer (1620) corresponds to the fourth gate electrode (G4), and a portion overlapping the seventh conductive layer (1620) of the first oxide semiconductor pattern (1510) becomes a channel region (C4), and both sides of the channel region (C4) may be conductive regions (S4, D4) doped with impurities or processed with plasma to be conductive. One of the conductive regions (S4, D4) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode. Of course, the positions of the source region and the drain region may be swapped depending on the properties of the transistor. This seventh conductive layer (1620) can be connected to the first emission control line (EML) through a contact hole (1620CT) formed in the second gate insulating layer (105), the first interlayer insulating layer (107), the second interlayer insulating layer (108), and the third gate insulating layer (109).

[0167] The eighth conductive layer (1630) may be positioned across the first pixel circuit (PC1) and the second pixel circuit (PC2) and may have an isolated shape. The eighth conductive layer (1630) may be connected to a horizontal connection line (DHL) described later, and may serve to electrically connect disconnected portions of the horizontal connection line (DHL). This will be described later.

[0168] A first reference gate line (GRL) may extend approximately along a first direction (x-axis direction) so as to pass through a first pixel circuit (PC1) and a second pixel circuit (PC2). The first reference gate line (GRL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). The first reference gate line (GRL) may be connected to a first conductive layer (1210) through a contact hole (GRLCT) formed in a second gate insulating layer (105), a first interlayer insulating layer (107), a second interlayer insulating layer (108), and a third gate insulating layer (109). A part of the first reference gate line (GRL) corresponds to the third gate electrode (G3), and a portion of the second oxide semiconductor pattern (1520) overlapping with the first reference gate line (GRL) becomes a channel region (C3), and both sides of this channel region (C3) may be conductive regions (S3, D3) doped with impurities or processed with plasma to become conductive. One of the conductive regions (S3, D3) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode. Of course, the positions of the source region and the drain region may be switched depending on the properties of the transistor.

[0169] A scan line (GWL) may extend approximately along a first direction (x-axis direction) so as to pass through a first pixel circuit (PC1) and a second pixel circuit (PC2). The scan line (GWL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). A part of the scan line (GWL) corresponds to a second gate electrode (G2), and a portion of the second oxide semiconductor pattern (1520) overlapping with the scan line (GWL) becomes a channel region (C2), and both sides of the channel region (C2) may be conductive regions (S2, D2) doped with impurities or processed with plasma to be conductive. One of the conductive regions (S2, D2) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode. Of course, the positions of the source and drain regions can be swapped depending on the properties of the transistor.

[0170] A second reference gate line (GCL) may extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second reference gate line (GCL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). A part of the second reference gate line (GCL) corresponds to the seventh gate electrode (G7), and a portion of the third oxide semiconductor pattern (1530) overlapping with the second reference gate line (GCL) becomes a channel region (C7), and both sides of the channel region (C7) may be conductive regions (S7, D7) doped with impurities or processed with plasma to be conductive. One of the conductive regions (S7, D7) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode. Of course, the positions of the source and drain regions can be swapped depending on the properties of the transistor.

[0171] The second emission control line (EMBL) may extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second emission control line (EMBL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). The second emission control line (EMBL) may be connected to the fourth conductive layer (1240) through a contact hole (EMBLCT) formed in the second gate insulating layer (105), the first interlayer insulating layer (107), the second interlayer insulating layer (108), and the third gate insulating layer (109). A part of the second emission control line (EMBL) corresponds to the sixth gate electrode (G6), and a portion overlapping the second emission control line (EMBL) of the first oxide semiconductor pattern (1510) becomes a channel region (C6), and both sides of this channel region (C6) may be conductive regions (S6, D6) doped with impurities or processed with plasma to become conductive. One of the conductive regions (S6, D6) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode. Of course, the positions of the source region and the drain region may be switched depending on the properties of the transistor.

[0172] The auxiliary power line (1640) may extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The auxiliary power line (1640) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2). The auxiliary power line (1640) may be connected to a driving voltage line (PL) described later, so that a set of the auxiliary power lines (1640) and the driving voltage lines (PL) may have a mesh structure in the display area (DA).

[0173] A third interlayer insulating layer (111) may be arranged to cover the third gate layer (1600). The third interlayer insulating layer (111) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The third interlayer insulating layer (111) may have a single-layer structure or a multi-layer structure. For example, the third interlayer insulating layer (111) may have a laminated structure of a layer including silicon oxide and a layer including silicon nitride. Of course, the third interlayer insulating layer (111) may be an organic insulating layer including an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0174] A first source-drain layer (1700) as illustrated in FIG. 19 may be disposed on the third interlayer insulating layer (111). In FIG. 19, the first source-drain layer (1700) is illustrated as including a driving voltage line (PL), a first connection electrode (1720), a second connection electrode (1730), a third connection electrode (1740), a fourth connection electrode (1750), a fifth connection electrode (1760), a sixth connection electrode (1772), a seventh connection electrode (1774), an eighth connection electrode (1776), a dummy connection electrode (1776'), and a horizontal connection line (DHL). These components in the first pixel circuit (PC1) and these components in the second pixel circuit (PC2) may be approximately symmetrical with respect to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0175] The driving voltage line (PL), the first connecting electrode (1720), the second connecting electrode (1730), the third connecting electrode (1740), the fourth connecting electrode (1750), the fifth connecting electrode (1760), the sixth connecting electrode (1772), the seventh connecting electrode (1774), the eighth connecting electrode (1776), and the horizontal connecting line (DHL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. The components included in the first source-drain layer (1700) can be formed simultaneously with the same material, and thus can have the same layer structure.

[0176] The driving voltage line (PL) may have a shape extending in the second direction (y-axis direction) along an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). This driving voltage line (PL) may be connected to an auxiliary power line (1640) through a contact hole (PLCT1) formed in the lower third interlayer insulating layer (111). Through this connection structure, a plurality of driving voltage lines (PL) and a plurality of auxiliary power lines (1640) may form a mesh structure in the display area (DA), thereby minimizing the voltage drop (IR drop) of the driving voltage (ELVDD). Meanwhile, the driving voltage line (PL) can be connected to the silicon semiconductor layer (1110) through a contact hole (PLCT2) formed in the first gate insulating layer (103), the second gate insulating layer (105), the first interlayer insulating layer (107), the second interlayer insulating layer (108), the third gate insulating layer (109), and the third interlayer insulating layer (111). Through this, the silicon semiconductor layer (1110) can be made to have a potential that is the same as or similar to the driving voltage (ELVDD).

[0177] The first connection electrode (1720) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The first connection electrode (1720) may be electrically connected to the first semiconductor layer (A1) of the first transistor (T1) through a contact hole (1720CT1) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). In addition, the first connection electrode (1720) can be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5) through a contact hole (1720CT2) formed in the first gate insulating layer (103), the second gate insulating layer (105), the first interlayer insulating layer (107), the second interlayer insulating layer (108), the third gate insulating layer (109), and the third interlayer insulating layer (111). Accordingly, the first connection electrode (1720) can electrically connect the first transistor (T1) and the fifth transistor (T5).

[0178] The second connection electrode (1730) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The second connection electrode (1730) may correspond to the first node (N1) in the pixel circuit (PC) of FIG. 10. The second connection electrode (1730) may be electrically connected to the first gate electrode (1610) of the first transistor (T1) through a contact hole (1730CT3) formed in the third interlayer insulating layer (111). In addition, the second connection electrode (1730) may be electrically connected to the third semiconductor layer (A3) through a contact hole (1730CT1) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). In addition, the second connection electrode (1730) can be electrically connected to the third conductive layer (1230) by passing through an opening formed in the fifth conductive layer (1310) through a contact hole (1730CT2) formed in the second gate insulating layer (105), the first interlayer insulating layer (107), the second interlayer insulating layer (108), the third gate insulating layer (109), and the third interlayer insulating layer (111). Accordingly, the second connection electrode (1730) can electrically connect the first gate electrode (G1) of the first transistor (T1), the third transistor (T3), and the first storage electrode (CEs1).

[0179] The third connection electrode (1740) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The third connection electrode (1740) may correspond to the second node (N2) in the pixel circuit (PC) of FIG. 10. The third connection electrode (1740) may be electrically connected to the fifth conductive layer (1310) including the second storage electrode (CEs2) and the second hold electrode (CEh2) through a contact hole (1740CT1) formed in the first interlayer insulating layer (107), the second interlayer insulating layer (108), the third gate insulating layer (109), and the third interlayer insulating layer (111). In addition, the third connection electrode (1740) can be electrically connected to the first oxide semiconductor pattern (1510) through a contact hole (1740CT2) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). The connection point of the third connection electrode (1740) and the first oxide semiconductor pattern (1510) can be located between an area corresponding to the first semiconductor layer (A1) and an area corresponding to the sixth semiconductor layer (A6, FIG. 17) among the first oxide semiconductor pattern (1510). Through this, the third connection electrode (1740) can electrically connect the second storage electrode (CEs2), the second hold electrode (CEh2), the first transistor (T1), and the sixth transistor (T6).

[0180] The fourth connection electrode (1750) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape, but may be integral with the first pixel circuit (PC1) and the pixel circuit positioned in the j-1th column, and may also be integral with the second pixel circuit (PC2) and the pixel circuit positioned in the j+2th column. The fourth connection electrode (1750) may be electrically connected to the third semiconductor layer (A3) through a contact hole (1750CT1) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). In addition, the fourth connection electrode (1750) may be electrically connected to the seventh semiconductor layer (A7) through a contact hole (1750CT2) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). This fourth connection electrode (1750) is electrically connected to a reference voltage line (VRL, FIG. 20) to be described later, and can transmit the reference voltage (VREF) to the third transistor (T3) and the seventh transistor (T7).

[0181] The fifth connection electrode (1760) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fifth connection electrode (1760) may be electrically connected to the second conductive layer (1220), which is the first hold electrode (CEh1) of the hold capacitor (Chd), through a contact hole (1760CT1) formed in the second gate insulating layer (105), the first interlayer insulating layer (107), the second interlayer insulating layer (108), the third gate insulating layer (109), and the third interlayer insulating layer (111). In addition, the fifth connection electrode (1760) may be electrically connected to the seventh semiconductor layer (A7) through a contact hole (1760CT2) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). Through this, the fifth connection electrode (1760) can electrically connect the first hold electrode (CEh1) and the seventh transistor (T7).

[0182] The sixth connection electrode (1772) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The sixth connection electrode (1772) may be electrically connected to the second semiconductor layer (A2) through a contact hole (1772CT) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). The sixth connection electrode (1772) may be electrically connected to a data line (DL, FIG. 20) to be described later, and may transmit a data signal (DATA) to the second transistor (T2).

[0183] The seventh connection electrode (1774) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The seventh connection electrode (1774) may be electrically connected to the fourth semiconductor layer (A4) of the fourth transistor (T4) through a contact hole (1774CT) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). The seventh connection electrode (1774) may be electrically connected to the pixel electrode (210) of the light-emitting diode (LED) as described below.

[0184] The eighth connection electrode (1776) located in the second pixel circuit (PC2) may have an isolated shape. In the second pixel circuit (PC2), the eighth connection electrode (1776) may be electrically connected to the fourth semiconductor layer (A4) of the fourth transistor (T4) through a contact hole (1776CT) formed in the third gate insulating layer (109) and the third interlayer insulating layer (111). The eighth connection electrode (1776) may be electrically connected to an initialization voltage line (VL, FIG. 20) passing through the second pixel circuit (PC2), as described below, to transmit the initialization voltage (VINT) to the fourth transistor (T4). For reference, the fourth transistor (T4) located in the first pixel circuit (PC1) located in the j-th column is electrically connected to the fourth transistor of the pixel circuit located in the j-1-th column (adjacent in the -x direction), as illustrated in FIG. 17. Therefore, the fourth transistor (T4) located in the first pixel circuit (PC1) may be electrically connected to the initialization voltage line (not illustrated) passing through the pixel circuit located in the j-1-th column (adjacent in the -x direction), rather than the initialization voltage line (VL, FIG. 20) passing through the first pixel circuit (PC1).

[0185] The dummy connection electrode (1776') located in the first pixel circuit (PC1) may have an isolated shape. The dummy connection electrode (1776') may be electrically connected to the fourth oxide semiconductor pattern (1540), which is also a dummy pattern, through a contact hole (1776CT'). For reference, the dummy connection electrode (1776') may be approximately symmetrical with the eighth connection electrode (1776) with respect to the imaginary line (IML).

[0186] Horizontal connection lines (DHL) extending approximately in the first direction (x-axis direction) but interrupted by the driving voltage line (PL) can be electrically connected to the eighth conductive layer (1630) through contact holes (DHLCT) formed in the third interlayer insulating layer (111). Accordingly, the set of the eighth conductive layer (1630) and the horizontal connection line (DHL) can correspond to a part of the data transmission line (DTL) described with reference to FIG. 8 or FIG. 9, for example, one of the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), or the third horizontal connection line (DHL3). If the horizontal connection line (DHL) needs to be electrically connected to the vertical connection line (DVL, see FIG. 20) described later, it can be electrically connected to the vertical connection line (DVL) at the part where the contact hole (DHLCT) is located.

[0187] In this way, a fourth interlayer insulating layer (113) may be disposed on the first source-drain layer (1700) described with reference to FIG. 19. The fourth interlayer insulating layer (113) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The fourth interlayer insulating layer (113) may have a single-layer structure or a multi-layer structure. For example, the fourth interlayer insulating layer (113) may have a laminated structure of a layer including silicon oxide and a layer including silicon nitride. Of course, the fourth interlayer insulating layer (113) may be an organic insulating layer including an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0188] A second source-drain layer (1800) as illustrated in FIG. 20 may be disposed on the fourth interlayer insulating layer (113). FIG. 20 illustrates that the second source-drain layer (1800) includes a data line (DL), a vertical connection line (DVL), an initialization voltage line (VL), a reference voltage line (VRL), and a ninth connection electrode (1810). These components in the first pixel circuit (PC1) and these components in the second pixel circuit (PC2) may be approximately symmetrical with respect to an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0189] Each of the data line (DL), the vertical connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) may extend along the second direction (y-axis direction). The data line (DL), the vertical connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the first pixel circuit (PC1), and the data line (DL), the vertical connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the second pixel circuit (PC2) may be substantially symmetrical with respect to an imaginary line (IML).

[0190] The data line (DL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the sixth connection electrode (1772) described with reference to FIG. 19 through a contact hole (DLCT) formed in the fourth interlayer insulating layer (113), thereby providing a data signal to the second transistor (T2).

[0191] The vertical connection line (DVL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may correspond to a portion of the data transmission line (DTL) described with reference to FIG. 8 or FIG. 9, for example, any one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3'). The vertical connection line (DVL) has a portion protruding in the first direction (x-axis direction), and thus, when it is necessary to be electrically connected to the horizontal connection line (DHL) located below, it may be electrically connected to the horizontal connection line (DHL) through a contact hole formed in the fourth interlayer insulating layer (113) at the protruding portion.

[0192] The initialization voltage line (VL) passing through the second pixel circuit (PC2) is electrically connected to the eighth connection electrode (1776) at the bottom through a contact hole (VLCT) formed in the fourth interlayer insulating layer (113), and the eighth connection electrode (1776) is electrically connected to the first oxide semiconductor pattern (1510) at the bottom through a contact hole (1776CT), so as to provide an initialization voltage to the fourth transistor (T4) of the second pixel circuit (PC2).

[0193] The initialization voltage line (VL) passing through the first pixel circuit (PC1) can be electrically connected to the dummy connection electrode (1776') through the contact hole (VLCT) formed in the fourth interlayer insulating layer (113). As described above with reference to FIG. 19, the fourth transistor (T4) located in the first pixel circuit (PC1) located in the j-th column is electrically connected to the fourth transistor of the pixel circuit located in the j-1-th column (adjacent in the -x direction) as illustrated in FIG. 17. Therefore, the fourth transistor (T4) located in the first pixel circuit (PC1) can be electrically connected to the initialization voltage line (not shown) passing through the pixel circuit located in the j-1-th column (adjacent in the -x direction), rather than the first initialization voltage line (VL) passing through the first pixel circuit (PC1).

[0194] Of course, if necessary, the semiconductor layer (1500) may be made symmetrical with respect to the imaginary line (IML) in the first pixel circuit (PC1) and the second pixel circuit (PC2) so that the fourth oxide semiconductor pattern (1540) of the first pixel circuit (PC1) becomes integral with the first oxide semiconductor pattern (1510). In this case, the initialization voltage line (VL) passing through the first pixel circuit (PC1) may be electrically connected to the fourth transistor (T4) of the first pixel circuit (PC1).

[0195] The reference voltage line (VRL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) can be electrically connected to the fourth connection electrode (1750) described above with reference to FIG. 19 through a contact hole (VRLCT) formed in the fourth interlayer insulating layer (113). As described above, the fourth connection electrode (1750) can be electrically connected to the second oxide semiconductor pattern (1520) and the third oxide semiconductor pattern (1530) to provide a reference voltage to the third transistor (T3) and the seventh transistor (T7).

[0196] For reference, the first pixel circuit (PC1) located in the j-th column can share a reference voltage line (VRL) with the pixel circuit located in the j-1-th column adjacent in the -x direction, and the second pixel circuit (PC2) located in the j+1-th column can share a reference voltage line (VRL) with the pixel circuit located in the j+2-th column adjacent in the +x direction.

[0197] The ninth connection electrode (1810) may each have an isolated shape. The ninth connection electrode (1810) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the seventh connection electrode (1774) described above with reference to FIG. 19 through a contact hole (1810CT) formed in the fourth interlayer insulating layer (113). The ninth connection electrode (1810) may also be electrically connected to the upper pixel electrode (210) through an upper contact hole (210CT). As described above, the seventh connection electrode (1774) may be electrically connected to the fourth transistor (T4) and the sixth transistor (T6). Accordingly, the seventh connection electrode (1774) and the ninth connection electrode (1810) can electrically connect the pixel electrode of the light-emitting diode (LED) to the fourth transistor (T4) and the sixth transistor (T6).

[0198] A planarization layer (115) may be arranged to cover the second source-drain layer (1800). The planarization layer (115) may be an organic insulating layer including an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0199] A light emitting diode (LED) may be arranged on the planarization layer (115). The light emitting diode (LED) may include a pixel electrode (210), an intermediate layer (220), and a common electrode (230) on the planarization layer (115). Fig. 21 illustrates arrangement of pixel electrodes (210). For reference, since the light emitting diode includes the pixel electrode (210), the position of the pixel electrode (210) may be referred to as the position of the light emitting diode. In Fig. 21, for convenience, the pixel electrodes (210) are illustrated overlapping the second source / drain layer (1800) thereunder.

[0200] As illustrated in FIG. 21, light emitting diodes (LEDs) may be arranged to be spaced apart from each other. FIG. 21 illustrates that a second light emitting diode (LED2) overlapping a first pixel circuit (PC1) and a second pixel circuit (PC2) is electrically connected to the first pixel circuit (PC1) located in the i-th row and the j-th column. In this way, the second light emitting diode (LED2) may be positioned on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2), but as illustrated in FIG. 21, the pixel electrode (210) of the second light emitting diode (LED2) may have a protrusion protruding in the -x direction and may be electrically connected to the first pixel circuit (PC1) through a contact hole (210CT) formed in the planarization layer (115) at the protrusion. Other light emitting diodes also have a pixel electrode (210) with a protrusion that can be electrically connected to a corresponding pixel circuit through a contact hole (210CT) underneath the protrusion.

[0201] Four third light-emitting diodes (LED3) can be arranged around the second light-emitting diode (LED2). In Fig. 21, the third light-emitting diodes (LED3) are shown as being positioned at the four corners of a square-shaped dotted line indicating the boundary of the set of the first pixel circuit (PC1) and the second pixel circuit (PC2). That is, in FIG. 21, the third light-emitting diode (LED3) located at the lower right is electrically connected to the second pixel circuit (PC2) located at the i-th row and the j+1-th column, the third light-emitting diode (LED3) located at the upper right is electrically connected to the pixel circuit located at the i-1-th row and the j+1-th column adjacent to the second pixel circuit (PC2) in the +y direction, the third light-emitting diode (LED3) located at the lower left is electrically connected to the pixel circuit located at the i-th row and the j-1-th column adjacent to the first pixel circuit (PC1) in the -x direction, and the third light-emitting diode (LED3) located at the upper left is electrically connected to the pixel circuit located at the i-1-th row and the j-1-th column.

[0202] For reference, the first light-emitting diode, which is not shown, may be electrically connected to a pixel circuit located at the i-1th row and jth column adjacent to the first pixel circuit (PC1) in the +y direction. In addition, the first light-emitting diodes may be electrically connected to a pixel circuit located at the i-th row and j+2th column adjacent to the second pixel circuit (PC2) in the +x direction, to a pixel circuit located at the i-th row and j-2th column, and to a pixel circuit located at the i+1th row and jth column adjacent to the first pixel circuit (PC1) in the -y direction. In the case of the first light-emitting diode, similarly to the second light-emitting diode (LED2), four third light-emitting diodes (LED3) may be arranged around the first light-emitting diode.

[0203] In this way, the pixel circuits arranged in the +x direction in the i-th row may be a set of pixel circuits for the first light-emitting diode, pixel circuits for the third light-emitting diode (LED3), pixel circuits for the second light-emitting diode (LED2), and pixel circuits for the third light-emitting diode (LED3) that are repeated. And, the pixel circuits arranged in the y-axis direction in the j-th column may be a set of pixel circuits for the first light-emitting diode and pixel circuits for the second light-emitting diode (LED2), and the pixel circuits arranged in the second direction (y-axis direction) in each of the j-1-th column and the j+1-th column may be pixel circuits for the third light-emitting diode (LED3).

[0204] For example, the first light-emitting diode may be a diode that emits red light, the second light-emitting diode (LED2) may be a diode that emits blue light, and the third light-emitting diode (LED3) may be a diode that emits green light.

[0205] Of course, the arrangement of light-emitting diodes is not limited to this arrangement and can be modified in various ways.

[0206] The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (210) may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof, and a transparent or translucent electrode layer positioned on the reflective layer. The transparent or translucent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO). x : It may include at least one selected from the group including ZnO or ZnO2), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (210) may have a three-layer structure of ITO / Ag / ITO.

[0207] A pixel definition film (119) may be disposed on the planarization layer (115). The pixel definition film (119) may cover the edge of the pixel electrode (210) and increase the distance between the pixel electrode (210) and the common electrode (230) above it, thereby preventing arcs from occurring at the edge of the pixel electrode (210). That is, as illustrated in FIGS. 21 and 22, the pixel definition film (119) may have an opening (119OP) to expose the central portion of the pixel electrode (210). In this way, the exposed portion of the pixel electrode (210) may be defined as a light-emitting area (EA). The pixel definition film (119) may be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by a method such as spin coating.

[0208] At least a portion of an intermediate layer (220) including an emission layer of a light emitting diode (LED) may be disposed within an opening formed in a pixel defining layer (119). An emission area of ​​the light emitting diode (LED) may be defined by this opening. This intermediate layer (220) may include an emission layer. The emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may be a low-molecular organic material or a high-molecular organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be further selectively disposed below and above the emission layer.

[0209] Alternatively, the intermediate layer (220) may include a first stack including a light-emitting layer and a functional layer, a second stack including a light-emitting layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. In the case of a tandem light-emitting diode (LED) having a plurality of light-emitting layers by the negative charge generation layer and the positive charge generation layer, the light-emitting efficiency can be further increased.

[0210] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0211] The light-emitting layer may have a patterned shape corresponding to the pixel electrode (210). Layers other than the light-emitting layer included in the intermediate layer (220) may be modified in various ways, such as being integral with a plurality of pixel electrodes (210).

[0212] The common electrode (230) may be a transparent electrode or a reflective electrode. For example, the common electrode (230) may be a transparent or semitransparent electrode, and may include a metal thin film with a small work function, such as Li, Ca, Al, Ag, Mg, or a compound thereof (e.g., LiF). In addition, the common electrode (230) may further include a TCO (transparent conductive oxide) film, such as ITO, IZO, ZnO, ZnO2, or In2O3, positioned on the metal thin film.

[0213] The common electrode (230) may be formed as a single body over the entire display area (DA) to cover the display area (DA), and may be arranged on the upper portion of the intermediate layer (220) and the pixel definition film (119). That is, each of the pixel electrodes (210) is arranged to correspond to each light-emitting diode (LED), and the common electrode (230) may be formed as a single body to correspond to a plurality of light-emitting diodes (LEDs). The plurality of light-emitting diodes (LEDs) may share the common electrode (230), and the stacked structure of the pixel electrode (210), the intermediate layer (220), and the common electrode (230) may correspond to a light-emitting diode (LED).

[0214] If necessary, an encapsulation layer may be disposed on the light emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0215] As described above, the fifth conductive layer (1310) may be both the second storage electrode (CEs2) of the storage capacitor (Cst) and the first hold electrode (CEh1) of the hold capacitor (Chd). If the potential of the second storage electrode (CEs2) of the storage capacitor (Cst) in each pixel circuit becomes unstable, the first transistor (T1), which is a driving transistor, may not be able to control the amount of current that accurately corresponds to the data signal (DATA). This may result in the display device not being able to display high-quality images.

[0216] However, in the case of the display panel (10) according to the present embodiment and the electronic device (1) including the same, as described above, the silicon semiconductor layer (1110) is electrically connected to the driving voltage line (PL). And, the extension portion (ETP) of the silicon semiconductor layer (1110) is located between the first transistor (T1) of the first pixel circuit (PC1) and the first transistor of the second pixel circuit (PC2) in the plan view. Specifically, the extension portion (ETP) of the silicon semiconductor layer (1110) is located between the fifth conductive layer (1310) corresponding to the second node (N2) of the first transistor (T1) of the first pixel circuit (PC1) and the fifth conductive layer (1310) corresponding to the second node (N2) of the first transistor (T1) of the second pixel circuit (PC2) in the plan view. Accordingly, the extension portion (ETP) of the silicon semiconductor layer (1110) having a potential of a driving voltage (ELVDD) or a voltage similar thereto can effectively prevent or minimize the second node (N2) of the first pixel circuit (PC1) and the second node (N2) of the second pixel circuit (PC2) from electrically affecting each other. Through this, a display panel (10) that displays high-quality images and an electronic device (1) including the same can be implemented.

[0217] In order to effectively prevent the second node (N2) of the first pixel circuit (PC1) and the second node (N2) of the second pixel circuit (PC2) from electrically affecting each other, the end of the extension (ETP) of the silicon semiconductor layer (1110) in the second direction (y-axis direction) may be made to coincide with the end of the portion adjacent to the extension (ETP) of the fifth conductive layer (1310) in the first pixel circuit (PC1) in the second direction (y-axis direction) and the end of the portion adjacent to the extension (ETP) of the fifth conductive layer (1310) in the second pixel circuit (PC2) in the second direction (y-axis direction).

[0218] For reference, as described above, the fifth transistors (T5), which are light-emitting control transistors in the first pixel circuit (PC1) and the second pixel circuit (PC2), include the main portion (MP) of the silicon semiconductor layer (1110) as a component. Accordingly, the fifth transistor (T5) of the first pixel circuit (PC1) may include a portion of the main portion (MP) located on one side with respect to the extension portion (ETP), that is, a portion of the main portion (MP) located in the -x direction with respect to the extension portion (ETP). Similarly, the fifth transistor (T5) of the second pixel circuit (PC2) may include a portion of the main portion (MP) located on the other side with respect to the extension portion (ETP), that is, a portion of the main portion (MP) located in the +x direction with respect to the extension portion (ETP). And each of the two ends of the main part (MP) can be electrically connected to the corresponding first transistor (T1) by the first connection electrode (1720) as described above.

[0219] So far, various electronic devices (1), display panels (10) and / or display modules (11) have been described, and each of these electronic devices (1), display panels (10) and / or display modules (11) can be said to fall within the scope of the present invention.

[0220] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

[0221] A display panel capable of displaying high-quality images and an electronic device including the same can be implemented.

Claims

1. First transistors arranged adjacently along the first direction; and A silicon semiconductor layer having a main portion extending along a first direction and an extension portion extending in a second direction intersecting the first direction, wherein the extension portion is interposed between the first transistors in a plan view; A display panel having a .

2. In paragraph 1, A display panel, wherein each of the first transistors has a first semiconductor layer and a first gate electrode positioned on the first semiconductor layer and overlapping the first semiconductor layer.

3. In paragraph 2, A display panel, wherein the first semiconductor layer includes an oxide semiconductor.

4. In paragraph 2, A display panel further comprising a gate insulating layer covering the silicon semiconductor layer, wherein the first semiconductor layer is positioned on top of the insulating layer.

5. In paragraph 4, A display panel further comprising capacitor electrodes disposed between the gate insulating layer and the first semiconductor layer and spaced apart from each other to correspond to the first transistors.

6. In paragraph 5, A display panel in which the extension portion is interposed between the capacitor electrodes in the plan view.

7. In paragraph 5, A display panel, wherein the end of the extension portion in the second direction coincides with the end of the portion adjacent to the extension portion of each of the capacitor electrodes in the second direction.

8. In paragraph 5, A display panel further comprising shield layers interposed between the capacitor electrodes and the first transistors.

9. In paragraph 8, A display panel, wherein each of the above shield layers is electrically connected to a corresponding one of the above capacitor electrodes.

10. In paragraph 1, Second transistors corresponding to the first transistors; and Data lines corresponding to the above second transistors; Equip more, Each of the second transistors has one end electrically connected to a corresponding one of the data lines and the other end electrically connected to a first gate electrode of a corresponding one of the first transistors. A display panel, wherein the second semiconductor layer of each of the second transistors is positioned on the same layer as the first semiconductor layer of each of the first transistors.

11. In paragraph 1, A display panel further comprising a driving voltage line electrically connected to the above silicon semiconductor layer.

12. In paragraph 11, The above driving voltage line is located on the upper part of the silicon semiconductor layer, the display panel.

13. In paragraph 1, It further comprises light-emitting control transistors including a part of the main part located on one side of the extension part and a part of the main part located on the other side, A display panel, wherein each of the above light-emitting control transistors is electrically connected to a corresponding one of the first transistors.

14. In paragraph 13, A display panel further comprising connection electrodes electrically connecting each of the two ends of the main portion to a corresponding one of the first transistors.

15. Display panel; and A lower cover forming an exterior and having an opening exposing a portion of the display panel; Includes, The above display panel, First transistors arranged adjacently along the first direction; and A silicon semiconductor layer having a main portion extending along a first direction and an extension portion extending in a second direction intersecting the first direction, wherein the extension portion is interposed between the first transistors in a plan view; An electronic device having.

16. In paragraph 15, An electronic device, wherein each of the first transistors has a first semiconductor layer and a first gate electrode positioned on the first semiconductor layer and overlapping the first semiconductor layer.

17. In paragraph 16, An electronic device wherein the first semiconductor layer includes an oxide semiconductor.

18. In paragraph 16, A gate insulating layer is further provided covering the silicon semiconductor layer, and the first semiconductor layer is positioned on top of the insulating layer. An electronic device further comprising capacitor electrodes interposed between the gate insulating layer and the first semiconductor layer and spaced apart from each other so as to correspond to the first transistors.

19. In paragraph 18, An electronic device in which the extension portion is interposed between the capacitor electrodes in the plan view.

20. In paragraph 15, An electronic device further comprising a driving voltage line electrically connected to the above silicon semiconductor layer.

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