Method and system for estimating integrated circuit yield

Abstract

A method, system, and apparatus for determining a yield estimate for an integrated circuit are provided. The method includes the acts of generating a set of vectors of scaled parameter values, simulating an output of the circuit to identify a subset of the set of vectors, identifying a set of points on boundaries of failure regions in the parameter space, generating a set of sample points for each failure region. and determining a yield estimate based on the sets of sample points

Description

METHOD AND SYSTEM FOR ESTIMATING INTEGRATED CIRCUIT YIELDTECHNICAL FIELD

[0001] The present disclosure relates to methods and systems for determining a yield estimate for manufacturing an integrated circuit and, in particular, determining an accurate yield estimate for rare failure events.BACKGROUND

[0002] Circuit design verification is used to test integrated circuit designs under varying manufacturing conditions. Foundry models (e.g., SPICE models) describe the variation in the manufacturing process. The foundry models describe distributions of parameters that may van' during manufacture, such as an oxide thickness, oxide length, or the like.

[0003] A design verification tool may be utilized to evaluate a circuit design relative to the manufacturing variability described in the foundry models. A designer defines outputs of the circuit design and performance specifications for the outputs. The design verification tool evaluates the circuit to determine a probability that a particular manufacturing variation described in the foundry models may cause the circuit design to fail to meet the performance specifications.

[0004] In some cases, designers may have concerns about the occurrences of rare failure events. One technique for estimating probability of failures is Monte Carlo (MC) sampling of variable parameters in the foundry model. MC techniques simulate the circuit design with samples at one or more process, voltage, and temperature (PVT) comers. The design verification tool may compare the results of the SPICE simulation against the performance specifications to determine whether failures occurred, which may inform the designers about whether the worst of the MC samples from the foundry models would cause outputs of the circuit design to fail to meet the performance specification.

[0005] Failure events with occurrence probabilities of less than one in a billion may require billions of circuit simulations to measure accurately. Some tools speed up MC sampling using machine learning. A machine learning model may be built to predict the probability of sample failing based on a few thousand SPICE simulations. The model may then be used to evaluate the full MC population much faster than brute forcing the MC population using a SPICE simulator. The samples that have highest failureprobability are simulated in SPICE. Using this technique, MC and SPICE-accurate estimates may be made for rare failure probabilities.

[0006] Despite the efficiency gains, machine learning methods suffer from a number of limitations. Generating billions of samples with many dimensions requires significant computational effort. These computational costs create a practical limit to how rare of a probability may be measured. Further, some outputs may be composite outputs with multiple sources of failure. This may happen either by combining multiple failure checks into a single output, for example, combining a series of rise / fall transition checks for a multi-bit flip flop into a single pass / fail output, or simply by the nature of the circuit that may have multiple components that may cause the output to fail a specification. This provides that one needs a complicated machine learning model in order to model the output. Complicated models require more training data and more computational effort, increasing the cost of modelling. In some cases, the complexity of the output makes it so the output simply cannot be modelled accurately enough to correctly select failing samples.

[0007] Further, generating the training data for the model may be tricky. Some methods use scaled MC samples to increase the likelihood of a failure. However, finding the right scale may be challenging. If the chosen scale is too small, not enough failures will be found. If the scale is too large, more failures will be found, but there is a risk that failures will be found from failure regions of very low probability relative to other failure regions that have a higher probability and actually matter to the yield. The presence of data from irrelevant failure regions makes it more difficult to build a useful model.SUMMARY

[0008] It is an object of the invention to provide a method for determining SPICE and MC-accurate yield estimates in fixed time.

[0009] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0010] In a first aspect, a method for determining a yield estimate for an integrated circuit is provided. The method is computer-implemented. The method includes generating a set of vectors, where each vector of the set of vectors includes a scaled sample of parameter values in a foundry model. The foundry model representsvariation of parameters of a manufacturing process for manufacturing the integrated circuit. The method includes simulating an output of the integrated circuit for each vector in the set to identify a subset of vectors where the output of the integrated circuit fails to meet a predefined specification. The method includes identifying a set of points based on the subset of vectors, where each point in the set of points lies on a boundary of a failure region in a parameter space of the foundry model and each failure region including a region of the parameter space where the output of the integrated circuit fails to meet the predefined specification. The method includes generating, for each point in the set of points, a set of sample points in the failure region associated with the point, where the set of sample points corresponds to a random distribution of points in a tail of a population of Monte Carlo-distributed points in the parameter space, and determining a yield estimate based on the sets of sample points.

[0011] Preferably, the set of vectors includes scaled samples of parameter values with different levels of scaling.

[0012] Preferably, simulating the output for each vector in the set of vectors includes simulating an output of the integrated circuit with a first vector including a scaled sample of parameter values with a first level of scaling, determining that the output fails to meet the predefined specification for the first vector, and simulating an output of the integrated circuit with a second vector including the parameter values of the first vector, with a second level of scaling, lower than the first level of scaling.

[0013] Preferably, simulating the output to identify the subset of vectors includes including a vector in the subset, where the level of scaling of the parameter values of the vector corresponds to a minimum level of scaling at which the simulated output of the circuit fails to meet the predefined specification.

[0014] Preferably, identifying the set of points includes: a) identifying a first vector from the subset as a first reference point relative to an origin point in the parameter space; b) sampling a plurality of points in a region of the first reference point in the parameter space; c) generating a classifier based on the plurality of points, where the classifier determines a second reference point; d) evaluating points along an arc between the first reference point and the second reference point, based on the classifier, to identify a third reference point in the failure region containing the first reference point, with a lower distance to the origin point than the first reference point; e) iteratively repeating acts b) - d) with the third reference point to obtain a point on the boundary of the failure region containing the first vector; and f) including the point onthe boundary' of the failure region in the set of points.

[0015] Preferably, identifying the set of points further includes, repeatedly: selecting a vector from the subset that does not lie in failure regions containing previously selected vectors; and repeating acts a) to f) for the selected vector, until there are no further vectors in the subset.

[0016] Preferably, generating a set of sample points in the failure region associated with a point includes: generating a set of sample vectors from a predefined probability distribution; and transforming each sample vector in the set of sample vectors into the failure region associated with the point.

[0017] Preferably , the predefined probability distribution is a multidimensional standard normal distribution.

[0018] Preferably, transforming each vector in the set of sample vectors into the failure region includes: a) splitting the sample vector into a first component and a second component, where the first component is parallel to the point associated with the failure region, and the second component is orthogonal to the point; b) transforming the first component to a further point in the failure region; and c) translating the second component to the further point in the failure region.

[0019] These and other aspects of the invention will be apparent from the embodiments described below.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conj unction with the accompanying drawings, in which:

[0021] Figure 1 shows an example of a computer system of the type that may be used to implement various embodiments;

[0022] Figure 2 illustrates an example design verification tool for estimating integrated circuit yield;

[0023] Figure 3 is a block diagram of a method for determining a yield estimate, according to an example;

[0024] Figure 4 is a block diagram of a method for identifying a point on a boundary of a failure region, according to an example;

[0025] Figures 5A and 5B show a graphical representation of classification of sample points in a parameter space, according to an example; and

[0026] Figures 6A and 6B show a graphical representation of a tail sampling method, according to an example.DETAILED DESCRIPTION

[0027] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments may be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0028] Accordingly, while embodiments may be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0029] The terminology used herein to describe embodiments is not intended to limit the scope. The articles '‘a,” “an,” and “the” are singular in that the articles have a single referent; how ever, the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular may number one or more unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms including technical and scientific terms used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0031] Various examples may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As shown in Figure 1, the computing device 101 includes a computing unit 103 with a processor unit 105 and a system memory 107. The processor unit 105 may be any type of programmable electronic device for executing software instructions, but willconventionally be a microprocessor. The system memory 107 may include both a readonly memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 1 11 may store software instructions for execution by the processor unit 105.

[0032] The processor unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processor unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117 that may be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (e.g., a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer, and speakers. With various examples of the computing device 101, one or more of the peripheral devices 1 15-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0033] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 may translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0034] The computing device 101 is illustrated as an example only and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1,which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multiprocessor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0035] Figure 2 shows an example of a design verification tool 200 for determining a yield estimated that may be implemented according to various embodiments. Figure 3 shows a block diagram of a method 300 for determining a yield estimate for an integrated circuit, according to various examples. Referring to Figures 2 and 3, the design verification tool 200, for example, implemented with the computing device 101 described in Figure 1, receives a circuit design 201 describing an electronic device, such as an integrated circuit, for example, in a transistor-level netlist format. The circuit design 201 may correspond to transistor-level netlists describing electronic circuits using metal-oxide-semiconductor (MOS) transistors, resistances, capacitors, inductances, or the like (e.g.. in a Simulation Program w ith Integrated Circuit Emphasis (SPICE) file format).

[0036] The design verification tool 200 receive a foundry model 202. The foundry model 202 describes process variation parameters that vary during manufacturing such as oxide thickness, oxide length, or the like. In some embodiments, the foundry model 202 describes the statistical conditions for manufacturing the circuit design 201, for example, defining a distribution of values for the manufacturing parameters. In some embodiments, the foundry model 202 is specified in a SPICE file format. In some cases, the combination of the circuit design 201 and the foundry model 202 is referred to as the test bench for the design verification tool 200.

[0037] The design verification tool 200 receives a specification 203 for the performance or operation of the circuit design 201 . In some embodiments, the specification 203 defines outputs associated with the circuit design 201 and defines when values for the outputs would correspond to a failure. In some examples, outputs may relate to electrical performance specification such as input / output voltage levels or noise margins. In other examples, outputs may relate to timing performance such as propagation delay or rise and fall times. In yet further examples, outputs may relate to thermal performance such as junction temperature. In yet further examples, outputs may relate to functional performance such as error rates. In other cases, other types of performance may also be identified in the specification 203.

[0038] The specification 203 may define a minimum value and a maximum value for an output in the circuit design 201. The performance of the circuit design 201 is deemed a failure for a given process variation, when an output value falls below the minimum value or exceeds the maximum value. The design verification tool 200 also receives process comers 204 defining a combination of factors, such as process, voltage, and temperature (PVT), for the manufacture and / or operation of integrated circuits described by the circuit design 201.

[0039] The design verification tool 200 includes a scaled sampling system 211 that, at block 301 of the method 300 in Figure 3, performs scaled sampling of the parameter space described by the foundry model 202, by generating a set of vectors. Each vector includes a scaled sample of parameter values based on the foundry model 202. According to examples, scaled sampling may be performed by scaling the parameter value distribution as described by the foundry model 202, and sampling from the scaled distribution using a normal distribution. The set of vectors may include a vector of parameter values at different levels of scaling. In other words, the set of vectors may include a first vector including scaled parameter values at a first level of scaling, a second vector including the same parameter values as the first vector, but at a second level of scaling that is lower than the first level of scaling, a third vector at a third level of scaling lower than the second level, and so on.

[0040] The design verification tool 200 includes a design simulator 212 that, at block 302, simulates an output of the integrated circuit for each vector in the set, to identify a subset of vectors where the output of the integrated circuit fails to meet the specification 203. The design simulator 212 may be a transistor-level simulator to simulate operation of the circuit design 201 having parameters that vary- based on parameter values as specified in a sampled vector. Since the operation of the circuit design 201 varies based on the values of the parameters, the design simulator 212 determines values for outputs defined in the specification 203 that also vary.

[0041] The design simulator 212 determines whether any of the values of the outputs determined during simulation fall outside of the specification 203, for example, by exceeding a maximum value for the output or falling below a minimum value for the output. When the design simulator identifies that an output falls outside of the specification 203, the design simulator 212 identifies the corresponding vector of parameters as a failure. The design simulator 212 may subsequently re-simulate the integrated circuit with a second vector that has the same parameter values at a lowerlevel of scaling to determine whether the output fails to meet the specification at the lower level of scaling. This may be repeated to find a lowest level of scaling at which a vector of parameter values fails. This method assumes that if a sample fails at a particular scale, the sample will fail at all larger scales, and if the sample passes at a particular scale, the sample will pass at all smaller scales. At the end of this process, a subset of the set of vectors is identified where each vector in the subset is scaled to a lowest scaling level at which the parameter values still fail.

[0042] An initial yield estimate may be determined before further acts are carried out to determine an accurate yield estimate. In some cases, an accurate yield estimate may be determined when the initial yield estimate is within a predefined range. If the initial yield estimate is very high or very low relative to this range, the method 300 may be terminated early. A method such as the method described in the US patent.US11,361,142 B2 may be used to give an initial yield estimate, based on the identified subset of vectors.

[0043] The design verification tool 200 includes a failure region sampling system 213 that, at block 303, identifies a set of points based on the subset of vectors. Each point in the set of points lies on a boundary of a failure region in the parameter space of the foundry' model 202. A failure region includes points in the parameter space of the foundry' model 202 where, for each point in the failure region, the output of the integrated circuit fails to meet the specification 203. In general, there may be multiple such failure regions. In some cases, failure regions may overlap.

[0044] Figure 4 shows a block diagram of a method 400 for identifying a point on a boundary' of a failure region. Figure 5A depicts a two-dimensional graphical representation of the method 400. The method 400 implements block 303 of the method 300. At block 401 of the method 400. a first vector, selected from the subset of vectors from block 302, is identified as a first reference point relative to an origin point in the parameter space. Referring to Figure 5 A, a first reference point 501 may be identified based on the selection of a first vector from the subset. At block 402. a plurality of points is sampled in a region around the first reference point in the parameter space.

[0045] At block 403, a classifier is generated to predict a failure region boundary based on the plurality of points. In Figure 5, the classifier is depicted as the line 502. Points in region 503 correspond to vectors of parameter values where the output of the integrated circuit meets the specification 203, and points 504 correspond to vectors of parameters values where the output of the integrated circuit fails to meet thespecification 203. The classifier 502 may not be a perfect prediction of the failure region boundary.

[0046] At block 404, points along an arc between the first reference point 501 and a second reference point 505 are evaluated in order to identify a most probable failure point in a particular failure region. This is depicted in Figure 5B. Vectors, such as vectors 506, 507, are selected at a number of points (e.g., several points) along the arc 508, with each vector set to the same norm as the first reference point 501. If any of the new vectors fail, then the norm of the vector is reduced until the output for the parameter values corresponding to the vector changes from a failure back to a pass. When that happens, the new vector determines a new reference point with a smaller norm than the first reference point.

[0047] Blocks 402 to 404 may be repeated with the new reference point replacing the first reference point. This may be continued iteratively until the reference point resolves to a most probable failure point for the particular failure region. The method 400 may be repeated to determine a set of points where each point corresponds to a most probable failure point of a different failure region, and where each point serves as a linear classifier for a pass / fail boundary for the failure region.

[0048] Referring again to Figures 2 and 3, the failure region sampling system, at block 304, generates, for each point in the set of points identified at block 303, a set of sample points in the failure region associated with the point. The set of sample points correspond to a random distribution of points in a tail of a population of Monte Carlo (MC) distributed points in the parameter space. The sets of sample points 221 are output by the design verification tool 200.

[0049] A set of sample points may be generated from a predefined distribution, such as a multidimensional normal distribution, and transformed into a failure region. Figures 6 A and 6B depict a method for transforming a vector drawn from a predefined distribution into a failure region. Figure 6A depicts sample points 601 drawn from a tw o-dimensional normal distribution, centered on the origin, a vector 602 corresponding to the point drawn from the set of points from block 302, and the classifier 603 for that point corresponding to the failure region boundary. The method for transforming a sample point drawn from the normal distribution proceeds as follows: an initial sample vector corresponding to, for example, one of the sample points 601, is separated into components parallel and orthogonal to the vector 602. The parallel component is used to determine a cumulative distribution function value to apply to determine a location inthe failure region. The orthogonal component is then translated into the failure region. Figure 6B depicts the result of transforming samples 601 into the region 604.

[0050] The transformed sample points may be interpreted as samples drawn from the tail of a population of brute force-generated MC samples. The number of samples represented, N, may be determined by the expected number of samples from a MC population that w ould be needed to produce the number of drawn tail samples:where n is the number of samples drawn from the failure region, F(x) is the cumulative distribution function for a standard normal distribution denoting P(X < x). and o is the magnitude of the vector to the tail region. For example, if the defined tail has a MC probability of 1 in 1 million and 1000 samples are drawn from that tail distribution, then that is equivalent to drawing 1 billion samples and selecting only the 1000 samples that are in the tail of the distribution.

[0051] A total number of MC samples may be estimated by using the norm of the failure regions or by using a more accurate yield estimation technique such as line sampling. Then, the points found at block 303 are set to the same magnitude, and samples are drawn in the tail using the tail sampling method. If there are too many samples (e.g., too many failures to find them all) or too few samples (e.g., yield is not measured accurately enough), then the MC population size may be adjusted and new samples draw n. If there is more than one failure region, it is possible that those failure regions are not completely independent. In order to prevent over sampling an overlapping region, samples for each failure region are produced one at a time. All samples draw n are checked against previous failure regions, and any sample that falls into a previously sampled tail is dropped. The selected samples are sorted according to the distance along the failure region vector with the samples farthest in the failure region simulated first.

[0052] The design verification tool 200 includes a yield estimation system 214 that, in a block 305 of Figure 3, estimates a yield 222. The yield estimation system 214 outputs the yield estimate 222, which may predict a yield for an output defined in the specification 203 given the parameter distributions described in the foundry models 202. The yield estimate is calculated based on sample points, generated by the failure region sampling system 213.

[0053] The methods and systems described herein result in a yield estimate that isequivalent to a brute-force MC yield estimate. In contrast to prior methods, the method described herein produces a yield estimate with this level of accuracy in fixed time. This method is more efficient than any previous method, particularly for very rare failure cases. The method is scalable to arbitrarily rare probabilities within a fixed computational overhead. By changing to focus on failure regions instead of specifications, outputs with multiple failure regions are naturally decomposed, and failure regions are solved one at a time. This provides a cleaner method compared to methods that solve all failure regions for a specification at once. Solving specific failure regions produces simpler learning models such as linear classifiers. Other methods also require far more training data. By sampling around failures and building simpler models, the initial sampling method becomes much simpler and may work with fewer initial failures.

[0054] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software, and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0055] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0056] The processor memory may be integrated together with the processing device (e.g., RAM or FLASH memory disposed within an integrated circuit microprocessor or the like). In other examples, the memory may include an independent device, such as an external disk drive, a storage array, a portable FLASH key7fob, or the like. The memory' and processing device may be operatively coupled together, or in communication with each other (e.g., by an I / O port, a network connection, or the like), and the processing device may read a file stored on the memory. Associated memorymay be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may include moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

[0057] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (e.g., or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may include storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0058] A program stored in a computer-readable storage medium may include a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program, or operation with unclear boundaries.

[0059] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices, and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary,and / or additional blocks may be added.

[0060] The present inventions may be embodied in other specific apparatus and / or methods. The described embodiments are to be considered in all respects as illustrative and not restrictive. In particular, the scope of the invention is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0061] The elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present invention. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent. Such new combinations are to be understood as forming a part of the present specification.

[0062] While the present invention has been described above by reference to various embodiments, it should be understood that many changes and modifications can be made to the described embodiments. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and / or combinations of embodiments are intended to be included in this description.

Claims

CLAIMS1. A method for determining a yield estimate for an integrated circuit, the method being computer-implemented and comprising: generating a set of vectors, each vector of the set of vectors comprising a scaled sample of parameter values in a foundry model, wherein the foundry model represents a variation of parameters of a manufacturing process for manufacturing the integrated circuit; simulating an output of the integrated circuit for each vector in the set of vectors, such that a subset of vectors of the set of vectors where the output of the integrated circuit fails to meet a predefined specification is identified; identifying a set of points based on the subset of vectors, each point in the set of points lying on a boundary of a failure region in a parameter space of the foundry model, each failure region comprising a region of the parameter space where the output of the integrated circuit fails to meet the predefined specification; generating, for each point in the set of points, a set of sample points in the failure region associated with the point, wherein the set of sample points corresponds to a random distribution of points in a tail of a population of Monte Carlo-distributed points in the parameter space; and determining a yield estimate for the integrated circuit based on the sets of sample points.2 The method of claim 1, wherein the set of vectors comprises scaled samples of parameter values with different levels of scaling.

3. The method of claim 2, wherein simulating the output for each vector in the set of vectors comprises: simulating an output of the integrated circuit with a first vector comprising a scaled sample of parameter values with a first level of scaling; determining that the output fails to meet the predefined specification for the first vector; and simulating an output of the integrated circuit with a second vector, the second vector comprising the parameter values of the of the first vector with a second level of scaling, the second level of scaling being lower than the first level of scaling.

4. The method of claim 3, further comprising including a vector in the subset of vectors, wherein a level of scaling of parameter values of the vector corresponds to a minimum level of scaling at which the simulated output of the integrated circuit fails to meet the predefined specification.

5. The method of claim 1. wherein identifying the set of points comprises: identifying a first vector from the subset of vectors as a first reference point relative to an origin point in the parameter space; sampling a plurality of points in a region of the first reference point in the parameter space; generating a classifier based on the plurality of points, wherein the classifier determines a second reference point; evaluating points along an arc between the first reference point and the second reference point, based on the classifier, such that a third reference point in the failure region containing the first reference point, with a smaller distance to the origin point than the first reference point, is identified; iteratively repeating the sampling, the generating of the classifier, and the evaluating with the third reference point, such that a point on the boundary of the failure region containing the first vector is obtained; and including the point on the boundary of the failure region in the set of points.

6. The method of claim 5, wherein identifying the set of points further comprises, repeatedly: selecting a vector from the subset of vectors that does not lie in failure regions containing previously selected vectors; and repeating the identifying of the first vector, the sampling, the generating of the classifier, the evaluating, the iteratively repeating, and the including of the point for the selected vector until there are no further vectors in the subset.

7. The method of claim 1, wherein for each point in the set of points, generating the set of sample points in the failure region associated with the point comprises: generating a set of sample vectors from a predefined probability distribution; andtransforming each sample vector in the set of sample vectors into the failure region associated with the point.

8. The method of claim 7, wherein the predefined probability distribution is a multidimensional standard normal distribution.

9. The method of claim 8, wherein transforming each sample vector in the set of sample vectors into the failure region comprises: splitting the sample vector into a first component and a second component, wherein the first component is parallel to the point associated with the failure region, and the second component is orthogonal to the point; transforming the first component to a further point in the failure region; and translating the second component to the further point in the failure region.

10. A system comprising: a memory’ system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, that is configured to: generate a set of vectors, each vector of the set of vectors comprising a scaled sample of parameter values in a foundry’ model, wherein the foundry model represents a variation of parameters of a manufacturing process for manufacturing an integrated circuit; simulate an output of the integrated circuit for each vector in the set of vectors, such that a subset of vectors where the output of the integrated circuit fails to meet a predefined specification is identified; identify a set of points based on the subset of vectors, each point in the set of points lying on a boundary’ of a failure region in a parameter space of the foundry’ model, each failure region comprising a region of the parameter space where the output of the integrated circuit fails to meet the predefined specification; generate, for each point in the set of points, a set of sample points in the failure region associated with the point, wherein the set of sample points corresponds to a random distribution of points in a tail of a population of Monte Carlo-distributed points in the parameter space; anddetermine a yield estimate for the integrated circuit based on the sets of sample points.1 1. The system of claim 10, wherein the set of vectors comprises scaled samples of parameter values with different levels of scaling.

12. The system of claim 11, wherein the computing system being configured to simulate the output of the integrated circuit for each vector in the set of vectors comprises the computing system being configured to: simulate an output of the integrated circuit with a first vector comprising a scaled sample of parameter values with a first level of scaling; determine that the output fails to meet the predefined specification for the first vector; and simulate an output of the integrated circuit with a second vector, the second vector comprising the parameter values of the of the first vector with a second level of scaling, the second level of scaling being lower than the first level of scaling.

13. The system of claim 12, wherein the computing system is further configured to: include a vector in the subset of vectors, wherein a level of scaling of parameter values of the vector corresponds to a minimum level of scaling at which the simulated output of the integrated circuit fails to meet the predefined specification.

14. The system of claim 10, wherein the computing system being configured to generate the set of sample points in the failure region associated with the point comprises the computing system being configured to: generate a set of sample vectors from a predefined probability distribution; and transform each sample vector in the set of sample vectors into the failure region associated with the point.

15. An apparatus comprising: at least one computer-readable memory device that stores instructions configured to cause one or more processing devices to perform operations, the instructions comprising:generating a set of vectors, each vector of the set of vectors comprising a scaled sample of parameter values in a foundry model, wherein the foundry model represents a variation of parameters of a manufacturing process for manufacturing an integrated circuit; simulating an output of the integrated circuit for each vector in the set of vectors, such that a subset of vectors of the set of vectors where the output of the integrated circuit fails to meet a predefined specification is identified; identifying a set of points based on the subset of vectors, each point in the set of points lying on a boundary of a failure region in a parameter space of the foundry model, each failure region comprising a region of the parameter space where the output of the integrated circuit fails to meet the predefined specification; generating, for each point in the set of points, a set of sample points in the failure region associated with the point, wherein the set of sample points corresponds to a random distribution of points in a tail of a population of Monte Carlo-distributed points in the parameter space; and determining a yield estimate for the integrated circuit based on the sets of sample points.

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