Systems and methods for digital-twin based open circuit switch fault detection for 5l-ANPC converters

Abstract

Process and device configurations are provided for digital-twin configurations for monitoring five-level active neutral point clamped (5L-ANPC) power converters. Processes include monitoring parameters to assess converter performance and detect open-circuit faults in switches of converters. Embodiments provide a fast fault diagnostic method that can diagnose a faulty switch within a fundamental period of the inverter output frequency. Processes can leverage load current data and switching patterns for fault detection and eliminate the need for load voltage sensors. Methods and configurations are robust and effective across various modulation indices and loading conditions providing practical applicability and can increase system reliability for multiple applications, including applications for utility power generation and electrified transportation vehicles. The digital-twin model for a 5L-ANPC can detect and analyze faults including fault flag parameters, a disturbance flag and fault onset time to identify a circuit switch of the 5L-ANPC.

Description

SYSTEMS AND METHODS FOR DIGITAL-TWIN BASED OPEN CIRCUIT SWITCH FAULT DETECTION FOR 5L-ANPC CONVERTERSCROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. provisional application No. 63 / 677,254 titled DIGITAL-TWIN BASED OPEN CIRCUIT SWITCH FAULT DETECTION FOR 5L-ANPC CONVERTERS filed on July 30, 2024, the content of which is expressly incorporated by reference in its entirety.FIELD

[0002] The present disclosure generally relates to circuit fault detection and control operations for monitoring power circuits using a digital-twin, including methods for detecting and controlling switching failures for multilevel neutral point converters including five-level active natural point clamped (5L-ANPC) power converters.STATEMENT OF GOVERNMENT SUPPORT

[0003] This invention was made with Government support and is supported in part by Award No. 2228872 awarded by the National Science Foundation. The Government has certain rights in the invention.BACKGROUND

[0004] Power systems often use converters for utility applications and conversion of electrical power. Many of these systems are applied to safety-critical applications. There is a desire to enhance system reliability for power converters and for fault detection. Recent studies have explored applications of digital-twin health monitoring models for power circuits. For example, models have be used for a DC-DC buck converter using particle swarm optimization. Other approaches have used artificial neural networks (ANN) for DC-DC boost converters. There is limited use of digital-twin models for power converters beyond DC-DC converters. Moreover, existing systems often rely on measuring components and diagnostics that require specialized sensors and equipment, such as load voltage sensors and current sensors for power converters. There exists a desire and a need for improvements to health monitoring of power circuits.BRIEF SUMMARY OF THE EMBODIMENTS

[0005] Disclosed and described herein are systems, methods and configurations for open-circuit fault diagnosis for power converters. In one embodiment, a method is provided for open-circuit fault diagnosis of a multilevel neutral point clamped converter including receiving, by a digitaltwin control device, phase load current for each phase of a multilevel neutral point clamped converter. The method also includes determining, by the digital-twin control device, at least one fault flag parameter for each phase of the multilevel neutral point clamped converter, wherein the at least one fault flag parameter is determined using real-time phase load current of each phase. The method also includes detecting, by the digital-twin control device, a disturbance flag using the fault flag parameters, and identifying, by the digital-twin control device, a faulty phase leg of multilevel neutral point clamped converter and at least one component of the multilevel neutral point clamped converter. The method also includes controlling, by the digital-twin control device, a digital-twin model for fault analysis of the multilevel neutral point clamped converter, the digital-twin model configured to determine a fault onset time for the faulty phase leg and identify a fault cell of the multilevel neutral point clamped converter. The method also includes outputting, by the digital-twin control device, a fault flag determination of the digital-twin model.

[0006] In one embodiment, the digital-twin control device is configured to include the digitaltwin model for fault analysis for a five-level active neutral point converter (5L-ANPC), and wherein the digital-twin model receives DC-link capacitor voltage of the multilevel neutral point clamped converter as input for fault analysis.

[0007] In one embodiment, the control device is a digital-twin fault detection device, and wherein the at least one fault flag parameter for each phase of the converter is determined using a difference between real-time current measurements and delayed currents in each phase of the multilevel neutral point clamped converter.

[0008] In one embodiment, detecting a disturbance flag includes monitoring fault flag parameters for each phase and comparing the fault flag parameters to a predetermined disturbance threshold.

[0009] In one embodiment, identifying a faulty phase leg includes comparing the fault flag parameters to identify a phase of the multilevel neutral point clamped converter and a circuit half of the multilevel neutral point clamped converter including circuit components.

[0010] In one embodiment, controlling the digital-twin model for fault analysis includes analyzing faults in a detected set of possible faulty switches and quantifying a difference between measured current and current determined by the digital-twin model.

[0011] In one embodiment, controlling the digital-twin model for fault analysis includes comparing voltage of a flying capacitor of the multilevel neutral point clamped converter with an adaptive threshold to identify a faulty switch of the multilevel neutral point clamped converter.

[0012] In one embodiment, output of the fault flag determination includes identification of a circuit switch of the converter and an open circuit fault condition of the switch.

[0013] In one embodiment, the digital-twin model for fault analysis includes an R-L load, and wherein the digital-twin model is configured to continuously monitor phase load current of each phase and to identify a faulty circuit switch within a fundamental period of converter output frequency.

[0014] In one embodiment, the method includes outputting, by the digital-twin model, a control signal to the multilevel neutral point clamped converter for control based on the fault flag determination.

[0015] Another embodiment is directed to a digital-twin control device for open-circuit fault diagnosis for a multilevel neutral point clamped converter. The digital-twin control device includes a communication interface, a memory storing executable instructions, and a controller coupled to the communication interface and the memory. The controller is configured to receive phase load currents of a multilevel neutral point clamped converter, and determine at least one fault flag parameter for each phase of the converter, wherein the fault flag parameters are determined using real-time phase load currents of each phase. The controller is configured to detect a disturbance flag using the fault flag parameters, and identify a faulty phase leg and at least one component of the converter. The controller is configured to control a digital-twin model for fault analysis of the converter, the digital-twin model configured to determine a faultonset time for the faulty phase leg and identify a fault cell of the converter. The controller is configured to output a fault flag determination of the digital -twin model.

[0016] Other aspects, features, and techniques will be apparent to one skilled in the relevant art in view of the following detailed description of the embodiments.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

[0018] FIG. 1A is a graphical representation of a digital-twin model for a converter according to one or more embodiments;

[0019] FIG. IB is a graphical representation of a five-level active neutral point clamped (5L- ANPC) power converter according to one or more embodiments;

[0020] FIG. 1C is a graphical representation of a digital-twin control device according to one or more embodiments;

[0021] FIG. ID is a graphical representation of a digital-twin model for a converter according to one or more embodiments;

[0022] FIG. 2 illustrates a process for open-circuit fault diagnosis of a multilevel neutral point clamped converter according to one or more embodiments;

[0023] FIG. 3 is a graphical representation of fault diagnosis and localization for a 5L-ANPC converter configuration according to one or more embodiments;

[0024] FIG. 4 illustrates phase voltage and three-phase current for an open-circuit fault according to one or more embodiments;

[0025] FIG. 5 illustrates DC-link voltages and measured and filtered flying capacitor voltages according to one or more embodiments;

[0026] FIG. 6 illustrates three phase load currents, a disturbance flag, fault flags for each phase, and a PWM pulse for a faulty switch according to one or more embodiments;

[0027] FIG. 7 illustrates phase currents and phase current comparisons according to one or more embodiments;

[0028] FIG. 8 illustrates three phase load currents, a disturbance flag, fault flags for each phase, and a PWM pulse for a faulty switch according to one or more embodiments;

[0029] FIG. 9 illustrates a comparison of measured phase current and digital-twin output according to one or more embodiments;

[0030] FIG. 10 illustrates a graphical representation of a current flow through a flying capacitor according to one or more embodiments;

[0031] FIG. 11 illustrates a comparison of flying capacitor voltage and adaptive thresholds according to one or more embodiments;

[0032] FIG. 12 illustrates three phase load currents, a disturbance flag, fault flags for each phase, and a PWM pulse for a faulty switch according to one or more embodiments;

[0033] FIG. 13 illustrates a comparison of phase current and digital -twin output according to one or more embodiments;

[0034] FIG. 14 illustrates capacitor voltages following a fault according to one or more embodiments;

[0035] FIG. 15 illustrates comparing capacitor voltage with adaptive thresholds according to one or more embodiments;

[0036] FIG. 16 illustrates a graphical representation of a 5L-ANPC inverter test rig according to one or more embodiments;

[0037] FIG. 17 illustrates three phase load currents, a disturbance flag, fault flags for each phase, and a PWM pulse for a faulty switch according to one or more embodiments;

[0038] FIG. 18 illustrates a comparison of measured current, digital-twin current and current differences according to one or more embodiments;

[0039] FIG. 19 illustrates open-circuit fault conditions according to one or more embodiments;

[0040] FIG. 20 illustrates open-circuit fault conditions according to one or more embodiments;

[0041] FIG. 21 illustrates open-circuit fault conditions according to one or more embodiments;

[0042] FIG. 22 illustrates load current step-up conditions according to one or more embodiments;

[0043] FIG. 23 illustrates load current step-down conditions according to one or more embodiments;

[0044] FIG. 24 illustrates frequency ramp-up conditions according to one or more embodiments;

[0045] FIG. 25 illustrates open-circuit fault conditions according to one or more embodiments; and

[0046] FIG. 26 illustrates open-circuit fault conditions according to one or more embodiments.DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTSOverview and Terminology

[0047] One aspect of the disclosure is directed to monitoring health and fault detection of power devices, including high power safety-critical applications. In one embodiment, processes and configurations are provided for detecting phase currents and parameters from power converters to detect open fault conditions. Detection of fault conditions is necessary for power safety and device operation. Operations and configurations discussed herein improve the detection and monitoring of faults. Embodiments are directed to open-circuit fault diagnosis for a multilevel neutral point clamped converters using a digital-twin strategy.

[0048] According to embodiments, processes, systems and device configurations include a digital-twin strategy tailored for monitoring the health condition of five-level active neutral point clamped (5L-ANPC) power converters, extensively utilized in high-power applications.Reliability of 5L-ANPC power converters may be compromised due to the large number of semiconductor devices they employ, posing challenges for converter deployment in safety- critical applications. Embodiments may utilize a real-time digital-twin replica of a 5L-ANPC that continuously monitors crucial parameters to assess the converter performance and detect open-circuit faults in the switches. Processes and device configurations enhance reliability and reduce maintenance downtime costs. Specifically focusing on open-circuit switching faults, embodiments present a fast online fault diagnostic method. Processes of the embodiments can leverage existing DC-link capacitor and flying capacitors voltage, along with load current data and switching patterns, eliminating the need for any load voltage sensors. Detection of an open circuit fault may take less than a fundamental period of the inverter output frequency to diagnose the faulty switch accurately. Experimental tests validate the robustness and effectiveness of the proposed processes and configurations and experimental results are described across various modulation indices and loading conditions. The experimental results highlight practical applicability and reliability enhancement capabilities of the embodiments.

[0049] According to embodiments, processes and configurations are described as relating to power converters, such as 5L-ANPC power converters. It should be appreciated that embodiments may equally apply to 5L-ANPC power inverters. In addition, embodiments andthe principles of the disclosure may also apply to other power converters, including other neutral point clamped configurations for power converters, inverters, etc.

[0050] As used herein, the terms “a” or “an” shall mean one or more than one. The term “plurality” shall mean two or more than two. The term “another” is defined as a second or more. The terms “including” and / or “having” are open ended (e.g., comprising). The term “or” as used herein is to be interpreted as inclusive or meaning any one or any combination. Therefore, “A, B or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B and C”. An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive.

[0051] Reference throughout this document to “one embodiment, certain embodiments, an embodiment,” or similar term means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of such phrases in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner on one or more embodiments without limitation.Exemplary Embodiments

[0052] FIG. 1 A is a graphical representation of a digital -twin model for a converter according to one or more embodiments. According to embodiments, systems, methods and device configurations provide a digital-twin for detecting and controlling switching failures for multilevel neutral point converters including five-level active natural point clamped (5L-ANPC) power converters. System 100 includes power converter 105 and digital -twin control device 110. Power converter 105 may be a five-level active neutral point clamped (5L-ANPC) power converter. Digital -twin control device 110 may be configured to communicate and / or control operations of power converter 105 including detecting one of more faults. Digital control device110 may communicate with power converter 105 by way of bidirectional communication bus111 which may include one or more communication channels for providing control data and receiving sensory data from power converter 105. According to embodiments, digital -twin control device 110 may be configured to operate using a digital -twin model 115 of power converter 105. As discussed herein, the digital -twin model may provide processes include monitoring parameters to assess converter performance and detect open-circuit faults in switches of converters. Digital -twin model 115 may be configured to include a digital representation or model of circuit components representing components of a 5L-ANPC power converter.According to embodiments, digital -twin model 115 includes R-L (resistor-inductor) load 116 for modeling power converter operation. FIG. IB illustrates components of a power converter that may be used in digital -twin model 115 for a power converter. It should be appreciated that the principles of the disclosure may be applied to other circuit configurations and are not limited to the circuit components shown for the 5L-ANPC power converter. A five-level converter may by similar to a three-level converter, however the five-level converter includes an additional capacitor. The five-level converter also uses five DC voltage levels, unlike three-level converters.

[0053] According to embodiments, one or more control devices may be configured for operation as digital control device 110 and / or digital-twin model, such as a connected device and / or device in communication with power converter 105. Digital-twin models and control devices (e.g., digital control device 110) for the digital-twin models can provide fast fault diagnostic methods that can diagnose a faulty switch within a fundamental period of the inverter output frequency. Processes can leverage load current data and switching patterns for fault detection and eliminatethe need for load voltage sensors. Digital-twin models and control devices as discussed herein are robust and effective across various modulation indices and loading conditions providing practical applicability and can increase system reliability for multiple applications, including applications for utility power generation and electrified transportation vehicles. The digital-twin model for a 5L-ANPC can detect and analyze faults including fault flag parameters, a disturbance flag and fault onset time to identify a circuit switch of the 5L-ANPC.

[0054] According to embodiments, digital control device 110 may be configured to use a digitaltwin (DT) model that includes a representation of a physical system on a digital platform (e.g., system microprocessors, cloud or edge data centers), replicating and predicting the performance of a physical system (i.e., physical twin). As shown in FIG. 1 A, using a power electronic converter as an example, an interactive virtual DT model is continuously updated with real-time sensory data acquired from the corresponding real-world physical systems, so the DT model can provide high-fidelity health monitoring information to the real converter system. Internet of Things (loT) technologies have accelerated the progress and importance of DT models. By establishing interconnected networks among various physical devices, loT enables seamless communication and data exchange. The abundance of data collected within the loT platform can be effectively analyzed using artificial intelligence (Al) techniques, facilitating the implementation of comprehensive DT models for various physical systems. Such transformative changes may revolutionize traditional power electronics design, control, and supervisory methodologies, ushering in a new era of innovative digital solutions.

[0055] The applications of DT technologies using embodiments of the disclosure may extend to various processes, products, and systems, offering notable advantages when applied to electrified transportation systems such as electric aircraft propulsion. In these domains, DT models may be employed to provide predictive system performance and enable the execution of extreme condition tests in a safe and cost-effective manner. The use of DT may also facilitate health monitoring, estimation and extension of the remaining useful lifetime, and fault-tolerance considering different stages of the mission profiles. Industries may implement DT in design verification, manufacturing processes, product lifecycle assessment, and health monitoring strategies. By leveraging the DT technologies, product designs, optimization, operation and maintenance, as well as recycling can be dramatically enhanced.

[0056] According to embodiments, processes, devices, and system configurations may be configured to provide a switch failure mechanism in power converters. Switching failures in power converters can be classified into two categories, namely, short-circuit failures and opencircuit failures. Short-circuit failures require very fast detection and protection (e.g., within 10 microseconds), so the detection and protection are generally implemented in associated gate drivers. For the emerging wide bandgap semiconductor devices such as Silicon Carbide (SiC) or Gallium Nitride (GaN) switches, the required short-circuit fault detection speed becomes faster, in the range of a few microseconds or even hundreds of nanoseconds, due to the increasing transconductance and decreasing thermal capacity with the small die size. Therefore, to guarantee prompt protection speed, instead of relying on online diagnostic algorithms embedded in microcontrollers, short-circuit detection is typically implemented through the gate driver desaturation circuits implemented in most of commercial gate drivers.

[0057] Open-circuit switching faults can be destructive to the system operation. Semiconductor internal wire-bonding lift-off due to thermal-mechanical stress and mismatched coefficients of thermal expansion (CTE) between wire-bonds, chips and the substrate may be root causes for open-circuit faults of power switches. Overload operation, gate driver failures, or a short-circuit- fault-induced switch rupture may also lead to such an open-circuit failure mode. Open-circuit faults usually result in significant DC offset current, distorted output voltage and current waveforms, unequal thermal stress over switching devices, and pulsating torque in motor-drive applications. Open circuit faults can cause cascaded failures and eventually result in collapse of the holistic power conversion system if an effective diagnostic method is unavailable. Embodiments can include detection and diagnosis of open-circuit faults of the 5L-ANPC inverter, with an innovative digital-twin health monitoring techniques.

[0058] FIG. IB is a graphical representation of a five-level active neutral point clamped (5L- ANPC) power converter according to one or more embodiments. Power converter 120 may include input 121 having input terminals 122 and be configured to receive source voltage 123 (Vdc). Power converter 120 may be configured as an inverter to connect a load to a neural point. Power converter 120 includes DC link capacitor 124 (Cdci) and DC link capacitor 125 (Cdc ) coupled to neutral point 127, and input terminals 122 are coupled to three-phase configuration including circuits 126i.neach including a circuit configuration 130 and corresponding phase outputs 1311-n. Converter 120 includes circuit configurations 150 for a 5L-NPC power converterincluding three cells, cell-1 (IGBT) 135, cell-2 (GaN) 136, and Cell-3 (GaN) 137. Cell-1 (IGBT) 135 includes IGBT switch 138 (SI) and switch 139 (S2) in a top half, and switch 140 (S3) and switch 141 (S4) in a bottom half. Cell-2 (GaN) 136 includes GaN switch 143 (S5) in a top half, and switch 144 (S6) in a bottom half. Between Cell-2 (GaN) 136 and Cell-3 (GaN) 137, power converter 120 includes a flying capacitor (CFC) 145. Cell-3 (GaN) 137 includes GaN switch 146 (S7) in a top half, and switch 147 (S8) in a bottom half. Three phase outputs 131 i.nare provided for each phase (phase a, b, c).

[0059] The schematic of a three-phase five-level active neutral point clamped (5L-ANPC) inverter is depicted in FIG. IB. The converter includes of three Cells, which are designed to operate at different switching frequencies in a typical phase-shifted-PWM (PS-PWM) modulation strategy. Specifically, the first cell, Cell-1, operates at a low switching frequency and the switches are rated at Vdc / 2, while Cell-2 and Cell-3 operate at a high switching frequency and the switches are rated at Vdc / 4.

[0060] Unlike fault diagnosis methods for 5L-ANPC converters that predominantly rely on analysis of inverter output voltage data, necessitating the inclusion of extra voltage sensors and high frequency bandwidth capture, embodiments may allow for operation without the use of extra voltage sensors or output filters. Embodiments may also allow for operation where the converter is directly connected to a motor. The disclosure presents an innovative digital-twin strategy for health monitoring of 5L-ANPC power converters that targets safety-critical applications such as electric aircraft propulsion or grid applications. Embodiments provide a digital-twin of a 5L-ANPC converter to continuously monitoring crucial parameters to evaluate converter performance and detect open-circuit (OC) faults in switches. Embodiments enhance systematic reliability and reduce downtime cost. Experimental results are described herein to validate the robustness and effectiveness of embodiments under various modulation indices and loading conditions. Experimental data also highlights the feasibility and reliability of the embodiments.

[0061] FIG. 1C is a graphical representation of a digital-twin control device according to one or more embodiments. Device 150 may relate to a control device or components of a device configured to provide a digital-twin model for fault analysis of the multilevel neutral point clamped converter. By way of further example, device 150 may be a digital -twin control devicefor open-circuit fault diagnosis for a multilevel neutral point clamped converter. According to one embodiment, device 150 includes controller 151, memory 152, communications module 153 and interface 154. According to embodiments, device configuration 150 may be used by a control device (e.g., digital-twin control device) and / or another control device for monitoring a power device, such as a power converter.

[0062] Controller 151 may relate to a processor or control device configured to execute one or more operations stored in memory 152, such as providing bidirectional communication and control for detection and analysis of faults and digital-twin functions. Communications module 153 may include a communication interface and may be configured to communicate with one or more other devices, such as a server device, network device, loT ( (e g., Internet of Things device). Controller 151 may be coupled to memory 152 storing executable instructions and communications module 153 providing a communication interface for the power converter.

[0063] According to one embodiment, controller 151 may be configured to receive phase load current for each phase of a multilevel neutral point clamped converter and determine at least one fault flag parameter for each phase of the multilevel neutral point clamped converter. The fault flag parameter may be determined using real-time phase load current of each phase. Controller 151 may also receive phase load current for each phase of a multilevel neutral point clamped converter and determine at least one fault flag parameter for each phase of the multilevel neutral point clamped converter. The at least one fault flag parameter is determined using real-time phase load current of each phase. The digital-twin model, may receive DC -link capacitor voltage of the multilevel neutral point clamped converter as input for fault analysis. Controller 151 may also detect a disturbance flag using the fault flag parameters, and identify a faulty phase leg of multilevel neutral point clamped converter and at least one component of the multilevel neutral point clamped converter. Controller 151 may also control a digital -twin model for fault analysis of the multilevel neutral point clamped converter. The digital-twin model may be configured to determine a fault onset time for the faulty phase leg and identify a fault cell of the multilevel neutral point clamped converter. Controller 151 may also output a fault flag determination of the digital-twin model. Controller 151 may perform one or more processes described herein, such as process 200 of FIG. 2.

[0064] FIG. ID is a graphical representation of a digital-twin model for a converter according to one or more embodiments. According to embodiments, a digital-twin configuration 155 is provided as a real-time digital-twin replica of a 5L-ANPC converter. Digital-twin configuration 155 continuously monitors crucial parameters to assess the inverter performance and detect open-circuit faults in the switches as soon as they occur. Digital-twin configuration 155 is configured to monitor converter 156 which may be a 5L-ANPC converter. According to embodiments, digital-twin configuration 155 may be configured to monitor other converter configurations as well. Digital-twin configuration 155 includes digital-twin 157 which may be a replica of converter 156, and communication bus 158 configured to receive may be configured for bidirectional communication of parameters 159 of converter 156 including phase voltage and three-phase current. According to embodiments, digital-twin model 157 may generate and / or model output based on the received parameters, such as pulse width modulated output 160. Based on received information and modeled data, fault analysis and location of the fault may be identified. Digital-twin 157 may be configured to only require the data analytics of the existing DC-link and flying capacitor voltage sensing information as well as the load currents for 5L- ANPC inverter systems. As a result, no additional sensors or hardware components are needed. Experimental tests described herein verify the robustness of the digital-twin configurations and processes at different operating points. Digital -twin 157 may be configured to use existing DC- link capacitor and flying capacitor voltages, alongside load current data and switching patterns. Digital-twin 157 may model the power converter with details on how the output voltage / current are expected (e.g., signal level expectation) in a specific switching pattern inside the controller and this information is provided as an input to the digital-twin model. The output of the 5L- ANPC at different switching conditions can be determined from Kirchhoff voltage and current laws (KVL and KCL). The output of the power converter at different operating points is estimated with the digital-twin model.

[0065] FIG. 2 illustrates a process for open-circuit fault diagnosis for a multilevel neutral point clamped converter according to one or more embodiments. Process 200 may be performed by a system (e.g., system 150) to provide open-circuit fault diagnosis for a multilevel neutral point clamped converter. According to embodiments, a digital-twin control device (e g., controller 151) may be configured to perform one or more operations of process 200 for monitoring converter operation and performance. The digital-twin control device may be a fault detectiondevice. According to embodiments, process 200 may be performed with control device having a model of a converter and output data from the converter. Process 200 may be performed using a digital-twin model for fault analysis of a five-level active neutral point converter, wherein the digital-twin model receives DC-link capacitor voltage of the multilevel neutral point clamped converter as input for fault analysis. Process 200 may be initiated at block 205 with receiving data for a neutral point clamped converter. Received data may be real-time data of an actual power converter, such as phase load current for each phase of a multilevel neutral point clamped converter. At block 205, process 200 may receive additional data and parameters for a power converter, including but not limited to DC-link and flying capacitor voltages in addition to load currents.

[0066] At block 210, process 200 includes detecting fault flag parameters for each phase of a converter. The fault flag parameters may be determined using real-time currents of each phase of the converter. A digital-twin model may receive phase load current for each phase of a multilevel neutral point clamped converter. The at least one fault flag parameter for each phase of the converter may be determined using a difference between real-time current measurements and delayed currents in each phase of the multilevel neutral point clamped converter. The digital-twin model for fault analysis may utilize an R-L load for the model. The digital-twin model may be configured to continuously monitor load current of each phase of the converted and to identify a faulty circuit switch within a fundamental period of converter output frequency. According to embodiments, detecting fault flag parameters may be based on a DIST signal. The Dist signal may be monitored and recorded continuously by the digital-twin model. This signal is generally zero at normal condition, but the Dist signal increases during system disturbances. To avoid false detection, the digital-twin model uses specific values (0.5 p.u for example) as a threshold. However, once the Dist signal has passed the threshold, the digital-twin model can track back the recorded data and mark the last time when the Dist function was zero as the fault time.

[0067] At block 215, process 200 includes detecting a disturbance flag using the fault flag parameters. Detecting a disturbance flag may include monitoring fault flag parameters for each phase and comparing the fault flag parameters to a predetermined disturbance threshold.

[0068] At block 220, process 200 includes identifying a faulty phase leg of multilevel neutral point clamped converter and at least one converter component of the multilevel neutral point clamped converter. Identifying a faulty phase leg may include the digital-twin model comparing the fault flag parameters to identify a phase of the multilevel neutral point clamped converter and a circuit half of the multilevel neutral point clamped converter including circuit components.

[0069] At block 225, process 200 includes controlling a digital-twin model for fault analysis of the multilevel neutral point clamped converter. The digital-twin model may be configured to determine a fault onset time for the faulty phase leg and identify a fault cell of the multilevel neutral point clamped converter. Controlling the digital-twin model for fault analysis includes analyzing faults in a detected set of possible faulty switches and quantifying a difference between measured current and current determined by the digital -twin model. Controlling the digital-twin model for fault analysis includes comparing voltage of a flying capacitor of the multilevel neutral point clamped converter with an adaptive threshold to identify a faulty switch of the multilevel neutral point clamped converter. Control of the digital-twin model may also include running the digital-twin model to consider faults on possible switches. To detect the location of a fault, a comparison may be made of fault analysis detections, including a root mean square error of the measure and digital-twin determined values for phase currents to identify the location of a fault such as a fault in cell-1, or a fault located in cell-2 or cell-3. When a fault is determined in cell-2 or cell-3, process 200 may compare the flying capacitor voltage with an adaptive threshold. FIG. 4 illustrates a graphical representation of digital-twin operations that may be performed by process 200. The root mean square error (RMSE) comparison may be considered as part of the fault detection process. The digital-twin model may need to be redefined to mirror the power converter after the fault and would need the fault detection process to redefine its state and replicate the power converter. In this case, the RMSE comparison can be considered as part of the digital-twin as well.

[0070] At block 230, process 200 includes outputting a fault flag determination of the digitaltwin model. Output of the fault flag determination includes identification of a circuit switch of the converter and an open circuit fault condition of the switch. According to embodiments, the fault flag determination may include determining a fault location, such as first identifying if the open circuit fault is located in cell-1 . If the open circuit fault is not located in cell-1 , process 200 may determine if the fault is location in cell- 2 or cell-3.

[0071] At block 235, process 200 optionally includes outputting a di ital -twin determination for converter status. The digital-twin determination may include a control signal to the multilevel neutral point clamped converter for control based on the fault flag determination. A digital-twin model can also be used to estimate the on-state resistance and load parameters as well.According to embodiments, a digital-twin may perform fault detection to send faulty switch information to the converter. The digital-twin model could output an analog or digital pulse going high to represent the faulty switch information. After fault detection, generally the converter needs to be reconfigured based on the faulty switch location and the predefined condition. Once a digital-twin outputs the faulty switch information and the converter may perform reconfiguration, digital-twin can reset the fault and confirm the health status of the converter.

[0072] FIG. 3 is a graphical representation of a fault diagnosis and localization for a 5L-ANPC converter configuration according to one or more embodiments.

[0073] DIGITAL-TWIN BASED OPEN-CIRCUIT FAULT DIAGNOSTIC METHOD

[0074] Embodiments may utilize DC-link capacitor and flying capacitor voltages, load current data and switching patterns. This approach eliminates the necessity for additional load voltage sensors. Notably, detection processes according to the embodiments are executed within a fundamental period of an inverter output frequency, considering the fact that faulty switches may not switch during half of a fundamental cycle. To address the open circuit fault detection issue, embodiments may be configured to detect faults across different switches.

[0075] Process 300 may be performed by a digital-twin control device and / or one or more devices executing a digital-twin model. In neutral point-clamped (NPC) converters, the primary factor influencing the variation of the neutral point (NP) voltage is the current flowing through the NP. Four switching states can impact the NP current of each phase

[0018] , and the average NP current causes the NP voltage to deviate from the center potential of the DC-link. The average NP current within a carrier period can be calculated as follows: iNP = ia+ iNP^ + iNPc~

[0076] According to embodiments, the neutral-point current of each phase can be determined based on the reference voltage, load current, and the switching states that select the redundantswitching state for balancing the flying capacitors. Performance of the balancing controller has a significant impact on the NP voltage. Additionally, the contribution of the NP currents from healthy phases may slow down the variation of the neutral point voltage, causing neutral point voltage to remain relatively stable after a fault and during the short period required for fault detection.

[0077] However, the flying capacitors (e.g., CFC 145) which conduct the load current, are influenced solely by the current and switching states in the phase they are associated with. The flying capacitor can become unbalanced as soon as one of the high-frequency switches fails into an open state, as these switches are crucial for maintaining capacitor balance.

[0078] The output current of the real converter, represented as zioad, is continuously monitored at each sampling interval and compared with its value from the preceding cycle. If any deviation exceeds the predetermined threshold, it triggers the fault detection algorithm, thereby initiating the fault diagnosis process.

[0079] Real-time three-phase load currents during normal operation can be defined as follows: i" = Imcos (mt)where m(= 2nf is the angular frequency, f is the fundamental frequency, and lmis the current amplitude.

[0080] To compare the real-time currents with the currents in the previous cycle, the phase currents can be simply delayed by one cycle as follows:where isx Ea b crepresents the delayed three-phase currents, and T = 1 / / is the fundamental period. Three fault flags, denoted as " FLTX x a,b,careintroduced, which essentiallyrepresents the difference between the real-time currents and the delayed currents in each phase, as shown below:FLTX= ix- ix.

[0081] During normal operation, subtracting real-time currents from the delayed ones would naturally yield zero for all three phases. However, in the event of a fault condition, the faulty load current is not sinusoidal throughout the entire period. This leads to non-zero and non- sinusoidal values when subtracted from the delayed currents. This phenomenon will be examined under various conditions throughout this disclosure. For instance, in a single-switch fault scenario, the healthy phase currents will exhibit the same DC offset and deviate similarly in direction from their corresponding values in the previous cycle. Nevertheless, given that the sum of the three phase currents remains zero (ia+ ib+ ic= 0), the faulty phase current will deviate in the opposite direction compared to the healthy ones. In cases of load or speed changes, the deviation from delayed signals for all three phases will vary over a single cycle period, as the phase currents continue to follow sinusoidal patterns. Subtracting them from the delayed values will still result in sinusoidal waveforms.

[0082] Additionally, a parameter referred to as "Dist" is introduced as the disturbance flag, distinguishing normal operation from significant changes such as load fluctuations, speed variations, or potential faults (see the second graph 610 in FIG. 6). A value exceeding 0.5 p.u. for this parameter indicates a disturbance within the system.Dist = \FLTa\ + \FLTb\ + \FLTC\

[0083] Process 300 may be initiated by detecting a disturbance at decision block 305. When a disturbance flag is not detected (e.g., “No” path out of decision block 305), the digital-twin may continue to monitor. The disturbance flag may be based on monitored parameters including phase current. FIG. 4 illustrates Vbnphase voltage and three phase load currents and a fault (e.g., see fault 406). FIG. 5 illustrates DC-link voltages and measured and filtered flying capacitor voltages. FIG. 6 illustrates the fault detection signals, which are used to analyze the system response to faults following the procedure outlined in FIG. 3. These signals are normalized based on the peak current value. Once a fault occurs, the "FLT" signals increase, consequently causing the "Dist" signal to increase as well until it reaches 0.5 p.u., highlighted with a circle 611. This signifies that the system is experiencing a transient or fault condition.

[0084] When a disturbance flag is detected at decision block 305, (e.g., “Yes” path out of decision block 305), fault flags may be compared to determine a faulty phase at 310. Process 300 may determine fault flags for determination of a disturbance flag.

[0085] Fault flag comparison is performed at decision blocks 311 i-n, these operations may compare the fault flags for each phase. For example, decision block 3111 determines if the fault flag of phase b is each to the fault flag of phase c. Similarly, block 31 h determines if the fault flag of phase a is equal to the fault flag of phase c, and block 31 lndetermines if the fault flag of phase a is equal to the fault flag of phase b. FLT signals are compared with each other. If two of the three signals are equal, then there is definitely a fault that causes the healthy phase currents to gain an equal DC offset. The phase that has a different FLT signal from the others would be identified as the faulty phase. Subsequently, the polarity of the FLT signal for the faulty phase would be checked. At 315, process 300 checks if the fault flags are greater than zero. Decision block 316i determines if the fault flag of phase a is greater than zero, decision block 3162 determines if the fault flag of phase b is greater than zero, and decision block 316ndetermines if the fault flag of phase c is greater than zero.

[0086] At 320, process 300 will check if the fault is in a bottom half or top half of the circuit. Decision block 32 L determines if the fault flag of phase a is in a bottom half, and decision block 3212 determines if the fault flag of phase a is in a top half. Decision block 32h determines if the fault flag of phase b is in a bottom half, and decision block 32U determines if the fault flag of phase b is in a top half. Decision block 3215 determines if the fault flag of phase c is in a bottom half, and decision block 32 lndetermines if the fault flag of phase c is in a top half.

[0087] If the faulty FLT is positive, this indicates that the phase current has acquired a negative DC offset, and the fault is located in the top half of the faulty phase (i.e., Si, 3, S5, or S7). However, if the faulty FLT is negative, this implies that the phase current has acquired a positive DC offset, and the fault is located in the bottom half of the faulty phase (i.e., S2.4, Se, or Ss). r , ( FLTr> 0 Phase c fault, top half{FLTa- FLTb}\FLT < 0. Phase c fault, bottom half r , ( FLTr> 0: Phase b fault, top half FLTa= FLTc}-. ] trLj Tlc< 0: Phase b fault, bottom halfPhase a fault, top half[FLT^ FLT^ f^f Phase a fault, bottom half

[0088] After identifying the faulty phase and the half-circuit in the related phase leg, embodiments include finding out the exact faulty Cell or switch, a task that involves leveraging the digital-twin model. At block 325, process 300 runs a digital-twin model to consider the possible fault on possible switches. The digital-twin model may be configured to mirrors the behavior of the actual converter until just before the fault occurs. However, once a fault is detected, the model no longer accurately represents the real system behavior and requires updating. Determining the closest possible state for the digital-twin model involves testing all possible fault conditions and observing which case aligns most closely with real-time measurements. This process necessitates information on the fault onset time.

[0089] The fault onset time is determined by tracing back the "Dist" signal to identify the point where it deviates from zero, as indicated by the 612 circle in the "Dist" plot of FIG. 6. Circle 612 serves as the reference for creating and analyzing faults in the DT model. In this case, the candidate faulty switches are (i.e., S1.3, S5, or S7). Consequently, the DT model runs three times, considering a fault in one of these switches in each case. The results are shown in FIG. 7.

[0090] At block 330, process 300 calculates the RMSE of the measure and digital-twin currents. According to embodiments, the root mean square error (RMSE) is defined as follows and is used to quantify the difference between the measured current and the current obtained from the digital-twin model after running with three different candidate fault caseswhere ixand ixrepresent the ithsamples of the measured current, z, and the modeled current for each possible fault case, ip, respectively, and N is the total number of samples within a cycle.

[0091] Faults in Cell-1

[0092] In the example of detection of a fault in Cell-1, it can be seen that the RMSE for the fault at Si, 3 is lower than the RMSE for other cases and stays minimum for at least a quarter cycle.Therefore, based on the fault detection process and operations in FIG. 3, it can be concluded that S1.3 are the faulty switches.

[0093] At decision block 335, process 300 determines if a cell-1 fault is present. When a cell-1 fault is determined at decision block 335 (e.g., “Yes” path out of decision block 335), output 336is provided. When a cell-1 fault is not detected (e.g., “No” path out of decision block 335), process 300 compares the flying capacitor voltage with an adaptive threshold at block 340. Output 345 includes a determination of a cell-2 or cell-3 fault. In process 300 at block 340, if the algorithm detects a fault in Cell-1, the algorithm will terminate. This is because the current waveforms for faults in Cell-1 are significantly different from those of other faults. Except for a tiny portion of current conduction through the diodes, one half-period of current is clipped. Consequently, after comparing the measured and modeled currents, the RMSE for faults in Si, 3 or 82,4 is considerably lower, allowing for a decisive fault detection.

[0094] Faults in Cell-2

[0095] The scenario involving a fault on S5 is depicted in FIG. 8. In this case, the distorted load current in the faulty phase is less pronounced compared to that in Cell-1. However, it is evident that the faulty phase current has acquired a negative DC offset, while the currents in the healthy phases have gained a positive offset. This condition results in FLTa= FLTC, and causes the FLT flag of phase b to become positive. Consequently, the Dist indicator also increases and crosses the predefined threshold of 0.5 p.u. With this information, the candidate faulty switches can be narrowed down to S1.3, S5, or S7. Running the DT model considering a fault on any of these switches would yield the results shown in FIG. 9.

[0096] For faults in Cell-2 or cell-3, the output current waveforms can be quite similar, as shown in FIG. 9. While the RMSE parameter correctly identifies the faulty switch, ensuring the reliability of fault identification and avoiding misdiagnosis requires an additional parameter to differentiate between Cell-2 and Cell-3 faults. According to embodiments, the flying capacitor voltage is selected as it is directly influenced by the load current and switching states of the associated phase. In addition, with a PS-PWM method, the ripple voltage of a flying capacitors may be determined by the high switching frequency cells, leading to these capacitors being sized smaller compared to the DC-link capacitors. DC-link capacitors are sized relatively larger to accommodate the voltage ripple caused by the low frequency switching of the IGBTs in Cell-1. Therefore, flying capacitor voltage can be more sensitive during the faults.

[0097] The current flow through the flying capacitor stage and its effect on charging or discharging are depicted in FIG. 10, where "C" and "D" represent charging and discharging states, respectively. States that do not impact the capacitor current are denoted as "N".Considering that this work may include switching faults, it can be deduced that an open-circuit fault in switches S5 or Se disrupts the charging current for the capacitor, while the discharging path remains intact. Consequently, a fault in Cell-2 leads to a decrease in the flying capacitor voltage.

[0098] An adaptive threshold is introduced to establish a reliable reference for comparing flying capacitor voltages. In addition, normalizing the measured voltages by subtracting them from their previous cycle values, similar to the procedure for load currents, aids in eliminating periodic oscillations.

[0099] The adaptive threshold for S5 is determined by the absence of positive current passing through the flying capacitor of the faulty phase. Similarly, the adaptive threshold for Se is established based on the absence of negative current passing through the flying capacitor of the faulty phase as below.wherec, is the capacitance of the flying capacitor and S5x,S6x,S7x, and SSxdenote the switching states of the specified switches, each taking a value of either 0 or 1. Additionally, ixosand ixegare defined as follows:■ neg > ( 0 > 0“ (ixix< 0

[0100] As shown in FIG. 11, the normalized residual flying capacitor voltage is compared with vth Ssband vth S7bto differentiate between faults in Cell-2 and 3. It is noticeable that upon a fault occurrence, the load current changes, leading to modifications in both the threshold values and the capacitor voltage. The faulty switch is identified as the one whose threshold is crossed by the flying capacitor voltage. Therefore, an open circuit fault in S3bis detected successfully.

[0101] Faults in Cell-3

[0102] The fault pattern observed in Cell-3 closely resembles that in Cell-2, with the key difference being the deviation in flying capacitor voltage, as illustrated in FIGs. 12 -14.Following the execution of the DT model and RMSE calculation, the output accurately identifies S7 as the faulty switch. However, to ensure accurate diagnosis and prevent misdiagnosis, embodiments may require examining flying capacitor voltage deviation. Therefore, after identifying a disturbance in the system and confirming it as a fault, and after narrowing down the faulty phase and half-circuit of the converter, the DT model is utilized. According to embodiments, if the comparison of output currents and RMSE values indicates a fault in either Cell-2 or 3, the adaptive threshold becomes useful in precisely locating the faulty switch.

[0103] According to FIG. 10, a fault in Cell-3 would result in the absence of discharging current while the charging path remains available. Consequently, the capacitor voltage will increase, as shown in FIG. 14. Previously, the adaptive threshold values for switches S5 and Se were defined. Similarly, the thresholds for S7 and Sx can be defined as follows:

[0104] It is important to note that the negative sign in vth S6xand vth s-7xtakes into account the current flow direction and whether there is a lack of discharging or charging current. For positive current cases, i^°s, if the capacitor lacks discharging current, and negative current cases, ixeawhere the capacitor lacks charging current, using the negative sign in the threshold calculation ensures alignment with the capacitor voltage deviation. Open-circuit fault detection may be diagnosed within a cycle as shown in FIG. 15.

[0105] FIG. 4 illustrates phase voltage and three-phase current for an open-circuit fault according to one or more embodiments. The phase voltage in graph 400 and three-phase load currents in graph 405 are measured during the open-circuit fault of Si or S3 are depicted in FIG.4. It is important to note that in all fault cases applied to Cell-1, faults are applied to a pair of switches. Since the switch pairs Si, S3 and S2, S4 are connected to the same PWM pin of the microcontroller, it is more reasonable to enable an open-circuit fault to both of the switches in apair. Consequently, faults in Cell-1 are applied to a pair of IGBT switches. The load in this scenario is an R-L load with resistance R = 5.7 and inductance L = 3.3 mH. Further details regarding the test and setup conditions are discussed herein.

[0106] The fault initiates at t = 8.83 ms in phase b. However, due to the conduction of the anti-parallel diode of Si and S3 during the negative cycle of current, the phase voltage remains normal until t = 9.11 ms, where these IGBT switches are expected to conduct following the current zero-crossing. After this moment, the converter fails to produce +Vae / 2 and one of the +Vdc / 4 voltage levels, resulting in the positive half-cycle of phase b being clipped. This situation introduces a negative DC offset for phase b current. Since the load is a balanced three-phase load, the current in the other two phases acquires a positive DC offset. This imbalance can lead to several consequences. If the converter does not shut down, the unbalanced currents generate negative-sequence three-phase currents at the motor terminals, leading to a reverse rotating magnetic field and torque, potentially causing motor overheating.

[0107] FIG. 5 illustrates DC-link voltages and measured and filtered flying capacitor voltages according to one or more embodiments. DC-link voltages are shown in graph 500. Measured and filtered flying capacitor voltages are shown in graph 505. An open-circuit fault in switch Si, 3 is shown as 506. A fault in Cell-1 switch pairs does not immediately impact the DC- link or flying capacitors, as the controller can effectively limit their variations due to the available redundant switching states. However, certain faults can lead to unbalanced flying capacitors, causing their voltage to rise up to Vdc / 2. This elevated voltage level poses a risk of damaging the low-voltage switches in the 5L-ANPC configuration.

[0108] FIG. 6 illustrates three phase load currents, a disturbance flag, and fault flags for each phase and a PWM pulse for a faulty switch according to one or more embodiments. FIG. 6 illustrates an open-circuit fault in switch Si, 3. Three-phase load currents are shown in graph 605, a "Dist" flag indicating disturbance is shown in graph 610, fault flags for each phase are shown in graph 615, and a PWM pulse for the faulty switch is shown in graph 620.

[0109] FIG. 7 illustrates phase currents and phase current comparisons according to one or more embodiments. FIG. 7 illustrates an open-circuit fault in switch Si,3. A comparison between the measured real-time Phase-b current and the digital-twin output current for differentpossible scenarios is shown in graph 700, and RMSE of current differences is shown in graph 705.

[0110] FIG. 8 illustrates three phase load currents, a disturbance flag, and fault flags for each phase and a PWM pulse for a faulty switch according to one or more embodiments. FIG. 8 illustrates an open-circuit fault in switch S5. Three-phase load currents are shown in graph 800, a "Dist" flag 806 indicating a disturbance is shown in graph 805, fault flags for each phase are shown in graph 810, and a PWM pulse for the faulty switch is shown in graph 815.

[0111] FIG. 9 illustrates a comparison of measure phase current and digital-twin output according to one or more embodiments. FIG. 9 illustrates an open-circuit fault in switch S5. A comparison between the measured real-time Phase-b current and the digital-twin output current for different possible scenarios is shown in graph 900, and an RMSE of current differences is shown in in graph 905.

[0112] FIG. 10 illustrates a graphical representation of a current flow through a flying capacitor according to one or more embodiments. Current flowing through flying capacitor 1005 (e.g., flying capacitor 145 CFC) is shown for a converter and its impact on the charging or discharging of the capacitor.

[0113] FIG. 11 illustrates a comparison of flying capacitor voltage and adaptive thresholds according to one or more embodiments. FIG. 11 illustrates an open-circuit fault in switch S5. Graph 1100 compares the normalized residual flying capacitor voltage with the adaptive thresholds of S5 and S7.

[0114] FIG. 12 illustrates three phase load currents, a disturbance flag, and fault flags for each phase and a PWM pulse for a faulty switch according to one or more embodiments. FIG.11 illustrates an open-circuit fault in switch S7. Graph 1200 shows three-phase load currents, graph 1205 includes "Dist" flag 1206 indicating disturbance, graph 1210 shows fault flags for each phase, and graph 1215 shows PWM pulse for the faulty switch.

[0115] FIG. 13 illustrates a comparison of phase current and digital-twin output according to one or more embodiments. FIG. 13 illustrates an open-circuit fault in switch S7. Graph 1300 shows a comparison between the measured real-time Phase-b current and the digital-twin output current for different possible scenarios, and graph 1305 shows RMSE of current differences.

[0116] FIG. 14 illustrates capacitor voltages following a fault according to one or more embodiments. FIG. 14 illustrates capacitor voltages following an open-circuit fault in switch S7. Graph 1400 shows DC-link capacitor voltages, and graph 1405 shows flying capacitor voltages.

[0117] FIG. 15 illustrates comparing capacitor voltage with adaptive thresholds according to one or more embodiments. FIG. 15 illustrates an open-circuit fault in switch S7. Graph 1500 shows a graph of comparing the normalized flying capacitor voltage with the adaptive thresholds of S5 and S7.

[0118] Embodiments provide open-circuit fault detection methods and configurations to accurately diagnose the faults in five-level ANPC converters within less than a cycle, considering the inactive half-cycle of switches. Results of experimentation are provided below for system performance under various operating conditions, a configuration test setup, and process robustness against load and frequency changes.

[0119] Experimental Results

[0120] FIG. 16 illustrates a graphical representation of a 5L-ANPC inverter test rig according to one or more embodiments. Robustness of the open-circuit fault detection processes and configurations are examined under different operating conditions. Attention is directed to open circuit fault cases in the bottom half-circuit with various modulation indices. 5L-ANPC inverter test setup 1600 is shown in FIG. 16. Test setup 1600 includes micro-control unit (MCU) 1601, laminated bus bar 1605, flaying capacitors (flying Caps.) 1610, DC capacitors (DC Caps.) 1615, immersion cooling setup 1620, 5L-ANPC converter 1625. A bottom view 1635 of 5L- ANPC converter 1625 is shown including IGBT switches 1640 and GaN switches 1645.

[0121] In experiments, switching frequency is set to 22.5 kHz, with a fundamental output frequency of 700 Hz, and a modulation index of 0.4. An R-L load with resistance R = 5.7 Q and inductance L = 3.3 mH is used. The peak current for this modulation index is 1.91 A, which is used as a baseline for per unit conversion in this set of tests. For fault diagnosis, a hybrid "Si+GaN" 5L-ANPC converter rated at 1 .5 kV, although it is operated at a DC-bus voltage of 150 V for fault studies. Such a low voltage setting during failure testing is due to the nature ofGaN transistor failures; GaN transistors fail in short most of the time, and an open-circuit often leads to destructive consequences, including potential explosions and melting of internal components like bond wires.

[0122] The open-circuit test on the gate terminal is also a destructive procedure. When the GaN transistor is in conduction mode and the gate terminal is made open, the voltage across the gate terminal is pulled high by the drain-source voltage. This results in unexpected switching of the GaN transistor, leading to failures. Open-circuit tests are typically conducted in low-power applications to ensure that any failure does not result in safety issues.

[0123] If a GaN transistor fails in open-circuit, there would be no channel available to carry current in the reverse direction, resulting in a complete open-circuit. However, during OC tests where PWM signals are set to zero, faulty GaN devices can conduct in reverse conduction mode with Vy8 = 0. This behavior can resemble the reverse current conduction through the antiparallel diodes of SiC MOSFETs or IGBT switches.

[0124] FIG. 17 illustrates three phase load currents, a disturbance flag, and fault flags for each phase and a PWM pulse for a faulty switch according to one or more embodiments. FIG.15 illustrates an open-circuit fault in switch 82,4. Graph 1700 shows a graph of three-phase load currents, graph 1705 shows "Dist" flag 1706 indicating a disturbance, graph 1710 shows fault flags for each phase, and graph 1715 shows the PWM pulse for the faulty switch.

[0125] In this section, various cases are explored to demonstrate the robustness of the proposed method against different operating scenarios in motor-drive applications. Through detailed analysis and comparison of fault detection signals, the effectiveness of the fault detection algorithm under low modulation index conditions, load changes, and speed variations are evaluated to verify the method's reliability in diverse scenarios.

[0126] Operation at low modulation

[0127] Starting with an 82,4 fault at a modulation index of M=0.4, FIG. 17 depicts the fault occurrence in Phase b at t = 9.24 ms, when the current waveform is in the negative cycle. Consequently, the Phase-Z> current gains a positive DC offset, leading to positive and equal FLT flags for Phases a and c, and a negative FLT flag for Phase b. The "Dist" indicator quickly identifies the system's transient state within 60 ps. Analysis of the FLTXsignals indicates thatthe fault has occurred in Phase b and one of the bottom-half switches (i.e., S2.4, Se, or Ss). Running the DT model and comparing the output currents to calculate the RMSE signals reveals that the RMSE for S2 is lower than that of the others and remains consistently low for at least a quarter cycle as shown in FIG. 18. Consequently, the algorithm is able to effectively detect the faulty switch even at a low modulation index.

[0128] FIG. 18 illustrates a comparison of measured current, digital-twin current and current differences according to one or more embodiments. FIG. 18 illustrates an open-circuit fault in switch 82,4. FIG. 15 illustrates an open-circuit fault in switch S7. Graph 1800 shows a comparison between the measured real-time Phase-b current and the digital-twin output current for different possible scenarios and graph 1805 shows RMSE of current differences.

[0129] FIG. 19 illustrates open-circuit fault conditions according to one or more embodiments. FIG. 19 illustrates an open-circuit fault in switch Se. Graph 1900 shows three- phase load currents, graph 1905 shows a "Dist" flag 1906 indicating disturbance, graph 1910 shows fault flags for each phase, and graph 1915 shows PWM pulse for the faulty switch. As another example under low modulation index conditions, a fault in switch Se is illustrated in FIG. 19. The key takeaway here is that the fault detection circuit can effectively identify the faulty phase and half-circuit even when the load currents exhibit less imbalance. Furthermore, as depicted in FIG. 20, the RMSE values for faults on Se and Ss are very close throughout an entire half-cycle after the fault occurrence. However, the algorithm can confidently determine that the fault lies in either Cell-2 or 3 up to this point. To precisely pinpoint the faulty switch, verification of the adaptive threshold is necessary.

[0130] FIG. 20 illustrates open-circuit fault conditions according to one or more embodiments. FIG. 20 illustrates an open-circuit fault in switch Se. Graph 2000 shows a comparison between the measured real-time Phase-A current and the digital-twin output current for different possible scenarios, and graph 2005 shows RMSE of current differences.

[0131] FIG. 21 illustrates open-circuit fault conditions according to one or more embodiments. For open-circuit fault of Se, graph 2100 compares the normalized flying capacitor voltage with the adaptive thresholds of Se and Ss. As evident from FIG. 21, the normalized residual voltage of the flying capacitor in phase b (Vr.FCb) surpasses the threshold for Se (i.e., Vth,se) within 0.165Z, indicating an Se open-circuit fault.

[0132] Load Change

[0133] Load change transients are common in motor-drive applications, and a fault detection circuit should be robust against these changes. In the experimental results, load step-up and step-down scenarios were tested to verify the robustness of the proposed fault detection method against these transients.

[0134] FIG. 22 illustrates load current step-up conditions according to one or more embodiments. FIG. 22 shows load current step-up at / = 5.11 ms. Graph 2200 shows three- phase load currents, graph 2205 shows a "Dist" flag indicating disturbance, and graph 2210 shows fault flags for each phase.

[0135] At a modulation index of 0.85, a 25 resistor was added in parallel with the load at t = 5.11 ms. The load currents and fault detection indicators are illustrated in FIG. 22. This resulted in an increase in the currents as the total load impedance decreases. The "Dist" parameter immediately responds to the load change transient and increases. However, none of the FLTXsignals match each other. This distinction clearly differentiates the current step-up from a switch fault, preventing the fault detection algorithm from triggering.

[0136] FIG. 23 illustrates load current step-down conditions according to one or more embodiments. FIG. 23 shows load current step-down at t = 4.76 ms. Graph 2300 shows three- phase load currents, graph 2305 shows "Dist" flag indicating disturbance, and graph 2310 shows fault flags for each phase. A current step-down was applied at a modulation index of 0.85 when the parallel 25 resistor was removed at t = 4.76 ms. The related load currents and fault detection indicators can be seen in FIG. 23. The current amplitude drops as the total load impedance increases. Once again, the "Dist" parameter promptly responded to the transient load change by increasing. However, none of the FLTXsignals match each other, clearly distinguishing the current reduction from a switch fault.

[0137] FIG. 24 illustrates frequency ramp-up conditions according to one or more embodiments. FIG. 24 shows frequency ramp-up between t = 30 ms and t = 35 ms. Graph 2400 shows simulated three-phase load currents, graph 2405 shows frequency command, and graph 2410 shows fault flags for each phase. To emulate a change in speed that affects the load current frequency, a frequency ramp-up test was conducted. As depicted in FIG. 24, the system received a frequency ramp-up command from t = 0.03 s to t = 0.035 s, increasing the frequency linearlyfrom 700 Hz to 1 kHz. While the FLTXsignals respond to this transient, none of them match, indicating that the fault diagnosis algorithm would not interpret this transient as a fault condition. Based on these analyses above, the proposed method demonstrates robustness against load fluctuations, speed changes, and variations in operating points of the 5L-ANPC inverter.

[0138] Different operating frequency

[0139] To further validate the processes and configurations described herein, the fundamental output frequency of the 5L-ANPC converter was changed to 400 Hz, aligning with the standard operating frequency in the present commercial aviation power conversion systems. While maintaining a modulation index of 0.85, a fault was induced at a different time in the cycle compared to the previous cases.

[0140] FIG. 25 illustrates open-circuit fault conditions according to one or more embodiments. FIG. 25 illustrates an open circuit fault of Sg at 400 Hz frequency. Graph 2500 shows Phase b voltage, graph 2505 shows three-phase load currents, graph 2510 shows "Dist" flag indicating disturbance, graph 2515 shows fault flags for each phase, and graph 2520 faulty switch PWM signal. FIG. 25 displays the phase b voltage in Volts, three-phase load currents in Amps, and fault identification signals. The open-circuit (OC) fault occurs at t = 8.69 ms on Se, triggering the "Dist" parameter response. However, since Phase b current is near the end of the negative cycle, the "Dist" parameter does not flag it as a disturbance initially, as the current continues through the body diode normally during the positive cycle (or through the third- quadrant conduction mode of the GaN transistor in the test case). When lb, turns negative at the zero crossing, the waveform distorts, giving the "Dist" signal enough time to detect the fault. Subsequently, the FLTXsignals correctly identify the faulty phase and half-circuit. By tracing back the "Dist" function, the fault onset point is determined, and the digital-twin model runs possible fault cases starting at t = 10.2 ms.

[0141] FIG. 26 illustrates open-circuit fault conditions according to one or more embodiments. FIG. 26 illustrates an open-circuit fault of Sr> at 400 Hz fundamental output frequency. Graph 2600 shows a comparison between the measured real-time Phase-6 current and the digital-twin output current for different possible scenarios, graph 2605 shows RMSE of current differences, and graph 2610 shows an adaptive threshold used to localized the exact faulty switch. FIG. 26 shows the digital-twin model output, accurately detecting the OC fault at t = 10.74 ms usingadaptive threshold comparison. It is noteworthy that the diagnosis method in this example requires one half-cycle to detect the fault, due to the fault occurring just before the active cycle of the switch ends. Considering the half-cycle duration when the faulty switch is inactive and open, the proposed method detects the fault in less than a fundamental cycle of the inverter output frequency. Additionally, at lower fundamental frequencies, capacitor voltage fluctuation is more significant, aiding the proposed fault detection method in identifying variations more straightforward.

[0142] 5L-ANPC power converters have been extensively utilized in numerous high- power industry applications, but are prone to reliability issues due to a large number of semiconductor switches utilized. To address this problem, an innovative digital-twin strategy for health monitoring of 5L-ANPC power converters has been proposed and verified. Embodiments introduce the first-ever real-time digital-twin replica of a 5L-ANPC converter. This digital replica continuously monitors crucial parameters to assess the inverter's performance and detect open-circuit faults in the switches as soon as it occurs. According to embodiments, processes and configurations discussed herein only require the data analytics of the existing DC-link and flying capacitor voltage sensing information as well as the load currents which are generally available in 5L-ANPC inverter systems, so no additional sensors or hardware components are needed. These approaches significantly enhance 5L-ANPC converter systematic reliability and reduces maintenance downtime cost.

[0143] Experimental validations across various modulation indices and loading conditions demonstrate the practical applicability and robustness of the proposed method. This research lays a foundation to integrate multilevel power converters into large-scale digital loT power conversion systems for high-power safety-critical applications (e.g., electric aircraft or ships) in the future.

[0144] While this disclosure has been particularly shown and described with references to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the claimed embodiments.

Claims

CLAIMSWhat is claimed is:

1. A method for open-circuit fault diagnosis for a multilevel neutral point clamped converter, the method comprising: receiving, by a digital-twin control device, phase load current for each phase of a multilevel neutral point clamped converter; determining, by the digital-twin control device, at least one fault flag parameter for each phase of the multilevel neutral point clamped converter, wherein the at least one fault flag parameter is determined using real-time phase load current of each phase; detecting, by the digital-twin control device, a disturbance flag using the fault flag parameters; identifying, by the digital-twin control device, a faulty phase leg of multilevel neutral point clamped converter and at least one component of the multilevel neutral point clamped converter; controlling, by the digital-twin control device, a digital-twin model for fault analysis of the multilevel neutral point clamped converter, the digital-twin model configured to determine a fault onset time for the faulty phase leg and identify a fault cell of the multilevel neutral point clamped converter; and outputting, by the digital-twin control device, a fault flag determination of the digitaltwin model.

2. The method of claim 1, wherein the digital -twin control device is configured to include the digital-twin model for fault analysis for a five-level active neutral point converter (5L-ANPC), and wherein the digital-twin model receives DC-link capacitor voltage of the multilevel neutral point clamped converter as input for fault analysis.

3. The method of claim 1, wherein the control device is a digital -twin fault detection device, and wherein the at least one fault flag parameter for each phase of the converter is determined using a difference between real-time current measurements and delayed currents in each phase of the multilevel neutral point clamped converter.

4. The method of claim 1, wherein detecting a disturbance flag includes monitoring fault flag parameters for each phase and comparing the fault flag parameters to a predetermined disturbance threshold.

5. The method of claim 1, wherein identifying a faulty phase leg includes comparing the fault flag parameters to identify a phase of the multilevel neutral point clamped converter and a circuit half of the multilevel neutral point clamped converter including circuit components.

6. The method of claim 1, wherein controlling the digital -twin model for fault analysis includes analyzing faults in a detected set of possible faulty switches and quantifying a difference between measured current and current determined by the digital-twin model.

7. The method of claim 1, wherein controlling the digital -twin model for fault analysis includes comparing voltage of a flying capacitor of the multilevel neutral point clamped converter with an adaptive threshold to identify a faulty switch of the multilevel neutral point clamped converter.

8. The method of claim 1, wherein output of the fault flag determination includes identification of a circuit switch of the converter and an open circuit fault condition of the switch.

9. The method of claim 1, wherein the digital -twin model for fault analysis includes an R-L load, and wherein the digital -twin model is configured to continuously monitor phase load current of each phase and to identify a faulty circuit switch within a fundamental period of converter output frequency.

10. The method of claim 1, further comprising outputting, by the digital -twin model, a control signal to the multilevel neutral point clamped converter for control based on the fault flag determination.

11. A digital-twin control device for open-circuit fault diagnosis for a multilevel neutral point clamped converter, the digital-twin control device comprising: a communication interface; a memory storing executable instructions; and a controller coupled to the communication interface and the memory, wherein the controller is configured to: receive phase load currents of a multilevel neutral point clamped converter; determine at least one fault flag parameter for each phase of the converter, wherein the fault flag parameters are determined using real-time phase load currents of each phase; detect a disturbance flag using the fault flag parameters;identify a faulty phase leg and at least one component of the converter; control a digital-twin model for fault analysis of the converter, the digital-twin model configured to determine a fault onset time for the faulty phase leg and identify a fault cell of the converter; and output a fault flag determination of the digital -twin model.

12. The digital-twin control device of claim 11, wherein the digital-twin control device is configured to include the digital-twin model for fault analysis for a five-level active neutral point converter (5L-ANPC), and wherein the digital-twin model receives DC-link capacitor voltage of the multilevel neutral point clamped converter as input for fault analysis.

13. The digital -twin control device of claim 11, wherein the control device is a digital-twin fault detection device, and wherein the at least one fault flag parameter for each phase of the converter is determined using a difference between real-time current measurements and delayed currents in each phase of the multilevel neutral point clamped converter.

14. The digital-twin control device of claim 11, wherein detecting a disturbance flag includes monitoring fault flag parameters for each phase and comparing the fault flag parameters to a predetermined disturbance threshold.

15. The digital -twin control device of claim 11, wherein identifying a faulty phase leg includes comparing the fault flag parameters to identify a phase of the multilevel neutral point clamped converter and a circuit half of the multilevel neutral point clamped converter including circuit components.

16. The digital -twin control device of claim 11, wherein controlling the digital -twin model for fault analysis includes analyzing faults in a detected set of possible faulty switches and quantifying a difference between measured current and current determined by the digital-twin model.

17. The digital -twin control device of claim 11, wherein controlling the digital -twin model for fault analysis includes comparing voltage of a flying capacitor of the multilevel neutral point clamped converter with an adaptive threshold to identify a faulty switch of the multilevel neutral point clamped converter.

18. The digital-twin control device of claim 11, wherein output of the fault flag determination includes identification of a circuit switch of the converter and an open circuit fault condition of the switch.

19. The digital-twin control device of claim 11, wherein the digital -twin model for fault analysis includes an R-L load, and wherein the digital-twin model is configured to continuously monitor phase load current of each phase and to identify a faulty circuit switch within a fundamental period of converter output frequency.

20. The digital-twin control device of claim 11, wherein the controller is configured to output a control signal to the multilevel neutral point clamped converter for control based on the fault flag determination.

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