Display panel

Abstract

A display panel (1), comprising a display region and a non-display region arranged on at least one side of the display region. The display panel (1) comprises a substrate (10), a first metal layer (21), an insulating layer (22), a passivation layer (23), a second metal layer (24), a planarization layer (25), and a third metal layer (26). The non-display region comprises a first via hole (27), the first via hole (27) passes through the planarization layer (25) to allow the second metal layer (24) to connected to the third metal layer (26) by means of the first via hole (27). By utilizing the structure of the display panel (1), when electrostatic discharge occurs beneath the first via hole (27) between the second metal layer (24) and the first metal layer (21), a two-layer structure consisting of the insulating layer (22) and the passivation layer (23) is at least present between the two metal layers, so as to avoid breakdown caused by electrostatic discharge, thereby effectively improving the yield of panels.

Description

Display panel

[0001] This application claims priority to Chinese Patent Application No. 202411087644.9, filed on August 8, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0003] In the pixel structure of a thin film transistor liquid crystal display (TFT-LCD), the signal of the Gate line can control the opening and closing of each row of the liquid crystal display, and the signal of the Data line can control the brightness and color of each column of the liquid crystal display, thereby realizing the control of the display picture. Since the Data line is relatively close to the pixel electrode, it will cause crosstalk and other adverse effects on the capacitive coupling of the pixel electrode. A black matrix (BM) is usually used to shield light or a shielding metal layer is used on the side of the Data line to shield the lateral electric field, but this will increase the pixel dark area and reduce the transmittance of the panel. Figure 1 shows a pixel structure that can improve the transmittance, a transparent shielding and storage electrode (TSS) structure, by adding a layer of transparent electrode (TSS ITO layer) as a storage capacitor and shielding electrode, to reduce the pixel dark area and improve the aperture ratio, thereby improving the transmittance of the panel. In the TSS structure shown in Figure 1, the TSS ITO layer needs to be connected to other electrode layers through a via hole, and when the thickness between the TSS ITO layer and the lower metal layer is too thin, it is easy to cause electrostatic breakdown, thereby reducing the yield of the panel. SUMMARY

[0004] Embodiments of the present application provide a display panel to at least solve the technical problem of low panel yield caused by electrostatic injury in the display panel.

[0005] In a first aspect, embodiments of the present application provide a display panel including a display area and a non-display area arranged at least one side of the display area, the display panel including: a substrate; a first metal layer arranged on the substrate, the first metal layer including a first metal trace arranged in the non-display area; an insulating layer arranged on a side of the first metal layer away from the substrate; a passivation layer arranged on a side of the insulating layer away from the substrate; a second metal layer arranged on a side of the passivation layer away from the substrate, the second metal layer including a second metal trace arranged in the non-display area; a planarization layer arranged on a side of the second metal layer away from the substrate; a third metal layer arranged on a side of the planarization layer away from the substrate, the third metal layer including a third metal trace arranged in the non-display area; wherein the non-display area further has a first via penetrating through the planarization layer, and the third metal trace is connected with the second metal trace through the first via.

[0006] In a second aspect, embodiments of the present application provide a display panel including a display area and a non-display area arranged at least one side of the display area, the display panel including: a substrate; a first metal layer arranged on the substrate, the first metal layer including a first metal trace arranged in the non-display area; an insulating layer arranged on a side of the first metal layer away from the substrate; a fourth metal layer arranged on a side of the insulating layer away from the substrate, the fourth metal layer including a fourth metal trace arranged in the non-display area; a passivation layer arranged on a side of the fourth metal layer away from the substrate; a raised layer arranged on a side of the passivation layer away from the substrate; a second metal layer arranged on a side of the raised layer away from the substrate, the second metal layer including a second metal trace arranged in the non-display area; a planarization layer arranged on a side of the second metal layer away from the substrate; a third metal layer arranged on a side of the planarization layer away from the substrate, the third metal layer including a third metal trace arranged in the non-display area; wherein the non-display area further has a first via penetrating through the planarization layer, and the third metal trace is connected with the second metal trace through the first via; and a projection of the raised layer on the substrate covers a projection of the second metal trace on the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1 is a schematic diagram of a TSS pixel structure provided in the related art;

[0008] FIG. 2 is a structural schematic diagram of a display panel provided in an optional embodiment of the present application;

[0009] FIG. 3 is a cross-sectional schematic diagram of a non-display area provided in an optional embodiment of the present application;

[0010] Fig. 4 is a schematic view of a cross section of a display region according to an embodiment of the present application;

[0011] Fig. 5 is a schematic view of a cross section of a non-display region according to another embodiment of the present application;

[0012] Fig. 6 is a schematic view of a cross section of a non-display region according to yet another embodiment of the present application;

[0013] Fig. 7 is a top view of a region where a first via and a second via are located according to an embodiment of the present application;

[0014] Fig. 8 is a schematic view of a structure of a display terminal according to an embodiment of the present application.

[0015] Explanation of Reference Numerals

[0016] 1, display panel; 2, display terminal; 3, terminal main body;

[0017] 10, substrate; 11, sub-pixel;

[0018] 20, pixel structure; 21, first metal layer; 211, first metal trace; 212, gate; 22, insulating layer; 23, passivation layer; 24, second metal layer; 241, second metal trace; 242, second common electrode layer; 25, planarization layer; 26, third metal layer; 261, third metal trace; 262, pixel electrode; 27, first via; 28, second via; 29, fourth metal layer; 291, source; 292, drain; 293, data line; 294, fourth metal trace; 30, elevation layer; 31, color resist layer; 32, third via; 33, active layer. Embodiments of the present application

[0019] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application, and should not be regarded as limiting the protection scope of the present application.

[0020] In addition, "a plurality of" in the embodiments of the present application refers to two or more. "First", "second", and the like in the embodiments of the present application are used to distinguish different technical features, and do not represent any order, quantity, or importance.

[0021] The direction terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like, are only the directions in the drawings. The direction terms used in the present application are used to explain and illustrate the present application, and are not used to limit the protection scope of the present application.

[0022] In the drawings, components of the same structure are denoted by the same reference numerals, and components similar in structure or function are denoted by similar reference numerals. In addition, for ease of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the size and thickness of each component are not limited in the present application.

[0023] The various embodiments provided in the present application are similar, and the features in different embodiments can be combined with each other.

[0024] The sequence of the following embodiment description is not limited as the preferred sequence of the embodiments.

[0025] In the periphery of the display area (non-display area) of the TTS pixel structure, a via hole is arranged to conduct the COM signal input from the Chip On FPC (Chip On FPC, referred to as COF) side from the first COM metal layer to the TSS ITO layer. Since the resistance of indium tin oxide (Indium Tin Oxide, referred to as ITO) is relatively large, in order to make the COM signal more uniform, more via holes are arranged. The connection mode of the via hole is generally that the TSS ITO layer is connected to the pixel electrode layer (first via hole), and the pixel electrode layer is connected to the first COM metal layer (second via hole), so as to realize conduction. However, static electricity accumulated in the process is easy to be discharged between the TSS ITO layer and the metal layer below the first via hole where the TSS ITO layer is connected to the pixel electrode layer, such as the first metal layer for forming the driving line or the second metal layer for forming the data line. If there is only a passivation layer or only an insulating layer between the TSS ITO layer and the metal layer, the thickness is relatively thin, which is easy to be broken down by static electricity discharge, causing explosion, thereby reducing the panel yield.

[0026] In order to solve the above problems, one embodiment of the present application provides a display panel. Referring to FIG. 2, the display panel 1 includes a display area AA and a non-display area NA. The display panel 1 can be a liquid crystal panel, and the display area AA is provided with a plurality of sub-pixels 11, and the display area AA is used for displaying a picture. The non-display area NA is arranged at least one side of the display area AA, for example, the non-display area NA can be arranged around the display area AA. The non-display area NA is provided with a driving circuit and the like, and the driving circuit is used for providing a driving signal for the sub-pixel 11 of the display area AA. For example, the driving circuit can include a gate driving circuit.

[0027] FIG. 3 is a schematic view of a non-display area of a display panel according to an embodiment of the present application, and FIG. 4 is a schematic view of a display area of a display panel according to an embodiment of the present application. As shown in FIGS. 3 and 4, the display panel 1 includes a substrate 10, which can be a rigid substrate or a flexible substrate. The rigid substrate can be made of glass or the like. The flexible substrate can be made of one of colorless polyimide (PI), polycarbonate (PC), poly (norbornene) (PNB), and polyethylene terephthalate (PET).

[0028] The first metal layer 21, the insulating layer 22, the passivation layer 23, the second metal layer 24, the planarization layer 25, and the third metal layer 26 are sequentially stacked in the vertical direction of the substrate 10. The first metal layer 21 is disposed on the substrate, and includes a first metal trace 211 disposed in the non-display area. The insulating layer 22 is disposed on the side of the first metal layer 21 away from the substrate 10. The passivation layer 23 is disposed on the side of the insulating layer 22 away from the substrate 10. The second metal layer 24 is disposed on the side of the passivation layer 23 away from the substrate 10, and includes a second metal trace 241 disposed in the non-display area. The planarization layer 25 is disposed on the side of the second metal layer 24 away from the substrate. The third metal layer 26 is disposed on the side of the planarization layer 25 away from the substrate 10, and includes a third metal trace 261 disposed in the non-display area.

[0029] The non-display area further includes a first via 27, which penetrates the planarization layer 25 and connects the third metal trace 261 and the second metal trace 241.

[0030] With the above structure of the display panel, when static electricity is released between the second metal trace 241 and the first metal trace 211 below the first via 27, there are at least two layers of the insulating layer and the passivation layer between the two metal layers, thereby avoiding breakdown caused by static electricity and effectively improving the yield of the panel.

[0031] The embodiments of the present application have at least the following beneficial effects:

[0032] The embodiment of the present application provides a display panel, which comprises a display area and a non-display area arranged on at least one side of the display area, and comprises a substrate and a first metal layer, an insulating layer, a passivation layer, a second metal layer, a planarization layer and a third metal layer which are sequentially stacked in the vertical direction of the substrate; wherein the second metal layer comprises a second metal trace arranged in the non-display area, and the third metal layer comprises a third metal trace arranged in the non-display area; the non-display area comprises a first via hole, and the first via hole penetrates through the planarization layer to connect the third metal trace arranged in the non-display area with the second metal trace. In the process of the display panel, static electricity is easily released between two metal layers, especially at the position of the via hole, through the structure of the display panel, when static electricity is released between the second metal layer and the first metal layer below the first via hole, there are at least two structures of the insulating layer and the passivation layer between the two metal layers, so that the breakdown caused by static electricity is avoided, and the panel yield is effectively improved.

[0033] Other beneficial effects of the embodiment of the present application will be further described in the following specific embodiments. In an optional embodiment, the non-display area further has a second via hole 28, the second via hole 28 penetrates through the planarization layer 25, the passivation layer 23 and the insulating layer 22, and the third metal trace 261 is connected with the first metal trace 211 through the second via hole 28. The third metal trace 261 is connected with the second metal trace 241 through the first via hole 27, and the third metal trace 261 is connected with the first metal trace 211 through the second via hole 28, so that the electrical connection between the second metal trace and the first metal trace can be realized.

[0034] Referring to FIG. 5, in an optional embodiment, the display panel further comprises a heightening layer 30, the heightening layer 30 is arranged on one side of the second metal trace 241 of the second metal layer 24 close to the passivation layer 23, and the orthographic projection of the heightening layer 30 on the substrate 10 covers the orthographic projection of the second metal trace 241 on the substrate 10.

[0035] By arranging the heightening layer 30, the film layer thickness between the first metal trace 211 and the second metal trace 241 can be further increased, and the risk of panel breakdown caused by static electricity release can be effectively avoided.

[0036] Referring to FIG. 4, in an optional embodiment, the display panel further comprises a color resistance layer 31, the color resistance layer 31 is arranged on the substrate 10, and the color resistance layer 31 is arranged in the display area. The heightening layer 30 is same layer and same material with the color resistance layer 31, that is, the heightening layer 30 and the color resistance layer 31 are located in the same layer and use the same material. The heightening layer 30 can be arranged in the same layer with the color resistance layer 31, and the heightening layer 30 is simultaneously manufactured with the color resistance layer 31 through one mask in the process of manufacturing the color resistance layer 31, so that the probability of panel breakdown caused by static electricity can be effectively reduced and the panel yield can be improved without increasing the process steps and production cost.

[0037] In the embodiments of the present application, the color resist layer 31 can include a plurality of red color resist, green color resist and blue color resist, and each color resist of the color resist layer is used to convert white light into color light of a corresponding color. In the display area, one color resist is arranged corresponding to one sub-pixel 11. For example, the sub-pixel 11 provided with the red color resist is a red sub-pixel, the sub-pixel 11 provided with the green color resist is a green sub-pixel, and the sub-pixel 11 provided with the blue color resist is a blue sub-pixel. The color resist layer 31 is usually composed of tiny red, green and blue (RGB) filters which are precisely placed on each sub-pixel of the liquid crystal panel. Each sub-pixel corresponds to a color, and by controlling the color and brightness of the light passing through the sub-pixel, a full-color image is finally combined. The structure of the color resist layer usually includes: a filter made of organic dye or inorganic pigment for filtering light of a specific wavelength; a black matrix arranged between the filters for absorbing excess light, preventing interference between colors and improving the contrast and clarity of the display; a protective layer covering the filters and the black matrix to prevent physical damage and environmental influences.

[0038] In an optional embodiment of the present application, the orthogonal projection of the insulating layer 22 on the substrate 10 covers the orthogonal projection of the second metal trace 241 on the substrate 10, and the orthogonal projection of the passivation layer 23 on the substrate 10 covers the orthogonal projection of the second metal trace 241 on the substrate 10.

[0039] In an optional embodiment of the present application, the orthogonal projection of the insulating layer 22 on the substrate 10 can cover the orthogonal projection of the first via 27 on the substrate 10, and the orthogonal projection of the passivation layer 23 on the substrate 10 can cover the orthogonal projection of the first via 27 on the substrate 10.

[0040] In the embodiments of the present application, the thickness of the insulating layer arranged in the non-display area can be consistent with the thickness of the insulating layer arranged in the display area, that is, formed by patterning in the same layer process, and the thickness of the passivation layer arranged in the non-display area can be consistent with the thickness of the passivation layer arranged in the display area, that is, formed by patterning in the same layer process.

[0041] It should be understood that in the present embodiment, the display panel 1 is a panel of COA (Color on Array) architecture. By arranging the display panel 1 as a panel of COA architecture, the color resist layer 31 can be arranged on the same substrate 10 as the pixel electrode 262, thereby avoiding the loss of aperture ratio due to the alignment deviation of two substrates when the color resist layer 31 and the pixel electrode 262 are arranged on different substrates, that is, adopting the COA architecture helps to increase the alignment accuracy of the color resist layer 31 and the pixel electrode 262 and improve the aperture ratio of the display panel 1.

[0042] The insulating layer 22 in the embodiments of the present application can be an insulating layer composed of inorganic substances, such as glass, quartz, ceramic, aluminum oxide, boron nitride, magnesium oxide, calcium silicate, borate glass, etc.

[0043] The planarization layer 25 in the embodiments of the present application is used to smooth the surface of the substrate to reduce surface roughness and unevenness, thereby providing better conditions for subsequent manufacturing processes. The materials of the planarization layer usually include oxides, nitrides, polysilicon, polymers, etc. The selection of these materials depends on the required electrical, mechanical and chemical properties. The manufacturing processes of the planarization layer include chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, spray coating, etc. These processes can ensure that the planarization layer is uniformly distributed on the substrate, forming a smooth surface. In the embodiments of the present application, the planarization layer 25 is used to ensure the uniformity and consistency of the display panel.

[0044] The passivation layer 23 in the embodiments of the present application can be formed by inorganic materials, such as silicon nitride.

[0045] Referring to FIG. 6, another embodiment of the present application further provides a display panel, which includes a display area and a non-display area arranged on at least one side of the display area. The film layer materials in the display panel can be shared with the materials in the above-mentioned embodiments, and the already described contents will not be repeated here.

[0046] The display panel includes a substrate 10 and a first metal layer 21, an insulating layer 22, a fourth metal layer 29, a passivation layer 23, a raised layer 30, a second metal layer 24, a planarization layer 25 and a third metal layer 26 which are sequentially stacked in the vertical direction of the substrate 10.

[0047] The first metal layer 21 is arranged on the substrate 10, and the first metal layer 21 includes a first metal trace 211 arranged in the non-display area; the insulating layer 22 is arranged on the side of the first metal layer 21 away from the substrate 10; the fourth metal layer 29 is arranged on the side of the insulating layer 22 away from the substrate 10, and includes a fourth metal trace 294 located in the non-display area; the passivation layer 23 is arranged on the side of the fourth metal layer 29 away from the substrate 10; the raised layer 30 is arranged on the side of the passivation layer 23 away from the substrate 10; the second metal layer 24 is arranged on the side of the raised layer 30 away from the substrate 10, and the second metal layer 24 includes a second metal trace 241 arranged in the non-display area; the planarization layer 25 is arranged on the side of the second metal layer 24 away from the substrate 10; and the third metal layer 261 is arranged on the side of the planarization layer 25 away from the substrate 10, and the third metal layer 261 includes a third metal trace 261 arranged in the non-display area.

[0048] The non-display area also has a first via hole 27 penetrating the planarization layer 25, and a third metal trace 261 is connected to the second metal trace 241 through the first via hole 27.

[0049] Referring to FIG. 4, FIG. 6 and FIG. 7, the fourth metal layer 29 is mainly used to form a source electrode 291 and a drain electrode 292 in the display area, a fourth metal trace 294 in the non-display area, and also can form a data line 293 in the display area and the non-display area. In the case that the non-display area contains the fourth metal trace 294, static electricity is easily released between the second metal trace 241 and the fourth metal trace 294 at the position of the first via hole 27, and if there is only the passivation layer 23 between the second metal trace 241 and the fourth metal trace 294, the passivation layer 23 is easily broken down by static electricity. The display panel structure provided in the embodiment of the present application sets the passivation layer 23 and the raised layer 3 between the second metal trace 241 and the fourth metal trace 294. In an optional implementation, the orthographic projection of the raised layer 30 on the substrate 10 covers the orthographic projection of the second metal trace 241 and the fourth metal trace 294 on the substrate 10, thereby effectively avoiding the problem of static electricity breakdown and improving the yield of the panel. The material and manufacturing process of the raised layer 30 are the same as those of the foregoing embodiments, and the content already stated will not be repeated here.

[0050] In an optional embodiment, the non-display area further includes a second via hole 28 penetrating at least the planarization layer 25, the passivation layer 23 and the insulating layer 22 to connect the first metal layer 21 to the third metal layer 26 through the second via hole 28. The first via hole 27 is used to connect the second metal layer 24 to the third metal layer 26 through the first via hole 27, and the second via hole 28 is used to connect the first metal layer 21 to the third metal layer 26 through the second via hole 28, so that the second metal layer 24 can be connected to the first metal layer 21.

[0051] Referring to FIG. 4, in an embodiment, the first metal layer 21 further includes a gate electrode 212 and a first common electrode (not shown) arranged in the display area. The first common electrode includes a plurality of electrodes connected together and is used to provide a common voltage signal, and the gate electrode is used to drive the corresponding thin film transistor of the sub-pixel to be turned on. The first common electrode is usually an integral surface, and the integral surface COM electrode is provided with the same voltage through one or more points. Its main function is to control the arrangement of liquid crystal molecules together with the pixel electrode, thereby affecting the light transmittance to realize the display of images. The COM electrode can be divided into regions in a row manner or a row-column manner. Each electrode region corresponds to a certain number of pixel units. By controlling the power supply unit and the selection unit, each electrode region is charged to the required voltage value, thereby effectively improving the adverse conditions caused by process limitations.

[0052] In an embodiment, the second metal layer 24 further comprises a second common electrode 242 disposed in the display area, and the second common electrode 242 is a transparent electrode. The second metal layer 24 can be a TSS ITO layer, which is mainly used to improve the transmittance of the liquid crystal display. The TSS transparent electrode can be used in a vertical alignment liquid crystal display (VA-LCD) to replace the traditional shielding and storage metal electrodes. The main purpose is to improve the transmittance and optical efficiency of the display, thereby achieving the effect of energy saving. In a traditional liquid crystal display, the shielding and storage electrodes are usually made of metal materials, which can absorb part of the light and reduce the transmittance of the display. The TSS transparent electrode reduces the absorption of light by using a transparent material, thereby improving the transmittance.

[0053] In an embodiment, the third metal layer 26 comprises a pixel electrode 262 disposed in the display area. One pixel electrode 262 corresponds to one sub-pixel 11. The fourth metal layer 29 comprises a source electrode 291 and a drain electrode 292 disposed in the display area. A source layer 33 is further disposed between the gate electrode 212 and the source-drain electrode. In this embodiment, the source layer 33 can be single crystal silicon, low-temperature polycrystalline silicon, oxide semiconductor, etc., but is not limited thereto. The gate electrode 212, the source electrode 291, the drain electrode 292 and the source layer 33 together constitute a thin film transistor. Each sub-pixel 11 is provided with a thin film transistor corresponding thereto, and the thin film transistor is disposed in the non-light-transmitting area of the sub-pixel 11. The thin film transistor comprises a drain electrode 292, which is electrically connected with the pixel electrode 262, and the thin film transistor can input a pixel voltage signal to the corresponding sub-pixel 11.

[0054] The second metal layer 24 and the third metal layer 26 can be transparent metals, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0055] In an optional embodiment, the color of the heightening layer 30 is consistent with the color of the color resistance layer 31 of the pixel area corresponding thereto, which can improve the surface uniformity of the panel.

[0056] Referring to FIG. 7, in an optional embodiment, the third metal layer 26 includes pixel electrodes 262 disposed in the display area, and the fourth metal layer 29 further includes data lines 293. The first metal trace 211 is connected to the third metal trace 261 through the second via 28, and the third metal trace 261 is connected to the second metal trace 241 through the first via 27. Specifically, the third metal layer 26 includes a plurality of pixel electrodes 262, and one pixel electrode corresponds to one sub-pixel 11. One thin film transistor is disposed corresponding to each sub-pixel 11, and the thin film transistor is disposed in the non-light-transmitting area of the sub-pixel 11. The third metal layer 26 can be a transparent metal, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), etc.

[0057] In the embodiment of the present application, the display panel 1 further includes a liquid crystal layer (not shown in the figure) disposed on the side of the third metal layer 26 away from the substrate 10. The display panel 1 further includes a common electrode layer (not shown in the figure) disposed on the side of the liquid crystal layer away from the substrate 10. The liquid crystal molecules in the liquid crystal layer are deflected in the electric field formed by the common electrode layer and the third metal layer 26, for controlling the light transmittance of the display panel 1, thereby realizing the display of brightness and darkness of the picture.

[0058] In the embodiment of the present application, the display panel 1 includes a counter substrate disposed on the side of the liquid crystal layer away from the substrate 10. The material of the counter substrate can be the same as or different from that of the substrate 10. The liquid crystal layer is disposed between the substrate 10 and the counter substrate. The common electrode layer can be disposed on the side of the counter substrate close to the liquid crystal layer.

[0059] In an optional embodiment, the color resistance layer 30 includes first openings (not shown in the figure) and second openings (not shown in the figure) disposed in the display area and spaced apart. The orthogonal projection of the sidewall of the first opening on the substrate covers part of the orthogonal projection of the drain on the substrate 10, and the orthogonal projection of the sidewall of the second opening on the substrate covers part of the orthogonal projection of the drain on the substrate 10, which can avoid the influence of the color resistance layer 30 on the electrical properties of the TFT.

[0060] Referring to FIG. 8, another embodiment of the present application further provides a display terminal 2, which includes the display panel 1 described in any of the above embodiments. In the embodiment, the display terminal 2 includes the display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one. The terminal body 3 can include a backlight module disposed on the side of the substrate 10 of the display panel 1 away from the color resistance layer 30. The backlight module is used to provide a light source for the display panel 1.

[0061] The display terminal can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0062] The principles and implementation manners of the present application are described herein by using specific examples, and the above example descriptions are only used to help understand the method and core idea of the present application; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as a limitation on the present application.

Claims

1. A display panel comprising a display area and a non-display area disposed on at least one side of the display area, the display panel comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a first metal trace disposed in the non-display area; an insulating layer disposed on a side of the first metal layer distal to the substrate; a passivation layer disposed on a side of the insulating layer distal to the substrate; a second metal layer disposed on a side of the passivation layer distal to the substrate, the second metal layer comprising a second metal trace disposed in the non-display area; a planarization layer disposed on a side of the second metal layer distal to the substrate; and a third metal layer disposed on a side of the planarization layer distal to the substrate, the third metal layer comprising a third metal trace disposed in the non-display area; wherein the non-display area further comprises a first via, the first via penetrating through the planarization layer, and the third metal trace is connected to the second metal trace through the first via. The display panel further comprises a height-increasing layer disposed on a side of the second metal layer proximal to the passivation layer, and a projection of the height-increasing layer on the substrate covers a projection of the second metal trace on the substrate. The non-display area further comprises a second via, the second via penetrating through the planarization layer, the passivation layer and the insulating layer, and the third metal trace is connected to the first metal trace through the second via. The display panel further comprises a color resist layer disposed on the substrate, and the color resist layer is disposed in the display area, the height-increasing layer and the color resist layer are of the same layer and the same material. The color resist layer comprises a plurality of red color resist, green color resist and blue color resist. The display area comprises a plurality of sub-pixels, and one color resist is disposed corresponding to one sub-pixel. The first metal layer further comprises a gate electrode and a first common electrode disposed in the display area. The second metal layer further comprises a second common electrode disposed in the display area, and the second common electrode is a transparent electrode. The third metal layer comprises a pixel electrode disposed in the display area.

2. The display panel of claim 1, wherein, The passivation layer is formed by inorganic material.

3. The display panel of claim 1 or 2, wherein, 11.A display panel comprising a display area and a non-display area disposed on at least one side of the display area, the display panel comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a first metal trace disposed in the non-display area; an insulating layer disposed on a side of the first metal layer distal to the substrate; a fourth metal layer disposed on a side of the insulating layer distal to the substrate, the fourth metal layer comprising a fourth metal trace disposed in the non-display area; a passivation layer disposed on a side of the fourth metal layer distal to the substrate; a height-increasing layer disposed on a side of the passivation layer distal to the substrate; a second metal layer disposed on a side of the height-increasing layer distal to the substrate, the second metal layer comprising a second metal trace disposed in the non-display area; and a planarization layer disposed on a side of the second metal layer distal to the substrate.

4. The display panel of claim 2, wherein, ​ 5. The display panel of claim 4, wherein, ​ 6. The display panel of claim 5, wherein, ​ 7. The display panel of claim 1, wherein, ​ 8. The display panel of claim 1, wherein, ​ 9. The display panel of claim 1, wherein, ​ 10. The display panel of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A third metal layer is disposed on a side of the planarization layer away from the substrate, and the third metal layer includes third metal traces disposed on the non-display region; The non-display region further has a first via hole, the first via hole penetrates the planarization layer, and the third metal traces are connected with the second metal traces through the first via hole; the orthographic projection of the heightening layer on the substrate covers the orthographic projection of the second metal traces on the substrate.

12. The display panel of claim 11, wherein, The non-display region further has a second via hole, the second via hole penetrates the planarization layer, the passivation layer and the insulating layer, and the third metal traces are connected with the first metal traces through the second via hole.

13. The display panel of claim 11, wherein, The display panel further includes a color resist layer, the color resist layer is disposed on the substrate, and the color resist layer is disposed on the display region, and the heightening layer and the color resist layer are of the same layer and the same material.

14. The display panel of claim 13, wherein, The color resist layer includes a plurality of red color resists, green color resists and blue color resists.

15. The display panel of claim 14, wherein, The display region includes a plurality of sub-pixels, and one color resist is correspondingly disposed with one sub-pixel.

16. The display panel of claim 11, wherein, The first metal layer further includes gate electrodes and first common electrodes disposed on the display region.

17. The display panel of claim 11, wherein, The second metal layer further includes second common electrodes disposed on the display region, and the second common electrodes are transparent electrodes.

18. The display panel of claim 11, wherein, The third metal layer includes pixel electrodes disposed on the display region.

19. The display panel of claim 11, wherein, The fourth metal layer includes data lines, source electrodes and drain electrodes disposed on the display region.

20. The display panel of claim 11, wherein, The passivation layer is formed by inorganic material.

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