Synchronous rectification turn-on control chip and control method

Abstract

Provided in the present invention are a synchronous rectification turn-on control chip and control method. A relative maximum voltage identification circuit, a synchronous measurement and comparison circuit and a logic circuit are integrated inside the control chip, wherein the relative maximum voltage identification circuit and the synchronous measurement and comparison circuit measure the drain-source voltage of a synchronous rectification switch transistor in real time, and send, when the drain-source voltage reaches the relative maximum value, an enable valid signal to the logic circuit; when the drain-source voltage is less than a turn-on threshold value, the synchronous measurement and comparison circuit outputs a first valid signal to the logic circuit, and the logic circuit controls the synchronous rectification switch transistor to turn on; and when the drain-source voltage is greater than a turn-off threshold value, the synchronous measurement and comparison circuit outputs a second valid signal to the logic circuit, and the logic circuit controls the synchronous rectification switch transistor to turn off. In the present invention, only the relative magnitude of a drain-source voltage is measured without the need for setting a measurement time, thereby eliminating the phenomenon of a synchronous rectification transistor failing to turn on due to time limitation. The present invention solves the problems encountered in the prior art, obtains wider application scenarios, and achieves a simpler chip peripheral.

Description

A synchronous rectification conduction control chip and a control method TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply converter, in particular to a synchronous rectification conduction control chip and a control method thereof. BACKGROUND

[0002] The output rectification circuit of flyback switching power supply generally adopts two ways of diode rectification and synchronous rectification. The diode rectification is shown in Fig. 1. When the PWM switch tube Q1 of the primary side of the switching power supply is turned on, the rectification diode D OUT is in the off state. After Q1 changes from on to off, the magnetic energy storage element T1 releases energy, the anode voltage of the rectification diode is greater than the cathode voltage, the rectification diode D OUT is turned on, and the IF current shown in Fig. 1 is generated. It utilizes the natural characteristics of the forward conduction and reverse blocking of the diode, and is simple, convenient and highly reliable. However, due to the inherent junction voltage drop of the diode, the conduction loss is large. The synchronous rectification mode adopts a MOS tube to rectify, without the junction voltage drop of the diode, and can greatly improve the rectification efficiency. As shown in Fig. 2, Q SR is a synchronous rectification switch tube. The current can pass through the body diode of Q SR , but in order to reduce the conduction loss, the MOS tube Q SR needs to be turned on during the stage of releasing energy of the magnetic energy storage element, so that the current passes through the channel of the MOS tube instead of the body diode, thereby reducing the conduction voltage drop and further reducing the loss. Because the rectification MOS tube Q SR does not have the natural turn-on and turn-off characteristics, it needs to be judged whether it is turned on by detecting the voltage between the drain and the source, that is, the synchronous rectification control technology. With the gradual reduction of the volume and the gradual increase of the working frequency of the switching power supply, the requirement for efficiency is also increasing, and therefore new requirements are put forward for the synchronous rectification control technology.

[0003] As shown in Fig. 3, the voltage time sequence waveforms of the key nodes of the flyback switching power supply are provided, including the gate voltage ideal waveform G1 of the primary side PWM switch tube Q1, the voltage waveform V DS between the drain and the source of the synchronous rectification tube Q SR , the gate waveform G SR of the synchronous rectification tube when normally turned on, and the gate waveform G SR(fault) of the synchronous rectification tube when mis-triggered to turn on. The basic principle of the synchronous rectification control is that the synchronous rectification tube is allowed to be turned on only when V DS is less than the turn-on threshold voltage V th(on) , and the synchronous rectification tube is turned off when V th(off) is greater than the turn-off threshold voltage V SR . The ideal state is shown in Fig. 3. V th(on)is a negative voltage, for example -100mV, the negative value indicates that the voltage of the source S of the synchronous rectifier is greater than the voltage of the drain D, which is a necessary condition for turning on the synchronous rectifier, but it is not a sufficient condition, because after the energy of the magnetic energy storage element is released, the leakage inductance of the magnetic energy storage element and the parasitic capacitance may resonate, and the negative pressure at the bottom of the resonance valley may also be less than V th(on) , at which time the synchronous rectifier should not be turned on but may be mistakenly triggered to turn on, as shown in the waveform of G SR(fault) in FIG. 3. How to distinguish between the negative pressure generated by the magnetic energy storage element during the energy release stage and the negative pressure generated by the leakage inductance resonance after the energy is released is a major technical difficulty in correctly turning on the synchronous rectifier.

[0004] To solve the above-mentioned problem of mistaken triggering, Chengdu Xinsu System Co., Ltd. proposes in Chinese Patent Application 201710561412.6 to use a conversion rate detection to achieve it. In some cases, the falling rate of V DS is large when the primary side PWM switch tube is just turned off, such as at times ① and ② shown in FIG. 3, which is larger than the falling rate during resonance, so a conversion rate window value is used to distinguish the resonance negative pressure, and when the conversion rate of the falling of V DS is less than a set value, it is considered to be a resonance negative pressure, and the synchronous rectifier is not allowed to be turned on. Because the conversion rate of different switching power supply resonance waveforms is different, a pin is often needed to set the conversion rate comparison threshold value for the application end to match the conversion rate. However, this scheme has three disadvantages: 1. A pin is usually needed to set the conversion rate comparison threshold value, and the adaptability is poor; 2. In order to reduce the size of the switching power supply, the operating frequency of the power supply is getting higher and higher, and the resonance frequency is also getting higher, so the conversion rate of the falling of V DS during the resonance stage is also large, and it is difficult to distinguish the conversion rate of the resonance by this method, or the available conversion rate window range is very narrow, resulting in low reliability; 3. In the application of soft-switching power supply topology, V DS may also rapidly fall during resonance, which cannot be effectively distinguished, and the synchronous rectifier should not be turned on at this time. The method in the patent application is not applicable to this scenario.

[0005] In addition, Shanghai Nanchip Semiconductor Technology Co., Ltd. proposes a synchronous rectification control method in Chinese Patent Application 202010137682.6, which proposes to start timing after detecting the peak value of V DS and compare the V DS voltage in real time. After a set time, if the V DS voltage is still relatively high, it is considered to be the plateau voltage. During the resonance stage, the waveform of V DS is circular, and under the clamping of the detection voltage and the detection time, the V DSWithout the platform characteristic, the negative pressure generated by resonance can be distinguished. This method will not misopen the synchronous rectification tube in the soft switching power supply, solving the problem encountered by patent application 201710561412.6 in this scenario. Technical problem

[0006] But it still has two defects: 1, still need a pin to design the detection time, in order to match the specific switching power supply parameters, so Shanghai Nanxin Semiconductor Technology Co., Ltd. still in patent 202010298524.9 also proposed a kind of self-adapting detection time of synchronous rectification control method to generate this adaptive detection time, because this time itself is very small, generally for nanosecond level, the actual adaptive range is limited; 2, in the light load of switching power supply, especially in the high frequency power supply with a working frequency of several hundred kHz, the conduction time of the primary side PWM switch tube Q1 is very small, which is close to the resonance period, resulting in V DS The platform voltage is less than the detection time (in order to distinguish the negative pressure of resonance, this time cannot be designed too small), resulting in the phenomenon that the synchronous rectification does not open. Technical solution

[0007] The purpose of the present application is to provide a synchronous rectification conduction control chip and its control method, which can solve the phenomenon that the synchronous rectification does not open due to the conduction time of the primary side PWM switch tube Q1 being very small when it is close to the resonance period, resulting in the platform voltage time of V DS being less than the detection time.

[0008] The purpose of the present application is achieved by the following technical solutions:

[0009] In a first aspect, the present application provides a synchronous rectification conduction control method, comprising the following steps:

[0010] Step S1, the relative maximum voltage identification circuit detects and identifies whether the drain-source voltage of the synchronous rectification switch tube appears a relative maximum voltage, and outputs an enable valid signal to the logic circuit if yes, and the logic circuit saves the enable valid signal with an enable register, and goes to step S2, otherwise, the drain-source voltage is continuously detected;

[0011] Step S2, the drain-source voltage of the synchronous rectification switch tube is continuously detected in real time, and when the drain-source voltage of the synchronous rectification switch tube is less than the turn-on threshold voltage, the synchronous detection comparison circuit outputs a first valid signal to the logic circuit, the logic circuit controls the synchronous rectification switch tube to turn on, and initializes the enable register;

[0012] Step S3, when detecting the drain-source voltage of the synchronous rectification switch tube > off threshold voltage, the synchronous detection comparison circuit outputs the second valid signal to the logic circuit, and the logic circuit controls the synchronous rectification switch tube to be turned off;

[0013] Step S4, after the synchronous rectification switch tube is turned off, returning to step S1, the next relative maximum voltage detection and identification is performed immediately or after a certain set time.

[0014] Further, the method for detecting and identifying whether the relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube appears includes the following steps:

[0015] Step S101, obtaining the relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube in the last period as a starting voltage, and generating a gradually decreasing capture threshold voltage;

[0016] Step S102, comparing the real-time detected drain-source voltage of the synchronous rectification switch tube with the capture threshold voltage, until the relative maximum voltage recognition circuit outputs an enable valid signal to the logic circuit when the drain-source voltage of the synchronous rectification switch tube approaches the capture threshold voltage;

[0017] Step S103, the enable register of the logic circuit saves the enable valid signal as a necessary condition for the synchronous rectification switch tube to be turned on, and goes to step S2; meanwhile, the drain-source voltage is continuously detected in real time until the relative maximum voltage in the current period is detected, the latest relative maximum voltage value is refreshed, and the operation returns to step S101 for circulation.

[0018] Further, the method for detecting and identifying whether the relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube appears includes the following steps:

[0019] Step S101', obtaining the relative maximum current of the synchronous rectification switch tube in the last period as a starting current, and generating a gradually decreasing capture threshold current;

[0020] Step S102', comparing the real-time sampling current with the capture threshold current, until the sampling current approaches the capture threshold current, and the relative maximum voltage recognition circuit outputs an enable valid signal to the logic circuit;

[0021] Step S103', the enable register of the logic circuit saves the enable valid signal as a necessary condition for the synchronous rectification switch tube to be turned on, and goes to step S2; meanwhile, the sampling current is continuously detected in real time until the relative maximum current in the current period is detected, the latest relative maximum current value is refreshed, and the operation returns to step S101' for circulation.

[0022] In a second aspect, the present application provides a synchronous rectification turn-on control chip, which internally integrates a relative maximum voltage identification circuit, a synchronous detection comparison circuit and a logic circuit; an input end of the relative maximum voltage identification circuit and an input end of the synchronous detection comparison circuit are respectively connected to a source detection input pin VS and a drain detection input pin VD of the synchronous rectification turn-on control chip to detect the drain-source voltage of a synchronous rectification switch tube; an output end of the relative maximum voltage identification circuit is connected to a first input end of the logic circuit; two output ends of the synchronous detection comparison circuit are respectively connected to a second input end and a third input end of the logic circuit; and an output end of the logic circuit is connected to an output pin of the synchronous rectification turn-on control chip.

[0023] The relative maximum voltage identification circuit and the synchronous detection comparison circuit detect the drain-source voltage of the synchronous rectification switch tube in real time, the relative maximum voltage identification circuit sends an enable valid signal to the logic circuit and saves it when the drain-source voltage of the synchronous rectification switch tube appears a relative maximum value, the synchronous detection comparison circuit outputs a first valid signal to the logic circuit when the drain-source voltage of the synchronous rectification switch tube is less than a turn-on threshold value, the logic circuit outputs a high level to the output pin of the control chip when it receives the enable valid signal and the first valid signal to control the synchronous rectification switch tube to turn on, and the synchronous detection comparison circuit outputs a second valid signal to the logic circuit when the drain-source voltage of the synchronous rectification switch tube is greater than a turn-off threshold value, and the logic circuit outputs a low level to the output pin of the control chip when it receives the second valid signal to control the synchronous rectification switch tube to turn off.

[0024] Further, the relative maximum voltage identification circuit comprises a sampling switch S1, a sampling capacitor C1, a first comparator CMP1, a monostable trigger MTRG and a micro-current source I1; one end of the sampling switch S1 and a positive input end of the first comparator CMP1 are respectively connected to the drain detection input pin VD of the synchronous rectification turn-on control chip; a negative input end of the first comparator CMP1 is respectively connected to a positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1; a negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded; an output end of the first comparator CMP1 is connected to an input end of the monostable trigger MTRG, an output end of the monostable trigger MTRG is respectively connected to a control end of the sampling switch S1 and a first input end of the logic circuit, and a ground of the relative maximum voltage identification circuit is connected to the source detection input pin VS of the synchronous rectification turn-on control chip.

[0025] Further, the relative maximum voltage identification circuit comprises a sampling resistor R S , a first N-channel MOS tube N1, a second N-channel MOS tube N2, a third N-channel MOS tube N3, a first P-channel MOS tube P1, a second P-channel MOS tube P2, a sampling switch S1, a sampling capacitor C1, a comparator CMP1, a monostable trigger MTRG and a micro-current source I1; the sampling resistor RS one end of the sampling resistor R S the other end of the sampling resistor R S the source of the first P-channel MOS transistor P1 is connected to the source of the second P-channel MOS transistor P2; the gate and the drain of the first P-channel MOS transistor P1 are connected and connected to the gate of the second P-channel MOS transistor P2 and the drain of the second N-channel MOS transistor N2 respectively; the drain of the second P-channel MOS transistor P2 and the drain of the third N-channel MOS transistor N3 are connected to the input end of the monostable trigger respectively; the output end of the monostable trigger is connected to the control end of the sampling switch S1 and the first input end of the logic circuit respectively; the gate of the third N-channel MOS transistor N3 is connected to the positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1 respectively; the source of the third N-channel MOS transistor N3, the negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded; the source detection input pin VS of the synchronous rectification conduction control chip is connected to the ground of the relative maximum voltage identification circuit.

[0026] Further, the relative maximum voltage identification circuit comprises: a sampling resistor R S , a first N-channel MOS transistor N1, a second N-channel MOS transistor N2, a third N-channel MOS transistor N3, a first P-channel MOS transistor P1, a second P-channel MOS transistor P2, a sampling switch S1, a sampling capacitor C1, a comparator CMP1, a monostable trigger MTRG and a micro-current source I1; one end of the sampling resistor R S is connected to the drain detection input pin VD, and the other end of the sampling resistor R SThe other end of the sampling switch S1 is connected with the drain and the gate of the first N-channel MOS transistor N1, the gate of the second N-channel MOS transistor N2, and the one end of the sampling switch S1 respectively; the source of the first N-channel MOS transistor N1 and the source of the second N-channel MOS transistor N2 are grounded; the source of the first P-channel MOS transistor P1 is connected with the source of the second P-channel MOS transistor P2; the gate and the drain of the first P-channel MOS transistor P1 are connected with each other and connected with the gate of the second P-channel MOS transistor P2 and the drain of the third N-channel MOS transistor N3 respectively; the drain of the second P-channel MOS transistor P2 and the drain of the second N-channel MOS transistor N2 are connected with the input end of the monostable trigger respectively; the output end of the monostable trigger is connected with the control end of the sampling switch S1 and the first input end of the logic circuit respectively; the gate of the third N-channel MOS transistor N3 is connected with the positive end of the micro-current source I1, the one end of the sampling capacitor C1, and the other end of the sampling switch S1 respectively; the source of the third N-channel MOS transistor N3, the negative end of the micro-current source I1, and the other end of the sampling capacitor C1 are grounded; the source detection input pin VS of the synchronous rectification conduction control chip is connected with the ground of the relative maximum voltage identification circuit.

[0027] Further, the synchronous detection comparison circuit comprises a second comparator CMP2 and a third comparator CMP3, the negative input end of the second comparator CMP2 and the positive input end of the third comparator CMP3 are connected with the drain detection input pin VD of the synchronous rectification conduction control chip respectively; the positive input end of the second comparator CMP2 inputs the turn-on threshold voltage of the synchronous rectification, and the negative input end of the third comparator CMP3 inputs the turn-off threshold voltage of the synchronous rectification; the output end of the second comparator CMP2 is connected with the second input end of the logic circuit, and the output end of the third comparator CMP3 is connected with the third input end of the logic circuit; the ground of the synchronous detection comparison circuit 402 is connected with the source detection input pin VS of the synchronous rectification conduction control chip.

[0028] Further, the logic circuit 403 comprises an enable register RS1, an AND gate AND1, and a synchronous rectification output control trigger RS2; the S input end of the enable register RS1 is the first input end of the logic circuit, the R input end of the enable register RS1 and the first input end of the AND gate AND1 are connected and are the second input end of the logic circuit, and the R input end of the synchronous rectification output control trigger RS2 is the third input end of the logic circuit; the output end Q of the enable register RS1 is connected with the second input end of the AND gate AND1, the output end of the AND gate AND1 is connected with the S input end of the synchronous rectification output control trigger RS2, and the output end Q of the synchronous rectification output control trigger RS2 is connected with the output pin VG of the synchronous rectification conduction control chip.

[0029] Further, the synchronous rectification switch tube is integrated in the synchronous rectification conduction control chip or placed outside the synchronous rectification conduction control chip. Advantages

[0030] The present application only detects V DS The relative size of the voltage, not the detection of V DS The conversion rate of V, which cannot be effectively distinguished due to the large resonance slope, will not produce false judgments in the application of soft-switching power supply topology. In addition, the present application does not need to set the detection time, so there is no phenomenon of synchronous rectifier not opening due to time limit. The relative maximum voltage detection device of the present application automatically tracks and judges, and does not need additional pins for parameter matching, so it solves the problems encountered in the prior art, obtains a wider application scenario, and the chip peripheral is also simpler. BRIEF DESCRIPTION OF DRAWINGS

[0031] Fig. 1 is a simplified schematic diagram of a diode rectification flyback switching power supply of the prior art;

[0032] Fig. 2 is a simplified schematic diagram of a synchronous rectification flyback switching power supply of the prior art;

[0033] Fig. 3 is a timing waveform diagram of key nodes of a synchronous rectification flyback switching power supply;

[0034] Fig. 4 is a circuit structure schematic diagram of the application of a synchronous rectification conduction control chip in a flyback switching power supply;

[0035] Fig. 5 is a principle diagram of a voltage type detection method of the synchronous rectification conduction control chip of the present application;

[0036] Fig. 6 is a key node waveform diagram of the voltage type detection method of the synchronous rectification conduction control chip of the present application;

[0037] Fig. 7 is a circuit structure schematic diagram of a synchronous rectification conduction control chip with built-in synchronous rectification switch tube of the present application;

[0038] Fig. 8 shows a circuit principle diagram of a current type detection method of the synchronous rectification conduction control chip of the present application;

[0039] Fig. 9 shows a key node waveform diagram of the current type detection method of the synchronous rectification conduction control chip of the present application;

[0040] Fig. 10 is another circuit principle diagram of the current type detection method of the synchronous rectification conduction control chip of the present application. Best mode for carrying out the present application

[0041] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0042] The following describes embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all. The present disclosure can also be implemented or applied by other different specific embodiments, and various modifications or changes can be made based on different views and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure. In the description of the present application, the positive input terminal of the comparator is connected to the reference voltage, and the negative input terminal is connected to the voltage detection terminal. Of course, it can also be connected in the opposite direction, as long as the output of the comparator is reversed in logic, and it does not affect the normal function. In addition, the NMOS transistor can also be replaced by an NPN transistor. It should be understood that when one element described in the present application is "connected" to another element, it can be directly connected or coupled to another element or there can be intermediate elements. Simple logic reversal and device replacement, or simple connection relationship changes in circuit structure without departing from the spirit of the present application, cannot be used to evade the present application.

[0043] The circuit provided by the present application is integrated in a chip. In order to facilitate intuitive understanding, the present application is described in detail in the embodiment of the present application by taking a flyback synchronous rectification switching power supply circuit as an example. However, this is not a limitation on the application range. It can also be applied to control chips of various power supply topologies such as BUCK voltage reduction chips and forward switching power supplies.

[0044] In order to solve the problem of false triggering of the synchronous rectification switch, Fig. 4 shows a structure diagram of the application of the synchronous rectification conduction control chip of the present application in a synchronous rectification flyback switching power supply circuit. As shown in Fig. 4, the synchronous rectification flyback switching power supply circuit comprises the synchronous rectification conduction control chip 40 of the present application, and the magnetic energy storage element 41, the primary side pulse width modulation chip 42, the primary side PWM switch tube 43, the synchronous rectification switch tube 44, and the capacitive energy storage element 45 of the prior art.

[0045] The working principle is as follows: when the primary side pulse width modulation chip 42 controls the PWM switch tube 43 to be turned on, the current flows from the input terminal V IN of the switching power supply circuit to the primary winding 411 of the magnetic energy storage element 41, and the magnetic energy storage element 41 stores energy; after the primary side pulse width modulation chip 42 controls the PWM switch tube 43 to be turned off, the magnetic energy storage element 41 releases energy, and the current flows from the secondary winding 412 of the magnetic energy storage element 41 through the synchronous rectification switch tube 44 to the output terminal V OUTThe energy is stored in the capacitive energy storage element 45 flowing out or flowing into the output end. Under the continuous circulation of storing energy and releasing energy in the magnetic energy storage element 41, the energy is transmitted from the V IN end of the flyback switching power supply circuit to the output end V OUT .

[0046] The magnetic energy storage element 41 includes a primary winding 411 and a secondary winding 412, which can be physically implemented in various ways, such as copper wire winding or PCB metal trace winding, etc.

[0047] The duty cycle of the primary side pulse width modulation chip 42 controlling the PWM switch tube 43 to turn on, that is, the ratio of the turn-on time to the switching period, can be realized by adjusting the turn-on time, the turn-off time, the switching period, or the combination thereof.

[0048] The primary side PWM switch tube 43 mainly plays a switching role, which can be an N-channel silicon MOS tube or a silicon carbide MOS tube, an NPN triode, a thyristor, or an insulated gate bipolar transistor, etc.

[0049] The synchronous rectification switch tube 44 mainly plays a switching role, which is closed when the magnetic energy storage element 41 stores energy and is turned on when the energy is diluted, and can be an N-channel silicon MOS tube, an N-channel silicon carbide MOS tube, an insulated gate bipolar transistor, etc.

[0050] The output capacitive energy storage element 45 is a capacitor device, which can be an electrolytic capacitor, a ceramic capacitor, a thin film capacitor, etc.

[0051] The key of the present application is to propose a synchronous rectification conduction control chip, which is internally integrated with a synchronous rectification control circuit for accurately judging the energy storage stage and the energy release stage of the magnetic energy storage element 41, and closing the synchronous rectification switch tube 44 in the energy storage stage and turning on the synchronous rectification switch tube 44 in the energy release stage. The synchronous rectification control circuit includes a relative maximum voltage identification circuit 401, a synchronous detection comparison circuit 402 and a logic circuit 403. These circuits are realized on a wafer to form a synchronous rectification conduction control chip 40. The synchronous rectification conduction control chip 40 includes at least three pins: a source detection input pin VS, a drain detection input pin VD and an output pin VG. The source detection input pin VS is connected to the source of the synchronous rectification switch tube 44, the drain detection input pin VD is connected to the drain of the synchronous rectification switch tube 44, VD and VS provide detection signals V DS for the internal circuit of the synchronous rectification conduction control chip, and the VG output signal controls the turn-on or turn-off of the synchronous rectification switch tube 44.

[0052] The synchronous rectification conduction control method of the present application includes the following steps:

[0053] Step S1, the relative maximum voltage recognition circuit detects and identifies whether the drain-source voltage of the synchronous rectification switch tube has a relative maximum voltage, and outputs an enable valid signal T if so EN to the logic circuit, which saves the enable valid signal T in an enable register EN , and goes to step S2, otherwise, continuously detects the drain-source voltage.

[0054] As shown in FIG. 3, the detection voltage V DS can be divided into an energy storage stage, an energy release stage and a resonance stage. A plurality of resonance peak values are generated in the resonance stage, and these resonance peak values are gradually attenuated, and generally, these resonance peak values are smaller than the voltage in the energy storage stage of the magnetic energy storage element 41, so as long as the maximum voltage value is detected in a cycle, the energy storage stage can be identified, and this maximum voltage is the maximum value in a cycle, and the voltage in the energy storage stage in the following cycle can be changed, for example, it changes with the input voltage, so the detected maximum voltage value should be a relative maximum value. DS DS

[0055] The relative maximum voltage recognition circuit 401 judges the energy storage stage of the magnetic energy storage element 41 by identifying the relative maximum voltage of the voltage difference V DS between the drain and the source of the synchronous rectification switch tube 44, and outputs the judgment result to the logic circuit 403.

[0056] Further, the method for detecting and identifying whether the drain-source voltage V DS of the synchronous rectification switch tube has a relative maximum voltage is a voltage type detection method, including the following steps:

[0057] Step S101, obtaining the relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube in the last cycle as a starting voltage, and generating a gradually decreasing capture threshold voltage V C .

[0058] The drain-source voltage of the synchronous rectification switch tube has a maximum value in each cycle, and the maximum voltage value in each cycle can be different. This maximum voltage value is relative to other peak voltages (including resonance peak voltages) in the same cycle, and can be smaller than the maximum voltage in other cycles, so it is called a relative maximum voltage, as shown in FIG. 6, V C1 , V C2 are relative maximum voltages in different cycles.

[0059] The rate of slow decrease of the capture threshold voltage is a judgment standard for not causing false detection of the resonance peak voltage. Preferably, the minimum value on the capture threshold voltage line in the resonance stage in a cycle should not be lower than V DS ​​The first resonant peak voltage, so even in the case of not shielding the first resonant peak, the resonant peak voltage will not be detected as the relative maximum voltage. (Note: this is only a preferred solution, because the following embodiments propose that the relative maximum voltage identification circuit starts to work after a certain time delay after the synchronous rectification switch is turned off, so that the first resonant peak or multiple resonant peaks can be shielded, and then the relative maximum voltage capture threshold voltage can be lower than the first resonant peak voltage).

[0060] The reason for setting the relative maximum voltage to decrease slowly is that the relative maximum voltage in different periods can not be the same, and if the relative maximum voltage in the next period is lower than that in the previous period, the relative maximum voltage in the next period cannot be collected if it is not decreased slowly. The capture threshold voltage needs to be decreased slowly so that it is eventually close to the relative maximum voltage that can be collected, so that the reduced relative maximum voltage can be continuously collected in the following periods.

[0061] Step S102, detecting the drain-source voltage V DS and comparing it with the capture threshold voltage until the drain-source voltage V DS of the synchronous rectification switch is detected.

[0062] Very close can be defined as being smaller than the capture threshold voltage by a certain value, which can be set according to actual needs, and can be set according to relative values or relative proportions. The size of the set value should not be considered as a limitation of the present application.

[0063] Step S103, the enable register of the logic circuit 403 saves the enable valid signal as a necessary condition for the conduction of the synchronous rectification switch, and goes to step S2; at the same time, the drain-source voltage V DS is continuously detected until the relative maximum voltage Vc1 in the current period is detected, the latest relative maximum voltage value is refreshed and saved, and the cycle operation returns to step S101.

[0064] Since the method of the present application only needs to identify whether the relative maximum voltage V DS appears, and does not need to accurately sample the specific size of the relative maximum voltage V DS , the present application further proposes a more preferred current type detection method for identifying the relative maximum voltage, which converts the voltage V DS into current on a sampling MOS connected in a sampling resistance and diode mode, then copies and saves the current on the sampling MOS through a current mirror, and uses direct comparison between currents to identify the relative maximum current, and then indirectly identifies the relative maximum voltage VDS The relative maximum voltage.

[0065] Current-type detection methods for relative maximum voltage identification include:

[0066] Step S101': Obtain the relative maximum current of the synchronous rectifier switch in the previous cycle and use it as the starting current (Ic in Figure 9) to generate a gradually decreasing capture threshold current (a downward sloping straight line in Figure 9).

[0067] The rate of decrease is slowed down to avoid false detection of the resonant peak current. Preferably, the minimum capture threshold current within one cycle should not be lower than V. DS The first resonant peak current will not be mistakenly detected as the relative maximum current, even if the first resonant peak is not shielded.

[0068] Step S102': Compare the real-time sampled current with the capture threshold current until the sampled current is very close to the capture threshold current, then the relative maximum voltage identification circuit 401 outputs an enable signal to the logic circuit 403.

[0069] The definition of "very close" is similar to that in step S102.

[0070] In step S103', the enable register of logic circuit 403 stores the enable valid signal as a necessary condition for the synchronous rectifier switch to be turned on, and then proceeds to step S2; at the same time, the sampling current continues to be detected in real time until the relative maximum current of this cycle (Ic1 in Figure 9) is detected, the latest relative maximum current value is refreshed and saved, and the process returns to step S101' to perform the loop operation.

[0071] V is indirectly sensed by detecting the relative maximum current. DS The current-type detection method for determining the relative maximum voltage has several advantages: ① The gate and drain of the sampling MOS are connected together, which is often referred to as a diode connection in the integrated circuit field. The resulting gate voltage changes less with current, thus providing a more accurate assessment of V. DS The sampling input voltage range is wide and will not be affected by V. DS If the voltage is too high and exceeds the comparator's operating range, it will not be affected by V. DS ① The voltage is too low and the signal-to-noise ratio is small; ② The current is easily mirrored and copied in the integrated circuit; ③ The comparison between currents is fast and not easily affected by interference, and the circuit structure is simple.

[0072] Step S2: Continue to monitor the drain-source voltage of the synchronous rectifier switch in real time. When the drain-source voltage V of the synchronous rectifier switch... DS <V when the threshold voltage is turned on th(on), the synchronous detection comparison circuit outputs a first active signal to the logic circuit, the logic circuit controls the synchronous rectification switch tube to be turned on, and initializes the enable register; when the active signal of the enable register is not received or the V DS <V th(on) , the synchronous rectification switch tube is prohibited to be turned on.

[0073] Step S3, when the drain-source voltage V DS of the synchronous rectification switch tube is detected to be greater than the turn-off threshold voltage V th(off) , the synchronous detection comparison circuit outputs a second active signal T off to the logic circuit, and the logic circuit controls the synchronous rectification switch tube to be turned off.

[0074] Step S4, after the synchronous rectification switch tube is turned off, returning to step S1, the detection and identification of the relative maximum voltage in the next (i.e. the next cycle) is immediately performed, or the detection of the relative maximum voltage in the next cycle is performed after a set time delay. The purpose of the set time delay is to shield the first or even multiple resonance peaks as much as possible. The synchronous rectification switch tube is turned on and turned off in the cycle. Embodiments of the present application

[0075] A synchronous rectification turn-on control chip 40 of the present application is shown in FIG. 5, which internally integrates a relative maximum voltage identification circuit 401, a synchronous detection comparison circuit 402 and a logic circuit 403. The relative maximum voltage identification circuit 401 and the synchronous detection comparison circuit 402 detect the drain-source voltage V DS of the synchronous rectification switch tube in real time, when the drain-source voltage V DS of the synchronous rectification switch tube appears a relative maximum value, the relative maximum voltage identification circuit 401 sends an enable active signal T EN to the logic circuit 403 and saves it. When the drain-source voltage V DS of the synchronous rectification switch tube is greater than the turn-on threshold V th(on) , the synchronous detection comparison circuit 402 outputs a first active signal T on to the logic circuit 403; when the logic circuit 403 receives the enable active signal T EN and the first active signal T on , a high level is output to the output pin VG of the control chip to control the synchronous rectification switch tube to be turned on. When the drain-source voltage V DS of the synchronous rectification switch tube is less than the turn-off threshold V th(off) , the synchronous detection comparison circuit 402 outputs a second active signal T off to the logic circuit 403; when the logic circuit 403 receives the second active signal T off , a low level is output to the output pin VG of the control chip to control the synchronous rectification switch tube to be turned off.

[0076] Further, as an embodiment of the present application, the relative maximum voltage identification circuit 401 is shown in Fig. 5, which comprises a sampling switch S1, a sampling capacitor C1, a first comparator CMP1, a monostable trigger MTRG, and a micro-current source I1. One end of the sampling switch S1 and the positive input end of the first comparator CMP1 are connected to the drain detection input pin VD respectively. The negative input end of the first comparator CMP1 is connected to the positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1 respectively. The negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded. The output end of the first comparator CMP1 is connected to the input end of the monostable trigger MTRG, and the output end of the monostable trigger MTRG is connected to the control end of the sampling switch S1 and the first input end of the logic circuit respectively. The ground of the relative maximum voltage identification circuit 401 is connected to the source detection input pin VS.

[0077] In Fig. 5, the voltage V C generated on the sampling capacitor C1 is the capture threshold voltage, which is compared with the input voltage V SAM of the positive input end of the first comparator CMP1, and the comparison result CR1 is output to the monostable trigger. DS When V SAM is greater than V C , the output CR1 of the comparator CMP1 flips, and further triggers the monostable trigger to output an enable valid signal T EN to the first input end of the logic circuit and the control end of the sampling switch S1 respectively. Under the action of the enable valid signal T EN , the sampling switch S1 is closed, the voltage of the sampling capacitor C1 is refreshed, and V C equals V SAM , at this time a new relative maximum voltage is saved. Due to the characteristics of the monostable trigger, after the enable valid signal T EN disappears, the sampling switch S1 is opened again, and under the action of the micro-current source I1, the capture threshold voltage V C slowly decreases from the relative maximum voltage, until V SAM is greater than V C again, a new round of sampling and refreshing action occurs. Such a cycle continues, and the enable valid signal and the relative maximum voltage are continuously output.

[0078] Further, as an embodiment of the present application, the synchronous detection and comparison circuit 402 comprises a second comparator CMP2 and a third comparator CMP3, and the negative input end of the second comparator CMP2 and the positive input end of the third comparator CMP3 are connected to the drain detection input pin VD respectively. The positive input end of the second comparator CMP2 is input with the turn-on threshold voltage V th(on), the negative input terminal of the third comparator CMP3 is inputted with the turn-off threshold value V th(off) of the synchronous rectification. The output terminal of the second comparator CMP2 is connected with the second input terminal of the logic circuit, and the output terminal of the third comparator CMP3 is connected with the third input terminal of the logic circuit. The ground terminal of the synchronous detection comparison circuit 402 is connected with the source detection input pin VS.

[0079] When the second comparator CMP2 detects that the voltage V DS is lower than the turn-on threshold value V th(on) of the synchronous rectification, the first valid signal T on is outputted to the second input terminal of the logic circuit; when the third comparator CMP3 detects that the voltage V DS is higher than the turn-off threshold value V th(off) of the synchronous rectification, the second valid signal T off is outputted to the third input terminal of the logic circuit.

[0080] Further, as an embodiment of the present application, the logic circuit 403 comprises an enable register RS1, an AND gate AND1 and a synchronous rectification output control flip-flop RS2. The S input terminal of the enable register RS1 is the first input terminal of the logic circuit, the R input terminal of the enable register RS1 and the first input terminal of the AND gate AND1 are connected and are the second input terminal of the logic circuit, and the R input terminal of the synchronous rectification output control flip-flop RS2 is the third input terminal of the logic circuit. The output terminal Q of the enable register RS1 is connected with the second input terminal of the AND gate AND1, and the output terminal of the AND gate AND1 is connected with the S input terminal of the synchronous rectification output control flip-flop RS2. The output terminal Q of the synchronous rectification output control flip-flop RS2 is connected with the output pin VG.

[0081] The enable register RS1 stores the record of the enable valid signal T EN ; when the two input terminals of the AND gate AND1 are both high, the valid signal is outputted to the synchronous rectification output control flip-flop RS2. After receiving the valid signal from the AND gate AND1, the synchronous rectification output control flip-flop RS2 outputs high voltage to the VG pin to turn on the synchronous rectification switch tube 44, and until the second valid signal T off is received by the synchronous rectification output control flip-flop RS2, low voltage is outputted to the VG pin to turn off the synchronous rectification switch tube 44.

[0082] As shown in FIG. 6, it is the timing waveform of the key nodes of the voltage type implementation method of the relative maximum voltage identification circuit 401. The working principle of the voltage type implementation method of the relative maximum voltage identification circuit 401 is further explained in detail in combination with the timing waveform as follows:

[0083] At time A, it is detected that the drain-source voltage V DS is greater than the voltage V C(That is, capturing the threshold voltage), the first comparator CMP1 flips, thereby triggering the monostable multivibrator to generate a high-level pulse enable signal T in segment A~B. EN1 T EN1 Close sampling switch S1, V C Follow V DS The size, store a relative maximum voltage V C1 Meanwhile, T EN1 The enable register RS1 is triggered to a high level, and the event of detecting a relative maximum voltage is recorded.

[0084] At time B, the monostable multivibrator automatically recovers to its steady-state value, sampling switch S1 opens, and due to the discharge effect of micro-current source I1, voltage V... C From the relative maximum voltage V at time B C1 It begins to gradually decrease. This is because the relative maximum voltage in later cycles may drop rapidly, significantly lower than V. C1 If V C Keep V C1 If it remains unchanged, it cannot capture the subsequent relative maximum voltage, therefore V is designed... C From the relative maximum value V C1 The slow descent function will eventually detect V. DS Very close to V C Continue to capture the relative maximum voltage after the drop.

[0085] At time C, the magnetic energy storage element 41 ends energy storage and begins to enter the energy release phase, V DS The voltage waveform begins to decrease.

[0086] At time D, V DS Drop to synchronous rectification activation threshold V th(on) The comparator CMP2 outputs T on If a valid signal is received, then both inputs of AND1 will receive a valid signal simultaneously, and the output high level will trigger RS2 to output a high-level voltage. Due to the register effect of the flip-flop RS2, even if the high level output of AND1 is removed, RS2 will still maintain a high-level voltage and continue to turn on the synchronous rectifier switch 44.

[0087] At time E, V DS Rise to synchronous rectification turn-off threshold V th(off) The comparator CMP3 outputs T off A valid signal causes the RS2 output voltage to flip from high to low, continuously shutting down the synchronous rectification until it is turned on again.

[0088] At time F, the first resonant peak occurs after the synchronous rectifier switch is turned off. This peak voltage should be less than the capture threshold voltage V.C This can be achieved by designing the current value of the micro-current source I1, so that none of the resonance peaks will be detected, and no enable valid signal T EN Then, even if V DS resonance to the synchronous rectification turn-on V th(on) The following, also will not trigger the opening of the synchronous rectification switch tube 44.

[0089] At time G, the relative maximum voltage is captured again, and a series of actions occur as at time A, the new relative maximum voltage V C2 is saved on the sampling capacitor C1, and the cycle of the new period is entered.

[0090] The maximum relative voltage V C1 , V C2 , and then V C3 , V C4 …… will continue to be detected, which are the voltage values at special moments of the capture threshold voltage V C , and this special moment is the enable valid signal T EN controls the time period of the sampling switch S1 refresh.

[0091] The monostable trigger is a commonly used logic unit in digital circuits, which has two states, a stable state and a temporary stable state. If the stable state is low, then the temporary stable state is high; conversely, if the stable state is high, then the temporary stable state is low. Under the action of an external pulse, the monostable trigger can be transferred from one stable state to a temporary stable state, and after a delay element, it returns to the original stable state from the temporary stable state. The external pulse can be high or low. Therefore, the monostable trigger, as a basic unit of digital circuits, has various implementation methods. In this embodiment, a high-level pulse is used for triggering to generate a high-level temporary stable state, which is only used to illustrate the working principle of the relative maximum voltage detection, and is not used to limit the protection scope.

[0092] In an embodiment, the micro-current source I1 can also use a resistor to achieve the effect of slow discharge.

[0093] In an embodiment, the clear port R of the enable register RS1 can also be triggered by T off , and another separate comparator can also be used to compare with the corresponding comparison threshold, and RS1 can be initialized according to the output result, because as long as V DS is detected to be as low as a certain threshold voltage, it indicates that the relative maximum voltage has appeared, and RS1 can be initialized for the detection of the relative maximum voltage in the next period.

[0094] In one embodiment, a small delay is added after the synchronous rectification switch 44 is turned off before the relative maximum voltage identification circuit 401 is allowed to detect the relative maximum voltage in the next cycle. This way, the sampling is done after the first or multiple resonance peaks, which is more effective in avoiding the influence of the resonance peaks.

[0095] In one embodiment, the synchronous rectification switch 44 can be integrated with the synchronous rectification control circuit to form a synchronous rectification on control chip 70. The chip then only has two pins, VS and VD, as shown in Figure 7. The working principle of the synchronous rectification control circuit is the same as that in Figure 4, and will not be described again.

[0096] In one embodiment, V DS In one embodiment, a sampling current is generated on a sampling resistor, and then a current mirror in an integrated circuit is used to copy the sampling and make a corresponding comparison, so that the relative maximum voltage can be indirectly sensed by capturing the relative maximum current, i.e. the current type detection method of the relative maximum voltage.

[0097] Figure 8 shows a schematic diagram of the circuit structure of the current type detection method of the relative maximum voltage. As shown in Figure 8, the relative maximum voltage identification circuit 401 includes: a sampling resistor R S , a first N-channel MOS tube N1, a second N-channel MOS tube N2, a third N-channel MOS tube N3, a first P-channel MOS tube P1, a second P-channel MOS tube P2, a sampling switch S1, a sampling capacitor C1, a comparator CMP1, a monostable trigger MTRG, and a micro-current source I1. One end of the sampling resistor R S is connected to the drain detection input pin VD, and the other end of the sampling resistor R S is connected to the drain and gate of the first N-channel MOS tube N1, the gate of the second N-channel MOS tube N2, and one end of the sampling switch S1, respectively. The source of the first N-channel MOS tube N1 and the source of the second N-channel MOS tube N2 are grounded. The source of the first P-channel MOS tube P1 is connected to the source of the second P-channel MOS tube P2. The gate and drain of the first P-channel MOS tube P1 are connected to the gate of the second P-channel MOS tube P2 and the drain of the second N-channel MOS tube N2, respectively. The drain of the second P-channel MOS tube P2 and the drain of the third N-channel MOS tube N3 are connected to the input end of the monostable trigger, respectively. The output end of the monostable trigger is connected to the control end of the sampling switch S1 and the first input end of the logic circuit, respectively. The gate of the third N-channel MOS tube N3 is connected to the positive end of the micro-current source I1, one end of the sampling capacitor C1, and the other end of the sampling switch S1, respectively. The source of the third N-channel MOS tube N3, the negative end of the micro-current source I1, and the other end of the sampling capacitor C1 are grounded. The ground of the relative maximum voltage identification circuit 401 is connected to the source detection input pin VS.

[0098] Drain-source voltage V DS At sampling resistor R S And the current I is converted on the N-channel MOSFET N1 DS Because the drain and source of N1 are connected together, a current I is generated. DS The corresponding gate-source voltages of N2 and N3 are the same as those of N1, thus N2 and N3 can proportionally mirror I. DS N3 mirrors I proportionally through sampling switch S1. DS Then gradually decrease it to generate the capture threshold current I. C P1 and P2 are also a pair of current mirrors. P2 replicates the current of P1 proportionally, so the sampling current I generated on P2 is... SAM Also with I DS Proportional relationship. The sampling current I... SAM With the capture threshold current I C The comparison is performed, and the output comparison result CR1 is passed to the monostable multivibrator. When I SAM Greater than I C At this time, CR1 becomes a high-level active signal, which further triggers the monostable multivibrator to output an enable signal T. EN Under the action of the enable signal, the sampling switch S1 is turned on, refreshing the voltage of the sampling capacitor C1, and making I... C equals I SAM At this point, a new relative maximum current is preserved. This is achieved with the enable signal T. EN After disappearing, sampling switch S1 is opened again, and under the action of micro-current source I1, I C The current decreases slowly from its relative maximum until it encounters I again. SAM Greater than I C At this time, a new round of sampling and refreshing occurs. This cycle continues, continuously outputting an enable signal and storing the relative maximum current. The circuit structure and principle of the synchronous detection and comparison circuit 402 and the logic circuit 403 are the same as those in Figure 4, and will not be described again.

[0099] Figure 9 shows the timing waveforms of key nodes in the current-mode implementation of the relative maximum voltage identification circuit 401. Compared with the key waveforms of the voltage-mode implementation shown in Figure 6, the voltage V needs to be... DS At sampling resistor R S The current is converted into an electric current, and then mirrored to generate I. SAM and I C The working principle of the 401 current-mode implementation method for the relative maximum voltage identification circuit is further explained in detail below with reference to timing waveform diagram 9:

[0100] At time A, the sampling current I is detected. SAMgreater than the capture threshold current I C , the node CR1 becomes high, and further triggers the monostable trigger to generate the enable valid signal T EN1 , T EN1 closes the sampling switch S1, and the voltage of the sampling capacitor C1 is refreshed, and then a relatively maximum current I C1 is saved on N3. EN1 T C triggers the enable register RS1 to high, and records the event that a relatively maximum current is detected.

[0101] At the moment B, the monostable trigger automatically returns to the steady state value, and the sampling switch S1 is opened. Due to the discharge effect of the micro-current source I1, the voltage V C of the sampling capacitor C1 gradually decreases, and then the capture threshold current I C1 gradually decreases from the relatively maximum current I C1 . Because the relatively maximum current of the subsequent period may quickly decrease and be much lower than I C , if I C1 remains unchanged, the subsequent relatively maximum current cannot be captured, and therefore I C is designed to slowly decrease from the relatively maximum value I C1 , and finally I SAM is very close to I C , and the subsequent relatively maximum current after the decrease is continuously captured.

[0102] At the moment C, the magnetic energy storage element 41 ends the energy storage and starts the energy release stage, and the voltage V DS waveform starts to decrease, and the sampling current I SAM also starts to decrease.

[0103] At the moment D, V DS decreases to the synchronous rectification turn-on threshold V th(on) , the comparator CMP2 outputs the T on valid signal, and then the two input ends of the AND gate AND1 simultaneously receive the valid signal, and outputs a high level to trigger RS2 to output a high voltage. Due to the register function of the trigger RS2, even if the high level output by the AND gate AND1 is revoked, RS2 still maintains a high voltage, and continuously turns on the synchronous rectification switch tube 44.

[0104] At the moment E, V DS rises to the synchronous rectification turn-off threshold V th(off) , the comparator CMP3 outputs the T off valid signal, and makes the RS2 output voltage flip from high to low, and continuously closes the synchronous rectification, until the next turn-on.

[0105] At F moment, the first resonance peak value after the synchronous rectification switch is closed appears, the sampling current I SAM should be less than the capture threshold current I C This can be achieved by designing the current value of the micro-current source I1, so that none of the resonance peaks will be detected, and no enable valid signal T EN , then even if V DS resonance to the synchronous rectification on V th(on) The following, the opening of the synchronous rectification switch 44 will not be triggered by mistake.

[0106] At G moment, the relative maximum current is captured again, and a series of actions occur as at A moment, the new relative maximum current I C2 is saved on N-type channel MOS tube N3, and the cycle of the new period is entered.

[0107] The maximum relative current I C1 , I C2 , and then I C3 , I C4 … will continue to be detected, these currents are the current values at the special moment of the capture threshold current I C , and this special moment is the enable valid signal T EN controls the time period of the sampling switch S1 refresh.

[0108] Figure 10 shows another circuit structure schematic diagram of the current type detection method of the relative maximum voltage. As shown in Figure 10, the relative maximum voltage identification circuit 401 includes: a sampling resistor R S , a first N-channel MOS tube N1, a second N-channel MOS tube N2, a third N-channel MOS tube N3, a first P-channel MOS tube P1, a second P-channel MOS tube P2, a sampling switch S1, a sampling capacitor C1, a comparator CMP1, a monostable trigger MTRG and a micro-current source I1. One end of the sampling resistor R S is connected to the drain detection input pin VD, and the other end of the sampling resistor R SThe other end of the sampling switch S1 is connected with the drain and gate of the first N-channel MOS transistor N1, the gate of the second N-channel MOS transistor N2, respectively. The source of the first N-channel MOS transistor N1 and the source of the second N-channel MOS transistor N2 are grounded. The source of the first P-channel MOS transistor P1 is connected with the source of the second P-channel MOS transistor P2. The gate and drain of the first P-channel MOS transistor P1 are connected with the gate of the second P-channel MOS transistor P2 and the drain of the third N-channel MOS transistor N3, respectively. The drain of the second P-channel MOS transistor P2 and the drain of the second N-channel MOS transistor N2 are connected with the input end of the monostable trigger, respectively. The output end of the monostable trigger is connected with the control end of the sampling switch S1 and the first input end of the logic circuit, respectively. The gate of the third N-channel MOS transistor N3 is connected with the positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1, respectively. The source of the third N-channel MOS transistor N3, the negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded. The source detection input pin VS is connected with the ground of the relative maximum voltage identification circuit 401.

[0109] In Fig. 10, P1 is connected with N3, then P2 generates the relative maximum current I C flows into the node CR1, which is opposite to that in Fig. 8; N2 does not generate the sampling current I SAM which flows out of the node CR1, which is opposite to that in Fig. 8. Since the maximum relative current and the sampling current adopt the comparison of opposite polarity as in Fig. 8, then the monostable trigger MTRG2 also needs to be correspondingly changed into the implementation mode of low-level triggering. Fig. 10 and Fig. 8 adopt the comparison logic of different polarities in circuit implementation, and also can indirectly perceive the occurrence of the relative maximum voltage V DS by detecting the relative maximum current. Industrial applicability

[0110] The synchronous rectification control circuit provided by the application detects the relative maximum voltage V DS between the drain and the source of the synchronous rectification switch tube, and only the energy storage stage of the magnetic energy storage element detects the relative maximum voltage, then generates the enable effective signal to allow the synchronous rectification to be opened, and the relative maximum voltage value cannot be detected in the resonance stage, thereby effectively avoiding the mis-triggered opening of the synchronous rectification switch tube. Since the conversion rate of V DS is not needed, there is no case that the resonance frequency is too large to effectively distinguish, and there is no V DSThe situation of the synchronous rectification mis-turn-on caused by the sudden drop does not need an extra pin to debug the comparison threshold of the matching slew rate; since the energy storage stage and the resonance stage are not distinguished by setting time, the time-related part in the present application is only the enable effective signal, which functions to refresh the sampling capacitor and trigger the enable register instead of directly determining whether to allow the synchronous rectification to turn on, and the time width can be as low as tens of nanoseconds, far lower than the time of the energy storage stage or even the resonance period, thus there is no problem of not turning on the synchronous rectification as in the conventional technology of distinguishing the energy storage stage by time.

[0111] The above merely illustrates the embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principle of the present application without creative labor shall be included in the protection scope of the present application.

Claims

1. A synchronous rectification turn-on control method, characterized by, The method comprises the following steps: Step S1, a relative maximum voltage identification circuit detects and identifies whether a relative maximum voltage of a drain-source voltage of a synchronous rectification switch tube occurs, and outputs an enable valid signal to a logic circuit if yes, and the logic circuit saves the enable valid signal in an enable register, and goes to step S2, otherwise, the drain-source voltage is continuously detected; Step S2, the drain-source voltage of the synchronous rectification switch tube is continuously detected in real time, and when the drain-source voltage of the synchronous rectification switch tube is less than a turn-on threshold voltage, a synchronous detection comparison circuit outputs a first valid signal to the logic circuit, and the logic circuit controls the synchronous rectification switch tube to be turned on, and initializes the enable register; Step S3, when it is detected that the drain-source voltage of the synchronous rectification switch tube is greater than a turn-off threshold voltage, the synchronous detection comparison circuit outputs a second valid signal to the logic circuit, and the logic circuit controls the synchronous rectification switch tube to be turned off; Step S4, after the synchronous rectification switch tube is turned off, the step S1 is returned, and the next detection and identification of the relative maximum voltage are performed immediately or after a delay set time.

2. The synchronous rectification turn-on control method according to claim 1, characterized by, The method for detecting and identifying whether the relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube occurs is a voltage type detection method, and comprises the following steps: Step S101, a relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube in a last period is obtained as a starting point voltage, and a capture threshold voltage gradually decreasing is generated; Step S102, the drain-source voltage of the synchronous rectification switch tube detected in real time is compared with the capture threshold voltage, and when it is detected that the drain-source voltage of the synchronous rectification switch tube approaches the capture threshold voltage, a relative maximum voltage identification circuit outputs an enable valid signal to a logic circuit; Step S103, an enable register of the logic circuit saves the enable valid signal as a necessary condition for the synchronous rectification switch tube to be turned on, and goes to step S2; meanwhile, the drain-source voltage is continuously detected in real time until the relative maximum voltage in the current period is detected, the latest relative maximum voltage value is refreshed, and the step S101 is returned to be operated in a loop.

3. The synchronous rectification turn-on control method according to claim 1, characterized by, The method for detecting and identifying whether the relative maximum voltage of the drain-source voltage of the synchronous rectification switch tube occurs is a current type detection method, and comprises the following steps: Step S101', a relative maximum current of the synchronous rectification switch tube in a last period is obtained as a starting point current, and a capture threshold current gradually decreasing is generated; Step S102', a real-time sampling current is compared with the capture threshold current, and when the sampling current approaches the capture threshold current, a relative maximum voltage identification circuit outputs an enable valid signal to a logic circuit; Step S103', an enable register of the logic circuit saves the enable valid signal as a necessary condition for the synchronous rectification switch tube to be turned on, and goes to step S2; meanwhile, the sampling current is continuously detected in real time until the relative maximum current in the current period is detected, the latest relative maximum current value is refreshed, and the step S101' is returned to be operated in a loop.

4. A synchronous rectification turn-on control chip, characterized in that, The internal integrated relative maximum voltage identification circuit, the synchronous detection comparison circuit and the logic circuit; the input end of the relative maximum voltage identification circuit and the input end of the synchronous detection comparison circuit are connected with the source detection input pin VS and the drain detection input pin VD of the synchronous rectification conduction control chip respectively, to detect the drain-source voltage of the synchronous rectification switch tube when it is off; The output end of the relative maximum voltage identification circuit is connected with the first input end of the logic circuit; the two output ends of the synchronous detection comparison circuit are connected with the second input end and the third input end of the logic circuit respectively; the output end of the logic circuit is connected with the output pin of the synchronous rectification conduction control chip; When the drain-source voltage of the synchronous rectification switch tube appears a relative maximum value, the relative maximum voltage identification circuit sends an enable effective signal to the logic circuit and saves it; when the drain-source voltage of the synchronous rectification switch tube is less than the turn-on threshold value, the synchronous detection comparison circuit outputs a first effective signal to the logic circuit; when the logic circuit receives the enable effective signal and the first effective signal, a high level is output to the output pin of the control chip to control the synchronous rectification switch tube to be turned on; when the drain-source voltage of the synchronous rectification switch tube is greater than the off threshold value, the synchronous detection comparison circuit outputs a second effective signal to the logic circuit; when the logic circuit receives the second effective signal, a low level is output to the output pin of the synchronous rectification conduction control chip to control the synchronous rectification switch tube to be turned off.

5. The synchronous rectification turn-on control chip of claim 4, wherein, The relative maximum voltage identification circuit comprises a sampling switch S1, a sampling capacitor C1, a first comparator CMP1, a monostable trigger MTRG and a micro-current source I1; one end of the sampling switch S1 and the positive input end of the first comparator CMP1 are connected with the drain detection input pin VD of the synchronous rectification conduction control chip respectively; the negative input end of the first comparator CMP1 is connected with the positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1 respectively; the negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded; the output end of the first comparator CMP1 is connected with the input end of the monostable trigger MTRG, the output end of the monostable trigger MTRG is connected with the control end of the sampling switch S1 and the first input end of the logic circuit respectively; the ground of the relative maximum voltage identification circuit is connected with the source detection input pin VS of the synchronous rectification conduction control chip.

6. The synchronous rectification turn-on control chip of claim 4, wherein, The relative maximum voltage identification circuit comprises a sampling resistor R S , a first N-channel MOS tube N1, a second N-channel MOS tube N2, a third N-channel MOS tube N3, a first P-channel MOS tube P1, a second P-channel MOS tube P2, a sampling switch S1, a sampling capacitor C1, a comparator CMP1, a monostable trigger MTRG and a micro-current source I1; one end of the sampling resistor R S is connected to a drain detection input pin VD, and the other end of the sampling resistor R S is respectively connected to the drain and the gate of the first N-channel MOS tube N1, the gate of the second N-channel MOS tube N2 and one end of the sampling switch S1; the source of the first N-channel MOS tube N1 and the source of the second N-channel MOS tube N2 are grounded; the source of the first P-channel MOS tube P1 is connected to the source of the second P-channel MOS tube P2; the gate and the drain of the first P-channel MOS tube P1 are connected and respectively connected to the gate of the second P-channel MOS tube P2 and the drain of the second N-channel MOS tube N2; the drain of the second P-channel MOS tube P2 and the drain of the third N-channel MOS tube N3 are respectively connected to the input end of the monostable trigger; the output end of the monostable trigger is respectively connected to the control end of the sampling switch S1 and the first input end of the logic circuit; the gate of the third N-channel MOS tube N3 is respectively connected to the positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1; the source of the third N-channel MOS tube N3, the negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded; and the ground of the relative maximum voltage identification circuit is connected to the source detection input pin VS of the synchronous rectification conduction control chip.

7. The synchronous rectification turn-on control chip of claim 4, wherein, The relative maximum voltage identification circuit comprises a sampling resistor R S , a first N-channel MOS tube N1, a second N-channel MOS tube N2, a third N-channel MOS tube N3, a first P-channel MOS tube P1, a second P-channel MOS tube P2, a sampling switch S1, a sampling capacitor C1, a comparator CMP1, a monostable trigger MTRG and a micro-current source I1; one end of the sampling resistor R S is connected to a drain detection input pin VD, and the other end of the sampling resistor R S is respectively connected to the drain and the gate of the first N-channel MOS tube N1, the gate of the second N-channel MOS tube N2 and one end of the sampling switch S1; the source of the first N-channel MOS tube N1 and the source of the second N-channel MOS tube N2 are grounded; the source of the first P-channel MOS tube P1 is connected to the source of the second P-channel MOS tube P2; the gate and the drain of the first P-channel MOS tube P1 are connected and respectively connected to the gate of the second P-channel MOS tube P2 and the drain of the third N-channel MOS tube N3; the drain of the second P-channel MOS tube P2 and the drain of the second N-channel MOS tube N2 are respectively connected to the input end of the monostable trigger; the output end of the monostable trigger is respectively connected to the control end of the sampling switch S1 and the first input end of the logic circuit; the gate of the third N-channel MOS tube N3 is respectively connected to the positive end of the micro-current source I1, one end of the sampling capacitor C1 and the other end of the sampling switch S1; the source of the third N-channel MOS tube N3, the negative end of the micro-current source I1 and the other end of the sampling capacitor C1 are grounded; and the ground of the relative maximum voltage identification circuit is connected to the source detection input pin VS of the synchronous rectification conduction control chip.

8. The synchronous rectification turn-on control chip of claim 4, wherein, The synchronous detection comparison circuit comprises a second comparator CMP2 and a third comparator CMP3, the negative input end of the second comparator CMP2 and the positive input end of the third comparator CMP3 are connected with the drain detection input pin VD of the synchronous rectification conduction control chip respectively; the positive input end of the second comparator CMP2 inputs the turn-on threshold voltage of the synchronous rectification, and the negative input end of the third comparator CMP3 inputs the off threshold voltage of the synchronous rectification; the output end of the second comparator CMP2 is connected with the second input end of the logic circuit, and the output end of the third comparator CMP3 is connected with the third input end of the logic circuit; the ground of the synchronous detection comparison circuit is connected with the source detection input pin VS of the synchronous rectification conduction control chip.

9. The synchronous rectification turn-on control chip of claim 4, wherein, The logic circuit comprises an enable register RS1, an AND gate AND1 and a synchronous rectification output control flip-flop RS2; an S input end of the enable register RS1 is used as a first input end of the logic circuit, an R input end of the enable register RS1 and a first input end of the AND gate AND1 are connected and used as a second input end of the logic circuit, and an R input end of the synchronous rectification output control flip-flop RS2 is used as a third input end of the logic circuit; an output end Q of the enable register RS1 is connected to a second input end of the AND gate AND1, an output end of the AND gate AND1 is connected to an S input end of the synchronous rectification output control flip-flop RS2, and an output end Q of the synchronous rectification output control flip-flop RS2 is connected to an output pin VG of the synchronous rectification conduction control chip.

10. The synchronous rectification turn-on control chip according to any one of claims 4 to 9, characterized in that, The synchronous rectification switch tube is integrated in the synchronous rectification conduction control chip or placed outside the synchronous rectification conduction control chip.

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