Substrate processing method and substrate processing device

Abstract

A substrate processing method according to the present disclosure comprises: a step for forming a zirconium silicide layer forming the bottom wall of a recess by supplying a first processing gas containing zirconium to a substrate provided with the recess in which a semiconductor layer containing silicon is exposed on the bottom surface and the side wall is formed by an insulator film; a step for removing zirconium remaining on the side wall of the recess by supplying a second processing gas to the substrate; and a film formation step for forming a conductive film in the recess by supplying a film formation gas to the substrate on which the removal step has been performed.

Description

Substrate processing method and substrate processing apparatus

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus.

[0002] In the manufacturing process of a semiconductor device, recesses constituting via holes, trenches, etc. are formed in an insulator layer formed on a semiconductor wafer (hereinafter referred to as "wafer"), which serves as a substrate. A process is then performed to fill the recesses with a conductive film, which is an interconnect material, so as to establish electrical continuity with the silicon-containing semiconductor layer exposed at the bottom of the recesses. Prior to this filling, the silicon at the bottom of the recesses may be converted into a metal silicide, thereby reducing the resistance (contact resistance) at the contact between the conductive film and the semiconductor layer.

[0003] Patent Document 1 discloses a manufacturing process for a semiconductor device in which a zirconium film is formed on a well formed on a Si substrate, and then BF2 and As are injected into the well through the zirconium film to form a source / drain junction. Subsequently, a titanium film is stacked on the zirconium film and heat treatment is performed, thereby forming titanium silicide and zirconium silicide at the junction, and defects due to ion implantation are believed to remain in the zirconium silicide of these metal silicides.

[0004] Japanese Patent Application Publication No. 9-171969

[0005] The present disclosure provides a technique capable of reducing the contact resistance between a conductive film formed on a semiconductor layer containing silicon in a recess in a substrate and the semiconductor layer.

[0006] The substrate processing method of the present disclosure includes the steps of: supplying a first process gas containing zirconium to a substrate having a recess in which a semiconductor layer containing silicon is exposed at the bottom surface and in which a sidewall is formed by an insulating film, thereby forming a zirconium silicide layer that forms the bottom wall of the recess; supplying a second process gas to the substrate to remove zirconium remaining on the sidewall of the recess; and supplying a film formation gas to the substrate after the removal step to form a conductive film in the recess.

[0007] The present disclosure can reduce the contact resistance between a conductive film formed on a semiconductor layer containing silicon in a recess in a substrate and the semiconductor layer.

[0008] 1 is a longitudinal sectional side view of a wafer before metal silicide is formed; FIG. 2 is a longitudinal sectional side view of a wafer on which a ZrSi layer is formed; FIG. 3 is a longitudinal sectional side view of a wafer on which a Ti film is formed; FIG. 4 is a longitudinal sectional side view of a wafer from which the Ti film has been removed; FIG. 5 is a longitudinal sectional side view of a wafer from which a Ru film has been embedded; FIG. 6 is a longitudinal sectional side view of a wafer from which CMP has been performed; FIG. 7 is a plan view of a substrate processing apparatus; FIG. 8 is a longitudinal sectional side view of a wafer before processing by the substrate processing apparatus; FIG. 9 is a longitudinal sectional side view of a processing module provided in the substrate processing apparatus; FIG. 10 is a plan view of a first modified example of a substrate processing apparatus; FIG. 11 is a plan view of a second modified example of a substrate processing apparatus; FIG. 12 is a plan view of a third modified example of a substrate processing apparatus; FIG. 13 is a graph showing the results of an evaluation test; FIG. 14 is a graph showing the results of an evaluation test;

[0009] An example of a substrate processing method according to an embodiment of the present disclosure will be described with reference to the longitudinal side views of wafer A in Figures 1 to 6. Figures 1 to 6 also show processing steps that are sequentially performed on wafer A when forming an NMOS field effect transistor.

[0010] The wafer A in FIG. 1 will be described. The wafer A has a silicon (Si) layer 11 on which SiO ２ The SiO layer 12 is laminated. ２ The layer 12 has holes formed in its thickness direction. ２ The bottom end of the hole formed in the layer 12 reaches the Si layer 11. ２ An SiN film (silicon nitride) 13 is formed so as to cover the side surface of the layer 12. The Si layer 11 contains an appropriate amount of dopant, such as phosphorus, to form an NMOS.

[0011] By providing each layer as described above, a recess 14 forming a trench or hole is formed in the wafer A, and the sidewall of this recess 14 is made of SiO ２The recess 14 is made up of an insulating layer consisting of a layer 12 and a SiN film 13. The bottom wall of the recess 14 is made of a Si layer 11, i.e., a semiconductor layer containing silicon. The Si layer 11 is exposed at the bottom surface of the recess 14.

[0012] To give an overview of the processing of wafer A in this embodiment, a Ru (ruthenium) film 15 is embedded in the recess 14 as a conductive film that forms a wiring metal with a relatively low resistance. Prior to this embedding, a gas treatment is performed to reduce the contact resistance between the Ru film 15 and the Si layer 11, thereby forming a ZrSi (zirconium silicide) surface layer on the bottom wall of the recess 14. This ZrSi is formed by a treatment using a plasmatized gas.

[0013] When forming a metal silicide as a contact portion between a semiconductor layer and a conductive film, it is also known to use a silicide of a metal other than Zr, such as TiSi (titanium silicide). In this embodiment, ZrSi is formed as the metal silicide forming the above-mentioned connection portion because, compared to forming a silicide of another metal such as TiSi, forming ZrSi reduces the Schottky barrier, which is an energy barrier formed between the metal silicide and the Si layer 11. It is known that the smaller this Schottky barrier, the smaller the contact resistance, and in an NMOS, electrons flow more easily from the Si layer 11 to the metal silicide.

[0014] However, when forming ZrSi in this manner, Zr (zirconium) contained in the gas for forming ZrSi remains on the sidewalls of the recesses 14 (i.e., the SiN film 13). When filling the recesses 14 with a conductive film (Ru film 15 in this embodiment), the larger the volume of the filled conductive film, the more the contact resistance can be reduced. Therefore, in this embodiment, the Zr remaining on the sidewalls of the recesses 14 is removed so as to increase the volume of the conductive film. If the ZrSi is etched more than necessary when removing this Zr, there is a risk that the contact resistance will not be sufficiently reduced. In this embodiment, wafer A is processed so as to suppress etching of ZrSi and prevent a decrease in the volume of the Ru film 15 filled in the recesses 14.

[0015] 1 to 6, the processes shown in FIGS. 1 to 5 are performed by supplying various gases to wafer A, which is placed on stage 66 in processing vessel 61, which is under a vacuum atmosphere, and heated to a predetermined processing temperature. As will be described in detail later in the description of the substrate processing apparatus, wafer A is processed by being transferred sequentially between multiple processing vessels 61.

[0016] First, ZrCl was applied to the wafer A described in FIG. ４ (zirconium chloride) gas, Ar gas, H ２ Plasma CVD is performed by supplying gas and applying high-frequency power. As a result, as described above, the surface layer of the Si layer 11 exposed at the bottom of the recess 14 reacts with the plasma, and the bottom wall of the recess 14 becomes a ZrSi layer 21. As this ZrSi layer 21 is formed, Zr (zirconium) is deposited on the outside and side walls of the recess 14 ( FIG. 2 , step S1). In the figure, this deposited Zr is shown as a Zr film 22. In reality, the deposited Zr may be scattered throughout the surface of the wafer A and not form a film, but for convenience, the description will be given assuming that it is a film.

[0017] The application of high frequency power was stopped and ZrCl ４ Gas, Ar gas, H ２After the supply of gas to wafer A was stopped, wafer A was ４ The reaction shown in the following formula 1 proceeds, and the Zr film 22 is converted into the gas ZrCl ２ The ZrCl ２ TiCl produced together with ２ is also a gas, and ZrCl ２ The Zr film 22 is removed from the wafer A together with the TiCl ４ Solid Ti is generated from the gas, and this Ti adheres to the outside of the recess 14 and to the sidewall of the recess 14 (FIG. 3, step S2). In the figure, this adhered Ti is shown as a Ti film 23, but like Zr, this Ti may actually be scattered and not form a film, but for convenience of illustration, it is shown as a film. As will be shown in the evaluation test described later, this TiCl ４ By supplying the gas, the Zr film 22 is etched as described above, but etching of the ZrSi layer 21 is suppressed. ４ → TiCl ２ + ZrCl ２

[0018] TiCl on wafer A ４ After the gas supply was stopped, BCl ３ The supply of boron trichloride gas and hydrogen fluoride gas is repeated alternately. ３ The gas reacts selectively with the Ti film 23 out of the ZrSi layer 21 and the Ti film 23, and Ti constituting the Ti film 23 is converted to TiCl ４ is vaporized and removed from wafer A, while BCl ３ B, which is a component of the gas, reacts with oxygen contained on the surface of wafer A, and B ２ O ３ (boron oxide) and adheres to various parts of the surface of the wafer A, including the sidewalls of the recesses 14, instead of Ti. ２ O ３ reacts with the HF gas to become fluoride, which is vaporized and removed from the surface of wafer A (FIG. 4, step S3).

[0019] BCl to wafer A ３ The supply of the gas and HF gas is stopped. By performing the processes of steps S2 and S3, Zr, Ti, and B contained in the gases used in steps S1 to S3 are removed from the sidewall of the recess 14, and Ti and B are also removed from the bottom wall of the recess 14. Ru3(CO) 12 Gas (dodecacarbonyltriruthenium gas) is supplied to perform CVD, and the Ru film 15 is buried in the recess 14 and laminated on the ZrSi layer 21 (FIG. 5, step S4).

[0020] As described above, the recess 14 is filled with the elements removed from the sidewalls and bottom wall thereof, so that the volume of the Ru film 15 in the recess 14 is relatively large. 12 After the supply of gas to the wafer A is stopped, the insulating layer (SiO ２ The portion formed on the insulating layer (layer 12 and SiN film 13) and the upper end of the insulating layer are removed as unnecessary portions (FIG. 6, step S5).

[0021] According to the above process, when the Ru film 15 is embedded in the recess 14 whose bottom wall is formed by the Si layer 11, the ZrSi layer 21 that forms the contact portion between the Si layer 11 and the Ru film 15 is formed, thereby making it possible to relatively lower the Schottky barrier and relatively increase the volume of the Ru film 15 occupying the recess 14. Therefore, the contact resistance between the Si layer 11 and the Ru film 15 can be reduced. Furthermore, when the Zr film 22 is removed to increase the volume of the Ru film 15 occupying the recess 14, etching of the ZrSi layer 21 is suppressed, thereby ensuring a sufficient thickness of the ZrSi layer 21 with high reliability. Therefore, the contact resistance can be more reliably reduced.

[0022] <Configuration of Substrate Processing Apparatus> Next, a substrate processing apparatus 3, which is an embodiment of a substrate processing apparatus capable of performing the processes of steps S1 to S4 among the above-described steps S1 to S5, will be described with reference to the plan view of Fig. 7. Also, Fig. 8 shows a wafer A before processing by this substrate processing apparatus 3. In this wafer A, the Si layer 11 on the bottom surface of the recess 14 is naturally oxidized to form SiO ２ In the substrate processing apparatus 3, as a pre-processing step S1, the SiO ２ The film 19 is also removed.

[0023] The substrate processing apparatus 3 includes a loader module 31, a load lock module 35, a first vacuum transfer module 41, a second vacuum transfer module 42, a connection module 43, a first processing module 51, a second processing module 52, a third processing module 53, a fourth processing module 54, and a fifth processing module 55. In the following description, the first vacuum transfer module 41 and the second vacuum transfer module 42 may be collectively referred to as the vacuum transfer modules 41 and 42. The first to fifth processing modules 51 to 55 may be simply referred to as the processing modules 51 to 55.

[0024] The loader module 31, the load lock module 35, the first vacuum transfer module 41, the connection module 43, and the second vacuum transfer module 42 are arranged in a straight line in the horizontal direction in this order. In the following description of the substrate processing apparatus 3, the side where the loader module 31 is located will be referred to as the front side, and the side where the second vacuum transfer module 42 is located will be referred to as the rear side.

[0025] The loader module 31 includes a housing whose interior is at atmospheric pressure, a transfer mechanism 32 for wafers A provided within the housing, and load ports 33. In this example, four load ports 33 are provided side by side on the front side of the housing. A transfer container 34 for storing wafers A, known as a FOUP (Front Opening Unified Pod), is placed on each load port 33. The transfer mechanism 32 is formed, for example, by an articulated arm that can move left and right, and is capable of transferring wafers A between the transfer container 34 on each load port 33 and each load lock module 35.

[0026] In this example, three load lock modules 35 are provided side by side. Each load lock module 35 has a housing, which is connected to the loader module 31 and the first vacuum transfer module 41 via gate valves G provided at the front and rear sides of the housing. When the gate valves G at the front and rear sides of the housing are closed, the pressure inside the housing can be freely changed between atmospheric pressure and vacuum pressure. A stage (not shown) on which the wafer A is placed is provided inside the housing, and the stage is configured to be able to transfer the wafer A to and from the transfer mechanism 32 and a transfer mechanism 44 (described later) that access the load lock module 35.

[0027] The first vacuum transfer module 41 and the second vacuum transfer module 42 are configured similarly to each other and include housings 41A and 42A, respectively. An exhaust port 45 is opened in each of the housings 41A and 42A, and one end of an exhaust pipe is connected to the exhaust port 45. The other end of the exhaust pipe is connected to an exhaust mechanism 46 composed of a turbomolecular pump, a valve, etc. The inside of the housing 41A and the inside of the housing 42A are each maintained in a vacuum atmosphere by exhausting air from the exhaust port 45 by the exhaust mechanism 46.

[0028] In this example, two connection modules 43 are provided side by side. The connection module 43 includes a housing 43A, which is connected to the housings 41A and 42A of the vacuum transfer modules 41 and 42. The exhaust mechanism 46 exhausts air, creating a vacuum atmosphere inside the housing 43A of the connection module 43 at the same pressure as inside the housings 41A and 42A. A wafer A is placed inside the housing 43A, and a stage (not shown) is provided therein that is configured to be able to transfer the wafer A between the housing 43A and the transfer mechanism 44, which will be described later. Hereinafter, the interiors of the housings 41A, 42A, and 43A, which are created into a vacuum atmosphere by the exhaust mechanism 46, will be collectively referred to as the vacuum transfer path 40 for the wafer A.

[0029] The housings 41A and 42A are filled with an inert gas, such as N ２ An inert gas supply mechanism 47 that supplies (nitrogen) gas and Ar gas is connected. The inert gas supply mechanism 47 includes a reservoir for the inert gas and a valve for switching on and off the supply of the inert gas from the reservoir to the inside of the housing 41A and the inside of the housing 42A. ２ The pressure in the vacuum transfer path 40 is adjusted to a desired vacuum pressure by supplying gas or Ar gas and exhausting by the exhaust mechanism 46. When the inert gas supply mechanism 47 does not supply inert gas, the exhaust mechanism 46 adjusts the vacuum transfer path 40 to a pressure of, for example, 1×10 -７ Torr (1.333×10 －５ The air can be evacuated to a first pressure less than 100 Pa.

[0030] A first processing module 51 and a third processing module 53 are connected via gate valves G1 to one of the left and right sides of the housing 41A of the first vacuum transfer module 41, and these processing modules 51, 53 are arranged side by side in the front and rear. A second processing module 52 and a fourth processing module 54 are connected via gate valves G1 to the other of the left and right sides of the housing 41A, and these processing modules 52, 54 are arranged side by side in the front and rear.

[0031] Two fifth process modules 55 are connected to each of the left and right sides of the housing 42A of the second vacuum transfer module 42 via gate valves G1. Two fifth process modules 55 are arranged front to back on each of the left and right sides of the housing 42A. The process modules 51 to 55 can process wafers A in parallel with each other. Because the process by the fifth process module 55 takes longer than the process by the other process modules 51 to 54, the fifth process module 55 is provided in the largest number of the process modules 51 to 55, thereby improving the throughput of the substrate processing apparatus 3.

[0032] A transfer mechanism 44 is provided within each of the housings 41A and 42A, and each transfer mechanism 44 is configured, for example, by an articulated arm that can move back and forth. The transfer mechanism 44 within the housing 41A transfers wafers A between the load lock module 35, the connection module 43, and each processing module connected to the housing 41A via a gate valve G1. The transfer mechanism 44 within the housing 42A transfers wafers A between the connection module 43 and each processing module connected to the housing 42A via a gate valve G1. The gate valves G and G1 are closed except when necessary to transfer wafers A between the modules, separating the atmospheres between the modules. Each stage of the load lock module 35 and the connection module 43 is provided with, for example, pins that can be protruded and retracted from the stage to enable transfer of wafers A between the transfer mechanisms.

[0033] The first processing module 51 and the second processing module 52 are made of SiO ２ These are processing modules for pre-processing to remove the film 19. The third processing module 53 performs steps S1 and S2 described with reference to Figures 1 to 3, the fourth processing module 54 performs step S3 described with reference to Figure 4, and the fifth processing module 55 performs step S4 described with reference to Figure 5.

[0034] The substrate processing apparatus 3 includes a control unit 30, which is a computer, and the control unit 30 includes a program. The program includes instructions (steps) for processing and transporting wafers A in each of the processing modules 51 to 55. The program is stored on a storage medium, such as a compact disc, hard disk, or DVD, and is installed in the control unit 30. The control unit 30 outputs control signals to each component of the substrate processing apparatus 3 using the program to control the operation of each component. Specifically, the control unit 30 controls the operation of the processing modules 51 to 55, the opening and closing of gate valves G and G1, the operation of transport mechanisms 32 and 44, the operation of the exhaust mechanism 46, the operation of the inert gas supply mechanism 47, and switching of the pressure within the load lock module 35. The control of the operation of the processing modules 51 to 55 includes controlling the temperature of wafer A on stage 66 by supplying power to heater 67, which will be described later, switching between supplying and stopping the supply of each gas into the processing chamber 61 by opening and closing valve V, and switching on and off high-frequency power supplies 69 and 75.

[0035] <Configuration of Third Processing Module 53> The third processing module 53, which performs the formation of the ZrSi layer 21 and the removal of the Zr film 22 (formation of the Ti film 23) in steps S1 and S2, will be described with reference to FIG. 9 , a vertical cross-sectional view. The third processing module 53 is a capacitively coupled plasma processing apparatus equipped with a metal processing vessel 61, which is grounded. A transfer port 62 for wafer A is provided in the sidewall of the processing vessel 61, and the transfer port 62 is opened and closed by the gate valve G1. A heater 63 for adjusting the temperature inside the processing vessel 61 is embedded in a shower head 71 (described below) that forms the sidewall and ceiling wall of the processing vessel 61. One end of an exhaust path 64 opens at the bottom of the processing vessel 61, and the other end of the exhaust path 64 is connected to an exhaust mechanism 65 including a valve and a vacuum pump. The exhaust mechanism 65 evacuates the processing vessel 61 to a vacuum atmosphere at a desired pressure.

[0036] A stage 66 is provided within the processing vessel 61, and the wafer A is placed on the stage 66 so that it is horizontal. Above the stage 66 is a processing space 70 to which gas is supplied from a shower head 71, which will be described later. A heater 67 is embedded in the stage 66 as a heating mechanism, and the heater 67 heats the placed wafer A to a preset processing temperature. The stage 66 also functions as a lower electrode, and is connected to a high-frequency power supply 69 via a matching box 68, which supplies high-frequency power for bias application (for attracting ions into the plasma). Although not shown, three pins are provided on the top surface of the stage 66 that can be raised and lowered by an elevation mechanism. The wafer A can be transferred between the top surface of the stage 66 and the transfer mechanism 44 via these pins.

[0037] A shower head 71 is provided on the ceiling wall of the processing vessel 61 and is attached to the processing vessel 61 via an insulating member 79. The shower head 71 includes a gas diffusion space 72 and a number of outlets 73 that open downward and discharge gas supplied from the diffusion space 72 toward the processing space 70. The shower head 71 is configured as an upper electrode, and is connected to a high-frequency power supply 75 via a matching box 74, which supplies high-frequency power for plasma generation.

[0038] High frequency power of a predetermined frequency is supplied from the high frequency power supply 75 to the shower head 71, thereby converting the gas supplied from the shower head 71 to the processing space 70 into plasma. While this high frequency power is being supplied from the high frequency power supply 75, high frequency power is supplied from the high frequency power supply 69 to the stage 66, and ions that constitute the plasma are drawn toward the stage 66. The frequency of the high frequency power supplied from the high frequency power supply 75 to the shower head 71 is higher than the frequency of the high frequency power supplied from the high frequency power supply 69 to the stage 66.

[0039] The downstream end of a gas flow path 76 is connected to the diffusion space 72 of the shower head 71. The upstream side of the gas flow path 76 branches to form gas flow paths 81 to 84. The upstream end of the gas flow path 81 is connected to a ZrCl ４The upstream end of the gas flow path 82 is connected to the gas supply source 81A. ４ The upstream end of the gas flow path 83 is connected to a gas supply source 82A, the upstream end of the gas flow path 83 is connected to an Ar (argon) gas supply source 83A, and the upstream end of the gas flow path 84 is connected to a H ２ Each of the gas flow paths 81 to 84 is connected to a (hydrogen) gas supply source 84A. A flow rate adjuster M, which is composed of a valve V, a mass flow controller, etc., is disposed in each of the gas flow paths 81 to 84 in order toward the upstream side. Opening and closing the valve V switches between supplying and stopping each gas from each of the gas supply sources 81A to 84A to the processing space 70 via the shower head 71. The flow rate adjuster M adjusts the flow rate of each gas supplied to the processing space 70 to a preset amount.

[0040] The Ar gas is used to ４ It is a carrier gas or dilution gas for the gas, and TiCl ４ It is a diluent gas for the gas. ２ For gas, ZrCl ４ As described above, in step S1, for example, ZrCl ４ In addition to gas, Ar gas, H ２ Gas is also supplied to the processing space 70, and plasma CVD is performed to process the wafer A as described with reference to FIG. ４ In addition to the gas, Ar gas is also supplied to the processing space 70, and the wafer A is processed as described with reference to FIG.

[0041] <Configuration of Other Processing Modules> Each processing module other than the third processing module 53 has a configuration generally similar to that of the third processing module 53, and can process the wafer A by heating the wafer A placed on the stage 66 with a heater 67 while supplying gas from a shower head 71. However, with regard to the gas supply source, instead of the supply sources that supply each gas described for the third processing module 53, supply sources that supply gas corresponding to the processing performed in each processing module are provided. Also, some processing modules do not perform plasma processing on the wafer A, and therefore differ from the third processing module 53 in that they do not have high-frequency power supplies 75, 69.

[0042] The first processing module 51 is a module that performs a process called COR (Chemical Oxide Removal), and includes a hydrogen fluoride (HF) gas supply source, an ammonia (NH ３ ) supply sources, and these gases are supplied to wafer A to form SiO ２ The film 19 is transformed into a compound having a relatively low sublimation temperature. The second processing module 52 is a module called PHT (Post Heat Treatment) for removing the transformed compound. This second processing module 52 is, for example, a N ２ The inert gas is supplied to the processing space 70 to create an inert gas atmosphere, and the wafer A is heated to remove the altered SiO ２ The film 19 is sublimated and removed from the wafer A. Since no plasma is used to process the wafer A, the first processing module 51 and the second processing module 52 do not include high frequency power supplies 69 and 75 .

[0043] The fourth processing module 54 is a BCl ３ gas supply source, HF gas supply source, H ２ The fourth process module is equipped with a gas supply. ２ The treatment can be carried out using gas, but this H ２ The fourth processing module 54 is equipped with high-frequency power supplies 69 and 75, similar to the third processing module 53, and is configured to generate H ２ When processing with gas, ２ The gas can be turned into plasma to process wafer A. The fifth processing module 55 is a Ru3(CO) 12 Gas Source and Ru(CO) 12 A supply source of CO (carbon monoxide) gas, which serves as a carrier gas for the gas, is provided, but high frequency power sources 69 and 75 are not provided.

[0044] ZrCl ４ The gas is a first processing gas, and is TiCl containing Ti as a metal (second metal) other than zirconium. ４The gas is a second process gas, BCl ３ The Ru(CO) gas and HF gas are the third process gas. 12 The gas is a deposition gas for a conductive film. ４ Gas supply source 81A and ZrCl ４ The gas flow path 81, which is a gas flow path, and the valve V and flow rate adjuster M provided in the gas flow path 81 constitute a first process gas supply unit. ４ Gas supply source 82A and TiCl ４ The gas flow path 82, which is a gas flow path, and the valve V and flow rate adjuster M provided in the gas flow path 82, constitute a second process gas supply unit.

[0045] As described above, the fourth process module 54 and the fifth process module 55 have substantially the same configuration as the third process module 53, except for the type of gas supplied to the wafer A. Therefore, the fourth process module 54 is configured to supply BCl ３ a gas supply source; and ３ a gas flow path for the gas; ３ The fifth process module 55 includes a third process gas supply unit, which includes a valve V and a flow rate regulator M provided in a gas flow path of the HF gas, an HF gas supply source, a gas flow path of the HF gas, and a valve V and a flow rate regulator M provided in the gas flow path of the HF gas. 12 A gas source and Ru(CO) 12 A gas flow path for the gas, and the Ru3(CO) 12 The deposition gas supply unit includes a valve V and a flow rate adjuster M provided in a gas flow path.

[0046] As described above, the substrate processing apparatus 3 is configured such that a processing module provided with a first processing gas supply unit and a second processing gas supply unit, a processing module provided with a third processing gas supply unit, and a processing module provided with a film forming gas supply unit are individually provided and arranged at different positions. The wafer A is transported sequentially between the processing modules thus arranged at different positions, and is heated to a processing temperature set in each processing module and subjected to gas processing, thereby performing the above steps S1 to S4.

[0047] As described above, the substrate processing apparatus 3 is configured such that separate processing modules are provided depending on the processing temperatures of wafer A in steps S1 to S4. Specifically, since the processing temperatures of wafer A are the same in the consecutive steps S1 and S2, these steps S1 and S2 are performed in the same processing module. However, since the processing temperatures of wafer A are different in the consecutive steps S2 and S3, the processing modules that perform these steps are separate and located at different positions. Since the processing temperatures of wafer A are also different in the consecutive steps S3 and S4, the processing modules that perform these steps are also separate and located at different positions.

[0048] <Operation of the Substrate Processing Apparatus> The procedure for processing wafer A by the substrate processing apparatus 3 will be described. -７ The pressure is set to a preset first pressure lower than Torr. The reason for setting the vacuum at such a high level is to sufficiently remove oxygen molecules and water molecules from the vacuum transfer path 40, and to prevent an increase in contact resistance due to oxidation of the ZrSi layer 21 by the oxygen molecules and water molecules during transfer of the wafer A from the formation of the ZrSi layer 21 until the Ru film 15 is embedded in the recesses 14. After the pressure in the vacuum transfer path 40 reaches the first pressure, N is supplied to the vacuum transfer path 40 by the inert gas supply mechanism 47. ２An inert gas such as Ar gas is supplied to increase the pressure in the vacuum transfer path 40. Then, the supply of this inert gas and the exhaust by the exhaust mechanism 46 are performed in parallel, so that the pressure in the vacuum transfer path 40 is maintained at a preset second pressure, for example, 800 mTorr (106.6 Pa).

[0049] While the pressure of the vacuum transfer path 40 is adjusted in this manner, the insides of the processing vessels 61 of the processing modules 51 to 55 are also evacuated by the exhaust mechanism 65, and are maintained at a preset pressure that is lower than the second pressure of the vacuum transfer path 40. By creating a pressure difference between the vacuum transfer path 40 and each processing vessel 61 in this manner, gas is prevented from flowing from each processing vessel 61 into the vacuum transfer path 40 when the gate valves G1 for transporting the wafer A between the vacuum transfer path 40 and each processing module 51 to 55 are opened.

[0050] Then, the SiO shown in FIG. ２ The wafer A with the film 19 formed thereon is transferred from the transfer vessel 34 and transferred in the order of the loader module 31, load lock module 35, and first vacuum transfer module 41. That is, the wafer A is transferred to the vacuum transfer path 40 in which a differential pressure is created within each processing vessel 61 as described above. The wafer A is then transferred into the first processing module 51 and placed on the stage 66 of the first processing module 51, where it is heated to a predetermined processing temperature. In this heated state, HF gas and NH ３ Gas is supplied to SiO ２ The film 19 is altered.

[0051] Next, the wafer A is transferred to the second processing module 52 via the first vacuum transfer module 41, and is placed on the stage 66 and heated to a predetermined processing temperature, while an inert gas is supplied to the processing space 70 of the processing module 52. By being heated in such an inert gas atmosphere, SiO ２ The altered material of the film 19 is sublimated and removed, and the Si layer 11 is exposed at the bottom of the recess 14 as described with reference to FIG.

[0052] Thereafter, the wafer A is transferred to the third processing module 53 via the first vacuum transfer module 41, and is placed on the stage 66 of the processing module 53, where it is heated to a predetermined processing temperature, for example, 450° C. In this heated state, ZrCl ４ Gas, H ２ Gas and Ar gas are supplied, and plasma CVD is performed. That is, the above-mentioned step S1 is performed, and the ZrSi layer 21 and the Zr film 22 are formed as described with reference to FIG.

[0053] After the plasma generation is stopped, TiCl ４ 3, the Zr film 22 is removed and the Ti film 23 is formed. During step S2, the wafer A is heated to the processing temperature of, for example, 450° C., the same as during step S1.

[0054] Subsequently, the wafer A is transferred to the fourth processing module 54 via the first vacuum transfer module 41, and is placed on a stage 66 in the processing module 54, where it is heated to a predetermined processing temperature, for example, 250° C. In this heated state, BCl ３ The BCl gas is supplied for a predetermined time, followed by the HF gas for a predetermined time. ３ The supply of BCl gas and the supply of HF gas constitute one cycle, and this cycle is repeated. ３ The SiO 2 gas and the HF gas are alternately and repeatedly supplied to the wafer A. That is, the above-described step S3 is performed, and the Ti film 23 is removed as shown in FIG.

[0055] Thereafter, wafer A is transferred in the order of first vacuum transfer module 41 → connection module 43 → second vacuum transfer module 42 → fifth processing module 55, and is placed on stage 66 in fifth processing module 55, where it is heated to a predetermined processing temperature, for example, 150° C. In this heated state, Ru(CO)12 5, the Ru film 15 is embedded in the recess 14. Thereafter, the wafer A is transferred in the order of the second vacuum transfer module 42, the connection module 43, the first vacuum transfer module 41, the load lock module 35, and the loader module 31, and then returned to the transfer container 34.

[0056] In the substrate processing apparatus 3 described above, the processing modules 51 to 54 are connected to the vacuum transfer path 40, and the wafer A is transferred through each of the processing modules 51 to 54 by a transfer mechanism 44 provided on the vacuum transfer path 40. Therefore, a vacuum atmosphere is maintained around the wafer A from the formation of the ZrSi layer 21 to the formation of the Ru film 15 on the ZrSi layer 21. Therefore, oxidation of the ZrSi layer 21 is suppressed, and an increase in contact resistance due to this oxidation can be prevented.

[0057] In addition, the vacuum transport path 40 is temporarily set to 1×10 -７ After the vacuum transfer path 40 is depressurized to a first pressure lower than Torr, the wafer A is transferred through the vacuum transfer path 40. In the process of depressurizing the vacuum transfer path 40 to the first pressure, most of the water and oxygen in the vacuum transfer path 40 are removed, so the concentrations of water and oxygen in the vacuum transfer path 40 during transfer of the wafer A are extremely low. Therefore, oxidation of the ZrSi layer 21 by the water and oxygen is suppressed, and an increase in contact resistance is more reliably prevented.

[0058] <Modifications of Substrate Processing Apparatus> Steps S1 and S2 may be performed at different processing temperatures. In this case, steps S1 and S2 are preferably performed in different processing modules to prevent a decrease in the processing efficiency of wafer A due to the need to change the temperature of each section in the processing module each time wafer A is loaded. Figure 10 shows a substrate processing apparatus 3A, which is a first modification of the substrate processing apparatus 3. In this substrate processing apparatus 3A, a processing module 53A that performs step S1 and a processing module 53B that performs step S2 are provided instead of the third processing module 53, in order to accommodate the fact that steps S1 and S2 are performed at different processing temperatures.

[0059] 9 except that processing module 53A is provided with a gas supply source that performs only step S1 of steps S1 and S2, and performs processing by heating wafer A to 400° C. Processing module 53B is provided with a gas supply source that performs only step S2 of steps S1 and S2, and does not include high-frequency power supplies 69 and 75 because plasma processing is not performed, and performs processing by heating wafer A to 450° C.

[0060] The substrate processing apparatus 3A will be further described, focusing on the differences from the substrate processing apparatus 3. As shown in the figure, processing modules 53A and 53B are connected to the first vacuum transfer module 41 instead of the third processing module 53 and the fourth processing module 54. In the substrate processing apparatus 3A, the fourth processing module 54 is connected to the second vacuum transfer module 42 instead of one of the four fifth processing modules 55 provided in the substrate processing apparatus 3. After the SiO2 film 19 has been removed in the second processing module 52, the wafer A is transferred via the vacuum transfer path 40 in the order of processing module 53A, processing module 53B, fourth processing module 54, and fifth processing module 55, and is subjected to the processing of steps S1 to S4.

[0061] As described above, the substrate processing apparatus 3A is provided with a processing module including a first processing gas supply unit and a second processing gas supply unit, a processing module including a third processing gas supply unit, and a processing module including a film forming gas supply unit, similar to the substrate processing apparatus 3. However, the processing module including the first processing gas supply unit and the processing module including the second processing gas supply unit are also provided separately.

[0062] In order to perform the processes at a more appropriate processing temperature for wafer A during steps S1 and S2, it is preferable to configure the substrate processing apparatus 3A so that steps S1 and S2 are performed by separate processing modules. When the Zr film 22 is formed on wafer A in step S1, the Zr film 22 is also formed on the inner wall of the processing vessel 61. In step S2, TiCl ４ In the substrate processing apparatus 3A in which steps S1 and S2 are performed in the processing modules 53A and 53B, respectively, the Zr film 22 on the inner wall is TiCl ４ The gas does not cause the particles to peel off and adhere to the wafer A as foreign matter. This is preferable because it suppresses a decrease in the yield of products manufactured from the wafer A. However, from the viewpoint of increasing the throughput by increasing the number of fifth process modules 55, which require a relatively long processing time as described above, it is preferable to configure the substrate processing apparatus 3 so that steps S1 and S2 are performed in the same process module.

[0063] 11 is a plan view of a substrate processing apparatus 3B which is a second modification of the substrate processing apparatus 3, and the substrate processing apparatus 3B will be described focusing on the differences from the substrate processing apparatus 3. The first processing module 51 of the substrate processing apparatus 3B heats the wafer A to a relatively high temperature during processing, thereby absorbing HF gas and NH ３ SiO by gas ２ Therefore, in the substrate processing apparatus 3, the SiO ２ The removal of the film 19 is performed in one processing module (processing module 51) in the substrate processing apparatus 3B.

[0064] Therefore, the first vacuum transfer module 41 of the substrate processing apparatus 3B is not connected to the second processing module 52. Instead, two fourth processing modules 54 are connected to the first vacuum transfer module 41. The wafer A processed in the first processing module 51 is transferred to the third processing module 53 for further processing, and then, as in the substrate processing apparatus 3, is transferred to the fourth processing module 54 and the fifth processing module 55 in that order for further processing.

[0065] 12 shows a substrate processing apparatus 3C which is a third modified example of the substrate processing apparatus 3. The substrate processing apparatus 3C will be described focusing on the differences from the substrate processing apparatus 3. Similar to the first vacuum transfer module 41 of the substrate processing apparatus 3A shown in FIG. 10, the first vacuum transfer module 41 of the substrate processing apparatus 3C is connected with process modules 53A and 53B instead of the process module 53. Similarly to the first vacuum transfer module 41 of the substrate processing apparatus 3B shown in FIG. 11, the first process module 51 of the substrate processing apparatus 3C is connected with a SiO ２ The substrate processing apparatus 3C is configured to be able to remove the film 19 by sublimation, and does not include a second processing module 52. Unlike the substrate processing apparatus 3B, the substrate processing apparatus 3C is provided with only one third processing module 54. The wafer A unloaded from the first processing module 51 is transferred to processing module 53A, and thereafter is transferred between processing modules in the same order as in the substrate processing apparatus 3A and processed.

[0066] As illustrated above, the configuration of the substrate processing apparatus 3 can be changed as appropriate. In the substrate processing apparatuses 3A to 3C, similarly to the substrate processing apparatus 3, the wafer A is transferred via the vacuum transfer path 40 after the ZrSi layer 21 is formed, and the vacuum transfer path 40 is temporarily set to a value of 1×10 -７ The pressure is set to be lower than Torr. This prevents oxidation of the ZrSi layer 21 during transport of the wafer A, thereby preventing an increase in contact resistance.

[0067] As described above, in the substrate processing apparatus 3 and 3A to 3C, ZrCl ４ , TiCl ４ , BCl ３ Therefore, when the Ru film 15 is formed in the fifth processing module, chlorine is attached to various parts of the surface of the wafer A, including the sidewalls of the recesses 14. When chlorine is attached to the sidewalls of the recesses 14, Ru(CO) 12Since the adsorption of Ru generated from the gas onto the sidewall is suppressed, the growth of the Ru film 15 from the sidewall of the recess 14 in the lateral direction (the direction perpendicular to the opening direction of the recess) is suppressed. This prevents the recess 14 from being closed before it is sufficiently filled with the Ru film 15. Therefore, an increase in contact resistance due to a reduction in the volume of the Ru film 15 formed in the recess 14 is more reliably suppressed.

[0068] However, in order to improve the adhesion of the Ru film 15 to the wall surface in the recess 14, a process of removing chlorine from the recess 14 may be performed before filling the Ru film 15. Specifically, after the process of step S4 of removing the Ti film 23 in the fourth process module 54, H ２ The gas is supplied, and the H ２ The gas is converted into plasma. When the wafer A is exposed to the plasma, the chlorine adhering to the wall surface of the recess 14 becomes HCl, which is vaporized and removed. Thereafter, the wafer A is transferred to the fifth processing module 55 as described above, and the Ru film 15 is embedded therein.

[0069] The processing steps illustrated in FIGS. 1 to 6 were described as steps for manufacturing an NMOS. However, for example, PMOS manufacturing may be performed in parallel with NMOS manufacturing. In that case, the processing steps illustrated in FIGS. 1 to 6 are performed on the PMOS portion of wafer A. Therefore, this technology is not limited to the manufacturing of NMOS. Furthermore, although the semiconductor layer forming the bottom wall of recess 14 is illustrated as being a Si layer 11 in FIGS. 1 to 6, it may be a semiconductor layer containing Si other than Si layer 11, such as a SiGe (silicon germanium) layer, and ZrSi layer 21 may be formed on the semiconductor layer other than Si layer 11. Note that "containing Si" here means containing Si as a constituent component, not as an impurity.

[0070] In step S2, TiCl ４ Instead of supplying gas, for example, MoCl ５ (molybdenum chloride) and WCl ５In step S2, the Zr film 22 may be removed by supplying a gas such as tungsten chloride, and in step S3, Mo or W remaining on the sidewall of the recess 14 may be removed instead of Ti. In this way, the second process gas supplied to the wafer A in step S2 may be TiCl ４ The second metal, which is a metal other than Zr and is contained in the second process gas, is not limited to Ti.

[0071] Alternatively, after step S1, HCl (hydrogen chloride) gas may be supplied to the wafer A as a second process gas to remove the Zr film 22, and then the Ru film 15 may be embedded in the recess 14 in step S4. Therefore, after the Zr film 22 is formed, TiCl ４ The gas includes the second process gas exemplified as BCl ３ The supply of the third process gas, exemplified as HCl gas and HF gas, may not be necessary. However, although the Zr film 22 can be removed by supplying HCl gas in this manner, the ZrSi layer 21 is also etched relatively significantly, as will be shown in the evaluation test described below. Therefore, in order to suppress etching of the ZrSi layer 21 and more reliably reduce the contact resistance, it is preferable to supply each gas to form the Ti film 22 and remove the Ti film 22 as described with reference to FIGS. 2 and 3 .

[0072] In step S3, BCl ３ Although the gas and HF gas are alternately supplied to wafer A, they may also be supplied simultaneously to wafer A. Furthermore, the conductive film embedded in recess 14 in step S4 is preferably a Ru film 15 to reduce wiring resistance, but may also be another metal film, specifically, a W film or an Mo film, for example. By adjusting the processing conditions for steps S1 to S4, the process described as a plasma process may be performed as a non-plasma process, and the process described as a non-plasma process may be performed as a plasma process.

[0073] It should be noted that the embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive, and the above-described embodiments may be omitted, substituted, modified, and / or combined in various forms without departing from the scope and spirit of the appended claims.

[0074] <Evaluation Test> Evaluation tests related to this technology are described below.

[0075] Evaluation Test 1 In Evaluation Test 1, a plurality of substrates were prepared, and a Zr film was formed on the Si layer constituting each substrate. Then, a different etching gas was supplied to each substrate, and the thickness of the Zr film remaining on the substrate was measured. Note that the Zr film reacts with the Si layer by heating the substrate during the Zr film formation to form a ZrSi film, so the measurement of the thickness of this Zr film corresponds to the measurement of the thickness of the ZrSi film. In Evaluation Test 1, TiCl ４ The test in which etching was performed by supplying gas and the test in which etching was performed by supplying HCl gas are referred to as Evaluation Tests 1-1 and 1-2, respectively. In each of Evaluation Tests 1-1 and 1-2, the supply time of the etching gas (etching time) was set to a different time for each substrate.

[0076] Evaluation Test 2: In Evaluation Test 2, a plurality of substrates were prepared, and the SiO ２ A Zr film was formed on the TiCl layer. Then, a different etching gas was supplied to each substrate, and the thickness of the Zr film remaining on the substrate was measured. ４ Tests in which etching was performed by supplying gas, tests in which etching was performed by supplying HCl gas, tests in which etching was performed by supplying ZrCl ４ The tests in which etching was performed by supplying gas are designated as Evaluation Tests 2-1, 2-2, and 2-3. In each of Evaluation Tests 2-1, 2-2, and 2-3, a different etching time was set for each substrate.

[0077] The graphs in Figures 13 and 14 show the results of evaluation tests 1 and 2, respectively. As shown in Figure 13, in evaluation test 1-2 using HCl gas as the etching gas, the thickness of the Zr film decreased as the etching time increased. However, when TiCl was used as the etching gas, ４In Evaluation Test 1-1 using gas, the change in Zr film thickness is suppressed even when the etching gas time is relatively long, and the Zr film thickness is larger than in Evaluation Test 1-1 except when the etching time is 0 seconds.

[0078] In addition, the results of evaluation test 2 show that, as shown in FIG. ４ In the evaluation test 2-3 using a gas, the change in the thickness of the Zr film due to the supply of the etching gas is small. Therefore, it can be seen that when step S1 described in the embodiment is performed, the thickness of the Zr film 22 formed on the side wall of the recess 14 is prevented from becoming excessively thick. ４ In the evaluation tests 2-1 and 2-2 using the gas HCl and HCl gas, the thickness of the Zr film relative to the etching time was significantly reduced compared to the evaluation test 2-3.

[0079] Therefore, from the evaluation test 2, for the Zr film that was not silicided, TiCl ４ It was shown that the ZrSi layer 21 can be etched at a relatively high etching rate with TiCl gas or HCl gas. As described in the embodiment, in step S1 of forming the ZrSi layer 21, the Zr film 22 is also formed on the SiN film 16 forming the sidewall of the recess 14. That is, the Zr film 22 is formed as a non-silicided film. However, the results of this evaluation test 2 show that such a Zr film 22 can be etched with TiCl ４ It can be seen that it can be removed by supplying gas.

[0080] From the results of the above evaluation tests 1 and 2, it was found that in step S2 described in the embodiment, TiCl ４ It was shown that supplying the gas makes it possible to etch the Zr film 22 while suppressing etching of the ZrSi layer 21 formed in step S1. In tests conducted separately from evaluation tests 1 and 2, images of the vertical cross section of the recess 14 were obtained after step S1 and before step S2, and after step S2 and before step S3. These images confirm that the Zr film 22 that was present on the SiN film 13 after step S1 was removed by performing step S2.

[0081] Evaluation Test 3: In Evaluation Test 3, a plurality of substrates were prepared, and a Ti film was formed on each substrate. ３ The etching of the Ti film was performed by repeatedly supplying a gas and then a HF gas, and the etching amount was measured. The combination of the substrate processing temperature during this cycle and the number of cycle repetitions was changed for each substrate. The substrate temperature was set to 250°C, 300°C, or 350°C.

[0082] FIG. 15 is a graph showing the results of Evaluation Test 3. The graph shows the measurement results of the etching amount, as well as an approximated line calculated from the measurement results at the same processing temperatures. The approximated line for the processing temperature of 250°C is calculated from the measurement results shown in the graph and the measurement results that are hidden because they are located outside the graph. As shown in the graph, the Ti film was etched at all processing temperatures of 250°C, 300°C, and 350°C, and the amount of etching of the Ti film increased with the number of cycles. Furthermore, the higher the substrate temperature, the greater the amount of etching. The results of Evaluation Test 3 demonstrated that the Ti film 23 formed by step S2 described in the embodiment can be removed by performing step S3.

[0083] A wafer 11 silicon (Si) layer 12 silicon oxide (SiO ２ ) layer 13 silicon nitride (SiN) film 14 recess 15 ruthenium (Ru) film 15

Claims

1. A substrate processing method comprising: a step of supplying a first process gas containing zirconium to a substrate having a recess in which a semiconductor layer containing silicon is exposed at the bottom surface and whose sidewalls are formed by an insulating film, thereby forming a zirconium silicide layer that forms the bottom wall of the recess; a step of supplying a second process gas to the substrate to remove zirconium remaining on the sidewall of the recess; and a film formation step of supplying a film formation gas to the substrate after the removal step to form a conductive film in the recess.

2. A substrate processing method according to claim 1, wherein the second processing gas is a gas containing a second metal other than zirconium, and the method further comprises a step of supplying a third processing gas to the substrate to remove the second metal remaining on the sidewall of the recess, the step being carried out after the step of removing the zirconium and before the step of forming the film.

3. A substrate processing method according to claim 2, wherein the second metal is titanium, tungsten or molybdenum, and the second processing gas is a gas of a chloride of the second metal.

4. A substrate processing method according to claim 2, wherein the third processing gas is a mixture of boron trichloride gas and hydrogen fluoride gas.

5. A substrate processing method according to claim 2, wherein the first processing gas, the second processing gas, and the third processing gas are chloride gases, and the method includes a step of exposing the substrate to hydrogen gas plasma to remove chlorine from within the recess before carrying out the film forming step.

6. A substrate processing apparatus comprising: a processing module having a processing vessel with a stage therein for placing a substrate having a recess with a sidewall formed by an insulating film to perform gas processing on the substrate; a first processing gas supply unit that supplies a first processing gas containing zirconium into the processing vessel in which the substrate, having a semiconductor layer containing silicon exposed at the bottom of the recess, is stored, to form a zirconium silicide layer that forms the bottom wall of the recess; a second processing gas supply unit that supplies a second processing gas into the processing vessel to remove zirconium remaining on the sidewall of the recess of the substrate; and a film formation gas supply unit that supplies a film formation gas into the processing vessel and forms a conductive film in the recess of the substrate after the second processing gas has been supplied.

7. A substrate processing apparatus according to claim 6, wherein a plurality of the processing modules are provided, each of the processing modules is connected to a substrate transport path equipped with a transport mechanism for transporting the substrate between the processing modules, and the first processing gas supply unit, the second processing gas supply unit, and the film forming gas supply unit are provided in any of the plurality of processing modules.

8. A substrate processing apparatus as described in claim 7, wherein the second processing gas is a gas containing a second metal other than zirconium, and a third processing gas supply unit is provided in any of the processing modules for supplying a third processing gas into the processing vessel in which the substrate is stored after the second processing gas has been supplied but before the film forming gas is supplied, thereby removing the second metal remaining on the side wall of the recess.

9. Evacuate the transport path to reduce the pressure in the transport path to 1 x 10 －７ 8. The substrate processing apparatus according to claim 7, comprising: an exhaust mechanism that sets a first pressure lower than Torr; an inert gas supply mechanism that supplies an inert gas to the transfer path set at the first pressure to increase the pressure to a second pressure; and a control unit that outputs a control signal so that the transfer mechanism transfers the substrate between the processing modules in a state in which the transfer path is set at the second pressure and the interior of each processing vessel is set at a pressure lower than the second pressure.

10. A substrate processing apparatus as described in claim 7, wherein the stage is provided with a heating mechanism for heating the substrate, and among the plurality of processing modules, the processing module in which the first processing gas supply unit and the second processing gas supply unit are provided, the processing module in which the third processing gas supply unit is provided, and the processing module in which the film forming gas supply unit is provided are individually provided processing modules, and the substrate is heated to mutually different temperatures by each of the heating mechanisms.

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