Core substrate and interposer

Abstract

A first conductor part (201) comprises a sintered compact, said first conductor part (201) penetrating a ceramic substrate (100) from a first surface (SF1) to a second surface (SF2). The first conductor part (201) includes a first conductor layer penetrating a first ceramic layer, a second conductor layer penetrating a second ceramic layer, and a third conductor layer penetrating a third ceramic layer. A first magnetic body portion (301) is embedded in the ceramic substrate (100) and is made of ceramic. In a ZX cross-sectional view parallel to the Z direction and the X direction, the first conductor layer, the second conductor layer, and the third conductor layer are disposed in the X direction in a first X range, a second X range, and a third X range, respectively. The second X range has a portion overlapping the first X range and a portion overlapping the third X range, and the third X range falls outside the first X range.

Description

Core substrate and interposer

[0001] The present invention relates to a core substrate and an interposer, and more particularly to a core substrate with a built-in inductor for constituting an interposer on which a semiconductor element is mounted.

[0002] According to Japanese Patent Laid-Open Publication No. 2019-179792 (Patent Document 1), in a semiconductor device, an interposer is disposed between a semiconductor element and a motherboard. The semiconductor element and the motherboard are each connected to the interposer using solder balls. The interposer is shown to be a multilayer printed wiring board, which includes a core substrate, three conductor circuit layers stacked on the core substrate so as to face the semiconductor element, and three conductor circuit layers stacked on the core substrate so as to face the motherboard. On the semiconductor element mounting side of the interposer, the wiring dimensions are gradually reduced by passing through the three conductor circuit layers.

[0003] Efficient power management is sometimes required for semiconductor devices such as integrated circuits (ICs). Typically, a voltage regulator controls the supply voltage to each of multiple computing cores in a processor chip (semiconductor device) depending on the processor's processing power, etc. A voltage regulator typically requires switches, capacitors, and inductors. Controlling the supply voltage for each computing core requires a separate switch, capacitor, and inductor for each computing core. In particular, inductors are difficult to incorporate into semiconductor devices and are typically prepared separately from the semiconductor device. High-performance processors, particularly those for data servers, have many computing cores to enhance their processing power, and correspondingly, the inductance required per unit area of ​​the processor chip is increasing. The inductance of an inductor can be increased by increasing the magnetic permeability near the inductor's current path. It is widely known to use magnetic materials for this purpose.

[0004] U.S. Patent Application Publication No. 2019 / 0279806 (Patent Document 2) discloses a package substrate (interposer) with an embedded inductor that is disposed between a die (semiconductor element) and a board (motherboard). The specification exemplifies forming a substrate core primarily made of organic material with conductive through-holes (conductor portions) and a magnetic coating (magnetic material portion) containing magnetic particles and disposed around the conductor portions. In this case, the magnetic material portion must be formed at a temperature equal to or lower than the heat resistance temperature of the organic material of the substrate core. A typical method for achieving this is to solidify a resin in which magnetic particles are dispersed. However, when the magnetic material portion is formed from magnetic particles dispersed in a resin, it is difficult to ensure a sufficiently high magnetic permeability due to limitations on the magnetic particle filling rate (the proportion of magnetic particles per volume).

[0005] International Publication No. 2022 / 163588 (Patent Document 3) discloses a core substrate with an embedded inductor for forming an interposer on which a semiconductor element is mounted. The core substrate includes a ceramic substrate, a conductor portion, and a magnetic material portion. The ceramic substrate has a first surface and a second surface opposite the first surface in the thickness direction, and a through hole between the first surface and the second surface. The conductor portion passes through the through hole. The conductor portion is made of sintered metal. The magnetic material portion surrounds the conductor portion at the through hole. The magnetic material portion is made of ceramics rather than resin with dispersed magnetic particles. This allows the ceramics to be densely sintered, thereby increasing the magnetic permeability of the magnetic material portion. Therefore, the core substrate can incorporate an inductor with a larger inductance per unit area.

[0006] JP 2019-179792 A U.S. Patent Application Publication No. 2019 / 0279806 WO 2022 / 163588

[0007] In the core substrate disclosed in WO 2022 / 163588, the inductance of the built-in inductor is roughly proportional to the dimension of the inductor in the thickness direction. However, depending on the application of the core substrate, it may be necessary to ensure inductance while suppressing the dimension.

[0008] The present invention has been made to solve the above problems, and one object of the present invention is to provide a core substrate that can improve the inductance of an inductor built into the core substrate while reducing the dimension in the thickness direction of the inductor. Another object of the present invention is to provide an interposer that can improve the inductance of an inductor built into the interposer while reducing the dimension in the thickness direction of the inductor.

[0009] Aspect 1 is a core substrate with an inductor built in for constituting an interposer on which a semiconductor element is mounted, the core substrate comprising a ceramic substrate having a first surface and a second surface opposite each other in the Z direction in an orthogonal coordinate system having an X direction, a Y direction, and a Z direction, and having a laminated structure formed by laminating a plurality of ceramic layers in the Z direction, the plurality of ceramic layers including a first ceramic layer, a second ceramic layer, and a third ceramic layer, the first ceramic layer, the second ceramic layer, and the third ceramic layer being laminated in this order, the core substrate further comprising a first conductor portion made of a sintered body and penetrating the ceramic substrate from the first surface to the second surface, The conductor portion includes a first conductor layer penetrating the first ceramic layer, a second conductor layer penetrating the second ceramic layer, and a third conductor layer penetrating the third ceramic layer, and the core substrate further includes a first magnetic portion embedded in the ceramic substrate and made of ceramic for increasing the inductance of the first conductor portion, and in a ZX cross-sectional view parallel to the Z direction and the X direction, the first conductor layer, the second conductor layer, and the third conductor layer are arranged in a first X range, a second X range, and a third X range with respect to the X direction, respectively, and the second X range has a portion overlapping the first X range and a portion overlapping the third X range, and the third X range is outside the first X range.

[0010] Aspect 2 is a core substrate according to aspect 1, comprising a second conductor portion made of a sintered body and penetrating between the first surface and the second surface of the ceramic substrate, a second magnetic portion for increasing the inductance of the second conductor portion, and a connecting portion for connecting the first conductor portion and the second conductor portion to each other on the first surface of the ceramic substrate.

[0011] Aspect 3 is the core substrate according to aspect 2, wherein, in the ZX cross-sectional view, the arrangement of the second conductor portions is symmetrical with respect to the arrangement of the first conductor portions with respect to an axis of symmetry along the Z direction.

[0012] Aspect 4 is the core substrate according to aspect 2, wherein, in the ZX cross-sectional view, the second conductor portions are arranged such that the first conductor portions are arranged parallel to each other along the X direction.

[0013] Aspect 5 is a core substrate described in any one of aspects 1 to 4, wherein the plurality of ceramic layers includes a fourth ceramic layer, the first ceramic layer, the second ceramic layer, the third ceramic layer, and the fourth ceramic layer are stacked in this order, the first conductor portion includes a fourth conductor layer penetrating the fourth ceramic layer, and in a YZ cross-sectional view parallel to the Y direction and the Z direction, with respect to the Y direction, the second conductor layer, the third conductor layer, and the fourth conductor layer are respectively arranged in a first Y range, a second Y range, and a third Y range, the second Y range having a portion overlapping the first Y range and a portion overlapping the third Y range, and the third Y range being outside the first Y range.

[0014] Aspect 6 is a core substrate according to any one of Aspects 1 to 4, wherein, in a planar view parallel to the X direction and the Y direction, the second conductor layer of the first conductor portion includes a first region, a second region, a third region, and a fourth region, the second conductor layer extends so that the first region, the second region, the third region, and the fourth region follow in this order, the second conductor layer is out of the region between the second region and the fourth region, the first conductor layer is connected to the first region away from the second region, the third region, and the fourth region of the second conductor layer, and the third conductor layer is connected to the fourth region away from the first region, the second region, and the third region of the second conductor layer.

[0015] Aspect 7 is the core substrate according to aspect 6, wherein the plurality of ceramic layers include a fourth ceramic layer and a fifth ceramic layer, and the first ceramic layer, the second ceramic layer, the third ceramic layer, the fourth ceramic layer, and the fifth ceramic layer are stacked in this order, the first conductor portion includes a fourth conductor layer penetrating the fourth ceramic layer and a fifth conductor layer penetrating the fifth ceramic layer, and in the plan view, the fourth conductor layer of the first conductor portion includes a fifth region, a sixth region, a seventh region, and an eighth region, and the fourth conductor layer extends so that the fifth region, the sixth region, the seventh region, and the eighth region are successively arranged in this order, and the fourth conductor layer is out of the region between the sixth region and the eighth region, The third conductor layer is connected to the fifth region, away from the sixth region, the seventh region, and the eighth region of the fourth conductor layer; the fifth conductor layer is connected to the eighth region, away from the fifth region, the sixth region, and the seventh region of the fourth conductor layer; the first region, the second region, the third region, and the fourth region of the second conductor layer form a first current path extending in this order, the first current path including a first section extending with a first direction vector; the fifth region, the sixth region, the seventh region, and the eighth region of the fourth conductor layer form a second current path extending in this order, the second current path including a second section extending with a second direction vector, and the dot product of the first direction vector and the second direction vector is positive.

[0016] Aspect 8 is a core substrate described in aspect 7, wherein the first direction vector of the first section of the first current path of the second conductor layer and the second direction vector of the second section of the second current path of the fourth conductor layer are the same.

[0017] Aspect 9 is a core substrate according to aspect 7 or 8, wherein, in the planar view, the second conductor layer has a first portion corresponding to the first section of the first current path, the fourth conductor layer has a second portion corresponding to the second section of the second current path, and the first portion and the second portion at least partially overlap.

[0018] A tenth aspect of the present invention is the core substrate according to any one of the first to ninth aspects, wherein the ceramic substrate is made of low-temperature co-fired ceramics or a composite material of glass and alumina.

[0019] Aspect 11 is the core substrate according to any one of aspects 1 to 10, wherein a sintered interface is formed between the first conductor portion and a portion of the core substrate other than the first conductor portion.

[0020] Aspect 12 is an interposer comprising a core substrate according to any one of aspects 1 to 11, and a wiring layer stacked on the core substrate, the wiring layer having a mounting surface on which the semiconductor element is to be mounted.

[0021] According to the first aspect, in the ZX cross-sectional view, the second X-range of the second conductor layer of the first conductor portion has a portion overlapping the first X-range of the first conductor layer of the first conductor portion and a portion overlapping the third X-range of the third conductor layer of the first conductor portion, and the third X-range is outside the first X-range. As a result, the second conductor layer of the first conductor portion has a portion extending outside the first X-range in the X-direction, and this portion contributes to inductance. This can improve the inductance of the inductor built into the core substrate.

[0022] According to the second aspect, the core substrate has a connection portion that connects the first conductor portion and the second conductor portion to each other. This forms a series circuit of an inductor formed by the first conductor portion and an inductor formed by the second conductor portion. This provides a combined inductance greater than that of the inductors formed by the first conductor portion and the second conductor portion, respectively.

[0023] According to the third aspect, in the ZX cross section, the arrangement of the second conductor portions is symmetrical with respect to the axis of symmetry along the Z direction with respect to the arrangement of the first conductor portions, which makes it easier to design the inductor.

[0024] According to the fourth aspect, in the ZX cross-sectional view, the second conductor portion is arranged by shifting the first conductor portion parallel to the X direction. This reduces the likelihood of forming a location in the vicinity of both the first and second conductor portions where the magnetic field caused by the current in the first conductor portion and the magnetic field caused by the current in the third conductor portion reinforce each other according to Ampere's law. This reduces the likelihood of magnetic saturation occurring in that location. This improves the current superposition characteristics of the inductor built into the core substrate.

[0025] According to the fifth aspect, in the Y-Z cross-sectional view, the second conductor layer, the third conductor layer, and the fourth conductor layer are respectively arranged in a first Y-range, a second Y-range, and a third Y-range with respect to the Y direction, and the second Y-range of the third conductor layer of the first conductor portion has a portion overlapping with the first Y-range of the second conductor layer of the first conductor portion and a portion overlapping with the third Y-range of the fourth conductor layer of the first conductor portion, and the third Y-range is outside the first Y-range. As a result, the third conductor layer of the first conductor portion has a portion extending outside the first Y-range in the Y direction, and this portion contributes to inductance. This further improves the inductance of the inductor built into the core substrate.

[0026] According to the sixth aspect, the second conductor layer of the first conductor is outside the region between the second region and the fourth region. This allows the third region of the first conductor to extend so as to bypass the region between the second region and the fourth region. This further improves the inductance of the inductor formed by the first conductor.

[0027] According to the seventh aspect, the first current path in the second conductor layer of the first conductor portion includes a first section extending along a first directional vector, and the second current path in the fourth conductor layer of the first conductor portion includes a second section extending along a second directional vector, and the dot product of the first and second directional vectors is positive. This allows the magnetic fields caused by the current flowing through the first section and the magnetic fields caused by the current flowing through the second section to mitigate each other according to Ampere's law. This makes it difficult for a magnetic saturation state to occur between the first and second sections. This improves the current superposition characteristics of the inductor built into the core substrate.

[0028] According to the eighth aspect, the first direction vector of the first section of the first current path in the second conductor layer is the same as the second direction vector of the second section of the second current path in the fourth conductor layer. This enhances the mutual attenuation effect of the magnetic fields caused by the current flowing in the first section and the magnetic fields caused by the current flowing in the second section. This further improves the current superposition characteristics of the inductor built into the core substrate.

[0029] According to the ninth aspect, in a plan view, the first portion of the second conductor layer, which corresponds to the first section of the first current path, and the second portion of the fourth conductor layer, which corresponds to the second section of the second current path, at least partially overlap each other. This enhances the mutual attenuation effect of the magnetic fields caused by the currents flowing in the first section and the second section. This further improves the current superposition characteristics of the inductor built into the core substrate.

[0030] According to the tenth aspect, the ceramic substrate is made of low-temperature co-fired ceramics or a composite material of glass and alumina, which makes it easier to form the ceramic substrate and the first conductors by co-firing in manufacturing the core substrate.

[0031] According to the above-mentioned Aspect 11, the core substrate has a sintered interface between the first conductor and the portion of the core substrate other than the first conductor. This prevents the heat resistance of the core substrate from being reduced due to the low heat resistance of the organic adhesive, unlike when the first conductor is bonded to the portion of the core substrate other than the first conductor via an organic adhesive. Therefore, the heat resistance of the core substrate can be improved.

[0032] According to the twelfth aspect, the interposer on which the semiconductor element is to be mounted includes a core substrate. In a ZX cross-sectional view of the core substrate, the second X-range of the second conductor layer of the first conductor portion includes a portion overlapping the first X-range of the first conductor layer of the first conductor portion and a portion overlapping the third X-range of the third conductor layer of the first conductor portion, and the third X-range is outside the first X-range. As a result, the second conductor layer of the first conductor portion includes a portion extending outside the first X-range in the X-direction, which portion contributes to inductance. This improves the inductance of the inductor included in the interposer.

[0033] The objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

[0034] FIG. 1 is a cross-sectional view schematically showing the configuration of an electronic device having an interposer. FIG. 2 is a schematic view showing an example of the configuration of a wiring layer provided on a surface of a core substrate of an interposer that faces a semiconductor element. FIG. 3 is a schematic view showing an example of the configuration of a wiring layer provided on a surface of a core substrate of an interposer opposite to the surface facing the semiconductor element. FIG. 4 is a cross-sectional view showing an electronic device of a modified example of FIG. 1. FIG. 5 is a schematic view showing the configuration of an inductor built into a core substrate. FIG. 6 is a circuit diagram showing an example of electrical connection of the first inductor and the second inductor shown in FIG. 5. FIG. 7 is a partial cross-sectional view schematically showing the configuration of a core substrate of a comparative example. FIG. 8 is a partial top view schematically showing the configuration of a core substrate in embodiment 1. FIG. 9 is a partial cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a diagram schematically showing a current path in the configuration of FIG. 9. FIG. 11 is a partial cross-sectional view schematically showing the configuration of a core substrate in embodiment 2. FIG. 12 is a diagram schematically showing a current path in the configuration of FIG. 11. FIG. 13 is a partial top view schematically showing the configuration of a core substrate in embodiment 3. FIG. 14 is a partial cross-sectional view taken along line XIV-XIV in each of FIGS. 13 and 16. FIG. 15 is a partial cross-sectional view taken along line XV-XV in each of FIGS. 13 and 16. FIG. 16 is a partial cross-sectional view taken along line XVI-XVI in each of FIGS. 13 to 15. FIG. 17 is a diagram schematically showing current paths in the configurations of FIGS. 14 and 15. FIG. 18 is a partial top view schematically showing the configuration of a core substrate in embodiment 4. FIG. 19 is a partial cross-sectional view taken along line XIX-XIX in FIG. 18. FIG. 20 is a plan view schematically showing the configuration of the second layer of the core substrate in FIG. 19. FIG. 21 is a plan view schematically showing the configuration of the fourth layer of the core substrate in FIG. 19. FIG. 22 is a diagram schematically showing current paths in the configuration of FIG. 19.

[0035] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0036] <Electronic Device Having an Interposer> Prior to describing the embodiments, a general configuration of an electronic device having an interposer will be described below as a preliminary explanation.

[0037] FIG. 1 is a cross-sectional view schematically illustrating the configuration of electronic device 901. Electronic device 901 includes interposer 700, semiconductor element 811, motherboard 812, and package substrate 813. Interposer 700 includes core substrate 600, wiring layer 791, and wiring layer 792. Wiring layer 791 and wiring layer 792 are laminated on first surface SF1 and second surface SF2 of core substrate 600, respectively. In other words, wiring layer 791 is provided on the surface of core substrate 600 facing semiconductor element 811, and wiring layer 792 is provided on the surface of core substrate 600 opposite the surface facing semiconductor element 811. Wiring layer 791 and wiring layer 792 may be laminated on core substrate 600 by a build-up method, a sputtering method, or the like, or may be bonded as separate wiring boards.

[0038] 2 is a schematic diagram showing an example of the configuration of the wiring layer 791. The wiring layer 791 has a stacking surface SG2 and a mounting surface SC that are opposite to each other. The stacking surface SG2 is stacked on the second surface SF2 of the core substrate 600. A semiconductor element 811 is mounted on the mounting surface SC. The wiring layer 791 also has an insulating portion 791i and a wiring portion 791j. The wiring portion 791j electrically connects the stacking surface SG2 and the mounting surface SC. The wiring portion 791j has a wiring group W1a that reaches the stacking surface SG2, a wiring group W1b that reaches the mounting surface SC, and wiring (not shown) that connects the wiring group W1a and the wiring group W1b.

[0039] The wiring layer 791 is preferably a multi-layer wiring layer configured so that the wiring dimensions (e.g., line and space (L / S) dimensions) are reduced from the stacking surface SG2 to the mounting surface SC. This makes it possible to configure an interposer 700 capable of mounting semiconductor elements 811 having a small terminal pitch even if the wiring dimensions (L / S) of the core substrate 600 are not particularly high. Specifically, the wiring layer 791 may be a laminate of a normal wiring layer facing the core substrate 600 and a fine wiring layer facing the semiconductor elements 811. In this case, the wiring group W1a belongs to the normal wiring layer, and the wiring group W1b belongs to the fine wiring layer.

[0040] A typical wiring layer may be formed by providing a wiring structure on a plate-shaped organic material (e.g., an epoxy-based member) or inorganic material (e.g., a low temperature co-fired ceramics (LTCC) material or a non-magnetic ferrite material). To form the wiring structure on this organic material, for example, Cu plating is used. To form the wiring structure on an inorganic material, when the inorganic material is formed by a firing process, the wiring structure is simultaneously formed by firing Ag (silver) or Cu (copper). From the viewpoint of ease of forming fine wiring, it is preferable that a fine wiring layer be formed by providing a wiring structure on a plate-shaped organic material (e.g., an epoxy-based or polyimide-based member). To form the wiring structure on this organic material, for example, Cu plating is used.

[0041] FIG. 3 is a schematic diagram showing an example of the configuration of the wiring layer 792. The wiring layer 792 has a stacking surface SG1 and a bottom surface SB that are opposite to each other. The stacking surface SG1 is stacked on the first surface SF1 of the core substrate 600. In the electronic device 901 of FIG. 3, the bottom surface SB faces the package substrate 813. The wiring layer 792 also has an insulating portion 792i and a wiring portion 792j. The wiring portion 792j electrically connects the stacking surface SG1 and the bottom surface SB. The wiring portion 792j has a wiring group W2a that reaches the bottom surface SB, a wiring group W2b that reaches the stacking surface SG1, and wiring (not shown) that connects the wiring group W2a and the wiring group W2b.

[0042] The semiconductor element 811 is connected to the wiring layer 791 of the interposer 700 by, for example, solder balls 821. The semiconductor element 811 may be an IC (Integrated Circuit) chip. In particular, when the IC chip is a processor chip having multiple processing cores, the voltage regulator described above can be configured using an inductor, which will be described later.

[0043] The interposer 700 is mounted on the package substrate 813 by bonding the wiring layer 792 to the package substrate 813. This bonding is performed, for example, by solder balls 823. The package substrate 813 is mounted on the motherboard 812, and this bonding is performed, for example, by using solder balls 822.

[0044] In the wiring layer 791 (FIG. 2), the pitch of the terminal group connected to the wiring group W1b on the mounting surface SC may be smaller than the pitch of the terminal group connected to the wiring group W1a on the stacking surface SG2, and in this case, the interposer 700 (FIG. 1) has the function of converting the terminal pitch. As a modified example, depending on the application of the interposer, either or both of the wiring layer 791 and the wiring layer 792 may be omitted.

[0045] 4 is a cross-sectional view showing an electronic device 902, which is a modified example of the electronic device 901 (FIG. 1). In the electronic device 902, the interposer 700 is bonded to the motherboard 812 without the package substrate 813 (FIG. 1), and this bonding is performed by, for example, solder balls 822.

[0046] 5 is a schematic diagram illustrating the configuration of inductors L1 to L6 built into the core substrate 600. The core substrate 600 has multiple inductors L1 and L2 built into it, and may also have additional inductors L3 to L6 built into it, with the number of inductors being arbitrary.

[0047] To configure an interposer such as interposer 700, a core substrate according to the present embodiment or its modified example, which will be described later, may be applied in place of the above-described core substrate 600. Therefore, detailed description of the interposer will not be repeated below.

[0048] <Core substrate using resin (comparative example)> Fig. 6 is a circuit diagram showing an example of the electrical connection of an inductor built into a core substrate 690 of a comparative example. Fig. 7 is a partial cross-sectional view showing the configuration of core substrate 690 of the comparative example. The built-in inductor of core substrate 690 has a series circuit of inductor L1 and inductor L2, which results in a combined inductance greater than the individual inductances of inductor L1 and inductor L2.

[0049] In the core substrate 690, a first magnetic material portion 391 and a first conductor portion 291 are formed in this order on the side wall of one through hole of a resin substrate 190 made of glass epoxy resin, with the first conductor portion 291 having a hollow structure filled with a resin material 281. Similarly, a second magnetic material portion 392 and a second conductor portion 292 are formed in this order on the side wall of another through hole of the resin substrate 190, with the second conductor portion 292 having a hollow structure filled with a resin material 282. The first conductor portion 291 and the second conductor portion 292 constitute inductors L1 and L2, respectively. The first conductor portion 291 and the second conductor portion are connected to each other by a connecting portion 450, thereby forming a series circuit of inductors L1 and L2. The first conductor portion 291 and the second conductor portion 292 are also collectively referred to as conductor portions 290.

[0050] As described above, the first magnetic material portion 391 and the second magnetic material portion 392 (collectively referred to as the magnetic material portion 390) are formed within the resin substrate 190. Therefore, the process for forming the magnetic material portion 390 must be performed at a temperature below the heat resistance temperature of the resin substrate 190. Due to this constraint, the magnetic material portion 390 is not made of a sintered ceramic body but of a resin in which magnetic particles are dispersed. In this case, the gaps between the magnetic particles in the magnetic material portion 390 are filled with resin, and it is generally difficult to increase this filling rate to 70% or more. As a result, it is difficult to increase the relative permeability of the first magnetic material portion 391 and the second magnetic material portion 392 compared to the first magnetic material portion 301 and the second magnetic material portion 302 ( FIG. 9 : Embodiment 1), which will be described later, and the relative permeability is, for example, approximately 6.

[0051] A design example of the core substrate 690 is described below. The resin substrate 190 has a square shape with sides of 50 mm in the in-plane direction and a dimension of 1000 μm in the thickness direction. The multiple through holes described above are arranged at a pitch of 500 μm. Each of the magnetic material portions 390 has an outer diameter of 400 μm and an inner diameter of 200 μm. Each of the conductor portions 290 has an outer diameter of 200 μm. The conductor portions 290 are formed by Cu plating. The magnetic material portions 390 are made of resin with dispersed magnetic particles, and their relative permeability is estimated to be 6. In this case, the inductance of one inductor (e.g., inductor L1) is estimated by the inventor to be approximately 1 nH at 140 MHz.

[0052] First Embodiment FIG. 8 is a partial top view schematically illustrating the configuration of a core substrate 601 according to a first embodiment. FIG. 9 is a partial cross-sectional view taken along line IX-IX in FIG. 8. FIG. 10 is a diagram schematically illustrating current paths in the configuration of FIG. 9. The core substrate 601 is used to form an interposer 700 (FIG. 1) on which a semiconductor element 811 is mounted, and includes multiple built-in inductors. In FIGS. 8 and 9, inductors L1 and L2 are shown as the multiple inductors. The core substrate 601 has a multilayer structure formed using multilayer ceramic technology (see the dashed lines in FIG. 9). The multilayer structure includes first to third layers a to c, and in this embodiment, a case in which the multilayer structure includes first to fifth layers a to e (FIG. 9) will be described in detail.

[0053] The core substrate 601 includes a ceramic substrate 100. The ceramic substrate 100 forms a first surface SF1 and a second surface SF2 of the core substrate 601. The first surface SF1 and the second surface SF2 are opposite surfaces of the ceramic substrate 100 in the Z direction. The ceramic substrate 100 has a layered structure formed by stacking multiple ceramic layers in the Z direction in a Cartesian coordinate system having the X, Y, and Z directions. Specifically, the ceramic substrate 100 is formed by first to fifth ceramic layers located in the first layer a to fifth layer e ( FIG. 9 ) of the layered structure of the core substrate 601, respectively, and these layers will hereinafter also be referred to as the first ceramic layer 100a to the fifth ceramic layer 100e. The first ceramic layer 100a to the fifth ceramic layer 100e are stacked in this order.

[0054] The core substrate 601 has a first conductor portion 201 that penetrates between the first surface SF1 and the second surface SF2 of the ceramic substrate 100. The first conductor portion 201 has first to fifth conductor layers that are located on the first layer a to fifth layer e ( FIG. 9 ) of the core substrate 601, respectively, and these layers will hereinafter also be referred to as the first conductor layer 201 a to fifth conductor layer 201 e. The first conductor layer 201 a to fifth conductor layer 201 e penetrate the first ceramic layer 100 a to fifth ceramic layer 100 e, respectively.

[0055] In a ZX cross-sectional view ( FIG. 9 ) parallel to the Z and X directions, the first to third conductor layers 201a to 201c are arranged in a first to third X range, respectively, in the X direction. In other words, the first to third X ranges are the ranges in which the first to third conductor layers 201a to 201c extend in the X direction. The second X range (the range in which the second conductor layer 201b extends in the X direction) has a portion overlapping the first X range (the range in which the first conductor layer 201a extends in the X direction) and a portion overlapping the third X range (the range in which the third conductor layer 201c extends in the X direction). The third X range is outside the first X range. Note that the second X range may also have an intermediate portion between the portion overlapping the first X range (the leftmost portion in FIG. 9 ) and the portion overlapping the third X range (the rightmost portion in FIG. 9 ).

[0056] The core substrate 601 has second conductor portions 202 that penetrate between the first surface SF1 and the second surface SF2 of the ceramic substrate 100. The configuration of the second conductor portions 202 may be approximately the same as the configuration of the above-described first conductor portions 201. In the ZX cross-sectional view ( FIG. 9 ), the arrangement of the second conductor portions 202 may be substantially symmetrical with respect to the arrangement of the first conductor portions 201 with respect to a symmetry axis (not shown) along the Z direction.

[0057] The core substrate 601 has at least one magnetic material portion embedded in the ceramic substrate 100, and in this embodiment, has a first magnetic material portion 301 and a second magnetic material portion 302 that are spaced apart from each other. The first magnetic material portion 301 and the second magnetic material portion 302 are intended to increase the inductance of the first conductor portion 201 and the second conductor portion 202. In the core substrate 601, the first conductor portion 201 is in contact with the first magnetic material portion 301, and the second conductor portion 202 is in contact with the second magnetic material portion 302. Note that in FIGS. 8 and 9 , the first magnetic material portion 301 and the second magnetic material portion 302 are spaced apart from each other via the ceramic substrate 100, but as a modified example, the first magnetic material portion 301 and the second magnetic material portion may be in contact with each other.

[0058] The ceramic substrate 100 is a substrate made of a sintered body. The ceramic sintered body is substantially free of organic components and may contain glass components. In other words, the ceramic substrate 100 may be made of a composite material of glass and ceramics, specifically a composite material of glass and alumina. The ceramic substrate 100 may be made of LTCC. LTCC is a ceramic that can be sintered at approximately 900°C or less, and can be sintered at a temperature well below the melting point of Ag or Cu. This allows for the simultaneous sintering of a low-electrical-resistance conductor primarily composed of Ag or Cu. LTCC primarily contains, for example, Ba-Si-Al-O elements. The ceramic substrate 100 preferably has a thermal expansion coefficient of 4 ppm / °C or more and 16 ppm / °C or less. The ceramic substrate 100 preferably has a relative dielectric constant of 8 or less and a dielectric loss tangent of 0.01 or less at 1 GHz.

[0059] The first conductor 201 is made of a sintered body, more specifically, a sintered metal, such as Ag and / or Cu. The second conductor 202 may be made of the same material.

[0060] The first magnetic body portion 301 is made of ceramics. Therefore, the first magnetic body portion 301 is made of a sintered body and does not contain organic components. In order to reduce the volume of the inductor, the magnetic material constituting the first magnetic body portion 301 preferably has high magnetic permeability, and the first magnetic body portion 301 preferably has a density of 70% or more. In order to reduce the electrical loss of the inductor, the magnetic material constituting the first magnetic body portion 301 is preferably a soft magnetic material with low magnetic loss at high frequencies. For example, a soft magnetic material with a magnetic loss tangent of 0.1 or less at a frequency of 100 MHz is preferably used. In order to reduce magnetic loss at high frequencies, the magnetic material constituting the first magnetic body portion 301 preferably has a high volume electrical resistivity, and specifically, is preferably an electrical insulator. The first magnetic body part 301 is preferably made of a ferrite-based material, and the crystal structure of the material is preferably a spinel structure from the viewpoint of ease of manufacturing, such as Ni-Zn ferrite or Ni-Zn-Cu ferrite, and from the viewpoint of high magnetic permeability, it is preferably a hexagonal structure with c-axis orientation along the thickness direction (the vertical direction in FIG. 8). The second magnetic body part 302 may be made of the same material.

[0061] The manufacturing method of the core substrate 601 may be performed using the multilayer ceramic technology as described above. The manufacturing method includes a firing process. In this firing process, the first conductor portion 201, the second conductor portion 202, the first magnetic material portion 301, and the second magnetic material portion 302 may be fired simultaneously with the ceramic substrate 100. As a result, the core substrate 601 has a sintered interface between the first conductor portion 201 and a portion of the core substrate 601 other than the first conductor portion 201. In other words, the first conductor portion 201 and the other portion are sintered to each other. Specifically, in FIG. 9 , the core substrate 601 has a sintered interface between the first conductor portion 201 and the first magnetic material portion 301. In other words, the first conductor portion 201 and the first magnetic material portion 301 are sintered to each other. The core substrate 601 also has a sintered interface between the first magnetic material portion 301 and the ceramic substrate 100. In other words, the first magnetic body 301 and the ceramic substrate 100 are sintered together. The interface between them does not contain any organic material, but is formed by bonding between inorganic materials. In other words, the interface between them is formed by inorganic bonding.

[0062] The core substrate 601 may have a connection portion 450 on the first surface SF1 of the ceramic substrate 100 that connects the first conductor portion 201 and the second conductor portion 202 to each other. As a result, the first conductor portion 201 of the inductor L1 and the second conductor portion 202 of the inductor L2 form a series circuit as shown in FIG. 6 . The series circuit has an input terminal TMin and an output terminal TMout. In this embodiment, the input terminal TMin and the output terminal TMout are disposed on the second surface SF2 of the core substrate 601. Because the second surface SF2 faces the semiconductor element 811 ( FIG. 1 ), the input terminal TMin and the output terminal TMout can be easily electrically connected to the semiconductor element 811. A current from the input terminal TMin to the output terminal TMout flows from the second surface SF2 to the first surface SF1 in the inductor L1, and flows from the first surface SF1 to the second surface SF2 in the inductor L2. The direction of the current can also be reversed.

[0063] According to the first embodiment, in the ZX cross-sectional view, the second X range (the range in which the second conductor layer 201b extends in the X direction) has a portion overlapping with the first X range (the range in which the first conductor layer 201a extends in the X direction) and a portion overlapping with the third X range (the range in which the third conductor layer 201c extends in the X direction), and the third X range is outside the first X range. As a result, the second conductor layer 201b has a portion extending outside the first X range in the X direction, and this portion contributes to the inductance. Therefore, the inductance of the inductor built into the core substrate 601 can be improved.

[0064] The core substrate 601 may have a connection portion 450 that connects the first conductor portion 201 and the second conductor portion 202 to each other. This forms a series circuit of an inductor L1 formed by the first conductor portion 201 and an inductor L2 formed by the second conductor portion 202. Therefore, a combined inductance greater than that of the inductors formed by the first conductor portion 201 and the second conductor portion 202 can be obtained.

[0065] In the ZX cross-sectional view ( FIG. 9 ), the arrangement of the second conductor portion 202 is line-symmetric with respect to the arrangement of the first conductor portion 201 with respect to the axis of symmetry along the Z direction. This facilitates the design of the inductor. Note that the above line symmetry does not need to be strict. For example, as shown in FIG. 10 , when a circuit formed by the first conductor portion 201 and the second conductor portion 202 is grasped by linear approximation, if the circuit has line symmetry, the first conductor portion 201 and the second conductor portion 202 are considered to have the above line symmetry. In this case, irregularities of the order of normal manufacturing errors in multilayer ceramic technology may be ignored.

[0066] The ceramic substrate 100 may be made of LTCC or a composite material of glass and alumina, which makes it easier to form the ceramic substrate 100 and the first conductors 201 by co-firing in the manufacture of the core substrate 601.

[0067] The core substrate 601 has a sintered interface between the first conductor 201 and the portion of the core substrate 601 other than the first conductor 201. This prevents the heat resistance of the core substrate 601 from being reduced due to the low heat resistance of the organic adhesive, unlike when the first conductor 201 is joined to the portion of the core substrate 601 other than the first conductor 201 via an organic adhesive. This makes it possible to improve the heat resistance of the core substrate 601.

[0068] The interposer 700 on which a semiconductor element is to be mounted has a core substrate 601. The inductance of the inductor built into the core substrate 601 can be improved for the reasons described above. Therefore, the inductance of the inductor included in the interposer 700 can be improved.

[0069] <Embodiment 2> Fig. 11 is a partial cross-sectional view schematically showing the configuration of a core substrate 602 in embodiment 2. Fig. 12 is a diagram schematically showing current paths in the configuration of Fig. 11. In core substrate 602, in the ZX cross-sectional view (Fig. 11), the arrangement of second conductor portions 202 is obtained by substantially translating the arrangement of first conductor portions 201 along the X direction. Note that the other configurations are substantially the same as those in embodiment 1 described above, and therefore the same or corresponding elements are designated by the same reference numerals, and description thereof will not be repeated.

[0070] According to the second embodiment, in the ZX cross-sectional view ( FIG. 11 ), the second conductor portion 202 is arranged by shifting the first conductor portion 201 parallel to the X direction. This reduces the likelihood of forming a location in the vicinity of both the first conductor portion 201 and the second conductor portion 202 where the magnetic field caused by the current in the first conductor portion 201 and the magnetic field caused by the current in the third conductor portion 202 reinforce each other according to Ampere's law. This reduces the likelihood of magnetic saturation occurring in that location. This improves the DC superposition characteristics of the inductor built into the core substrate 602.

[0071] <Third Embodiment> Fig. 13 is a partial top view schematically illustrating the configuration of a core substrate 603 in a third embodiment. Fig. 14 is a partial cross-sectional view taken along line XIV-XIV in each of Figs. 13 and 16. Fig. 15 is a partial cross-sectional view taken along line XV-XV in each of Figs. 13 and 16. Fig. 16 is a partial cross-sectional view taken along line XVI-XVI in each of Figs. 13 to 15. Fig. 17 is a diagram schematically illustrating a current path in the configuration of Figs. 14 and 15. Note that the symbol combining a circle and an X in the current path shown in Fig. 17 represents an extension from the front to the back of the page.

[0072] The core substrate 603 has a laminated structure (see dashed lines in Figures 14 to 16) formed using laminated ceramic technology, and this laminated structure includes a first layer a to a fourth layer d. Hereinafter, the portions of the ceramic substrate 100 located on the first layer a to the fourth layer d will also be referred to as the first ceramic layer 100a to the fourth ceramic layer 100d. The first ceramic layer 100a to the fourth ceramic layer 100d are laminated in this order. The portions of the first conductor portion 201 located on the first layer a to the fourth layer d will also be referred to as the first conductor layer 201a to the fourth conductor layer 201d. The first conductor layer 201a to the fourth conductor layer 201d are laminated in this order. The first conductor layer 201a to the fourth conductor layer 201d each penetrate the first ceramic layer 100a to the fourth ceramic layer 100d.

[0073] In a YZ cross-sectional view ( FIG. 16 ) parallel to the Y and Z directions, the second to fourth conductor layers 201b to 201d are arranged in first to third Y ranges, respectively, in the Y direction. In other words, the first to third Y ranges are ranges in which the second to fourth conductor layers 201b to 201d extend in the Y direction. The second Y range (the range in which the third conductor layer 201c extends in the Y direction) has a portion that overlaps with the first Y range (the range in which the second conductor layer 201b extends in the Y direction) and a portion that overlaps with the third Y range (the range in which the fourth conductor layer 201d extends in the Y direction). The third Y range is outside the first Y range. The second Y range may also have an intermediate portion between the portion overlapping with the first Y range (the leftmost portion in FIG. 16) and the portion overlapping with the third Y range (the rightmost portion in FIG. 16).

[0074] Note that the configuration other than that described above is substantially the same as that of the first or second embodiment, and therefore the same or corresponding elements are given the same reference numerals and their description will not be repeated.

[0075] According to the third embodiment, in the YZ cross-sectional view ( FIG. 16 ), the second Y range (the range in which the third conductor layer 201c extends in the Y direction) has a portion that overlaps with the first Y range (the range in which the second conductor layer 201b extends in the Y direction) and a portion that overlaps with the third Y range (the range in which the fourth conductor layer 201d extends in the Y direction), and the third Y range is outside the first Y range. As a result, the third conductor layer 201c has a portion that extends outside the first Y range in the Y direction, and this portion contributes to the inductance. Therefore, the inductance of the inductor built into the core substrate 603 can be further improved.

[0076] <Fourth Embodiment> Fig. 18 is a partial top view schematically showing the configuration of a core substrate 604 in a fourth embodiment. Fig. 19 is a partial cross-sectional view taken along line XIX-XIX in Fig. 18. Figs. 20 and 21 are plan views each schematically showing the configuration of the second layer b and the fourth layer d of the core substrate 604 in Fig. 19. Fig. 22 is a diagram schematically showing a current path in the configuration in Fig. 19. Note that the symbol combining a circle and an X in the current path shown in Fig. 22 represents an extension from the front to the back of the page.

[0077] As in the first embodiment, the ceramic substrate 100 has first to fifth ceramic layers located on the first to fifth layers (FIG. 19), respectively, which are also referred to as the first to fifth ceramic layers 100a to 100e. The first conductor portion 201 has first to fifth conductor layers located on the first to fifth layers (FIG. 19), respectively, which are also referred to as the first to fifth conductor layers 201a to 201e.

[0078] In a field of view parallel to the X and Y directions, i.e., in a plan view (FIG. 20), the second conductor layer 201b includes a first region RG1 to a fourth region RG4. The second conductor layer 201b extends so that the first region RG1 to the fourth region RG4 continue in this order. The second conductor layer 201b is outside a region RD1 between the second region RG2 and the fourth region RG4. The region RD1 is a region sandwiched in one direction by the second region RG2 and the fourth region RG4, and in FIG. 20, it is a region sandwiched in the X direction. As shown in FIG. 20, the second conductor layer 201b may extend in an approximately U-shape.

[0079] The first conductor layer 201a (the first conductor portion 201 located on the a layer in FIG. 19) is connected to the first region RG1 at a distance from the second region RG2 to the fourth region RG4 of the second conductor layer 201b (FIG. 20). The third conductor layer 201c (the first conductor portion 201 located on the third layer c in FIG. 19) is connected to the fourth region RG4 at a distance from the first region RG1 to the third region RG3 of the second conductor layer 201b. In the configuration shown in FIG. 20, the fourth region RG4 has a connection portion RG4a and a path portion RG4b, and the third conductor layer 201c is connected to the connection portion RG4a rather than the path portion RG4b. The path portion RG4b connects the connection portion RG4a and the third region RG3 to each other.

[0080] In a plan view ( FIG. 21 ), the fourth conductor layer 201d includes a fifth region RG5 to an eighth region RG8. The fourth conductor layer 201d extends such that the fifth region RG5 to the eighth region RG8 continue in this order. The fourth conductor layer 201d is outside the region RD2 between the sixth region RG6 and the eighth region RG8. The region RD2 is a region sandwiched in one direction between the sixth region RG6 and the eighth region RG8, and in FIG. 21 , it is a region sandwiched in the Y direction.

[0081] The third conductor layer 201c (the first conductor portion 201 located on the third layer c in FIG. 19) is connected to the fifth region RG5 at a distance from the sixth region RG6 to the eighth region RG8 of the fourth conductor layer 201d (FIG. 21). The fifth conductor layer 201e (the first conductor portion 201 located on the fifth layer e in FIG. 19) is connected to the eighth region RG8 at a distance from the fifth region RG5 to the seventh region RG7 of the fourth conductor layer 201d. In the configuration shown in FIG. 21, the eighth region RG8 has a connection portion RG8a and a path portion RG8b, and the fifth conductor layer 201e (the first conductor portion 201 located on the fifth layer e in FIG. 19) is connected to the connection portion RG8a, not the path portion RG8b. The path portion RG8b connects the connection portion RG8a and the seventh region RG7 to each other.

[0082] The first region RG1 to the fourth region RG4 (FIG. 20) of the second conductor layer 201b constitute a first current path extending in this order. The first current path includes a first section extending with a first directional vector V1a. Note that the first current path may also include a section extending with a directional vector V1b. The fifth region RG5 to the eighth region RG8 (FIG. 21) of the fourth conductor layer 201d constitute a second current path extending in this order. The second current path includes a second section extending with a second directional vector V2a. Note that the second current path may also include a section extending with a directional vector V2b.

[0083] The dot product of the first direction vector V1a ( FIG. 20 ) of the first section of the first current path and the second direction vector V2a ( FIG. 21 ) of the second section of the second current path is positive. Furthermore, they may be substantially the same as each other, and in the example shown in FIGS. 20 and 21 , they are both oriented in the positive Y direction. Similarly, the dot product of the direction vector V1b ( FIG. 20 ) of the other section of the first current path and the direction vector V2b ( FIG. 21 ) of the other section of the second current path may be positive. Furthermore, they may be substantially the same as each other, and in the example shown in FIGS. 20 and 21 , they are both oriented in the negative X direction.

[0084] In a plan view, the second conductor layer 201b (FIG. 20) has a second region RG2 as a first portion corresponding to the first section of the first current path. The fourth conductor layer 201d (FIG. 21) has a seventh region RG7 as a second portion corresponding to the second section of the second current path. The first portion (second region RG2) and the second portion (seventh region RG7) may at least partially overlap in a plan view, in other words, in the layout in the XY plane.

[0085] Note that the configuration other than that described above is substantially the same as that of the first or second embodiment, and therefore the same or corresponding elements are given the same reference numerals and their description will not be repeated.

[0086] According to the fourth embodiment, the second conductor layer 201b (FIG. 20) is outside the region RD1 between the second region RG2 and the fourth region RG4. As a result, the third region RG3 of the first conductor portion 201 extends so as to bypass the region RD1 between the second region RG2 and the fourth region RG4. This further improves the inductance of the inductor L1 formed by the first conductor portion 201.

[0087] The dot product of the first directional vector V1a of the first current path in the second conductor layer 201b (FIG. 20) and the second directional vector V2a of the second current path in the fourth conductor layer 201d is positive. As a result, according to Ampere's law, the magnetic field caused by the current flowing in the first section and the magnetic field caused by the current flowing in the second section mitigate each other. This makes it difficult for a magnetic saturation state to occur between the first and second sections. This improves the DC bias characteristics of the inductor built into the core substrate 604. When the first directional vector V1a and the second directional vector V2a are substantially the same, the magnetic field mitigation effect is enhanced, thereby further improving the DC bias characteristics.

[0088] In a plan view, the first portion (second region RG2) corresponding to the first section of the first current path and the second portion (seventh region RG7) corresponding to the second section of the second current path at least partially overlap. This enhances the mutual attenuation effect of the magnetic fields caused by the current flowing in the first section and the magnetic fields caused by the current flowing in the second section. This further improves the DC superposition characteristics of the inductor built into the core substrate 604.

[0089] The above-described embodiments and modifications may be freely combined with each other. Although the present invention has been described in detail, the above description is illustrative in all respects and does not limit the present invention. It is understood that countless modifications not illustrated can be envisioned without departing from the scope of the present invention.

[0090] 100: Ceramic substrate 301, 302: First and second magnetic material portions 450: Connection portions 600 to 604: Core substrate 700: Interposer 791: Wiring layer 811: Semiconductor element 901, 902: Electronic device L1 to L6: First to sixth inductors RG1 to RG8: First to eighth regions SC: Mounting surface SF1, SF2: First and second surfaces V1a, V2a: First and second direction vectors a to e: First to fifth layers

Claims

1. A core substrate with an embedded inductor for configuring an interposer on which a semiconductor element is mounted, comprising: a ceramic substrate having a laminated structure formed by stacking a plurality of ceramic layers in the Z direction, the ceramic substrate having a first surface and a second surface opposite each other in the Z direction in an orthogonal coordinate system having an X direction, a Y direction, and a Z direction, the plurality of ceramic layers including a first ceramic layer, a second ceramic layer, and a third ceramic layer, the first ceramic layer, the second ceramic layer, and the third ceramic layer being stacked in this order; the core substrate further comprising: a first conductor portion made of a sintered body penetrating the ceramic substrate from the first surface to the second surface, the first conductor portion including a first conductor layer penetrating the first ceramic layer, a second conductor layer penetrating the second ceramic layer, and a third conductor layer penetrating the third ceramic layer; the core substrate further comprising: a first magnetic portion made of ceramics embedded in the ceramic substrate for increasing the inductance of the first conductor portion; a core substrate, in which, in a ZX cross-sectional view parallel to the Z direction and the X direction, the first conductor layer, the second conductor layer, and the third conductor layer are arranged in a first X range, a second X range, and a third X range, respectively, with respect to the X direction, the second X range has a portion overlapping the first X range and a portion overlapping the third X range, and the third X range is outside the first X range.

2. A core substrate according to claim 1, comprising: a second conductor portion made of a sintered body and penetrating between the first surface and the second surface of the ceramic substrate; a second magnetic portion for increasing the inductance of the second conductor portion; and a connecting portion for connecting the first conductor portion and the second conductor portion to each other on the first surface of the ceramic substrate.

3. A core substrate according to claim 2, wherein, in the ZX cross-sectional view, the arrangement of the second conductor portions is symmetrical with respect to the arrangement of the first conductor portions with respect to an axis of symmetry along the Z direction.

4. A core substrate according to claim 2, wherein, in the ZX cross-sectional view, the second conductor portions are arranged such that the first conductor portions are arranged parallel to the X direction.

5. A core substrate according to any one of claims 1 to 4, wherein the plurality of ceramic layers includes a fourth ceramic layer, and the first ceramic layer, the second ceramic layer, the third ceramic layer, and the fourth ceramic layer are laminated in this order; the first conductor portion includes a fourth conductor layer penetrating the fourth ceramic layer; and in a YZ cross-sectional view parallel to the Y direction and the Z direction, the second conductor layer, the third conductor layer, and the fourth conductor layer are respectively arranged in a first Y range, a second Y range, and a third Y range with respect to the Y direction, the second Y range having a portion overlapping the first Y range and a portion overlapping the third Y range, and the third Y range being outside the first Y range.

6. A core substrate according to any one of claims 1 to 4, wherein, in a plan view parallel to the X direction and the Y direction, the second conductor layer of the first conductor portion includes a first region, a second region, a third region, and a fourth region, the second conductor layer extends so that the first region, the second region, the third region, and the fourth region continue in this order, the second conductor layer being out of the region between the second region and the fourth region, the first conductor layer being connected to the first region at a distance from the second region, the third region, and the fourth region of the second conductor layer, and the third conductor layer being connected to the fourth region at a distance from the first region, the second region, and the third region of the second conductor layer.

7. A core substrate according to claim 6, wherein the plurality of ceramic layers include a fourth ceramic layer and a fifth ceramic layer, and the first ceramic layer, the second ceramic layer, the third ceramic layer, the fourth ceramic layer and the fifth ceramic layer are laminated in this order; the first conductor portion includes a fourth conductor layer penetrating the fourth ceramic layer and a fifth conductor layer penetrating the fifth ceramic layer; in the plan view, the fourth conductor layer of the first conductor portion includes a fifth region, a sixth region, a seventh region and an eighth region, and the fourth conductor layer extends so that the fifth region, the sixth region, the seventh region and the eighth region follow in this order, and the fourth conductor layer is off-limits to a region between the sixth region and the eighth region; the third conductor layer is connected to the fifth region at a distance from the sixth region, the seventh region and the eighth region of the fourth conductor layer, and the fifth conductor layer is connected to the eighth region at a distance from the fifth region, the sixth region and the seventh region of the fourth conductor layer; a core substrate, wherein the first region, the second region, the third region, and the fourth region of the second conductor layer form a first current path extending in this order, the first current path including a first section extending with a first direction vector; and the fifth region, the sixth region, the seventh region, and the eighth region of the fourth conductor layer form a second current path extending in this order, the second current path including a second section extending with a second direction vector, and an inner product of the first direction vector and the second direction vector is positive.

8. A core substrate according to claim 7, wherein the first direction vector of the first section of the first current path of the second conductor layer is the same as the second direction vector of the second section of the second current path of the fourth conductor layer.

9. A core substrate as described in claim 7, wherein, in the plan view, the second conductor layer has a first portion corresponding to the first section of the first current path, and the fourth conductor layer has a second portion corresponding to the second section of the second current path, and the first portion and the second portion at least partially overlap.

10. A core substrate according to any one of claims 1 to 4, wherein the ceramic substrate is made of low-temperature co-fired ceramics or a composite material of glass and alumina.

11. A core substrate according to any one of claims 1 to 4, wherein a sintered interface is formed between the first conductor portion and a portion of the core substrate other than the first conductor portion.

12. An interposer comprising: a core substrate according to any one of claims 1 to 4; and a wiring layer laminated on the core substrate, the wiring layer having a mounting surface on which the semiconductor element is to be mounted.

Images