Quantum verification circuit and method for verifying quantum gate by using same

Abstract

This quantum verification circuit comprises: a first verification circuit unit to which a plurality of qubits are input, and which performs an operation based on the qubits so as to output same to a gate to be verified; and a second verification circuit unit to which qubits in an entangled state are input from the gate to be verified, and which performs an operation based on the qubits in the entangled state, and receives an output of the second verification circuit unit, and determines the entangled state of the qubits so as to determine whether the gate to be verified is normally implemented.

Description

Quantum verification circuit and verification method of quantum gate using the same

[0001] The present invention relates to a quantum verification circuit and a method for verifying quantum gates using the same. More specifically, the present invention relates to a quantum verification circuit for implementing the hardware of a quantum computer and a method for verifying quantum gates using the same.

[0002] It is known that some algorithms that increase exponentially in computational complexity on conventional computers can be executed in polynomial time on quantum computers. Unlike conventional computers, quantum computers possess extremely high parallelism due to the properties of quantum entanglement and quantum superposition. Consequently, quantum computing has been utilized to elucidate previously intractable physical phenomena and chemical principles. However, due to the difficulty of implementing quantum computers, quantum measurement errors are very serious. Consequently, research on computers that tolerate quantum defects and quantum error correction technologies are advancing.

[0003] Quantum algorithms are developed at the circuit level for quantum information processing, and quantum circuits can be created in various versions for experimentation. In digital logic circuits, complex and diverse logic gates such as NAND or NOR gates can be used. Similarly, research is underway to identify a universal gate set, which proves that circuits can be replaced with other gates to design gate-based algorithms in quantum circuits. Universal gate sets include the Hadamard gate, the T-gate, and the CNOT (Controlled NOT, CX gate).

[0004] One object of the present invention is to provide a quantum verification circuit for effectively verifying the implementation of a CNOT gate.

[0005] Another object of the present invention is to provide a method for verifying a quantum gate using the quantum verification circuit.

[0006] However, the purpose of the present invention is not limited to the above-described purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0007] In order to achieve the above-described object of the present invention, a quantum verification circuit according to an embodiment of the present invention may include a first verification circuit unit that inputs a plurality of qubits, performs an operation based on the qubits, and outputs the result to a verification target gate, a second verification circuit unit that inputs entangled qubits from the verification target gate, and performs an operation based on the entangled qubits, and a measurement unit that receives an output of the second verification circuit unit, determines an entanglement state of the qubits, and determines whether the verification target gate is normally implemented.

[0008] In one embodiment, the verification target gate may be a CNOT gate.

[0009] In one embodiment, the first verification circuit unit may include at least one selected from the group consisting of a Pauli-X-gate, a CNOT gate, and a Hadamard gate, and the second verification circuit unit may include a Hadamard gate.

[0010] In one embodiment, the first verification circuit may further include a controlled Hadamard gate defined as a gate that performs a matrix operation according to the following [Formula 1].

[0011] [Formula 1]

[0012]

[0013] In one embodiment, the first to fourth qubits can be input into the first verification circuit.

[0014] In one embodiment, the first verification circuit unit can generate an output according to the following [Formula 2] including first to third vectors based on the first to fourth qubits.

[0015] [Formula 2]

[0016]

[0017] Here, means the output of the first verification circuit section, means the first vector above, means the second vector, means the third vector, and 1, 2, 1', 2' mean the first qubit, the second qubit, the third qubit, and the fourth qubit, respectively. , , and is defined by [Formula 3] below.

[0018] [Formula 3]

[0019]

[0020] In one embodiment, the first to third vectors may be orthogonal to each other.

[0021] In one embodiment, when each of the first to fourth qubits is input as |0>, the measuring unit can measure a verification probability defined as the probability that the values ​​of the qubits output from the second verification circuit are all 0 based on the first and second qubits, thereby determining whether the verification target gate is normally implemented.

[0022] In one embodiment, if the value of the verification probability is less than about 0.125, the measurement unit can determine that the normal implementation of the verification target gate has been successful.

[0023] In one embodiment, when the value of the verification probability is greater than or equal to about 0.125 and less than or equal to about 0.375, the measuring unit may determine that normal implementation of the verification target gate has failed.

[0024] In one embodiment, the second verification circuit may include at least one selected from the group consisting of a Pauli-X-gate, a CNOT gate, and a Hadamard gate.

[0025] In one embodiment, the second verification circuit may further include a controlled Hadamard gate, and the first verification circuit may include a Hadamard gate.

[0026] In one embodiment, when each of the first to fourth qubits is input as |0>, the measurement unit can determine whether the verification target gate is normally implemented by calculating the sum of measurement probabilities defined as the probability that the value for each of the first and second qubits output from the second verification circuit has a specific value.

[0027] In one embodiment, the specific value for each of the first and second qubits is 0, and the measurement unit can calculate the sum of the measurement probabilities according to [Formula 4] below.

[0028] [Formula 4]

[0029]

[0030] Here, is the above verification probability, are the measurement probabilities, respectively, and a, b, c, and d represent the values ​​output to the measurement unit for the first to fourth qubits, respectively.

[0031] In one embodiment, if the value of the verification probability is less than 0.125, the measurement unit can determine that the normal implementation of the verification target gate has been successful.

[0032] In one embodiment, the measurement unit can determine whether the verification target gate is normally implemented by calculating a verification probability defined as a probability that the value of each of the first to fourth qubits output from the second verification circuit has a specific value.

[0033] In order to achieve another object of the present invention described above, a method for verifying a quantum gate according to an embodiment of the present invention may include a step of generating qubits in a preliminary state for verification based on at least two or more qubits, a step of inputting the qubits in the preliminary state into a gate to be verified to generate an entanglement state, and a step of measuring the entanglement state to determine whether the gate to be verified is normally implemented.

[0034] In one embodiment, in the step of generating the qubits in the preliminary state, the qubits in the preliminary state are generated based on the first and second qubits, and each of the first and second qubits and the third and fourth qubits is input with a value of |0>, and in the step of determining whether the gate to be verified is normally implemented, the sum of measurement probabilities defined as the probability that each value of the qubits output based on the first and second qubits has a specific value can be calculated to determine whether the gate to be verified is normally implemented.

[0035] In one embodiment, in the step of determining whether the verification target gate is normally implemented, the specific value output based on the first and second qubits is 0, the verification probability is calculated according to [Formula 5] below, and when the verification probability is less than 0.125, it can be determined that the normal implementation of the verification target gate is successful.

[0036] [Formula 5]

[0037]

[0038] Here, is the above verification probability, are the measurement probabilities, respectively, and a, b, c, and d represent the values ​​output to the measurement unit for the first to fourth qubits, respectively.

[0039] In one embodiment, in the step of generating the qubits in the preliminary state, the qubits in the preliminary state are generated based on the first to fourth qubits, and in the step of determining whether the gate to be verified is normally implemented, if the probability that the values ​​of the qubits output based on the first and second qubits are all 0 is less than 0.125, it is determined that the normal implementation of the gate to be verified is successful, and in the step of determining whether the gate to be verified is normally implemented, if the probability that the values ​​of the qubits output based on the first and fourth qubits are all 0 is 0.125 or more and 0.375 or less, it is determined that the normal implementation of the gate to be verified is failed.

[0040] In a quantum verification circuit according to embodiments of the present invention and a verification method of a quantum gate using the quantum verification circuit, a verification target gate is placed between a first verification circuit and a second verification circuit, and the states of qubits passing through the first verification circuit, the verification target gate, and the second verification circuit are measured to determine whether the verification target gate is normally implemented, so it is possible to easily determine whether the quantum gate, which is the verification target gate, succeeds or fails to implement an entanglement state. Accordingly, the verification accuracy and efficiency of the quantum gate (e.g., a CNOT gate) implementing an entanglement state can be improved. Accordingly, since the quantum gate can be applied to a quantum circuit and a device, the performance of the quantum circuit and the device using the quantum gate can be improved.

[0041] However, the effects of the present invention are not limited to the effects described above, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0042] FIG. 1 is a block diagram showing the operation of a quantum verification circuit according to one embodiment of the present invention.

[0043] Fig. 2 is a diagram showing an example of the quantum verification circuit of Fig. 1.

[0044] Figure 3 is a drawing showing the first verification circuit part of Figure 2.

[0045] Fig. 4 is a diagram showing the second verification circuit unit of Fig. 2.

[0046] Figures 5 to 7 are drawings showing a quantum gate verification method using the quantum verification circuit of Figure 2.

[0047] Fig. 8 is a diagram showing another example of the quantum verification circuit of Fig. 1.

[0048] Fig. 9 is a drawing showing the first verification circuit part of Fig. 8.

[0049] Fig. 10 is a drawing showing the second verification circuit of Fig. 8.

[0050] Figures 11 to 13 are drawings showing a quantum gate verification method using the quantum verification circuit of Figure 8.

[0051] Figures 14 to 16 are drawings for explaining the effect of the quantum verification circuit of Figure 1.

[0052] With respect to the embodiments of the present invention disclosed in the text, specific structural and functional descriptions are merely illustrative for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms and should not be construed as being limited to the embodiments described in the text.

[0053] The present invention is susceptible to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the present invention to specific disclosed forms, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

[0054] While terms like "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms may be used to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a "second component," and similarly, a second component could also be referred to as a "first component."

[0055] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Other expressions that describe the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", should be interpreted similarly.

[0056] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a described feature, number, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0057] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by those of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0058] Meanwhile, if a particular embodiment can be implemented differently, the functions or operations specified within a particular block may occur in a different order than specified in the flowchart. For example, two consecutive blocks may actually be executed substantially simultaneously, or, depending on the related functions or operations, the blocks may be executed in reverse order.

[0059] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings will be designated by the same reference numerals, and redundant descriptions of identical components will be omitted.

[0060] FIG. 1 is a block diagram showing the operation of a quantum verification circuit according to one embodiment of the present invention.

[0061] Referring to FIG. 1, at least one qubit may be input into a quantum verification circuit (100) according to an embodiment of the present invention. For example, a system qubit (SQB) and an auxiliary qubit (AQB) may be input into the quantum verification circuit (100). The system qubit (SQB) may include a first qubit (QB1) and a second qubit (QB2). The auxiliary qubit (AQB) may include a third qubit (QB3) and a fourth qubit (QB4). The first to fourth qubits (QB1, QB2, QB3, QB4) may have different or the same values. Although the number of qubits input into the quantum verification circuit (100) is illustrated as four, the number of qubits input into the quantum verification circuit (100) according to embodiments of the present invention is not limited thereto, and various numbers of qubits may be input into the quantum verification circuit (100).

[0062] The quantum verification circuit (100) may be connected to the verification target gate (200). For example, the quantum verification circuit (100) may be connected to one end of the verification target gate (200) and the other end opposite to the one end, respectively. Accordingly, the quantum verification circuit (100) may adjust, measure, or control the states of the qubits input to the verification target gate (200) and the qubits output from the verification target gate (200). The first to fourth qubits (QB1, QB2, QB3, QB4) may be in a superposition state or an entangled state as they pass through the quantum verification circuit (100) and the verification target gate (200). The quantum verification circuit (100) may perform an operation based on the first to fourth qubits (QB1, QB2, QB3, QB4). The verification target gate (200) can perform operations based on the first and second qubits (QB1, QB2). However, the number of qubits on which the quantum verification circuit (100) and the verification target gate (200) according to embodiments of the present invention can perform operations is not limited thereto, and each of the quantum verification circuit (100) and the verification target gate (200) can perform operations on a variety of qubits.

[0063] In one embodiment, the verification target gate (200) may be a CNOT (controlled NOT) gate. Qubits passing through the CNOT gate may be in a quantum entangled state. The CNOT gate may include a target unit and a control unit. A control qubit for control may be input to the control unit, and a target qubit corresponding to the target may be input to the target unit. The CNOT gate may perform an operation based on a Pauli-X-gate on the target qubit according to the state of the control qubit, or may pass the target qubit as is. Specifically, the CNOT gate may pass the target qubit input to the CNOT gate as is when the control qubit input to the CNOT gate is |0>. In addition, the CNOT gate may perform an operation by a Pauli-X-gate on the target qubit input to the CNOT gate when the control qubit input to the CNOT gate is |1>.

[0064] The output of the verification target gate (200) can be input to the quantum verification circuit (100). The quantum verification circuit (100) can perform an operation based on the output of the verification target gate (200). After performing the operation, the quantum verification circuit (100) can output qubits based on the first to fourth qubits (QB1, QB2, QB3, QB4). In addition, the quantum verification circuit (100) can generate a probability distribution of the values ​​of the output qubits. The quantum verification circuit (100) can determine whether the verification target gate (200) is normally implemented using the values ​​of the probability distribution.

[0065] Fig. 2 is a diagram showing an example of the quantum verification circuit of Fig. 1. Fig. 3 is a diagram showing a first verification circuit section of Fig. 2. Fig. 4 is a diagram showing a second verification circuit section of Fig. 2.

[0066] Referring to FIGS. 1 to 4, the quantum verification circuit (100) may include a first verification circuit unit (110), a second verification circuit unit (120), and a measurement unit (130). The first verification circuit unit (110) may be connected to one end of a verification target gate (200). The second verification circuit unit (120) may be connected to the other end of the verification target gate (200) opposite to the one end.

[0067] The system qubit (SQB) and the auxiliary qubit (AQB) can be input to the first verification circuit unit (110). For example, the first verification circuit unit (110) can receive the first to fourth qubits (QB1, QB2, QB3, QB4) and perform an operation based on the first to fourth qubits (QB1, QB2, QB3, QB4) to generate qubits in a preliminary state for verification. The qubits in the preliminary state can be input to the verification target gate (200). Qubits based on the system qubit (SQB) can be input to the verification target gate (200). Qubits based on the system qubit (SQB) can be input to the second verification circuit unit (120). The measurement unit (130) can measure qubits based on the system qubit (SQB). In addition, the measurement unit (130) can generate a probability distribution using the values ​​of the qubits based on the system qubit (SQB) to determine whether the verification target gate (200) is normally implemented.

[0068] The first verification circuit unit (110) may include a Pauli-X gate, a CNOT gate, a Hadamard gate, and a controlled Hadamard gate. The controlled Hadamard gate may be a gate in which the target portion of the CNOT gate is replaced with the Hadamard gate. That is, the controlled Hadamard gate may include the Hadamard gate and the control portion. Specifically, the controlled Hadamard gate may perform a matrix operation according to the following [Formula 1].

[0069] [Formula 1]

[0070]

[0071] In one embodiment, the first verification circuit (110) may include a plurality of CNOT gates. For example, the first verification circuit (110) may include three CNOT gates that perform operations based on a first qubit (QB1) and a second qubit (QB2), one CNOT gate that performs operations based on a first qubit (QB1) and a third qubit (QB3), and one CNOT gate that performs operations based on a second qubit (QB2) and a fourth qubit (QB4).

[0072] The first qubit (QB1) input to the first verification circuit (110) can sequentially pass through the Hadamard gate, the control unit of the CNOT gate, the Hadamard gate included in the controlled Hadamard gate, two control units of two CNOT gates, the Hadamard gate, and the control unit of the CNOT gate.

[0073] The second qubit (QB2) input to the first verification circuit (110) can sequentially pass through the Pauli-X-gate, the target portion of the CNOT gate, the control portion included in the controlled Hadamard gate, the target portion of the CNOT gate, the control portion of the CNOT gate, and the target portion of the CNOT gate.

[0074] In one embodiment, the first verification circuit unit (110) can output according to the following [Formula 2] including the first to third vectors based on the first to fourth qubits (QB1, QB2, QB3, QB4).

[0075] [Formula 2]

[0076]

[0077] Here, means the output of the first verification circuit section, means the first vector above, means the second vector, means the third vector, and 1, 2, 1', 2' mean the first qubit, the second qubit, the third qubit, and the fourth qubit, respectively. , , and is defined by [Formula 3] below.

[0078] [Formula 3]

[0079]

[0080] In one embodiment, the first to third vectors may be orthogonal to each other. For example, the first vector may be |10>, the second vector may be |01>, and the second vector may be |11>. However, the combination of the first to third vectors according to embodiments of the present invention is not limited thereto.

[0081] However, the arrangement of gates included in the first verification circuit unit (110) according to embodiments of the present invention is not limited thereto, and depending on the number of input qubits, the type of input qubits, the combination of the basis states of the input qubits, etc., the arrangement of gates included in the first verification circuit unit (110) may have various arrangements, or one or more gates may be added or removed from the first verification circuit unit (110).

[0082] The second verification circuit unit (120) may include the Hadamard gate. The Hadamard gate may perform an operation based on the first qubit (QB1). However, the arrangement of the Hadamard gate included in the second verification circuit unit (120) according to embodiments of the present invention is not limited thereto, and the Hadamard gate may be arranged to perform an operation based on one of the second to fourth qubits (QB2, QB3, QB4).

[0083] Figures 5 to 7 are drawings showing a quantum gate verification method using the quantum verification circuit of Figure 2.

[0084] Referring to FIGS. 5 to 7, the first to fourth qubits (QB1, QB2, QB3, QB4) can be input to the quantum verification circuit (100). For example, the first to fourth qubits (QB1, QB2, QB3, QB4) can each be input as |0> to the first verification circuit unit (110). Specifically, the first to fourth qubits (QB1, QB2, QB3, QB4) can be input as |0>|0>|0>|0>. However, the combination of the first to fourth qubits (QB1, QB2, QB3, QB4) input to perform the quantum gate verification method according to embodiments of the present invention is not limited thereto, and each of the first to fourth qubits (QB1, QB2, QB3, QB4) is input as |0> or |1>, so that the input of the first to fourth qubits (QB1, QB2, QB3, QB4) may form a variety of combinations.

[0085] The first verification circuit unit (110) can generate qubits in a preliminary state for verification based on the first to fourth qubits (QB1, QB2, QB3, QB4). The qubits in the preliminary state can be input to the verification target gate (200). The verification target gate (200) can generate an entangled state by operating the qubits in the preliminary state. For example, the verification target gate (200) can generate an entangled state by operating the qubits in the preliminary state based on the first qubit (QB1) and the second qubit (QB2).

[0086] The output of the verification target gate (200) can be output to the second verification circuit unit (120). Since the verification target gate (200) performed an operation based on the first qubit (QB1) and the second qubit (QB2), the second verification circuit unit (120) can also perform an operation based on the first qubit (QB1) and the second qubit (QB2). The output of the second verification circuit unit (120) can be input to the measurement unit (130). Since the second verification circuit unit (120) performed an operation based on the first qubit (QB1) and the second qubit (QB2), the measurement unit (130) can also measure the qubits based on the first qubit (QB1) and the second qubit (QB2) to determine whether the verification target gate (200) is normally implemented.

[0087] In one embodiment, the measurement unit (130) can measure the entanglement state generated by the verification target gate (200) to determine whether the verification target gate (200) is normally implemented. For example, since the verification target gate (200), which is a CNOT gate, is a gate that generates an entanglement state, the measurement unit (130) can determine that the verification target gate (200) is normally implemented as the verification probability of the first to fourth qubits (QB1, QB2, QB3, QB4) is lower. In addition, the measurement unit (130) can determine that the verification target gate (200) is not normally implemented as the verification probability of the first to fourth qubits (QB1, QB2, QB3, QB4) is higher.

[0088] Specifically, when the first to fourth qubits (QB1, QB2, QB3, QB4) are each input to the first verification circuit (110) as |0>, the measurement unit (130) can generate a probability distribution of the values ​​of the qubits output based on the first qubit (QB1) and the second qubit (QB2). The probability distribution can include the probability that the values ​​of the qubits have 00, 01, 10, and 11, respectively. For example, the probability distribution can include the probability P when the values ​​of the qubits are 00. 00 , the probability P when the values ​​of the above qubits are 01 01 , the probability P when the values ​​of the above qubits are 10 10 , the probability P when the values ​​of the above qubits are 11 11 All of these can include the probability that the values ​​of the qubits are all 0 (for example, the probability P when the values ​​of the qubits are 00) 00 ) is less than about 0.125, the measurement unit (130) can determine that the normal implementation of the verification target gate (200) is successful. In addition, when the verification probability is greater than or equal to about 0.125 and less than or equal to about 0.375, the measurement unit (130) can determine that the normal implementation of the verification target gate (200) is unsuccessful. In addition, when the verification probability is greater than or equal to about 0.375, the measurement unit (130) can determine that the normal implementation of the verification target gate (200) is successful. In the case where the verification probability is greater than or equal to about 0.375, the verified target gate can generate a Psi (-) state.

[0089] Specifically, when the first to fourth qubits (QB1, QB2, QB3, QB4) are input as |0>|0>|0>|0>, the measurement unit (130) outputs the first measurement probability P, which is the probability that |0>|0>|0>|0> 0000 The second measurement probability P is the probability that |0>|0>|0>|1> will be output. 0001The third measurement probability P is the probability that |0>|0>|1>|0> will be output. 0010 The fourth measurement probability P is the probability that |0>|0>|1>|1> will be output. 0011 can be measured. The measuring unit (130) can calculate the sum of the first to fourth measurement probabilities. In one embodiment, the measuring unit (130) can calculate the sum of the first to fourth measurement probabilities according to the following [Formula 4].

[0090] [Formula 4]

[0091]

[0092] Here, is the above verification probability, are the measurement probabilities, respectively, and a, b, c, and d represent the values ​​output to the measurement unit for the first to fourth qubits, respectively.

[0093] In one embodiment, the measurement unit (130) may determine that the verification target gate (200) is successfully implemented without error when the verification probability is 0. In addition, the measurement unit (130) may determine that the verification target gate (200) is successfully implemented with a noise ratio equal to the value obtained by multiplying the verification probability by a constant when the verification probability is greater than 0 and less than about 0.125. For example, the constant may be about 0.25. However, the range value of the verification probability and the constant value according to embodiments of the present invention are not limited thereto.

[0094] As described above, in the quantum verification circuit (100) and the quantum gate verification method using the quantum verification circuit (100), the verification target gate (200) is placed between the first verification circuit unit (110) and the second verification circuit unit (120), and the states of the qubits that have passed through the first verification circuit unit (110), the verification target gate (200), and the second verification circuit unit (120) are measured to determine whether the verification target gate (200) is normally implemented, so it is possible to easily determine whether the quantum gate, which is the verification target gate (200), has failed or succeeded in implementing the entanglement state. Accordingly, the verification accuracy and efficiency of the quantum gate (e.g., CNOT gate) that implements the entanglement state can be improved. Accordingly, since the quantum gate can be applied to a quantum circuit and a device, the performance of the quantum circuit and the device using the quantum gate can be improved.

[0095] Fig. 8 is a diagram showing another example of the quantum verification circuit of Fig. 1. Fig. 9 is a diagram showing the first verification circuit section of Fig. 8. Fig. 10 is a diagram showing the second verification circuit section of Fig. 8.

[0096] The quantum verification circuit (100A) described with reference to FIGS. 8 to 10 may be substantially the same as or similar to the quantum verification circuit (100) described with reference to FIGS. 2 to 4, except for the arrangement of the first verification circuit unit (110A) and the second verification circuit unit (120A), and the measurement target of the measurement unit (130A). Hereinafter, any content overlapping with that described with reference to FIGS. 2 to 4 will be omitted or simplified.

[0097] Referring to FIGS. 8 to 10, the quantum verification circuit (100A) may include a first verification circuit unit (110A), a second verification circuit unit (120A), and a measurement unit (130A). The first verification circuit unit (110A) may have a structure substantially the same as or similar to the second verification circuit unit (120) of FIG. 2. For example, the first verification circuit unit (110A) may include the Hadamard gate. The second verification circuit unit (120A) may have a structure substantially the same as or similar to the first verification circuit unit (110) of FIG. 2. For example, the second verification circuit unit (120A) may include the Pauli-X gate, the CNOT gate, the Hadamard gate, and the controlled Hadamard gate.

[0098] A system qubit (SQB) may be input into the first verification circuit unit (110A). For example, a first qubit (QB1) and a second qubit (QB2) may be input into the first verification circuit unit (110A). That is, an auxiliary qubit (AQB) may not be input into the first verification circuit unit (110A). Accordingly, the first verification circuit unit (110A) may perform operations based on the first qubit (QB1) and the second qubit (QB2). The first verification circuit unit (110A) may not perform operations based on the third qubit (QB3) and the fourth qubit (QB4). Accordingly, the first qubit (QB1) and the second qubit (QB2) may not create an overlapping or entanglement relationship with the third qubit (QB3) and the fourth qubit (QB4) until they pass through the second verification circuit (120A).

[0099] Since the first verification circuit unit (110A) performs an operation based on the first qubit (QB1) and the second qubit (QB2) and outputs the operation to the verification target gate (200), the verification target gate (200) can perform an operation based on the first qubit (QB1) and the second qubit (QB2). The verification target gate (200) can generate an entangled state and output the entangled state to the second verification circuit unit (120A).

[0100] The second verification circuit unit (120A) may receive the output of the verification target gate (200), the third qubit (QB3), and the fourth qubit (QB4). The second verification circuit unit (120A) may perform an operation based on the Pauli-X gate, the CNOT gate, the Hadamard gate, and the controlled Hadamard gate and output the result to the measurement unit (130A).

[0101] The measuring unit (130A) can measure qubits based on the system qubit (SQB) and the auxiliary qubit (AQB). For example, the measuring unit (130A) can measure the values ​​of qubits output based on the first to fourth qubits (QB1, QB2, QB3, QB4). Unlike the measuring unit (130) of FIG. 2, which measures the values ​​of two qubits, the measuring unit (130A) of FIG. 8 can measure the values ​​of four qubits. The measuring unit (130A) can generate a probability distribution using the values ​​of the qubits based on the system qubit (SQB) and the auxiliary qubit (AQB), and determine whether the verification target gate (200) is normally implemented.

[0102] Figures 11 to 13 are drawings showing a quantum gate verification method using the quantum verification circuit of Figure 8.

[0103] The quantum gate verification method described with reference to FIGS. 11 to 13 may be substantially the same or similar to the quantum gate verification method described with reference to FIGS. 5 to 7, except that it utilizes the quantum verification circuit (100A) of FIG. 8. Hereinafter, any content overlapping with that described with reference to FIGS. 5 to 7 is omitted or simplified.

[0104] Referring to FIGS. 11 to 13, the first to fourth qubits (QB1, QB2, QB3, QB4) can be input to the quantum verification circuit (100A). For example, the first qubit (QB1) and the second qubit (QB2) can each be input to the first verification circuit (110A) as |0>. The third qubit (QB3) and the fourth qubit (QB4) can each be input to the second verification circuit (120A) as |0> or |1>. Specifically, the first to fourth qubits (QB1, QB2, QB3, QB4) can be input as |0>|0>|0>|0>, |0>|0>|0>|1>, |0>|0>|1>|0>, |0>|0>|1>|1>. However, the combination of the first to fourth qubits (QB1, QB2, QB3, QB4) input to perform the quantum gate verification method according to embodiments of the present invention is not limited thereto, and each of the first to fourth qubits (QB1, QB2, QB3, QB4) is input as |0> or |1>, so that the input of the first to fourth qubits (QB1, QB2, QB3, QB4) may form a variety of combinations.

[0105] The first verification circuit unit (110A) can generate qubits in a preliminary state for verification based on the first qubit (QB1) and the second qubit (QB2). The qubits in the preliminary state are input to the verification target gate (200), and the verification target gate (200) can generate an entangled state by operating the qubits in the preliminary state. The output of the verification target gate (200), the third qubit (QB3), and the fourth qubit (QB4) are input to the second verification circuit unit (120A), and the second verification circuit unit (120A) can perform an operation based on the first to fourth qubits (QB1, QB2, QB3, QB4). The second verification circuit unit (120A) can perform an operation based on the first to fourth qubits (QB1, QB2, QB3, QB4) and output the operation to the measurement unit (130A). Since the second verification circuit unit (120A) performs operations based on the first to fourth qubits (QB1, QB2, QB3, QB4), the measurement unit (130A) can also measure qubits based on the first to fourth qubits (QB1, QB2, QB3, QB4) to determine whether the verification target gate (200) is normally implemented.

[0106] In one embodiment, the measuring unit (130A) can measure the verification probability, which is defined as the probability that each value of the qubits output based on the first to fourth qubits (QB1, QB2, QB3, QB4) has a specific value. For example, when the first to fourth qubits (QB1, QB2, QB3, QB4) are input as |0>|0>|0>|0>, 0>|0>|0>|1>, |0>|0>|1>|0>, |0>|0>|1>|1>, the measuring unit (130A) can measure the verification probability, which is the probability that each value of the qubits output based on the first to fourth qubits (QB1, QB2, QB3, QB4) is 0. Specifically, when the first to fourth qubits (QB1, QB2, QB3, QB4) are input so that the number of times the first to fourth qubits (QB1, QB2, QB3, QB4) are input as 0>|0>|0>|0>, the number of times the first to fourth qubits (QB1, QB2, QB3, QB4) are input as 0>|0>|0>|1>, the number of times the first to fourth qubits (QB1, QB2, QB3, QB4) are input as |0>|0>|1>|0>, and the number of times the first to fourth qubits (QB1, QB2, QB3, QB4) are input as |0>|0>|1>|1> are equal to each other, the measuring unit (130A) can measure the verification probability, which is the probability that |0>|0>|0>|0> is output. In other words, the verification probability may be the probability that 0>|0>|0>|0> is output to the measuring unit (130A) when the number of times 0>|0>|0>|0> is input, the number of times 0>|0>|0>|1> is input, the number of times 0>|0>|1>|0> is input, and the number of times 0>|0>|1>|1> is input are equal to each other. The verification probability described with reference to FIGS. 11 to 13 is the first verification probability P described with reference to FIGS. 5 to 7. 0000 can respond to.

[0107] Although the measuring unit (130A) has been described as calculating the sum of the first to fourth measurement probabilities, the measuring unit (130A) according to embodiments of the present invention is not limited to this.

[0108] If the verification probability is less than about 0.125, the measurement unit (130A) can determine that the normal implementation of the verification target gate (200) is successful. In addition, if the verification probability is greater than or equal to about 0.125 and less than or equal to about 0.375, the measurement unit (130A) can determine that the normal implementation of the verification target gate (200) is unsuccessful. In addition, if the verification probability is greater than about 0.375, the measurement unit (130A) can determine that the normal implementation of the verification target gate (200) is successful. In the case where the verification probability is greater than about 0.375, the verified target gate can generate a PSI (-) state.

[0109] In one embodiment, the measurement unit (130A) may determine that the verification target gate (200) is successfully implemented without error when the verification probability is 0. In addition, the measurement unit (130A) may determine that the verification target gate (200) is successfully implemented when the verification probability is greater than 0 and less than about 0.125, with a noise ratio equal to the value of the verification probability multiplied by a constant. For example, the constant may be about 0.25. However, the range of the value of the verification probability and the constant value according to embodiments of the present invention are not limited thereto.

[0110] As described above, in the quantum verification circuit (100A) and the quantum gate verification method using the quantum verification circuit (100A), the verification target gate (200) is placed between the first verification circuit unit (110A) and the second verification circuit unit (120A), and the states of the qubits that have passed through the first verification circuit unit (110A), the verification target gate (200), and the second verification circuit unit (120A) are measured to determine whether the verification target gate (200) is normally implemented, so it is possible to easily determine whether the quantum gate, which is the verification target gate (200), has failed or succeeded in implementing the entanglement state. Accordingly, the verification accuracy and efficiency of the quantum gate (e.g., CNOT gate) that implements the entanglement state can be improved. Accordingly, since the quantum gate can be applied to a quantum circuit and a device, the performance of the quantum circuit and the device using the quantum gate can be improved.

[0111] Figures 14 to 16 are drawings for explaining the effect of the quantum verification circuit of Figure 1.

[0112] Referring to FIGS. 14 to 16, the values ​​of the probability distribution measured using the quantum verification circuit (100) of FIG. 2 can be confirmed for the verification target gate according to the comparative example and the embodiment.

[0113] Comparative Example 1 according to Fig. 14 used an XX gate connected between the first verification circuit unit (110) and the second verification circuit unit (120) of Fig. 2 as a verification target gate. Specifically, Comparative Example 1 used an XX gate combined with a Hadamard gate connected to the first qubit (QB1) and a Hadamard gate connected to the second qubit (QB2) instead of a CNOT gate.

[0114] Comparative Example 2 according to Fig. 15 used a controlled Hadamard gate connected between the first verification circuit unit (110) and the second verification circuit unit (120) of Fig. 2 as a verification target gate. Specifically, Comparative Example 2 used a controlled Hadamard gate including a control unit connected to the first qubit (QB1) and a Hadamard gate connected to the second qubit (QB2) instead of a CNOT gate.

[0115] The embodiment according to Fig. 16 uses a CNOT gate connected between the first verification circuit unit (110) and the second verification circuit unit (120) of Fig. 2 as a verification target gate. Specifically, the embodiment uses a CNOT gate including a control unit connected to the first qubit (QB1) and a target unit connected to the second qubit (QB2).

[0116] The quantum verification circuit (100) of Fig. 2 was repeatedly operated for 2048 times using the examples and comparative examples. The verification probability P according to the examples and comparative examples 00 The values, noise ratios, and success or failure of implementing the entanglement state of the quantum gate are as shown in Table 1 below. The inputs of the first to fourth qubits of each of the examples and comparative examples are |0>|0>|0>|0>.

[0117] P 00 Noise ratio (%) Success comparison example 10.2612-Failure comparison example 20.09522.5 Successful example 0.01950.5 Success

[0118] The verification probability of Comparative Example 1 was measured to be the largest, and the verification probability of the embodiment was measured to be the smallest. In addition, since the verification probabilities measured in Comparative Example 2 and the embodiment, which include gates advantageous for generating an entangled state, have values ​​less than 0.125, the implementation of the entangled state of the quantum gate in Comparative Example 2 and the embodiment was successful. In addition, since the verification probability measured in Comparative Example 1 had a value greater than 0.125, the implementation of the entangled state of the quantum gate in Comparative Example 1 failed. Accordingly, it can be confirmed that the quantum verification circuit (100) of FIG. 2 can easily and accurately verify a quantum entangled state through a quantum gate, and that the verification probability most suitable for the CNOT gate is derived.

[0119] The quantum verification circuit (100, 100A) and the verification target gate (200) according to embodiments of the present invention can be used to verify or operate quantum circuits included in various devices. The quantum verification circuit (100, 100A) can be included in the device or connected externally to the device. The device can correspond to various types of electronic devices such as a mobile user terminal (e.g., a smart phone, a laptop, a wearable device, etc.) or a fixed management device (e.g., a server, a PC, etc.). In addition, the device can be an exemplary hardware / software architecture such as a device for designing or implementing a quantum circuit.

[0120] In addition, the quantum verification circuit (100, 100A) and the verification target gate (200) according to embodiments of the present invention may be implemented by hardware, firmware, software, or a combination thereof. In the case of hardware implementation, it may be implemented by one or more ASICs (Application Specific Integrated Circuits), DSPs (Digital Signal Processors), DSPDs (Digital Signal Processing Devices), PLDs (Programmable Logic Devices), FPGAs (Field Programmable Gate Arrays), general processors, controllers, microcontrollers, microprocessors, etc.

[0121] The operation according to the quantum gate verification method using the quantum verification circuit (100, 100A) of the present invention can be implemented by software or machine-executable instructions (e.g., an operating system, an application, firmware, a program, etc.) that are to be executed on a device or a computer, and a non-transitory computer-readable medium in which such software or instructions are stored and can be executed on the device or the computer.

[0122] Although the present invention has been described above with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0123] <Explanation of symbols>

[0124] 100, 100A: Quantum verification circuit 110, 110A: First verification circuit

[0125] 120, 120A: Second verification circuit 130, 130A: Measurement section

[0126] 200: Verification target gate SQB: System qubit

[0127] AQB: auxiliary qubit

[0128] QB1, QB2, QB3, QB4: 1st to 4th qubits

Claims

1. A first verification circuit unit that inputs multiple qubits, performs operations based on the qubits, and outputs the results to a verification target gate; A second verification circuit unit that inputs entangled qubits from the verification target gate and performs an operation based on the entangled qubits; and A quantum verification circuit including a measurement unit that receives the output of the second verification circuit unit and determines whether the verification target gate is normally implemented by determining the entanglement state of the qubits.

2. A quantum verification circuit, characterized in that the verification target gate in the first paragraph is a CNOT gate.

3. In the first paragraph, the first verification circuit unit includes at least one selected from the group consisting of a Pauli-X-gate, a CNOT gate, and a Hadamard gate, A quantum verification circuit characterized in that the second verification circuit section includes a Hadamard gate.

4. A quantum verification circuit according to claim 3, characterized in that the first verification circuit section further includes a controlled Hadamard gate defined as a gate that performs a matrix operation according to the following [Formula 1]. [Formula 1] 5. A quantum verification circuit, characterized in that in the first paragraph, first to fourth qubits are input to the first verification circuit unit.

6. A quantum verification circuit according to claim 5, characterized in that the first verification circuit generates an output according to the following [Formula 2] including the first to third vectors based on the first to fourth qubits. [Formula 2] Here, means the output of the first verification circuit section, means the first vector above, means the second vector, means the third vector, and 1, 2, 1', 2' mean the first qubit, the second qubit, the third qubit, and the fourth qubit, respectively. , , and is defined by [Formula 3] below. [Formula 3] 7. A quantum verification circuit, characterized in that the first to third vectors in the sixth paragraph are orthogonal to each other.

8. In the fifth paragraph, if each of the first to fourth qubits is input as |0>, A quantum verification circuit characterized in that the measurement unit measures a verification probability defined as the probability that all values ​​of qubits output from the second verification circuit are 0 based on the first and second qubits to determine whether the verification target gate is normally implemented.

9. A quantum verification circuit, characterized in that in the 8th paragraph, if the value of the verification probability is less than 0.125, the measurement unit determines that the normal implementation of the verification target gate has been successful.

10. A quantum verification circuit characterized in that, in the 8th paragraph, if the value of the verification probability is 0.125 or more and 0.375 or less, the measurement unit determines that the normal implementation of the verification target gate has failed.

11. A quantum verification circuit according to claim 1, characterized in that the second verification circuit unit includes at least one selected from the group consisting of a Pauli-X-gate, a CNOT gate, and a Hadamard gate.

12. In the 11th paragraph, the first verification circuit includes a Hadamard gate, A quantum verification circuit characterized in that the second verification circuit section further includes a controlled Hadamard gate.

13. In the first paragraph, if each of the first to fourth qubits is input as |0>, A quantum verification circuit characterized in that the measurement unit calculates the sum of measurement probabilities defined as the probability that the value of each of the first and second qubits output from the second verification circuit has a specific value, thereby determining whether the verification target gate is normally implemented.

14. In paragraph 13, The specific value for each of the first and second qubits is 0, A quantum verification circuit characterized in that the above measurement unit calculates the sum of the above measurement probabilities according to [Formula 4] below. [Formula 4] Here, is the above verification probability, are the measurement probabilities, respectively, and a, b, c, and d represent the values ​​output to the measurement unit for the first to fourth qubits, respectively.

15. A quantum verification circuit, characterized in that in the 14th paragraph, if the value of the verification probability is less than 0.125, the measurement unit determines that the normal implementation of the verification target gate has been successful.

16. In the first paragraph, if each of the first to fourth qubits is input as |0>, A quantum verification circuit characterized in that the measurement unit calculates a verification probability defined as the probability that each of the first to fourth qubits output from the second verification circuit has a value of 0 to determine whether the verification target gate is normally implemented.

17. A step of generating qubits in a preliminary state for verification based on at least two or more qubits; A step of generating an entangled state by inputting the qubits in the above preliminary state into the verification target gate; and A method for verifying a quantum gate, comprising a step of measuring the entanglement state to determine whether the gate to be verified is normally implemented.

18. In the step of generating the qubits in the preliminary state in the 17th paragraph, Generate the qubits in the preliminary state based on the first and second qubits, Each of the first and second qubits and the third and fourth qubits is input with a value of |0>, A method for verifying a quantum gate, characterized in that, in the step of determining whether the gate to be verified is normally implemented, the method determines whether the gate to be verified is normally implemented by calculating the sum of measurement probabilities defined as the probability that each value of the qubits output based on the first and second qubits will have a specific value.

19. In the step of determining whether the verification target gate is normally implemented in the 18th paragraph, the specific value output based on the first and second qubits is 0, The above verification probability is calculated according to [Formula 5] below, A method for verifying a quantum gate, characterized in that if the verification probability is less than 0.125, the normal implementation of the gate to be verified is determined to be successful. [Formula 5] Here, is the above verification probability, are the measurement probabilities, respectively, and a, b, c, and d represent the values ​​output to the measurement unit for the first to fourth qubits, respectively.

20. In the step of generating the qubits in the preliminary state in the 17th paragraph, Generate the qubits in the preliminary state based on the first to fourth qubits, In the step of determining whether the above verification target gate is normally implemented, if the probability that the values ​​of the qubits output based on the first and second qubits are all 0 is less than 0.125, it is determined that the normal implementation of the verification target gate is successful. A method for verifying a quantum gate, characterized in that, in the step of determining whether the gate to be verified is normally implemented, if the probability that the values ​​of the qubits output based on the first and fourth qubits are all 0 is 0.125 or more and 0.375 or less, it is determined that the normal implementation of the gate to be verified has failed.

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