Wafer with a plurality of sensor units that include an organic semiconductor

Abstract

A wafer including a plurality of sensor units, each sensor unit including (a) a substrate with a primary surface; (b) a first layer of a first conductive material disposed over the primary surface of the substrate; (c) a plurality of projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections including (i) a layer of an insulator disposed over the first layer of the first conductive material and (ii) a second layer of a second conductive material disposed over the layer of the insulator; and (d) an organic semiconductor disposed over the first layer of the first conductive material and the projections. A method of manufacturing sensor units. The method includes a dicing step that includes separating the plurality of sensor units from the wafer.

Description

Attorney Docket No.: SP24-216WAFER WITH A PLURALITY OF SENSOR UNITS THAT INCLUDE AN ORGANIC SEMICONDUCTOR AND METHOD OF MAKING THE WAFERCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit ofpriority under 35 U.S.C. § 119 of U.S. Provisional Application Serial No. 63 / 682554 filed on August 13, 2024 and U.S. Provisional Application Serial No. 63 / 680342 filed on August 7, 2024, the contents of each of which are relied upon and incorporated herein by reference in their entireties.TECHNICAL FIELD

[0002] The present invention generally relates to a wafer including a plurality of sensor units, each including a plurality of projections of stacked metal layers and an organic semiconductor over the plurality of projections. Each sensor unit can be utilized as a chemical sensor to detect the presence of a target substance within a fluid.BACKGROUND

[0003] Organic semiconductors provide many potential benefits over inorganic semiconductors. Among them include increased flexibility, less expensive raw materials, less expensive application methods, and increased ability to tailor the chemical structure compared to inorganic semiconductors. The potential benefits have led to the proposed and actualized utilization of organic semiconductors in a variety of applications, such as organic light emitting diodes, organic photovoltaics, organic thin-film transistors, organic field-effect transistors, and organic sensors.

[0004] In the context of organic sensors, organic semiconductors can be functionalized to interact with a specific molecule that is desired to be detected. When the organic semiconductor interacts with the specific molecule, a change can occur in a measurable property of the organic semiconductor (e.g., electrical conductivity). However, a need exists to improve existing organic sensors, particularly in terms of suitable sensors for breach analysis and large-scale manufacture of such sensors.SUMMARY

[0005] The present disclosure provides a wafer including a plurality of sensor units and a method of manufacturing the same. Processes and equipment utilized in the mature semiconductor industry are adapted to form the wafer and thus the sensor units of the present disclosure.

[0006] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description orAttorney Docket No.: SP24-216 recognized by practicing the aspects as described herein, including the detailed description which follows, the claims, as well as the appended Drawings.

[0007] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide an overview or framework to understanding the nature and character of the claims. The accompanying drawings are included to provide a further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate one or more aspects, and together with the description serve to explain principles and operation of the various aspects.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the Drawings:

[0009] FIG. 1 is a perspective of a wafer of the present disclosure, illustrating a plurality of sensor units;

[0010] FIG. 2 is an overhead view of one of the plurality of sensor units, illustrating (a) a first layer of a first conductive material at a surrounding portion surrounding a second layer of a second conductive material at a contact pad and a plurality of fingers extending therefrom and (b) an organic semiconductor disposed over the first layer of the first conductive material and the second layer of the second conductive material;

[0011] FIG. 3 is an elevational view of a cross-section of the sensor unit of FIG. 2 taken through line III-III thereof, illustrating, from the bottom up, a substrate, a dielectric layer, the first layer of the first conductive material, projections that include a layer of an insulator, the second layer of the second conductive material, and layer of a metal oxide (in phantom), and the organic semiconductor over everything else;

[0012] FIG. 4 is schematic diagram of a method of manufacturing the sensor units, illustrating at least a dicing step to separate the plurality of sensor units from the wafer of the present disclosure;

[0013] FIG. 5 is a schematic diagram of a master mold forming a daughter mold, which manipulates resist material into a predetermined design as part of one or more lithography steps;

[0014] FIG. 6 is a scanning electron microscope (SEM) image of material that has been molded into a predetermined three-dimensional design with a daughter mold, illustrating micrometer size features; and

[0015] FIG. 7 is a further magnified image similar to the image of FIG. 6.Attorney Docket No.: SP24-216DETAILED DESCRIPTION

[0016] Reference will now be made in detail to various aspects of the disclosure, examples of which are illustrated in the accompanying Drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0017] Referring to FIG. 1, a wafer 10 of the present disclosure is herein described. The wafer 10 includes a plurality of sensor units 12. As will be detailed below, the plurality of sensor units 12 can be separated from the wafer 10. The wafer 10 further includes a largest dimension 14, which is the case of a circular wafer 10, as circular, is a diameter 14. In aspects, the largest dimension (e.g., diameter) 14 is within a range of from 25.4 mm (1 inch) to 300 mm (11.8 inches). For example, the largest dimension (e.g., diameter) 14 can be 25.4 mm, 30 mm, 50 mm, 100 mm, 150 mm, 200 mm, 203.2 mm (8 inches), 250 mm, 300 mm, or within any range bounded by any two of those values (e.g., from 200 mm to 250 mm, from 30 mm to 150 mm, and so on).

[0018] Referring now to FIGS . 2 and 3, in some aspects each sensor unit 12 includes a substrate 16, a first layer of the first conductive material 18 of a first conductive material, and a plurality of projections 20. The substrate 16 includes a primary surface 22. The substrate 16 can be made of or include any material typically used in the semiconductor industry. In aspects, the substrate 16 is made of or includes silicon, a glass, a ceramic, or a plastic, or any combination thereof. Suitable glass compositions for the substrate 16 include borosilicate glass compositions, aluminosilicate glass compositions, fused silica, soda lime glass compositions, alkali aluminosilicate, or any combination thereof, among other options. Suitable ceramic compositions for the substrate 16 include aluminum oxide, aluminum nitride, silicon carbide, beryllium oxide, zirconium oxide, silicon nitride, or any combination thereof, among other options. Suitable plastic compositions include polyethylene terephthalate, polyethylene naphthalate, polyimide, or any combination thereof, among other options. When the material of the substrate 16 is not sufficiently dielectric, such as silicon, each sensor unit 12 in some aspects then further includes a dielectric layer 24 disposed on the primary surface 22 of the substrate 16. Suitable materials for the dielectric layer 24 include, without limitation, silicon dioxide (SiCh), silicon nitride (SisN^, silicon oxynitride (SiON), or any combination thereof, among other options.

[0019] The first layer of the first conductive material 18 is disposed over the primary surface 22 of the substrate 16. In aspects where each sensor unit 12 includes the dielectric layer 24, the dielectric layer 24 is sandwiched between the substrate 16 and the first layer of the first conductive material 18. In aspects, the first conductive material comprises Al, Au, Ag, Mo,Attorney Docket No.: SP24-216 Ti, TiN, Cu, Co, MoOs, indium tin oxide, a conductive layer derived from a conductive ink, or any combination thereof. That list is not meant to be exhaustive.

[0020] The plurality of projections 20 extend from the first layer of the first conductive material 18 away from the primary surface 22 of the substrate 16. Each ofthe projections 20 include at least a layer of an insulator 26 and a second layer of a second conductive material 28. The layer of the insulator 26 is disposed over the first layer of the first conductive material 18. Suitable materials for the insulator 26 include any known intermetal dielectric material used in the semiconductor industry. Particular examples include silicon dioxide, silicon nitride, fluorinated silica glass, tetraethyl orthosilicate, zirconium oxide, hydrogen silsesquioxane, methyl silsesquioxane, organic silicate glasses, organic aromatic polymers, or any combination thereof, among other options. The second layer of the second conductive material 28 is disposed over the layer of the insulator 26. Suitable materials for the second conductive material include Al, Au, Ag, Mo, Ti, TiN, Cu, Co, MoOs, indium tin oxide, a conductive layer derived from a conductive ink, or any combination thereof. That list is not meant to be exhaustive.

[0021] The conductive material (e.g., the first conductive material, second conductive material, or both) can be any suitable conductive material, such as, for example, Al, Au, Ag, Mo, Ti, TiN, Cu, Co, MoOs, indium tin oxide (ITO), a conductive layer derived from a conductive ink, or any combination thereof, as described elsewhere herein. In some aspects, the conductive material is derived from a conductive ink. A conductive ink, as used herein, refers to a type of ink that contains conductive materials, in particle and / or dissolved form, such as but not limited to, silver, copper, carbon, graphene, gold, nickel, conductive polymers, or any combination thereof. These materials when not dissolved are typically dispersed in a solvent, which can be water-based or organic -based, depending on the specific formulation considering solubility and compatibility concerns, as would be understood in the art. The ink may also contain a binder, which is a polymer that helps to adhere the conductive materials / particles to a substrate upon application. The binder, if employed, is not particularly limited. A dispersant may also be included to prevent the conductive materials / particles from agglomerating, ensuring a uniform distribution throughout the ink. The dispersant, if employed, is not particularly limited. Upon application of the conductive ink to a substrate, the solvent begins to evaporate, a process that can be accelerated by applying heat to cure the layer. As the solvent evaporates, the conductive materials and / or particles are left behind, which can be bound together by the binder, forming a solid, conductive layer on a substrate. The resulting layer of conductive material can beAttorney Docket No.: SP24-216 employed in the devices herein, which layer has properties such as conductivity, flexibility, and durability depending on the specific type of conductive ink used and the curing process.

[0022] Suitable conductive inks include, for example, silver conductive ink, copper conductive ink, carbon conductive ink, graphene conductive ink, gold conductive ink, nickel conductive ink, conductive polymer ink, silver chloride ink, silver nanowire ink, silver-coated copper nanowire ink, carbon nanotube ink, or any combination thereof.

[0023] The silver conductive ink typically contains silver particles, a binder (such as an acrylic or epoxy resin), a solvent (such as water or an alcohol), and possibly a dispersant. The silver particles are often nano-sized to maximize their surface area and conductivity.

[0024] The copper conductive ink is similar to silver conductive ink, but with copper particles instead of silver. The copper particles are also often nano-sized.

[0025] The carbon conductive ink typically contains carbon particles (such as graphite or carbon black), a binder, a solvent, and possibly a dispersant. The carbon particles provide conductivity and also give the ink its black color.

[0026] The graphene conductive ink contains graphene particles, a binder, a solvent, and possibly a dispersant. Graphene is a single layer of carbon atoms arranged in a hexagonal lattice, and it has exceptional electrical and thermal conductivity.

[0027] The gold conductive ink contains gold particles, a binder, a solvent, and possibly a dispersant. Gold is highly conductive and resistant to oxidation, but it is also expensive, so gold conductive inks are typically used in specialized applications.

[0028] The nickel conductive ink is similar to silver and copper conductive inks, but with nickel particles. Nickel is less conductive than silver or copper, but it is also less expensive.

[0029] The conductive polymer ink contains conductive polymers (such as PEDOT:PSS), a solvent, and possibly a dispersant. Conductive polymers are flexible and can be used to make flexible and stretchable electronics.

[0030] The silver chloride conductive ink contains silver chloride particles, a binder, a solvent, and possibly a dispersant. Silver chloride is highly conductive.

[0031] The silver nanowire conductive ink contains silver nanowires, a binder, a solvent, and possibly a dispersant. Silver nanowires are highly conductive.

[0032] The silver-coated copper nanowire conductive ink contains silver-coated copper nanowires, a binder, a solvent, and possibly a dispersant. The silver coating enhances the conductivity of the copper nanowires.

[0033] The carbon nanotube conductive ink contains carbon nanotubes, a binder, a solvent, and possibly a dispersant. Carbon nanotubes are highly conductive and mechanically strong.Attorney Docket No.: SP24-216

[0034] Each sensor unit 12 further includes an organic semiconductor 30. The organic semiconductor 30 is disposed over the first layer of the first conductive material 18 and the projections 20. Examples of suitable organic semiconductors 30 include heterocyclic organic compounds, such as fused thiophene compounds. More particular examples include the organic semiconductor polymers described in International Patent Application Publication No. W02020112394A1, which is incorporated herein by reference, such as:Other more particular examples include the organic semiconductor polymers described in International Patent Application Publication No. WO2020117556A1, which is incorporated herein by reference, such as:or a combination thereof. Still other more particular examples include the organic semiconductor polymers described in International Patent Application Publication No. W02020076882A1, which is incorporated herein by reference, such as:Attorney Docket No.: SP24-216where n is at least 4, x is at least 1, and y is at least 1. Still other more particular examples include the organic semiconductor polymers described in United States Patent Application Publication No. US20220031228A1, which is incorporated herein by reference, such as:

[0035] The composition of the organic semiconductor 30 is selected to interact with at least one target substance. Examples of the at least one target substance include ammonia, acetone, chloroform, ethanol, NO2, H2S, CO, or any combination thereof. The universe of suitable target substances expands as research discovers new markers indicative of certain health conditions. The provided list is thus not meant to be exclusive but only exemplary. “Interact” for purposes of this disclosure means any form of interaction that causes a measurable change in one or more conditions, including one or more electrical conditions (e.g., voltage, current, and so on). The interaction may be adherence of the target substance to the organic semiconductor 30, for example, by any covalent or non-covalent bonding mechanism.

[0036] In aspects, the second conductive material and the organic semiconductor 30 are selected so that an absolute difference between a work function of the second conductive material and a Lowest Unoccupied Molecular Orbital (LUMO) energy of the organic semiconductor 30 is less than or equal to a predetermined maximum value. In aspects, the predetermined maximum value is within a range of from 1.20 eV to 1.50 eV. For example, the predetermined maximum value can be 1.20 eV, 1.22 eV, 1.24 eV, 1.26 eV, 1.28 eV, 1.30 eV, 1.32 eV, 1.34 eV, 1.36 eV, 1.38 eV, 1.40 eV, 1.42 eV, 1.44 eV, 1.46 eV, 1.48 eV, 1.50 eV, or within any range bounded by any two of those values (e.g., from 1 .26 eV to 1.48 eV, from 1.32Attorney Docket No.: SP24-216 eV to 1.38 eV, and so on). “Work function” refers to the minimum energy required to remove an electron from the surface of the material to a point just outside the material (in a vacuum). Work functions for various metals and other materials are set forth in Table 1 below. In turn, the LUMO energy indicates the ability of the material to accept electrons. The LUMO energy of any considered organic semiconductor 30 material can be determined via known experimental methods such as cyclic voltammetry. The closer the absolute values of the work function of the second conductive material and the LUMO energy of the organic semiconductor 30 are to each other, the more efficient charge injection is, which facilitates low voltage operation of each of the sensor units 12.

[0037] In aspects, each sensor unit 12 further includes one or more of nanoparticles and nanowires 34 dispersed throughout the organic semiconductor 30. The presence of the one or more of nanoparticles and nanowires 34 is believed to enable large changes in current as a function of the presence of the target substance. The nanoparticles and nanowires 34 alter the charge transfer of the organic semiconductor 30, improving sensitivity of each of the sensor units 12. The one or more of nanoparticles and nanowires 34 can be made of a metal or a conductive material like indium tin oxide (ITO). The metal can be silver, gold, copper, aluminum, chromium, any alloy thereof, or any combination thereof. That list is not meant to be exhaustive, and other conductive materials and / or metals are envisioned.

[0038] In aspects, each sensor unit 12 further includes a polymer 36 (see FIG. 4) disposed over the organic semiconductor 30. Among other purposes, the polymer 36 can protect the other constituents of the sensor units 12 during separation of the sensor units 12 from the wafer 10.Attorney Docket No.: SP24-216 For example, dicing of the sensor units 12 from the wafer 10 can involve sawing the wafer 10 with a saw. The sawing can produce debris and typically includes contacting the saw with a liquid such as water. The polymer 36 protects the other constituents of the sensor unit 12 from the liquid and the debris. The composition of the polymer 36 is not particularly important. However, the polymer 36 should be removably soluble in a solvent to permit removal of the polymer 36 from the remainder of each of the sensor units 12 after separation of the sensor units 12 from the wafer 10.

[0039] In aspects, each sensor unit 12 further includes a contact pad 38 (see FIG. 2). The contact pad 38 comprises the second conductive material and is contiguous with the second layer of the second conductive material 28 of each of the plurality of projections 20. The plurality of projections 20 can extend from the contact pad 38 as a series of aligned fingers 40. The first layer of the first conductive material 18 laterally surrounds the contact pad 38 and the plurality of projections 20 at a surrounding portion 42, and the first layer of the first conductive material 18 is also underneath the contact pad 38 and the plurality of projections 20 as shown in FIG. 3. The organic semiconductor 30 covers not just the second layer of the second conductive material 28 at the projections 20 but, at least in some aspects, also at least a portion of the second layer of the second conductive material 28 at the contact pad 38, as well as at at least a portion of the surrounding portion 42 of the first layer of the first conductive material 18. In some aspects, however, the organic semiconductor 30 covers the second layer of the second conductive material 28 at the projections 20, but does not cover the second layer of the second conductive material 28 at the contact pad 38. The features of FIG. 2 can be more easily visualized and understood by reference to FIG. 3 described elsewhere herein, which is an elevational view of a cross-section of FIG. 2 taken through line III-III.

[0040] Referring now to FIG. 4, a method 100 of manufacturing the sensor units 12 is herein described. At a dicing step 102, the method 100 includes separating the plurality of sensor units 12 from the wafer 10. In aspects, the dicing step 102 includes impinging the wafer 10 with a laser beam to separate each of the plurality of sensor units 12 from the wafer 10. However, any technique known in the semiconductor field to divide wafers 10 can be utilized, such as sawing as described elsewhere herein.

[0041] As mentioned, in aspects, the plurality of sensor units 12 can further includes a polymer (not shown) disposed over the organic semiconductor 30. In such aspects, the method 100 can further include a polymer removal step 146. The polymer removal step 146 occurs after the dicing step 102. The polymer removal step 146 includes removing the polymer (not shown) from the plurality of sensor units 12 by dissolving the polymer in a solvent. The solvent canAttorney Docket No.: SP24-216 be any solvent in which the polymer is soluble, and which does not otherwise affect any of the other structures present. Examples include water, acetone, propylene glycol methyl ether acetate (PGMEA), ethyl acetate, dichloromethane, methanol, ethanol, propanol, tetrahydrofuran, or any combination thereof.

[0042] In aspects, the method 100 further includes a polymer deposition step 144. The polymer deposition step 144 occurs before the dicing step 102 and the polymer removal step 146. In such aspects, the polymer deposition step 144 includes depositing the polymer (not shown) over the organic semiconductor 30 of the wafer 10. The polymer deposition step 144 can include spin-coating, dip-coating, spraying, or any combination thereof, of the polymer onto the organic semiconductor 30 of the wafer 10. Other processes to deposit the polymer onto the wafer 10 are envisioned. The polymer can cover an entirety, or only a portion, of a surface area of the wafer 10. The polymer has a composition but the composition is not particularly important, other than the polymer is soluble in a solvent to permit subsequent removal of the polymer from the sensor units 12 during the polymer removal step 146 without otherwise affecting the other structures present. Suitable examples include but are not limited to water- soluble polymers such as polyvinyl alcohol (PVA), polyethylene glycol (PEG), polyacrylic acid (PAA), polyvinylpyrrolidone (PVP), carboxymethyl cellulose (CMC), hydroxyethyl cellulose (HEC), or any combination thereof; acetone -soluble polymers such as polymethyl methacrylate (PMMA), polystyrene (PS), cellulose acetate, polyvinyl butyral (PVB), polylactic acid (PLA), or any combination thereof; polymers soluble in propylene glycol methyl ether acetate (PGMEA) such as PMMA, PS, PVP, poly(tert-butyl acrylate) (PtBA), or any combination thereof; or any combination of any of the aforementioned polymers.

[0043] In aspects, the method 100 further includes (a) presenting a patterned workpiece 132 and (b) an organic semiconductor deposition step 140. The patterned workpiece 132 includes the substrate 16, the optional dielectric layer 24 (if separately added), the first layer of the first conductive material 18, and the projections 20 extending from the first layer of the first conductive material 18. The projections 20 include the insulator 26 and the second conductive material 28. The organic semiconductor deposition step 140 includes depositing an organic semiconductor 30 over the first layer of the first conductive material 18 and the projections 20 of the patterned workpiece 132 thus forming the wafer 10. The organic semiconductor 30 can be deposited on an entire surface area, or only a portion, of the patterned workpiece 132. Spincoating, dip-coating, spraying, or any combination thereof, among other processes, can be utilized to deposit on the patterned workpiece 132 the organic semiconductor 30 that isAttorney Docket No.: SP24-216 dissolved in solution or present in suspension. The solvent can be subsequently removed, which leaves behind the organic semiconductor 30 disposed upon the patterned workpiece 132.

[0044] In aspects, the method 100 further includes, before the organic semiconductor deposition step 140, a surface treatment step 138. The surface treatment step 138 includes manipulating exposed surfaces of the first layer of the first conductive material 18 and the projections 20 of the patterned workpiece 132 to improve adhesion of the organic semiconductor 30 thereto. The manipulation mentioned can include a plasma treatment, an ozone treatment, or an application of an adhesion promoter (e.g., silane coupling agent) to the exposed surfaces of the first layer of the first conductive material 18 and the projections 20 of the patterned workpiece 132.

[0045] In aspects, the method 100 further includes, before the organic semiconductor deposition step 140, presenting an etchable workpiece 120 and an etching step 126. The etchable workpiece 120 includes the substrate 16, the optional dielectric layer 24, the first layer of the first conductive material 18, the layer of the insulator 26, the second layer of the second conductive material 28, an optional layer of metal oxide 112 (if added to manipulate the work function of the second layer of the second conductive material 28, as further discussed), and the resist material 116 with a predetermined design. The etching step 126 includes etching the etchable workpiece 120 to remove a portion 128 of the layer of the insulator 26 and a portion 130 of the second layer of the second conductive material 28, thus forming a patterned workpiece 132. The patterned workpiece 132 includes the substrate 16, the optional dielectric layer 24 (if separately added), the first layer of the first conductive material 18, and the projections 20 extending from the first layer of the first conductive material 18. The projections 20 include the insulator 26 and the second conductive material 28. The resist material 116 resists etching and thus protects the insulator 26 and the second conductive material 28 from being etched away in the locations where the resist material 116 is present in the predetermined design over the insulator 26 and the second conductive material 28. Where the resist material 116 is not present, the etching step 126 removes the portion 128 of the layer of the insulator 26 and the portion 130 of the second layer of the second conductive material 28, leaving behind the projections 20 and, in some instances, the contact pad 38 of the second conductive material (see FIG. 2). The surrounding portion 42 of the first conductive material is now exposed (see FIG. 2), for each of what will be the sensor units 12. The projections 20 of the patterned workpiece 132, may further include resist material 116 disposed over the second conductive material 28. In such aspects, the resist material 116 that remains can be dissolved in and removed with a solvent.Attorney Docket No.: SP24-216

[0046] In aspects, the method 100 further includes, before the etching step 126, presenting a first workpiece (not separately illustrated) and one or more lithography steps 118. The first workpiece includes the substrate 16 with the primary surface 22, the first layer of the first conductive material 18 disposed over the primary surface 22 of the substrate 16, the layer of the insulator 26 disposed over the first layer of the first conductive material 18, the second layer of the second conductive material 28 disposed over the layer of the insulator 26, and the resist material 116 (not yet with the predetermined design) disposed over the second layer of the second conductive material 28. The one or more lithography steps 118 includes manipulating the resist material 116 so as to have the predetermined design thus forming the etchable workpiece 120.

[0047] In aspects, the resist material 116 is a photoresist material. In such aspects, the one or more lithography steps 118 include selectively exposing the resist material 116 to ultraviolet (UV) electromagnetic radiation or a beam of electrons and developing the resist material 116 to manipulate the resist material 116 into the predetermined design. When UV electromagnetic radiation is utilized, the resist material 116 includes a chemical constituent that increases or decreases the solubility of the resist material 116 upon interacting with the UV electromagnetic radiation. A mask can be utilized to selectively block or allow transmission of the UV electromagnetic radiation so that the solubility of the resist material 116 changes only where appropriate to achieve the predetermined design after developing the resist material 116. The resist material 116 is then developed (contacted with a suitable solvent) to remove the resist material 116 where solubility did or, alternatively, did not, change.

[0048] Referring now to FIGS. 5-7, in other aspects, the one or more lithography steps 118 includes imprinting the resist material 116 into the predetermined design. Instead of selectively exposing the resist material 116 to UV electromagnetic radiation or an electron beam, the resist material 116 can be physically shaped with a mold 122 into the predetermined design. A master mold 124 (see FIG. 5), such as made of quartz, can be fabricated. Thereafter, a daughter mold 122 can be prepared by stamping the master mold 124 into a material to imprint a negative of the predetermined design into the daughter mold 122. The daughter mold 122 can be forced onto the resist material 116 to move or pattern the resist material 116 or other materials into the predetermined design. As depicted in FIGS. 6 and 7, the organic semiconductor can be shaped into a predetermined design with micron-sized features.

[0049] Referring back to FIG. 4, the method 100 further includes, before the one or more lithography steps 118, presenting a second workpiece 119 and a resist deposition step 114. The second workpiece 119 includes the substrate 16 with the primary surface 22, the first layer ofAttorney Docket No.: SP24-216 the first conductive material 18 disposed over the primary surface 22 of the substrate 16, the layer of the insulator 26 disposed over the first layer of the first conductive material 18, and the second layer of the second conductive material 28 disposed over the layer of the insulator 26. The resist deposition step 114 includes depositing the resist material 116 over the second layer of the second conductive material 28 thus forming the first workpiece. The resist material 116 can be a positive photoresist or a negative photoresist. The resist deposition step 114 can include spin-coating the resist material 116 dissolved in a solvent over the second layer of the second conductive material 28 (or oxide layer thereupon) and then evaporating the solvent such as via a thermal treatment. The resist material 116 can cover an entirety, or only a portion, of a surface area of the second layer of the second conductive material 28 (or oxide layer thereupon).

[0050] In some aspects, the resist deposition step 114 and lithography step 118 are combined into a single step, such as where resist material is directly patterned onto the second layer of the second conductive material 28 (or oxide layer thereupon), including by way of a stamp or other suitable technique as described elsewhere herein, so as to form the predetermined design on the etchable workpiece 120.

[0051] In aspects, the method 100 further includes, before the resist deposition step 114, presenting a third workpiece 121 and a second conductive material deposition step 110. The third workpiece 121 includes the substrate 16 with the primary surface 22, the first layer of the first conductive material 18 disposed over the primary surface 22 of the substrate 16, and the layer of the insulator 26 disposed over the first layer of the first conductive material 18. The second conductive material deposition step 110 includes depositing the second layer of the second conductive material 28 over the layer of the insulator 26 thus forming the second workpiece. The second layer of the second conductive material 28 can cover an entirety, or only a portion, of a surface area of the layer of the insulator 26. In aspects, a physical vapor deposition (PVD) process is performed to cause atoms of the second conductive material 28 to eject from a target material and then to condense on the layer of the insulator 26. In other aspects, a thermal or electron beam evaporation process is performed to cause a source of the second conductive material 28 to evaporate and then to condense on the layer of the insulator 26. In still other aspects, a CVD process is performed to cause the second conductive material 28 to form from a precursor gas and to condense on layer of the insulator 26. Other procedures to deposit the second layer of the second conductive material 28, such as electroplating, are envisioned. In some aspects, the second conductive material deposition step 110 includesAttorney Docket No.: SP24-216 depositing a conductive ink and allowing the ink to dry and / or cure to form the second layer of the second conductive material 28.

[0052] In aspects, the second conductive material deposition step 110 further includes depositing or forming a metal oxide 112 on the second conductive material 28. As mentioned elsewhere herein, it may be desirable for the absolute values of the work function of the second conductive material of the second layer of the second conductive material 28 and the LUMO energy of the organic semiconductor 30 to be as close to each other as possible, such as within a predetermined difference. One way to achieve that is to modify the work function of the second conductive material 28 by depositing or forming a layer of metal oxide 112 on the second layer of the second conductive material 28. A thermal oxidation process can be utilized to form the layer of metal oxide 112 on the second layer of the second conductive material 28. The thermal oxidation process causes the second conductive material to oxidize. Other processes can be utilized instead. Causing the second conductive material to oxidize tends to increase the work function to increases. For example, the work function of copper is 4.7 eV (as set forth in Table 1), while the work function of CU2O is 5.0 eV. As another example, the work function of nickel is 5.01 eV, while the work function of NiO is 5.6 eV. The layer of metal oxide 112 can cover an entirety, or only a portion, of a surface area of the second layer of the second conductive material 28.

[0053] In aspects 100, the method 10 further includes, before the second conductive material deposition step 110, presenting a fourth workpiece 123 and an insulator deposition step 108. The fourth workpiece 123 includes the substrate 16 with the primary surface 22 and the first layer of the first conductive material 18 disposed over the primary surface 22 of the substrate 16. The insulator deposition step 108 includes depositing the layer of the insulator 26 over the first layer of the first conductive material 18 thus forming the third workpiece. The insulation deposition step 108 can include performing CVD, spin -coating, among other options, to deposit the layer of the insulator 26. The layer of the insulator 26 can cover an entirety, or only a portion, of a surface area of the first layer of the first conductive material 18.

[0054] In aspects, the method 100 further includes, before the insulator deposition step 108, presenting a fifth workpiece 125 and a first conductive material deposition step 106. The fifth workpiece 125 includes the substrate 16 with the primary surface 22. The first conductive material deposition step 106 includes depositing the first layer of the first conductive material 18 over the optional dielectric layer 24 of the substrate 16 thus forming the fourth workpiece. Any of the processes mentioned in connection with the second conductive material deposition step 110, such as PVD, can be utilized to perform the first conductive material deposition stepAttorney Docket No.: SP24-216 106. In some aspects, the first conductive material deposition step 106 includes depositing a conductive ink and allowing the ink to dry and / or cure to form the first layer of the first conductive material 18.

[0055] In aspects, the method 100 further includes, before first conductive material deposition step 106, a dielectric deposition step 104. The dielectric deposition step 104 includes depositing or forming the dielectric layer 24 over the primary surface 22 of the substrate 16. The substrate 16 is the structural foundation of the wafer 10 and has the largest dimension 14, such as a diameter, approximately equivalent of that which the diameter 14 of the wafer 10 is to be. The dielectric deposition step 104 may be useful when the substrate 16 is not sufficiently dielectric for the intended applications. In aspects, the dielectric deposition step 104 can include performing a thermal oxidation procedure to form a dielectric layer 24 of Si O2 on the silicon. In other aspects, the dielectric deposition step 104 can include performing a chemical vapor deposition (CVD) procedure, such as plasma-enhanced chemical vapor deposition (PECVD), to contact the primary surface 22 of the substrate 16 with a precursor gas that reacts therewith to deposit the dielectric layer 24. The dielectric layer 24 comprising Si O2- SisN^ or SiON, among other compositions may be formed in such a manner. In still other aspects, the dielectric deposition step 104 can include spin-coating a liquid precursor to the dielectric layer 24 on the primary surface 22 of the substrate 16. Other procedures to deposit or form the dielectric layer 24 are envisioned. The dielectric layer 24 can be added over an entirety of a surface area of the primary surface 22 of the substrate 16.

[0056] Each of the sensor units 12 can be assembled on a different printed circuit board using wire bonding or other suitable technique to create an electrical connection between the sensor unit 12 and metal pads on the printed circuit board.

[0057] The wafer 10 and the method 100 of the present disclosure are highly suitable for large- scale production of the sensor units 12. Further, the sensor units 12 include the projections 20 with first layer of the first conductive material 18 of the first layer of the first conductive material 18 stacked with the second layer of the second conductive material 28, which increase sensitivity and speed of responsiveness of the sensor units 12 when interacting with the target substance.

[0058] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the claims.

[0059] According to aspect (1) of the present disclosure, a wafer comprises: a plurality of sensor units, each sensor unit comprising: a substrate with a primary surface; a first layer of a first conductive material disposed over the primary surface of the substrate; a plurality ofAttorney Docket No.: SP24-216 projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections comprising (i) a layer of an insulator disposed over the first layer of the first conductive material and (ii) a second layer of a second conductive material disposed over the layer of the insulator; and an organic semiconductor disposed over the first layer of the first conductive material and the projections.

[0060] According to aspect (2) of the present disclosure, the wafer of aspect (1) further comprising a largest dimension within a range of from 25.4 mm (1 inch) to 300 mm (11.8 inches).

[0061] According to aspect (3) of the present disclosure, the wafer of any one of aspects (1) through (2), wherein each sensor unit further comprises a dielectric layer disposed on the primary surface of the substrate, the dielectric layer sandwiched between the substrate and the first layer of the first conductive material.

[0062] According to aspect (4) of the present disclosure, the wafer of any one of aspects (1) through (3), wherein the substrate comprises silicon, a glass, a ceramic, or a plastic.

[0063] According to aspect (5) of the present disclosure, the wafer of any one of aspects (1) through (4), wherein the first conductive material comprises Al, Au, Ag, Mo, Ti, TiN, Cu, Co, MoOs, indium tin oxide, a conductive layer derived from a conductive ink, or any combination thereof.

[0064] According to aspect (6) of the present disclosure, the wafer of any one of aspects (1) through (5), wherein the second conductive material comprises Al, Au, Ag, Mo, Ti, TiN, Cu, Co, MoOs, indium tin oxide, a conductive layer derived from a conductive ink, or any combination thereof.

[0065] According to aspect (7) of the present disclosure, the wafer of any one of aspects (1) through (6), wherein the second conductive material and the organic semiconductor are selected so that an absolute difference between a work function of the second conductive material and a Lowest Unoccupied Molecular Orbital energy of the organic semiconductor is less than or equal to a predetermined maximum value.

[0066] According to aspect (8) of the present disclosure, the wafer of any one of aspects (1) through (7), wherein each sensor unit further comprises one or more of nanoparticles and nanowires dispersed throughout the organic semiconductor.

[0067] According to aspect (9) of the present disclosure, the wafer of any one of aspects (1) through (8), wherein each sensor unit further comprises a polymer disposed over the organic semiconductor.Attorney Docket No.: SP24-216

[0068] According to aspect (10) of the present disclosure, the wafer of aspect (9), wherein the polymer is removably soluble in a solvent.

[0069] According to aspect (11) of the present disclosure, the wafer of any one of aspects (1) through (10), wherein each sensor unit further comprises a contact pad and the plurality of projections extend from the contact pad as a series of aligned fingers.

[0070] According to aspect (12) of the present disclosure, a method of manufacturing sensor units, the method comprising: (a) presenting a wafer comprising: a plurality of sensor units, each sensor unit comprising: a substrate with a primary surface; a first layer of a first conductive material disposed over the primary surface of the substrate; a plurality of projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections comprising (i) a layer of an insulator disposed over the first layer of the first conductive material and (ii) a second layer of a second conductive material disposed over the layer of the insulator; and an organic semiconductor disposed over the first layer of the first conductive material and the projections; and (b) a dicing step comprising separating the plurality of sensor units from the wafer.

[0071] According to aspect (13) of the present disclosure, the method of aspect (12), wherein the dicing step comprises impinging the wafer with a laser beam.

[0072] According to aspect (14) of the present disclosure, the method of any one of aspects (12) through (13), wherein (i) each of the plurality of sensor units further comprise a polymer disposed over the organic semiconductor, and (ii) the method further comprises a polymer removal step comprising removing the polymer from the plurality of sensor units by dissolving the polymer in a solvent.

[0073] According to aspect (15) of the present disclosure, the method of aspect (14), wherein the solvent is water, acetone, propylene glycol methyl ether acetate (PGMEA), ethyl acetate, dichloromethane, methanol, ethanol, propanol, tetrahydrofuran, or any combination thereof.

[0074] According to aspect (16) of the present disclosure, the method of any one of aspects (14) through (15) further comprises: before the dicing step, a polymer deposition step comprising depositing the polymer over the organic semiconductor of the wafer.

[0075] According to aspect (17) of the present disclosure, the method of aspect (16), wherein the polymer deposition step comprises spin-coating or dip-coating the polymer onto the organic semiconductor.

[0076] According to aspect (18) of the present disclosure, the method of any one of aspects (12) through (17) further comprises: (a) presenting a patterned workpiece comprising: the substrate with the primary surface; the first layer of the first conductive material disposed overAttorney Docket No.: SP24-216 the primary surface of the substrate; and the plurality of projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections comprising (i) the layer of the insulator disposed over the first layer of the first conductive material and (ii) the second layer of the second conductive material disposed over the layer of the insulator; and (b) an organic semiconductor deposition step comprising depositing the organic semiconductor over the first layer of the first conductive material and the projections thus forming the wafer.

[0077] According to aspect (19) of the present disclosure, the method of aspect (18), wherein the organic semiconductor deposition step comprises spin-coating or dip-coating the organic semiconductor over the patterned workpiece.

[0078] According to aspect (20) of the present disclosure, the method of any one of aspects (18) through (19) further comprises, before the organic semiconductor deposition step: a surface treatment step comprising manipulating exposed surfaces of the first layer of the first conductive material and the projections of the patterned workpiece to improve adhesion of the organic semiconductor thereto.

[0079] According to aspect (21) of the present disclosure, the method of any one of aspects (18) through (20) further comprises, before the organic semiconductor deposition step: (a) presenting an etchable workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, the layer of the insulator disposed over the first layer of the first conductive material, the second layer of the second conductive material disposed over the layer of the insulator, and resist material disposed in predetermined design over the second layer of the second conductive material; and (b) an etching step comprising etching the etchable workpiece to remove a portion of the layer of the insulator and a portion of the second layer of the second conductive material, thus forming the patterned workpiece.

[0080] According to aspect (22) of the present disclosure, the method of aspect (21) further comprising, before the etching step: (a) presenting a first workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, the layer of the insulator disposed over the first layer of the first conductive material, the second layer of the second conductive material disposed over the layer of the insulator, and resist material disposed over the second layer of the second conductive material; and one or more lithography steps comprising manipulating the resist material into the predetermined design thus forming the etchable workpiece.Attorney Docket No.: SP24-216

[0081] According to aspect (23) of the present disclosure, the method of aspect (22), wherein (i) the resist material is a photoresist material, and (ii) the one or more lithography steps comprise selectively exposing the resist material to ultraviolet (UV) electromagnetic radiation or a beam of electrons and developing the resist material to manipulate the resist material into the predetermined design.

[0082] According to aspect (24) of the present disclosure, the method of aspect (22), wherein the one or more lithography steps comprise imprinting the resist material with a mold to manipulate the resist material into the predetermined design.

[0083] According to aspect (25) of the present disclosure, the method of any one of aspects (22) through (24) further comprising, before the one or more lithography steps: (a) presenting a second workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, the layer of the insulator disposed over the first layer of the first conductive material, and the second layer of the second conductive material disposed over the layer of the insulator, and a resist deposition step comprising depositing the resist material over the second layer of the second conductive material thus forming the first workpiece.

[0084] According to aspect (26) of the present disclosure, the method of aspect (25) further comprising, before the resist deposition step: (a) presenting a third workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, and the layer of the insulator disposed over the first layer of the first conductive material, and (b) a second conductive material deposition step comprising depositing the second layer of the second conductive material over the layer of the insulator thus forming the second workpiece.

[0085] According to aspect (27) of the present disclosure, the method of aspect (26), wherein the second conductive material deposition step further comprises depositing or forming a metal oxide on the second conductive material, the second layer comprising the second conductive material and the metal oxide.

[0086] According to aspect (28) of the present disclosure, the method of aspect (26), wherein the second conductive material and the organic semiconductor are selected so that an absolute difference between a work function of the second conductive material and a Lowest Unoccupied Molecular Orbital energy of the organic semiconductor is less than or equal to a predetermined maximum value.Attorney Docket No.: SP24-216

[0087] According to aspect (29) of the present disclosure, the method of any one of aspects (26) through (28), wherein the second conductive material deposition step comprises depositing the second layer of the second conductive material via physical vapor deposition.

[0088] According to aspect (30) of the present disclosure, the method of any one of aspects (26) through (29) further comprises, before the second conductive material deposition step: (a) presenting a fourth workpiece comprising: the substrate with the primary surface, and the first layer of the first conductive material disposed over the primary surface of the substrate, and (b) an insulator deposition step comprising depositing the layer of the insulator over the first layer of the first conductive material thus forming the third workpiece.

[0089] According to aspect (31) of the present disclosure, the method of aspect (30), wherein the insulator deposition step comprises depositing the layer of the insulator via chemical vapor deposition.

[0090] According to aspect (32) of the present disclosure, the method of any one of aspects (30) through (31) further comprises, before the insulator deposition step: (a) presenting a fifth workpiece comprising: the substrate with the primary surface; and (b) a first conductive material deposition step comprising depositing the first layer of the first conductive material over the substrate thus forming the fourth workpiece.

[0091] According to aspect (33) of the present disclosure, the method of aspect (32), wherein the first conductive material deposition step comprises depositing the first layer of the first conductive material via physical vapor deposition.

[0092] According to aspect (34) of the present disclosure, the method of any one of aspects (32) through (33) further comprising, before the first conductive material deposition step: a dielectric deposition step comprising depositing or forming a dielectric layer over the primary surface of the substrate, and wherein, during the first conductive material deposition step, the first layer of the first conductive material is deposited over the dielectric layer.

Claims

Attorney Docket No.: SP24-216CLAIM(S)What is claimed is:1 . A wafer comprising : a plurality of sensor units, each sensor unit comprising: a substrate with a primary surface; a first layer of a first conductive material disposed over the primary surface of the substrate; a plurality of projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections comprising (i) a layer of an insulator disposed over the first layer of the first conductive material and (ii) a second layer of a second conductive material disposed over the layer of the insulator; and an organic semiconductor disposed over the first layer of the first conductive material and the projections.

2. The wafer of claim 1 further comprising: a largest dimension within a range of from 25.4 mm (1 inch) to 300 mm (11.8 inches).

3. The wafer of any one of claims 1-2, wherein each sensor unit further comprises a dielectric layer disposed on the primary surface of the substrate, the dielectric layer sandwiched between the substrate and the first layer of the first conductive material.

4. The wafer of any one of claims 1-3, wherein the substrate comprises silicon, a glass, a ceramic, or a plastic.

5. The wafer of any one of claims 1-4, wherein the first conductive material comprises Al, Au, Ag, Mo, Ti, TiN, Cu, Co, MoOs, indium tin oxide, a conductive layer derived from a conductive ink, or any combination thereof.

6. The wafer of any one of claims 1-5, wherein the second conductive material comprises Al, Au, Ag, Mo, Ti, TiN, Cu, Co, MoOs, indium tin oxide, a conductive layer derived from a conductive ink, or any combination thereof.Attorney Docket No.: SP24-2167. The wafer of any one of claims 1-6, wherein the second conductive material and the organic semiconductor are selected so that an absolute difference between a work function of the second conductive material and a Lowest Unoccupied Molecular Orbital energy of the organic semiconductor is less than or equal to a predetermined maximum value.

8. The wafer of any one of claims 1-7, wherein each sensor unit further comprises one or more of nanoparticles and nanowires dispersed throughout the organic semiconductor.

9. The wafer of any one of claims 1-8, wherein each sensor unit further comprises a polymer disposed over the organic semiconductor.

10. The wafer of claim 9, wherein the polymer is removably soluble in a solvent.

11. The wafer of any one of claims 1-10, wherein each sensor unit further comprises a contact pad and the plurality of projections extend from the contact pad as a series of aligned fingers.

12. A method of manufacturing sensor units, the method comprising: presenting a wafer comprising: a plurality of sensor units, each sensor unit comprising: a substrate with a primary surface; a first layer of a first conductive material disposed over the primary surface of the substrate; a plurality of projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections comprising (i) a layer of an insulator disposed over the first layer of the first conductive material and (ii) a second layer of a second conductive material disposed over the layer of the insulator; and an organic semiconductor disposed over the first layer of the first conductive material and the projections; andAttorney Docket No.: SP24-216 a dicing step comprising separating the plurality of sensor units from the wafer.

13. The method of claim 12, wherein the dicing step comprises impinging the wafer with a laser beam.

14. The method of any one of claims 12-13, wherein each of the plurality of sensor units further comprise a polymer disposed over the organic semiconductor, and the method further comprises a polymer removal step comprising removing the polymer from the plurality of sensor units by dissolving the polymer in a solvent.

15. The method of claim 14, wherein the solvent is water, acetone, propylene glycol methyl ether acetate (PGMEA), ethyl acetate, dichloromethane, methanol, ethanol, propanol, tetrahydrofuran, or any combination thereof.

16. The method of any one of claims 14-15 further comprising: before the dicing step, a polymer deposition step comprising depositing the polymer over the organic semiconductor of the wafer.

17. The method of claim 16, wherein the polymer deposition step comprises spin-coating or dip-coating the polymer onto the organic semiconductor.

18. The method of any one of claims 12-17 further comprising: presenting a patterned workpiece comprising: the substrate with the primary surface; the first layer of the first conductive material disposed over the primary surface of the substrate; and the plurality of projections extending from the first layer of the first conductive material away from the primary surface of the substrate, each of the projections comprising (i) the layer of the insulator disposed over the first layer of the first conductive material and (ii) the second layer of the second conductive material disposed over the layer of the insulator; andAttorney Docket No.: SP24-216 an organic semiconductor deposition step comprising depositing the organic semiconductor over the first layer of the first conductive material and the projections thus forming the wafer.

19. The method of claim 18, wherein the organic semiconductor deposition step comprises spin-coating or dip-coating the organic semiconductor over the patterned workpiece.

20. The method of any one of claims 18-19 further comprising, before the organic semiconductor deposition step: a surface treatment step comprising manipulating exposed surfaces of the first layer of the first conductive material and the projections of the patterned workpiece to improve adhesion of the organic semiconductor thereto.

21. The method of any one of claims 18-20 further comprising, before the organic semiconductor deposition step: presenting an etchable workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, the layer of the insulator disposed over the first layer of the first conductive material, the second layer of the second conductive material disposed over the layer of the insulator, and resist material disposed in predetermined design over the second layer of the second conductive material; and an etching step comprising etching the etchable workpiece to remove a portion of the layer of the insulator and a portion of the second layer of the second conductive material, thus forming the patterned workpiece.

22. The method of claim 21 further comprising, before the etching step: presenting a first workpiece comprising: the substrate with the primary surface,Attorney Docket No.: SP24-216 the first layer of the first conductive material disposed over the primary surface of the substrate, the layer of the insulator disposed over the first layer of the first conductive material, the second layer of the second conductive material disposed over the layer of the insulator, and resist material disposed over the second layer of the second conductive material; and one or more lithography steps comprising manipulating the resist material into the predetermined design thus forming the etchable workpiece.

23. The method of claim 22, wherein the resist material is a photoresist material, and the one or more lithography steps comprise selectively exposing the resist material to ultraviolet (UV) electromagnetic radiation or a beam of electrons and developing the resist material to manipulate the resist material into the predetermined design.

24. The method of claim 22, wherein the one or more lithography steps comprise imprinting the resist material with a mold to manipulate the resist material into the predetermined design.

25. The method of any one of claims 22-24 further comprising, before the one or more lithography steps: presenting a second workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, the layer of the insulator disposed over the first layer of the first conductive material, and the second layer of the second conductive material disposed over the layer of the insulator, and a resist deposition step comprising depositing the resist material over the second layer of the second conductive material thus forming the first workpiece.Attorney Docket No.: SP24-21626. The method of claim 25 further comprising, before the resist deposition step: presenting a third workpiece comprising: the substrate with the primary surface, the first layer of the first conductive material disposed over the primary surface of the substrate, and the layer of the insulator disposed over the first layer of the first conductive material, and a second conductive material deposition step comprising depositing the second layer of the second conductive material over the layer of the insulator thus forming the second workpiece.

27. The method of claim 26, wherein the second conductive material deposition step further comprises depositing or forming a metal oxide on the second conductive material.

28. The method of claim 26, wherein the second conductive material and the organic semiconductor are selected so that an absolute difference between a work function of the second conductive material and a Lowest Unoccupied Molecular Orbital energy of the organic semiconductor is less than or equal to a predetermined maximum value.

29. The method of any one of claims 26-28, wherein the second conductive material deposition step comprises depositing the second layer of the second conductive material via physical vapor deposition.

30. The method of any one of claims 26-29 further comprising, before the second conductive material deposition step: presenting a fourth workpiece comprising: the substrate with the primary surface, and the first layer of the first conductive material disposed over the primary surface of the substrate, and an insulator deposition step comprising depositing the layer of the insulator over the first layer of the first conductive material thus forming the third workpiece.Attorney Docket No.: SP24-21631. The method of claim 30, wherein the insulator deposition step comprises depositing the layer of the insulator via chemical vapor deposition.

32. The method of any one of claims 30-31 further comprising, before the insulator deposition step: presenting a fifth workpiece comprising: the substrate with the primary surface; and a first conductive material deposition step comprising depositing the first layer of the first conductive material over the substrate thus forming the fourth workpiece.

33. The method of claim 32, wherein the first conductive material deposition step comprises depositing the first layer of the first conductive material via physical vapor deposition.

34. The method of any one of claims 32-33 further comprising, before the first conductive material deposition step: a dielectric deposition step comprising depositing or forming a dielectric layer over the primary surface of the substrate, and wherein, during the first conductive material deposition step, the first layer of the first conductive material is deposited over the dielectric layer.

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