Semiconductor structure and forming method therefor

Abstract

A semiconductor structure and a forming method therefor. The method comprises: providing a base (200), wherein the base (200) comprises a substrate (201) and an epitaxial layer (202) located on the substrate (201); etching the base (200), in order to form gate trenches (207) located in the epitaxial layer (202); performing doping treatment on the base (200) exposed by the gate trenches (207), in order to form implanted doped regions (209) located below the gate trenches (207), wherein the implanted doped regions (209) are positionally aligned with the gate trenches (207); and forming a gate structure (211) in each gate trench (207). The presence of gate trenches (207) allows a greater embedding depth of implanted doped regions (209) in a drift region (203) than that of implanted doped regions (209) formed by means of implantation from the surface of an epitaxial layer (202) under the same implantation energy, so that the implanted doped regions (209) can deplete the drift region (203) to a greater extent, thereby improving the breakdown voltage of semiconductor devices. In addition, the implanted doped regions (209) are located below the gate trenches (207), and the implanted doped regions (209) are positionally aligned with the gate trenches (207), and thus the implanted doped regions (209) and the gate trenches (207) are formed using the same mask, thereby eliminating one photolithography process, saving one mask, and reducing process costs.

Description

Semiconductor structure and method of forming the same

[0001] This application claims priority to the Chinese patent application No. 202411111987.4, filed on August 13, 2024, and entitled "Semiconductor structure and method of forming the same", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a method of forming the same. BACKGROUND

[0003] Trench gate metal oxide semiconductor field effect transistor (MOSFET) devices are widely used in power conversion circuits. The on-resistance and breakdown voltage of the trench gate MOSFET are important parameter indicators, and obtaining higher breakdown voltage and lower on-resistance can improve the competitiveness of the product. In order to improve the on-resistance of the middle and high voltage (50V-200V) trench gate, the super junction-trench gate concept realized by implantation is proposed, and the bottom end of the implantation area assisting the drift region depletion is as close as possible to the highly doped substrate to make the drift region as long as possible.

[0004] However, the current super junction-trench gate metal oxide semiconductor field effect transistor still has some deficiencies. SUMMARY

[0005] The problem solved by the present application is how to deepen the depth of the implantation region so that the bottom end of the implantation region is as close as possible to the bottom of the substrate, thereby making the implantation region deplete the drift region as much as possible.

[0006] To solve the above problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a drift region; a gate structure located partially in the drift region; an implantation doped region with a doping type opposite to that of the drift region, the implantation doped region being located below the gate structure, and the position of the implantation doped region corresponding to the position of the gate structure.

[0007] Optionally, the projection of the implantation doped region on the substrate surface at least partially overlaps with the projection of the gate structure on the substrate surface.

[0008] Optionally, the projection of the gate structure on the substrate surface is located within the projection of the implantation doped region on the substrate surface.

[0009] Optionally, a transition doped region of the same doping type is located between the gate structure and the implanted doped region, the transition doped region is in electrical contact with the implanted doped region, and the position of the transition doped region corresponds to the implanted doped region.

[0010] Optionally, the doping concentration of the transition doped region is greater than the doping concentration of the implanted doped region.

[0011] Optionally, the projection of the implanted doped region on the substrate surface at least partially overlaps with the projection of the transition doped region on the substrate surface.

[0012] Optionally, the projection of the implanted doped region on the substrate surface is located within the projection of the transition doped region on the substrate surface.

[0013] Optionally, the transition doped region further extends to between the gate structure and the drift region.

[0014] Optionally, a body doped region of the opposite doping type to the drift region is located on the drift region, the gate structure penetrates the body doped region in the direction perpendicular to the substrate surface, and the body doped region is in electrical contact with the transition doped region.

[0015] Optionally, the transition doped region further extends to between the gate structure and the body doped region.

[0016] Optionally, a first heavily doped layer of the opposite doping type to the body doped region is located on the body doped region, and the gate structure penetrates the first heavily doped layer in the direction perpendicular to the substrate surface.

[0017] Optionally, a conductive plug penetrating the first heavily doped layer is in electrical contact with the body doped region, and a second heavily doped layer is located at the bottom of the conductive plug, the second heavily doped layer is in electrical contact with the conductive plug, the second heavily doped layer is of the same doping type as the body doped region, and the doping concentration of the second heavily doped layer is greater than the doping concentration of the body doped region.

[0018] Correspondingly, the application further provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate and an epitaxial layer located on the substrate; etching the substrate to form a gate trench in the epitaxial layer; performing a doping treatment on the substrate exposed by the gate trench to form an implanted doped region under the gate trench, the position of the implanted doped region corresponding to the position of the gate trench; and forming a gate structure in the gate trench.

[0019] Optionally, the step of etching the substrate to form the gate trench in the epitaxial layer comprises: forming a hard mask layer with an opening on the substrate; and etching the substrate to form the gate trench in the epitaxial layer with the hard mask layer as a mask.

[0020] Optionally, in the process of doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench, the substrate exposed by the gate trench is doped with the hard mask layer as a mask.

[0021] Optionally, after doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region, the method further comprises: forming a gate structure in the gate trench.

[0022] Optionally, in the process of doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region, the substrate between the gate trench and the implanted doping region is doped with the hard mask layer as a mask.

[0023] Optionally, the dopant dose of the doping process for doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench is less than the dopant dose of the doping process for doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region.

[0024] Optionally, in the process of doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region, an angle between an implantation direction of the doping process and a normal direction of the substrate ranges from 15° to 45°.

[0025] Optionally, further comprising: after the step of etching the substrate to form the gate trench in the epitaxial layer, and before the step of doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench, performing an oxidation repair process on the gate trench to form a sacrificial protection layer on the surface of the gate trench; and in the step of doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench, doping the substrate exposed by the gate trench with the sacrificial protection layer on the surface of the trench to form the implanted doping region under the gate trench.

[0026] Optionally, further comprising: after the step of forming the transition doping region, and before the step of forming the gate structure in the gate trench, removing the hard mask layer and the sacrificial protection layer.

[0027] Optionally, the step of forming the gate structure in the gate trench comprises: forming a first gate oxide layer on the sidewall of the gate trench and the bottom of the gate trench by using a low-temperature thermal oxidation process; forming a second gate oxide layer on the first gate oxide layer by using a deposition process; and forming a gate layer in the gate trench with the first gate oxide layer and the second gate oxide layer on the first gate oxide layer to form the gate structure.

[0028] Optionally, before the step of etching the substrate to form the gate trench in the epitaxial layer, further comprising: doping the epitaxial layer to form a drift region and an initial body doping region on the drift region.

[0029] Optionally, further comprising: after the step of forming the gate structure, doping the initial body doping region on both sides of the gate structure to form a first heavily doped layer.

[0030] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0031] In the semiconductor structure of the technical scheme of the present application, the implanted doping region is located under the gate structure and corresponds to the position of the gate structure, the depth of the implanted doping region is greater, the bottom of the implanted doping region is closer to the bottom of the substrate, and the drift region can be depleted to a greater extent, thereby improving the breakdown voltage of the semiconductor device.

[0032] The forming method of the semiconductor structure of the technical scheme of the present application includes doping the substrate exposed by the gate trench to form an implanted doping region under the gate trench. The presence of the gate trench makes the depth of the implanted doping region embedded into the drift region under the same implantation energy greater than the depth of the implanted doping region formed by implantation from the surface of the epitaxial layer. The bottom of the implanted doping region is closer to the bottom of the substrate. The implanted doping region can more greatly deplete the drift region, thereby improving the breakdown voltage of the semiconductor device. In addition, the implanted doping region is located under the gate trench, and the position of the implanted doping region corresponds to the position of the gate trench. The same mask is used to form the implanted doping region and the gate trench, thereby reducing one photolithography process and saving one mask, and reducing the process cost. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIGS. 1 and 2 are structural schematic diagrams of a semiconductor structure according to an embodiment;

[0034] FIGS. 3 to 16 are structural schematic diagrams of various steps of a forming method of a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] As known from the background, the prior art super-junction-trench-gate has many problems. The present application analyzes the causes of the problems in combination with a super-junction-trench-gate:

[0036] Referring to FIGS. 1 and 2, FIG. 2 is a sectional view of FIG. 1 at position AA1. The semiconductor structure includes a substrate 100 including a drift region; a gate structure 103 partially located in the drift region; and an implanted doping region 104 having a doping type opposite to that of the drift region, the implanted doping region 104 being located between two adjacent gate structures 103.

[0037] The substrate 100 includes a substrate 101 and an epitaxial layer 102 located on the substrate 101. The epitaxial layer 102 is subjected to a doping process to form the drift region.

[0038] The step of forming the gate structure 103 partially located in the drift region includes: forming a first mask layer having an opening on the substrate 100; using the first mask layer as a mask to etch the substrate 100 to form a gate trench in the epitaxial layer 102; and forming the gate structure 103 in the gate trench.

[0039] The opening of the first mask layer is adapted to define the position of the gate structure 103.

[0040] The step of forming the implanted doped region 104 of a doping type opposite to that of the drift region includes: forming a second mask layer with openings on the substrate 100; using the second mask layer as a mask, doping the substrate 100 to form the implanted doped region 104 between two adjacent gate structures 103.

[0041] The openings of the second mask layer are adapted to define the positions of the implanted doped region 104.

[0042] The implanted doped region 104 is formed using the second mask layer as a mask and the gate trench is formed using the first mask layer as a mask, so that two masks and two photolithography processes are required to form the implanted doped region 104 and the gate trench, which results in high process cost. In addition, the implanted energy of the implanted doped region 104 needs to be greater than 2500KeV to make the bottom end of the implanted doped region 104 as close as possible to the bottom of the highly doped substrate 100, but high-energy implantation brings great difficulty to process integration.

[0043] To solve the above technical problem, the present application provides a method for forming a semiconductor structure, which includes: providing a substrate including a substrate and an epitaxial layer on the substrate; etching the substrate to form a gate trench in the epitaxial layer; doping the substrate exposed by the gate trench to form an implanted doped region under the gate trench, the position of the implanted doped region corresponding to the position of the gate trench; and forming a gate structure in the gate trench.

[0044] In the method for forming a semiconductor structure of the present application, compared with forming a gate structure first and then forming an implanted doped region between two gate structures, the substrate exposed by the gate trench is doped to form an implanted doped region under the gate trench. The existence of the gate trench makes the depth of the implanted doped region embedded in the drift region under the same implanted energy greater than that of the implanted doped region formed by implantation from the surface of the epitaxial layer, so that the implanted doped region can more greatly deplete the drift region and improve the breakdown voltage of the semiconductor device. In addition, the implanted doped region is located under the gate trench and the position of the implanted doped region corresponds to the position of the gate trench, so that the same mask is used to form the implanted doped region and the gate trench, one photolithography process is saved and one mask is saved, thereby reducing the process cost.

[0045] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0046] Please refer to FIG. 3, a substrate 200 is provided, which includes a substrate 201 and an epitaxial layer 202 on the substrate 201.

[0047] The material of the substrate 201 comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide; the material of the epitaxial layer 202 comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide. Specifically, in some embodiments of the present application, the material of the substrate 201 is silicon, and the material of the epitaxial layer 202 is silicon.

[0048] Specifically, in some embodiments of the present application, after the substrate 200 is provided, the method further comprises: performing a doping process on the epitaxial layer 202 to form a drift region 203 and an initial body doping region 204 on the drift region 203.

[0049] Specifically, in some embodiments of the present application, the substrate 201 is N-type doped, the drift region 203 is N-type doped, and the doping concentration of the drift region 203 ranges from 5E15 atom / cm 3 to 1E17 atom / cm 3 . The initial body doping region 204 is P-type doped. In other embodiments, the substrate further comprises P-type doping, the drift region further comprises P-type doping, and the initial body doping region further comprises N-type doping.

[0050] After the initial body doping region 204 is formed, the method further comprises: performing a thermal push process on the initial body doping region 204. Compared with performing the thermal push process after the implant doping region 209 is formed, the thermal push process is performed before the implant doping region 209 is formed, which avoids excessive lateral diffusion of the implant doping region 209 under the thermal push process and is conducive to controlling the morphology of the implant doping region 209.

[0051] Please refer to FIGS. 4 and 5. The substrate 200 is etched to form a gate trench 207 in the epitaxial layer 202.

[0052] The step of etching the substrate 200 to form the gate trench 207 in the epitaxial layer 202 comprises: forming a hard mask layer 206 with an opening on the substrate 200 as shown in FIG. 4; and etching the substrate 200 to form the gate trench 207 in the epitaxial layer 202 using the hard mask layer 206 as a mask as shown in FIG. 5.

[0053] Specifically, in some embodiments of the present application, before the hard mask layer 206 with an opening is formed on the substrate 200, the method further comprises: forming a barrier layer 205 on the substrate 200. The material of the barrier layer 205 comprises silicon nitride. The method of forming the barrier layer 205 comprises deposition. The barrier layer 205 serves as an etching stop layer when the hard mask layer 206 is subsequently removed, which is used to reduce the loss of the substrate 200.

[0054] The step of forming the hard mask layer 206 includes: forming a hard mask material layer on the barrier layer 205; forming a photoetching material layer on the hard mask material layer; performing photoetching on the photoetching material layer to form a photoresist layer; and etching the hard mask material layer with the photoresist layer as a mask to form the hard mask layer 206 with an opening. Specifically, in some embodiments of the present application, after the hard mask layer 206 with the opening is formed, the photoresist layer is removed.

[0055] The position of the opening of the hard mask layer 206 defines the position of the gate trench 207.

[0056] Specifically, in some embodiments of the present application, the material of the hard mask layer 206 includes silicon oxide, and the method of forming the hard mask material layer includes deposition.

[0057] Specifically, in some embodiments of the present application, the width of the gate trench 207 is less than 1 μm. The width of the gate trench 207 refers to the size of the gate trench 207 in the direction of the gate trench 207 pointing to the adjacent gate trench 207.

[0058] Please refer to FIG. 6. After the step of etching the substrate 200 to form the gate trench 207 in the epitaxial layer 202, an oxidation repair treatment is performed on the gate trench 207 to form a sacrificial protective layer 208 on the surface of the gate trench 207.

[0059] Specifically, in some embodiments of the present application, the hard mask layer 206 is not removed during the oxidation repair treatment. The oxidation repair treatment is to repair the damage and defects on the surface of the gate trench 207.

[0060] Specifically, in some embodiments of the present application, the material of the sacrificial protective layer 208 includes silicon oxide.

[0061] Please refer to FIG. 7. The substrate 200 exposed by the gate trench 207 is doped to form an implanted doped region 209 under the gate trench 207, and the position of the implanted doped region 209 corresponds to the position of the gate trench 207.

[0062] The substrate 200 exposed by the gate trench 207 is doped to form the implanted doped region 209 under the gate trench 207. With the depth of the gate trench 207, the maximum implantation depth of the implanted doped region 209 is deeper under the same implantation energy, the bottom of the implanted doped region 209 is closer to the bottom of the substrate 200, the implanted doped region 209 can deplete the drift region 203 to a greater extent, and the breakdown voltage of the semiconductor device is improved.

[0063] The position of the implanted doped region 209 corresponds to the position of the gate trench 207, i.e. the projection of the implanted doped region 209 on the surface of the substrate 200 at least partially overlaps with the projection of the gate trench 207 on the surface of the substrate 200. Specifically, in some embodiments of the present application, the projection of the gate trench 207 on the surface of the substrate 200 is located within the projection of the implanted doped region 209 on the surface of the substrate 200.

[0064] The hard mask layer 206 is not removed during the oxidation repair process, so as to be used as a mask for performing a doping treatment on the substrate 200 exposed by the gate trench 207 in the process of forming the implanted doped region 209 under the gate trench 207.

[0065] The implanted doped region 209 is located under the gate trench 207, and the position of the implanted doped region 209 corresponds to the position of the gate trench 207, so that the same mask is used for forming the implanted doped region 209 and forming the gate trench 207, one photolithography process is saved and one mask is saved, and the process cost is reduced.

[0066] Specifically, in some embodiments of the present application, in the step of performing a doping treatment on the substrate 200 exposed by the gate trench 207 to form the implanted doped region 209 under the gate trench 207, the doping treatment is performed on the substrate 200 exposed by the gate trench 207 with the sacrificial protective layer 208 on the surface of the trench to form the implanted doped region 209 under the gate trench 207.

[0067] In the process of performing a doping treatment on the substrate 200 exposed by the gate trench 207 to form the implanted doped region 209 under the gate trench 207, the sacrificial protective layer 208 is adapted to serve as a protective liner of the gate trench 207 to protect the surface of the gate trench 207.

[0068] Specifically, in some embodiments of the present application, in the process of performing a doping treatment on the substrate 200 exposed by the gate trench 207 to form the implanted doped region 209 under the gate trench 207, the included angle between the implantation direction of the doping treatment and the normal direction of the substrate 200 ranges from 0° to 7°.

[0069] Specifically, in some embodiments of the present application, the doping ions of the implanted doped region 209 are boron ions; and the implantation dose of the implanted doped region 209 ranges from 1E12 atom / cm 2 to 1E13 atom / cm 2The implantation energy of the implantation and doping region 209 ranges from 50KeV to 4000KeV.

[0070] Please refer to FIG. 8 to FIG. 10, FIG. 8 is a top view of FIG. 9 and FIG. 10, FIG. 9 is a sectional view of FIG. 8 at BB1 position, and FIG. 10 is a sectional view of FIG. 8 at CC1 position. The hard mask layer 206 and the barrier layer 205 are not shown in FIG. 8. After the substrate 200 exposed by the gate trench 207 is doped to form the implantation and doping region 209 under the gate trench 207, the substrate 200 between the gate trench 207 and the implantation and doping region 209 is doped to form the transition doping region 210 between the bottom of the gate trench 207 and the implantation and doping region 209. The transition doping region 210 is electrically connected with the implantation and doping region 209, and the position of the transition doping region 210 corresponds to the position of the implantation and doping region 209.

[0071] The position of the transition doping region 210 corresponds to the position of the implantation and doping region 209, that is, the projection of the implantation and doping region 209 on the surface of the substrate 200 at least partially overlaps with the projection of the transition doping region 210 on the surface of the substrate 200. Specifically, in some embodiments of the present application, the projection of the implantation and doping region 209 on the surface of the substrate 200 is located in the projection range of the transition doping region 210 on the surface of the substrate 200.

[0072] Specifically, please refer to FIG. 10. In some embodiments of the present application, the transition doping region 210 also extends between the gate trench 207 and the drift region 203. The transition doping region 210 also extends between the gate trench 207 and the initial body doping region 204.

[0073] Specifically, in some embodiments of the present application, please refer to FIG. 10. The length of the gate trench 207 is greater than 10μm. The length of the gate trench 207 is the size of the gate trench 207 along the extension direction of the gate trench 207.

[0074] In the process of doping the substrate 200 between the gate trench 207 and the implantation and doping region 209 to form the transition doping region 210 between the bottom of the gate trench 207 and the implantation and doping region 209, the substrate 200 between the gate trench 207 and the implantation and doping region 209 is doped with the hard mask layer 206 as a mask.

[0075] The transition doped region 210 is located between the bottom of the gate trench 207 and the implanted doped region 209, and the position of the transition doped region 210 corresponds to the position of the implanted doped region 209, so that the transition doped region 210 is formed without introducing a new mask, thereby reducing the process cost.

[0076] The substrate 200 exposed by the gate trench 207 is subjected to a doping process to form the implanted doped region 209 under the gate trench 207, and the doping dose of the doping process is less than that of the doping process for the substrate 200 between the gate trench 207 and the implanted doped region 209 to form the transition doped region 210 between the bottom of the gate trench 207 and the implanted doped region 209. The transition doped region 210 is a heavily doped implant, and the doping concentration of the transition doped region 210 is greater than that of the implanted doped region 209.

[0077] The transition doped region 210 is used to electrically connect the implanted doped region 209, and the doping concentration of the transition doped region 210 is high, so that the resistance of the semiconductor device is reduced and the response speed is increased.

[0078] The implant dose of the transition doped region 210 ranges from 1E14 atom / cm 2 to 5E15 atom / cm 2 . The implant energy of the transition doped region 210 ranges from 10 KeV to 100 KeV. Specifically, in some embodiments of the present application, when the implant ion of the transition doped region 210 is impurity boron (B), the implant energy ranges from 2 KeV to 25 KeV, and the implant dose ranges from 1E14 atom / cm 2 to 5E15 cm atom / cm 2 . When the implant ion of the transition doped region 210 is boron difluoride (BF2), the implant energy ranges from 10 KeV to 100 KeV, and the implant dose ranges from 1E14 atom / cm 2 to 5E15 atom / cm 2 .

[0079] Table 1 is a data chart of the breakdown voltage of the device with the change of the doping dose of the transition doped region 210.

[0080] Table 1

[0081] As the doping dose of the transition doped region 210 increases, the resistance of the transition doped region 210 decreases, and the response speed of the device increases. At the same time, as can be seen from Table 1, as the doping dose of the transition doped region 210 increases, the breakdown voltage of the device decreases.

[0082] Therefore, the dose of the dopant of the transition doped region 210 needs to be controlled to avoid the dose of the dopant of the transition doped region 210 being too large to reduce the breakdown voltage of the device or too small to slow down the response speed of the device.

[0083] In the process of forming the transition doped region 210 between the bottom of the gate trench 207 and the implant doped region 209, the angle between the implant direction of the doping process and the normal direction of the substrate 200 ranges from 15° to 45°. The inclined implant angle makes the cross-sectional area of the transition doped region 210, which is parallel to the substrate surface and is formed between the sidewall of the gate trench 207 and the bottom of the gate trench 207, larger than that of the implant doped region 209, increases the contact area of the transition doped region 210 and the initial body doped region 204, and strengthens the electrical connection between the transition doped region 210 and the initial body doped region 204.

[0084] Please refer to FIG. 11, which has the same view angle as FIG. 9. After the transition doped region 210 is formed, the hard mask layer 206 (as shown in FIG. 9) and the sacrificial protection layer 208 (as shown in FIG. 9) are removed.

[0085] Specifically, in some embodiments of the present application, the hard mask layer 206 and the sacrificial protection layer 208 are removed by wet etching. The hard mask layer 206 and the sacrificial protection layer 208 are removed in one step, which saves the process cost.

[0086] Please refer to FIG. 12, which shows the formation of the gate structure 211 in the gate trench 207.

[0087] The step of forming the gate structure 211 in the gate trench 207 includes forming a gate dielectric layer 212 on the sidewall of the gate trench 207 and the bottom of the gate trench 207, and forming a gate electrode layer 213 in the gate trench 207 with the gate dielectric layer 212.

[0088] Specifically, in some embodiments of the present application, a low-temperature thermal oxidation process is used to form a first gate oxide layer on the sidewall of the gate trench 207 and the bottom of the gate trench 207, a deposition process is used to form a second gate oxide layer on the first gate oxide layer, and the gate electrode layer 213 is formed in the gate trench 207 with the first gate oxide layer and the second gate oxide layer on the first gate oxide layer to form the gate structure 211.

[0089] Specifically, in some embodiments of the present application, the step of forming the second gate oxide layer includes: depositing a TEOS silicon oxide layer; and performing rapid annealing on the TEOS silicon oxide layer. The purpose of the rapid annealing is to densify the TEOS silicon oxide layer.

[0090] The material of the gate electrode layer 213 is polysilicon. The step of forming the gate electrode layer 213 includes: forming an initial gate electrode layer in the gate trench 207 having the first gate oxide layer and the second gate oxide layer on the first gate oxide layer; and performing a planarization process on the initial gate electrode layer to form the gate electrode layer 213.

[0091] The planarization process includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing, etc. Specifically, in the present embodiment, the first planarization process is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing, the chemical mechanical polishing avoids the surface damage caused by pure mechanical polishing and the slow polishing speed, poor surface flatness and poor polishing consistency caused by pure chemical polishing, etc. by the combined action of chemical and mechanical. The chemical mechanical polishing is widely used for high planarization polishing of various materials at nanometer level.

[0092] Specifically, in some embodiments of the present application, the thickness of the first gate oxide layer ranges from 100 angstroms to 400 angstroms; the oxidation temperature of the low-temperature thermal oxidation process ranges from 800°C to 930°C; and the time of the low-temperature thermal oxidation process is less than 30 minutes.

[0093] The first gate oxide layer and the second gate oxide layer are formed by combining low-temperature oxidation and deposition, which reduces the thermal process introduced by thermal growth and reduces the degree of lateral diffusion of the implanted doped region 209.

[0094] The doping method of the transition doped region 210 is heavy doping implantation. After thermal diffusion, the diffusion speed of the transition doped region 210 in the direction parallel to the surface of the substrate 200 is greater than the diffusion speed of the implanted doped region 209 in the direction parallel to the surface of the substrate 200.

[0095] Please refer to FIG. 13. After forming the gate structure 211, the initial body doped region 204 (as shown in FIG. 12) located on both sides of the gate structure 211 is doped to form a first heavy doped layer 214 and a body doped region 217; an interlayer dielectric layer 215 is formed on the gate structure 211 and the first heavy doped layer 214; a via hole is formed through the first heavy doped layer 214 and the interlayer dielectric layer 215; and the body doped region exposed at the bottom of the via hole is doped to form a second heavy doped layer 216.

[0096] The first heavily doped layer 214 is a source end heavily doped layer. Specifically, in some embodiments of the present application, the first heavily doped layer 214 is N-type heavily doped, and the second heavily doped layer 216 is P-type heavily doped. In other embodiments, the first heavily doped layer can also be P-type heavily doped, and the second heavily doped layer can also be N-type heavily doped.

[0097] Specifically, in some embodiments of the present application, the transition doped region 210 also extends between the gate structure 211 and the body doped region 217.

[0098] The step of forming the via through the first heavily doped layer 214 and the interlayer dielectric layer 215 includes: forming a mask layer on the interlayer dielectric layer 215, the mask layer exposing part of the interlayer dielectric layer 215; etching the interlayer dielectric layer 215 with the mask layer as a mask to form the via through the first heavily doped layer 214 and the interlayer dielectric layer 215. Specifically, in some embodiments of the present application, the mask layer is not removed after the via is formed.

[0099] The step of doping the body doped region 217 exposed at the bottom of the via to form the second heavily doped layer 216 includes: doping the body doped region 217 exposed at the bottom of the via with the mask layer as a mask to form the second heavily doped layer 216. The second heavily doped layer 216 is of a doping type opposite to that of the first heavily doped layer 214. Specifically, in some embodiments of the present application, the second heavily doped layer 216 is P-type heavily doped, and in other embodiments, the second heavily doped layer can also be N-type heavily doped.

[0100] After the second heavily doped layer 216 is formed, it further includes: forming a conductive plug 218 in the via.

[0101] Please refer to FIG. 14 to FIG. 16, FIG. 14 is a top view of FIG. 15 and FIG. 16, FIG. 15 is a sectional view of FIG. 14 at BB1 position, and FIG. 16 is a sectional view of FIG. 14 at CC1 position. A drain end metal layer 219 is formed on the side of the substrate 201 away from the epitaxial layer 202; a source end metal layer 220 is formed on the conductive plug 218, and a gate end metal layer 221 is formed on the gate structure 211.

[0102] Correspondingly, an embodiment of the present application also provides a semiconductor structure, please refer to FIG. 15, which includes: a substrate 200, the substrate 200 including a drift region 203; a gate structure 211 partially located in the drift region 203; an implanted doped region 209 of a doping type opposite to that of the drift region 203, the implanted doped region 209 being located below the gate structure 211, and the position of the implanted doped region 209 corresponding to that of the gate structure 211.

[0103] The semiconductor structure comprises a substrate 200, wherein the substrate 200 comprises a drift region 203.

[0104] The substrate 200 comprises a substrate 201 and an epitaxial layer 202 (as shown in Fig. 5) on the substrate 201, and the drift region 203 is located in the epitaxial layer 202.

[0105] The material of the substrate 201 comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide; and the material of the epitaxial layer 202 comprises silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium arsenide. Specifically, in some embodiments of the present application, the material of the substrate 201 is silicon, and the material of the epitaxial layer 202 is silicon.

[0106] Specifically, in some embodiments of the present application, the substrate 201 is N-type doped, and the epitaxial layer 202 is N-type doped, and the doping concentration of the epitaxial layer 202 ranges from 5E15 atom / cm 3 to 1E17 atom / cm 3 .

[0107] The semiconductor structure comprises a body doped region 217 on the drift region 203, and the doping type of the body doped region 217 is opposite to that of the drift region 203. Specifically, in some embodiments of the present application, the body doped region 217 is P-type doped. In other embodiments, the substrate further comprises P-type doped, the epitaxial layer further comprises P-type doped, and the body doped region 217 further comprises N-type doped.

[0108] The semiconductor structure comprises a gate structure 211 partially located in the drift region 203.

[0109] The gate structure 211 comprises a gate dielectric layer 212 and a gate layer 213 on the gate dielectric layer 212; specifically, in some embodiments of the present application, the gate structure 211 comprises a first gate oxide layer, a second gate oxide layer on the first gate oxide layer, and a gate layer 213 on the second gate oxide layer.

[0110] The material of the first gate oxide layer is silicon oxide, the material of the second gate oxide layer is silicon oxide, and the material of the gate layer 213 is polysilicon. The thickness of the first gate oxide layer ranges from 100 angstrom to 400 angstrom.

[0111] The semiconductor structure comprises an implanted doped region 209 with a doping type opposite to that of the drift region 203, and the implanted doped region 209 is located below the gate structure 211, and the position of the implanted doped region 209 corresponds to that of the gate structure 211.

[0112] The projection of the implant doped region 209 on the surface of the substrate 200 at least partially overlaps with the projection of the gate structure 211 on the surface of the substrate 200. In particular, in some embodiments of the application, the projection of the gate structure 211 on the surface of the substrate 200 is located within the projection of the implant doped region 209 on the surface of the substrate 200.

[0113] The semiconductor structure comprises a transition doped region 210 of the same doping type as the implant doped region 209 between the gate structure 211 and the implant doped region 209, the transition doped region 210 being in electrical contact with the implant doped region 209 and the transition doped region 210 being located in correspondence of the implant doped region 209.

[0114] The transition doped region 210 has a higher doping concentration than the implant doped region 209.

[0115] The projection of the implant doped region 209 on the surface of the substrate 200 at least partially overlaps with the projection of the transition doped region 210 on the surface of the substrate 200.

[0116] The projection of the implant doped region 209 on the surface of the substrate 200 is located within the projection of the transition doped region 210 on the surface of the substrate 200.

[0117] The transition doped region 210 further extends between the gate structure 211 and the drift region 203.

[0118] The gate structure 211 penetrates the body doped region 217 in a direction perpendicular to the surface of the substrate 200 and the body doped region 217 is in electrical contact with the transition doped region 210.

[0119] The transition doped region 210 further extends between the gate structure 211 and the body doped region 217.

[0120] The semiconductor structure comprises a first heavily doped layer 214 on the body doped region 217, the first heavily doped layer 214 having a doping type opposite to the doping type of the body doped region 217.

[0121] The gate structure 211 penetrates the first heavily doped layer 214 in a direction perpendicular to the surface of the substrate 200.

[0122] The semiconductor structure includes: a conductive plug 218 penetrating the first heavily doped layer 214, the conductive plug 218 being electrically connected with the body doped region; a second heavily doped layer 216 at the bottom of the conductive plug 218, the second heavily doped layer 216 being electrically connected with the conductive plug 218, the second heavily doped layer 216 having the same doping type as the body doped region, and the second heavily doped layer 216 having a doping concentration greater than that of the body doped region.

[0123] The semiconductor structure includes: a drain end metal layer 219 on the side of the substrate 201 away from the epitaxial layer 202.

[0124] The semiconductor structure includes: a source end metal layer 220 on the conductive plug 218 and a gate end metal layer 221 on the gate structure 211.

[0125] Although the present application has been disclosed with reference to the above embodiments, it is not intended to limit the present application. Any modification and change within the spirit and scope of the present application will be apparent to those skilled in the art. Therefore, the protection scope of the present application should be limited by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate comprising a drift region; a gate structure located partially within the drift region; an implanted doped region of a doping type opposite to that of the drift region, the implanted doped region being located under the gate structure, the implanted doped region corresponding in position to the gate structure.

2. The semiconductor structure of claim 1, wherein, A projection of the implanted doped region on a substrate surface at least partially overlaps a projection of the gate structure on the substrate surface.

3. The semiconductor structure of claim 1, wherein, The projection of the gate structure on the substrate surface is located within the projection of the implanted doped region on the substrate surface.

4. The semiconductor structure of claim 1, wherein, Further comprising: a transition doped region of the same doping type between the gate structure and the implanted doped region, the transition doped region being in electrical contact with the implanted doped region and the transition doped region corresponding in position to the implanted doped region.

5. The semiconductor structure of claim 4, wherein, The transition doped region has a doping concentration greater than that of the implanted doped region.

6. The semiconductor structure of claim 4, wherein, The projection of the implanted doped region on the substrate surface at least partially overlaps a projection of the transition doped region on the substrate surface.

7. The semiconductor structure of claim 4, wherein, The projection of the implanted doped region on the substrate surface is located within the projection of the transition doped region on the substrate surface.

8. The semiconductor structure of claim 4, wherein, The transition doped region further extends between the gate structure and the drift region.

9. The semiconductor structure of claim 4, wherein, Further comprising: a body doped region on the drift region, the body doped region being of a doping type opposite to that of the drift region; The gate structure penetrates the body doped region in a direction perpendicular to the substrate surface and the body doped region is in electrical connection with the transition doped region.

10. The semiconductor structure of claim 9, wherein, The transition doped region further extends between the gate structure and the body doped region.

11. The semiconductor structure of claim 9, wherein the first and second semiconductor layers are formed of a same material. Further comprising: a first heavily doped layer on the body doped region, the first heavily doped layer being of a doping type opposite to that of the body doped region; The gate structure penetrates the first heavily doped layer in a direction perpendicular to the substrate surface.

12. The semiconductor structure of claim 11, wherein, Further comprising: a conductive plug penetrating the first heavily doped layer, the conductive plug being in electrical connection with the body doped region; a second heavily doped layer at the bottom of the conductive plug, the second heavily doped layer being in electrical connection with the conductive plug, the second heavily doped layer being of the same doping type as the body doped region and having a doping concentration greater than that of the body doped region.

13. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate comprising a substrate and an epitaxial layer on the substrate; etching the substrate to form a gate trench in the epitaxial layer; doping the substrate exposed by the gate trench to form an implanted doped region under the gate trench, the implanted doped region corresponding in position to the gate trench; forming a gate structure in the gate trench.

14. The method of forming a semiconductor structure of claim 13, wherein, The step of etching the substrate to form a gate trench in the epitaxial layer comprises: forming a hard mask layer with an opening on the substrate; etching the substrate to form a gate trench in the epitaxial layer with the hard mask layer as a mask.

15. The method of forming a semiconductor structure of claim 14, wherein, In the process of doping the substrate exposed by the gate trench to form an implanted doped region under the gate trench, the substrate exposed by the gate trench is doped with the hard mask layer as a mask.

16. The method of forming a semiconductor structure of claim 14, wherein, After the step of doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench, before the step of forming the gate structure in the gate trench, the method further comprises: doping the substrate between the gate trench and the implanted doping region to form a transition doping region between the bottom of the gate trench and the implanted doping region, the transition doping region is electrically connected with the implanted doping region and the position of the transition doping region corresponds to the position of the implanted doping region.

17. The method of forming a semiconductor structure of claim 16, wherein, In the step of doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region, the substrate between the gate trench and the implanted doping region is doped by taking the hard mask as a mask.

18. The method of forming a semiconductor structure of claim 17, wherein, The doping dose of the doping process for doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench is less than the doping dose of the doping process for doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region.

19. The method of forming a semiconductor structure of claim 16, wherein, In the step of doping the substrate between the gate trench and the implanted doping region to form the transition doping region between the bottom of the gate trench and the implanted doping region, the included angle between the implantation direction of the doping process and the normal direction of the substrate ranges from 15° to 45°.

20. The method of forming a semiconductor structure of claim 13, wherein, The method further comprises: After the step of etching the substrate to form the gate trench in the epitaxial layer, before the step of doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench, the method further comprises: performing an oxidation repair process on the gate trench to form a sacrificial protection layer on the surface of the gate trench; and in the step of doping the substrate exposed by the gate trench to form the implanted doping region under the gate trench, the substrate exposed by the gate trench with the sacrificial protection layer on the surface of the trench is doped to form the implanted doping region under the gate trench.

21. The method of forming a semiconductor structure of claim 13, wherein, The step of forming the gate structure in the gate trench comprises: forming a first gate oxide layer on the sidewall of the gate trench and the bottom of the gate trench by using a low-temperature thermal oxidation process; forming a second gate oxide layer on the first gate oxide layer by using a deposition process; forming a gate layer in the gate trench with the first gate oxide layer and the second gate oxide layer on the first gate oxide layer to form the gate structure.

22. The method of forming a semiconductor structure of claim 13, wherein, Before the step of etching the substrate to form the gate trench in the epitaxial layer, the method further comprises: doping the epitaxial layer to form a drift region and an initial body doping region on the drift region.

23. The method of forming a semiconductor structure of claim 22, wherein The method further comprises: After the step of forming the gate structure, doping the initial body doping regions on both sides of the gate structure to form a first heavily doped layer.

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