Gallium nitride integrated device

Abstract

Provided in the present application is a gallium nitride integrated device, comprising a substrate, a semiconductor epitaxial layer, a first source electrode, a first gate electrode, a first drain electrode, and a first cap layer. Specifically, the semiconductor epitaxial layer is disposed on a side of the substrate; the semiconductor epitaxial layer includes an enhancement mode gallium nitride device region and a depletion mode gallium nitride device region; the first source electrode, the first gate electrode, and the first drain electrode are all disposed in the depletion mode gallium nitride device region, and are disposed at intervals on the side of the semiconductor epitaxial layer away from the substrate; the first cap layer is disposed between the first gate electrode and the semiconductor epitaxial layer; and the first cap layer has a hollow portion. Specifically, the first cap layer is disposed between the semiconductor epitaxial layer and the first gate electrode, and the first cap layer has a hollow portion. The design of the first cap layer makes it unnecessary to etch the passivation layer when the first gate electrode is formed in the D-HEMT device region, thereby avoiding damage to the surface of a barrier layer (AlGaN) in the semiconductor epitaxial layer.

Description

Gallium nitride integrated devices Technical Field

[0001] This application relates to the field of semiconductor device technology, and more particularly to a gallium nitride integrated device. Background Technology

[0002] With the continuous upgrading of application scenarios, gallium nitride E&D-HEMT (Enhancement-Depletion High Electron Mobility Transistor) integrated devices with high current drive capability, high switching current ratio and low static power consumption have attracted widespread attention.

[0003] Currently, the gate formation of D-HEMT devices in integrated devices usually involves etching the passivation layer above the AlGaN (barrier layer) and then depositing the gate metal; however, this etching method can cause damage to the surface of the AlGaN layer. Technical solutions

[0004] This application provides a gallium nitride integrated device that can solve the problem of AlGaN surface damage caused during gate formation of D-HEMT devices in integrated devices.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a gallium nitride integrated device, comprising:

[0006] Substrate;

[0007] A semiconductor epitaxial layer is disposed on one side of the substrate; wherein the semiconductor epitaxial layer includes an enhancement-mode gallium nitride device region and a depletion-mode gallium nitride device region;

[0008] The first source, the first gate, and the first drain are all disposed in the depletion-type gallium nitride device region and are spaced apart on the side of the semiconductor epitaxial layer away from the substrate;

[0009] A first capping layer is disposed between the first gate and the semiconductor epitaxial layer;

[0010] The first cap layer has a perforated portion.

[0011] Unlike existing technologies, the beneficial effect of this application is that the gallium nitride integrated device provided in this application, in the depletion-mode gallium nitride (D-HEMT) device region, retains a first capping layer between the semiconductor epitaxial layer and the first gate, and the first capping layer has a cutout portion. When the device is forward-biased, the 2DEG (two-dimensional electron gas) in the semiconductor epitaxial layer located below the cutout portion is unaffected and can normally provide current. When the device is reverse-biased and cut off, as the voltage on the first gate increases in the reverse direction, the 2DEG below the area of ​​the first capping layer that does not correspond to the cutout portion is depleted first, followed by the 2DEG below the cutout portion gradually being depleted, thereby forming a large-area depletion region that blocks the conduction between the source and drain in the 2DEG region, thus turning off the device. In this way, the design of the first capping layer means that when forming the first gate in the D-HEMT device region, there is no need to etch the passivation layer, thereby avoiding damage to the surface of the barrier layer (AlGaN) in the semiconductor epitaxial layer. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0013] Figure 1 is a schematic diagram of a gallium nitride integrated device according to an embodiment of the present application;

[0014] Figure 2 is a partial structural schematic diagram of the gallium nitride integrated device shown in Figure 1;

[0015] Figure 3 is a top view of the gallium nitride integrated device shown in Figure 2;

[0016] Figure 4 is a cross-sectional view of the gallium nitride integrated device shown in Figure 1 along line AA in Figure 3;

[0017] Figure 5 is a cross-sectional view of the gallium nitride integrated device shown in Figure 1 along line BB in Figure 3;

[0018] Figure 6 is a cross-sectional view along line AA in Figure 3 of another embodiment of the gallium nitride integrated device provided in this application.

[0019] Label Explanation:

[0020] Substrate-101; Semiconductor epitaxial layer-102; First semiconductor layer-1021; Channel layer-1022; Second semiconductor layer-1023; First source-103; Second source-104; First gate-105; Second gate-106; First drain-107; Second drain-108; First capping layer-109; Sub-capping portion-1090; Second capping layer-110; Isolation layer-111; Passivation layer-112; First Schottky contact metal-113; Second Schottky contact metal-114; First field plate dielectric-115; First field plate metal-116; Second field plate dielectric-117; Second field plate metal-118; Insulating layer-119; First source interconnect metal-120; Second source interconnect metal-121; First drain interconnect metal-122; Second drain interconnect metal-123;

[0021] Enhancement-mode gallium nitride (GaN) device region - A1; Depletion-mode gallium nitride (GaN) device region - A2;

[0022] First direction - X, second direction - Y; thickness direction - Z. Embodiments of the present invention

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0024] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] In related technologies, to avoid AlGaN surface damage caused during gate formation in D-HEMT devices, a thin passivation layer can be grown on the AlGaN (barrier layer) surface to prevent this problem. However, this method is difficult to apply to E&D-HEMT integrated devices, mainly because:

[0028] 1) Since the passivation layer between the gate and the barrier layer in the E-HEMT device region needs to be thicker, the passivation layer in the D-HEMT device region will become thicker while satisfying the structure of the E-HEMT device in the integrated device, which in turn causes the threshold voltage of the D-HEMT device in the integrated device to reach -30V~-40V.

[0029] 2) To avoid the threshold voltage of D-HEMT devices in integrated devices being too negative, a photomask needs to be added to etch or thin the passivation layer under the gate of the D-HEMT device region, which increases the cost.

[0030] To address this situation, please refer to Figures 1-6. Figure 1 is a schematic diagram of the structure of an embodiment of the gallium nitride integrated device provided in this application; Figure 2 is a partial schematic diagram of the structure of the gallium nitride integrated device shown in Figure 1; Figure 3 is a top view of the gallium nitride integrated device shown in Figure 2; Figure 4 is a cross-sectional view of the gallium nitride integrated device shown in Figure 1 along line AA in Figure 3; Figure 5 is a cross-sectional view of the gallium nitride integrated device shown in Figure 1 along line BB in Figure 3; Figure 6 is a cross-sectional view of another embodiment of the gallium nitride integrated device provided in this application along line AA in Figure 3. This application provides a gallium nitride integrated device, including a substrate 101, a semiconductor epitaxial layer 102, a first source 103, a second source 104, a first gate 105, a second gate 106, a first drain 107, a second drain 108, a first capping layer 109, and a second capping layer 110.

[0031] The substrate 101 may include a base and a transition layer. Silicon (Si) or sapphire (Al₂O₃) can be used as the base; AlGaN can be used as the transition layer. Alternatively, the substrate 101 may consist only of a base.

[0032] The semiconductor epitaxial layer 102 is disposed on one side of the substrate 101; and the semiconductor epitaxial layer 102 includes a first semiconductor layer 1021, a channel layer 1022, and a second semiconductor layer 1023. Specifically, the first semiconductor layer 1021 is disposed on one side of the substrate 101, and the material of the first semiconductor layer 1021 includes GaN, serving as a buffer layer; the second semiconductor layer 1023 is disposed on the side of the first semiconductor layer 1021 facing away from the substrate 101, and the material of the second semiconductor layer 1023 includes AlGaN, serving as a barrier layer to prevent charge carriers in the channel layer 1022 from flowing toward the barrier layer; the channel layer 1022 is located between the interface of the first semiconductor layer 1021 and the second semiconductor layer 1023, and can be used to provide a channel for charge carrier movement, and the channel layer 1022 includes unintentionally doped GaN to form a two-dimensional electron gas (2DEG).

[0033] The semiconductor epitaxial layer 102 includes an enhancement-mode gallium nitride (E-HEMT) region A1 and a depletion-mode gallium nitride (D-HEMT) region A2. In one embodiment, the gallium nitride integrated device further includes an isolation layer 111 that penetrates the semiconductor epitaxial layer 102 along the thickness direction Z to divide the semiconductor epitaxial layer 102 into the enhancement-mode gallium nitride region A1 and the depletion-mode gallium nitride region A2.

[0034] Specifically, the isolation layer 111 is disposed between the enhancement-mode gallium nitride device region A1 and the depletion-mode gallium nitride device region A2 to block the 2DEG channel between E&D-HEMT and prevent short circuits between E-HEMT and D-HEMT devices in the integrated device.

[0035] The isolation layer 111 can be formed by ion implantation, and the implanted ions of the isolation layer 111 include, but are not limited to, at least one element selected from H, He, F, Mg, Ar, Zn, and Si.

[0036] The first source 103, the first gate 105 and the first drain 107 are all disposed in the depletion-type gallium nitride device region A2 and are spaced apart on the side of the semiconductor epitaxial layer 102 away from the substrate 101.

[0037] The second source 104, the second gate 106, and the second drain 108 are all disposed in the enhancement-mode gallium nitride device region A1 and are spaced apart on the side of the semiconductor epitaxial layer 102 away from the substrate 101.

[0038] In this embodiment, the first source 103, the second source 104, the first gate 105, the second gate 106, the first drain 107, and the second drain 108 are all arranged at intervals along the first direction X and all extend along the second direction Y; and the first source 103 and the first drain 107 are located on opposite sides of the first gate 105, and the second source 104 and the second drain 108 are located on opposite sides of the second gate 106.

[0039] In this embodiment, the first direction X, the second direction Y, and the thickness direction Z of the substrate 101 all intersect each other. In this embodiment, the first direction X and the second direction Y are both parallel to the surface of the semiconductor epitaxial layer 102 away from the substrate 101, and the first direction X and the second direction Y are perpendicular. Furthermore, the thickness direction Z of the substrate 101, the first direction X, and the second direction Y are all perpendicular.

[0040] The conductive metal systems of the first source 103, the second source 104, the first gate 105, the second gate 106, the first drain 107, and the second drain 108 include, but are not limited to, Ti, Al, Ni, Au, or Ta, as well as alloys or compounds containing the above-mentioned metal systems.

[0041] The first capping layer 109 is disposed between the first gate 105 and the semiconductor epitaxial layer 102 and extends toward the second direction Y; and the first capping layer 109 has a hollow portion.

[0042] The second capping layer 110 is disposed between the second gate 106 and the semiconductor epitaxial layer 102 and is connected to the second gate 106, and the second capping layer 110 extends toward the second direction Y.

[0043] The materials of the first capping layer 109 and the second capping layer 110 include, but are not limited to, p-GaN, p-AlGaN, p-InGaN or p-InAlGaN, etc., and are not limited here.

[0044] Specifically, in the enhancement-mode gallium nitride device region A1, the second capping layer 110 is used to deplete the 2DEG below the first gate 105, thereby turning off the E-HEMT device. This is prior art and will not be described in detail here.

[0045] In the depletion-mode gallium nitride device region A2, by retaining a first capping layer 109 between the semiconductor epitaxial layer 102 and the first gate 105, and the first capping layer 109 having a cutout portion, when the device is forward-biased, the 2DEG in the semiconductor epitaxial layer 102 located below the cutout portion region is unaffected and can provide current normally; when the device is reverse-biased and cut off, as the voltage on the first gate 105 increases in the reverse direction, the 2DEG below the region of the first capping layer 109 that does not correspond to the cutout portion is depleted first, and then the 2DEG below the cutout portion region is gradually depleted, thereby forming a large area depletion region that blocks the conduction between the source and drain in the 2DEG region, and thus the D-HEMT device is turned off.

[0046] Furthermore, by adjusting the size of the cutout, the threshold voltage of the D-HEMT device region can be controlled, thus preventing the threshold voltage of the D-HEMT device region from being too positive or too negative.

[0047] Therefore, the design of the first capping layer 109 allows the D-HEMT device region to form the first gate 105 without etching or thinning the passivation layer 112, thereby reducing the number of photomasks and avoiding damage to the surface of the barrier layer.

[0048] Furthermore, it is understandable that since the capping layers (first capping layer 109 and second capping layer 110) deplete the underlying 2DEG, the larger the size of the capping layer, the stronger the depletion effect on the underlying 2DEG. Therefore, the threshold voltage of the depletion-mode gallium nitride device region A2 is negatively correlated with the area of ​​the hollow portion in the first capping layer 109. That is, the larger the area of ​​the hollow portion in the first capping layer 109, the weaker the depletion effect of the capping layer 109 on the 2DEG below the hollow portion, and the more negative the negative voltage required to turn off the D-HEMT device; the smaller the area of ​​the hollow portion in the first capping layer 109, the stronger the depletion effect of the capping layer 109 on the 2DEG below the hollow portion, and the more positive the negative voltage required to turn off the D-HEMT device.

[0049] Furthermore, it is understandable that since the first capping layer 109 and the second capping layer 110 are formed in the same process, forming the first capping layer 109 in the depletion-mode gallium nitride device region A2 will not require additional fabrication processes.

[0050] In one embodiment, referring to Figures 1-3, the first cap layer 109 includes a plurality of sub-cap portions 1090 spaced apart along the second direction Y, the interval region between the plurality of sub-cap portions 1090 serves as a cutout portion, and the orthographic projection of the first gate 105 on the first cap layer 109 covers the plurality of sub-cap portions 1090 and the interval region between two adjacent sub-cap portions 1090.

[0051] Specifically, the first capping layer 109 includes a plurality of sub-capping portions 1090 spaced apart along the second direction Y. When the device is forward-biased, the 2DEG in the semiconductor epitaxial layer 102 located below the gap region between two adjacent sub-capping portions 1090 is unaffected and can provide current normally. When the device is reverse-biased, as the voltage on the first gate 105 increases in the reverse direction, the 2DEG below the regions of the plurality of sub-capping portions 1090 are first depleted, and then the 2DEG below the gap region between two adjacent sub-capping portions 1090 are gradually depleted, thereby forming a large area of ​​depletion region that blocks the conduction between the source and drain in the 2DEG region, and thus the D-HEMT device is turned off.

[0052] Furthermore, it is understandable that the threshold voltage of the D-HEMT device region can be controlled by adjusting the density between multiple sub-cap portions 1090 (the spacing between two adjacent sub-cap portions 1090).

[0053] Each subcap portion 1090 can be a continuous seamless structure (see Figure 3), or each subcap portion 1090 can be patterned, which is not limited here.

[0054] Specifically, after patterning each sub-cap portion 1090, the cutout portion of the first cap layer 109 includes the spacing region between two adjacent sub-cap portions 1090 and the patterned region on each sub-cap portion 1090. Furthermore, the threshold voltage of the D-HEMT device region is also related to the patterned region on each sub-cap portion 1090.

[0055] In one embodiment, referring to FIG1, the gallium nitride integrated device further includes a passivation layer 112 covering the semiconductor epitaxial layer 102.

[0056] The passivation layer 112 has a first opening (not shown) corresponding to the first source 103, a second opening (not shown) corresponding to the first drain 107, a fourth opening (not shown) corresponding to the second source 104, a fifth opening (not shown) corresponding to the second drain 108, and a sixth opening (not shown) corresponding to the second capping layer 110. Specifically, the first source 103 is at least partially disposed within the first opening and in contact with the semiconductor epitaxial layer 102; the first drain 107 is at least partially disposed within the second opening and in contact with the semiconductor epitaxial layer 102; the second source 104 is at least partially disposed within the fourth opening and in contact with the semiconductor epitaxial layer 102; the second drain 108 is at least partially disposed within the fifth opening and in contact with the semiconductor epitaxial layer 102; and the second capping layer 110 is disposed within the sixth opening and in contact with the semiconductor epitaxial layer 102.

[0057] The second gate 106 is disposed on the side of the passivation layer 112 away from the substrate 101, and at least a portion of the second gate 106 extends into the sixth opening and is connected to the second capping layer 110.

[0058] In one embodiment, referring to Figures 4 and 5, the first capping layer 109 is in contact with the semiconductor epitaxial layer 102, and the passivation layer 112 also covers each sub-capping portion 1090. The first gate 105 is disposed on the side of the passivation layer 112 away from the substrate 101. The passivation layer 112 spaces the first gate 105 from each sub-capping portion 1090, and the first gate 105 is capacitively coupled to the first capping layer 109 through the passivation layer 112.

[0059] Understandably, in this embodiment, the first gate 105 is capacitively coupled to the first capping layer 109 through the passivation layer 112. When forming the first gate 105, there is no need to etch or thin the passivation layer 112, thereby reducing the primary photomask and avoiding damage to the surface of the barrier layer.

[0060] In another embodiment, referring to FIG6, the first capping layer 109 is in contact with the semiconductor epitaxial layer 102, the passivation layer 112 has a third opening corresponding to the region of each sub-capping portion 1090, the first gate 105 is disposed on the side of the passivation layer 112 away from the substrate 101, and at least a portion of the first gate 105 extends into the third opening and is connected to the sub-capping portion 1090.

[0061] Understandably, in this embodiment, the third opening on the passivation layer 112 terminates at the first capping layer 109. Thus, when the first gate 105 is formed, the first gate 105 is connected to the first capping layer 109 through the third opening, which can avoid damage to the surface of the barrier layer.

[0062] In this embodiment, referring to FIG1, each sub-cap portion 1090 has a first Schottky contact metal 113 disposed on the surface opposite to the substrate 101, and the first gate 105 is connected to the sub-cap portion 1090 through the first Schottky contact metal 113. Furthermore, the second cap layer 110 has a second Schottky contact metal 114 disposed on the surface opposite to the substrate 101, and the second gate 106 is connected to the second cap layer 110 through the second Schottky contact metal 114.

[0063] The first Schottky contact metal 113 and the second Schottky contact metal 114 include, but are not limited to, Ti, Ag, Ni, Al, etc., as well as alloys or compounds containing the above metal systems. In the embodiments of this application, the first Schottky contact metal 113 and the second Schottky contact metal 114 can be TIN. The first Schottky contact metal 113 and the second Schottky contact metal 114 are used to reduce the leakage current of the first gate 105 and the second gate 106.

[0064] In gallium nitride devices, a large electric field peak exists at the gate edge when the device is turned off. In this embodiment, a multi-level field plate is added above the passivation layer 112 to alleviate the dense electric field lines in the gate region and regulate the voltage withstand capability of the device.

[0065] Specifically, referring to Figure 1, the gallium nitride integrated device also includes a primary field plate dielectric 115 and a primary field plate metal 116. The primary field plate dielectric 115 is disposed in the enhancement-mode gallium nitride device region A1 and the depletion-mode gallium nitride device region A2, and is located on the surface of the passivation layer 112 opposite to the substrate 101. The primary field plate metal 116 is disposed in the enhancement-mode gallium nitride device region A1 and the depletion-mode gallium nitride device region A2, and at least a portion of the projection of the primary field plate metal 116 onto the substrate 101 overlaps with at least a portion of the projection of the primary field plate dielectric 115 onto the substrate 101.

[0066] It should be noted that the primary field plate metal 116 includes a first field plate portion 1161 located in the enhancement-mode gallium nitride device region A1 and a second field plate portion 1162 located in the depletion-mode gallium nitride device region A2, and the first field plate portion 1161 and the second field plate portion 1162 are insulated from each other.

[0067] Specifically, the primary field plate dielectric 115 and the primary field plate metal 116 located in the enhancement-mode gallium nitride device region A1 and the depletion-mode gallium nitride device region A2, respectively, can improve the voltage withstand capability of the corresponding device regions. Furthermore, the overlapping area of ​​the projection of the field plate dielectric and the primary field plate metal 116 also forms an equivalent capacitance, further improving the voltage withstand capability of the device.

[0068] In this embodiment of the application, during the fabrication process, the morphology near the first gate 105 and the second gate 106 can be adjusted by designing the thickness of the primary field plate dielectric 115, and the device's withstand voltage capability can be further improved when forming multi-stage field plates in the future.

[0069] In this embodiment, in the enhancement-mode gallium nitride device region A1, the source field plate serves as the first field plate portion 1161 of the primary field plate metal 116; in the depletion-mode gallium nitride device region A2, the end of the first gate 105 near the first drain 107 serves as the second field plate portion 1162 of the primary field plate metal 116.

[0070] Further, referring to Figure 1, the gallium nitride integrated device may further include a secondary field plate dielectric 117 and a secondary field plate metal 118. The secondary field plate dielectric 117 is disposed in the enhancement-mode gallium nitride device region A1 and the depletion-mode gallium nitride device region A2, and is disposed on the surface of the passivation layer 112 facing away from the substrate 101, covering the primary field plate dielectric 115 and the primary field plate metal 116; the secondary field plate metal 118 is disposed in the enhancement-mode gallium nitride device region A1, and the secondary field plate metal 118, the secondary field plate dielectric 117, the primary field plate metal 116, and the primary field plate dielectric 115 have a projected overlapping region on the substrate 101.

[0071] Specifically, the secondary field plate dielectric 117 and the secondary field plate metal 118 can further improve the device breakdown voltage in the corresponding region. The primary field plate dielectric 115, the primary field plate metal 116, and the secondary field plate dielectric 117 located in the depletion-type gallium nitride device region A2 effectively form a secondary field plate capacitor. The primary field plate dielectric 115, the primary field plate metal 116, the secondary field plate dielectric 117, and the secondary field plate metal 118 located in the enhancement-type gallium nitride device region A1 effectively form a tertiary field plate capacitor, thereby further enhancing the device breakdown voltage.

[0072] Furthermore, in this application, the secondary field plate dielectric 117 can achieve insulation between the first source 103, the second source 104, the first gate 105, the second gate 106, the first drain 107, and the second drain 108.

[0073] In this embodiment, the gallium nitride integrated device further includes an insulating layer 119, which is disposed in the enhancement-mode gallium nitride device region A1 and the depletion-mode gallium nitride device region A2, and is located on the side of the secondary field plate dielectric 117 away from the substrate 101, and covers the secondary field plate metal 118.

[0074] Specifically, the insulating layer 119 is used to prevent moisture and other substances from entering the device and can also play a certain role in insulation protection.

[0075] In this embodiment of the application, please continue to refer to Figure 1. The gallium nitride integrated device also includes a first source interconnect metal 120, a second source interconnect metal 121, a first drain interconnect metal 122, and a second drain interconnect metal 123.

[0076] Specifically, a first source interconnect metal 120 is disposed on the side of the insulating layer 119 away from the substrate 101, and the first source interconnect metal 120 is connected to the first source 103 through a seventh opening (not shown) penetrating the insulating layer 119 and the secondary field plate dielectric 117; a second source interconnect metal 121 is disposed on the side of the insulating layer 119 away from the substrate 101 and spaced from the first source interconnect metal 120, and the second source interconnect metal 121 is connected to the second source 104 through an eighth opening (not shown) penetrating the insulating layer 119 and the secondary field plate dielectric 117; a first drain interconnect metal 122 is disposed on the insulating layer 119. 19 is disposed on the side of the insulating layer 119 away from the substrate 101 and spaced apart from the first source interconnect metal 120 and the second source interconnect metal 121, and the first drain interconnect metal 122 is connected to the first drain 107 through a ninth opening (not shown) penetrating the insulating layer 119 and the secondary field plate dielectric 117; the second drain interconnect metal 123 is disposed on the side of the insulating layer 119 away from the substrate 101 and spaced apart from the first drain interconnect metal 122 and the second source interconnect metal 121, and the first drain interconnect metal 122 is connected to the second drain 108 through a tenth opening (not shown) penetrating the insulating layer 119 and the secondary field plate dielectric 117.

[0077] Specifically, the first source interconnect metal 120 serves as the output terminal of the logic circuit of the external electrode of the first source 103, the second source interconnect metal 121 serves as the ground terminal of the logic circuit of the external electrode of the second source 104, the first drain interconnect metal 122 serves as the power input terminal of the logic circuit of the external electrode of the first drain 107, and the second drain interconnect metal 123 serves as the output terminal of the logic circuit of the external electrode of the second drain 108.

[0078] In one embodiment, the first source interconnect metal 120 and the second drain interconnect metal 123 are shared. That is, the first source 103 and the second drain 108 are shorted together through the first source interconnect metal 120 and the second drain interconnect metal 123. Specifically, setting the first source 103 and the second drain 108 to share interconnect metal can reduce the number of ports in the integrated device, simplify the process, and reduce costs.

[0079] Specifically, this application provides a gallium nitride integrated device, the structure of which includes, from bottom to top, a substrate 101, a first semiconductor layer 1021 (buffer layer), a channel layer 1022, a second semiconductor layer 1023 (barrier layer), capping layers (first capping layer 109 and second capping layer 110), and a passivation layer 112. A Schottky contact metal is grown above the capping layer, forming a Schottky contact with the lower capping layer. The first capping layer 109 of the D-HEMT device region is spaced apart in the extension direction, and the threshold voltage of the D-HEMT device region can be controlled by adjusting the density of the multiple sub-capping portions 1090 in the first capping layer 109. The first source 103, first drain 107, second source 104, and second drain 108 form ohmic contacts with the barrier layer after etching the passivation layer 112 and part of the barrier layer. Furthermore, an isolation layer 111 is formed through ion implantation to block the 2DEG channel between E&D-HEMT, preventing short circuits in the device.

[0080] Then, an insulating dielectric is grown over the passivation layer 112 and the source-drain ohmic metal, and a portion of the dielectric grown between the source and drain is etched. The remaining dielectric between the source and drain serves as the primary field plate dielectric 115 to improve the device's withstand voltage capability. The passivation layer 112 above the second capping layer 110 is also etched for interconnection between the second gate 106 and the Schottky contact metal above the second capping layer 110. Gate metal and field plate metal are grown. The gate metal forms a first gate 105 and a second gate 106, which are connected in series after the external electrode to serve as the input terminal Vin of the logic circuit. At the same time, the second gate 106 is interconnected with the lower Schottky contact metal, and the first gate 105 forms a Schottky contact with the lower passivation layer 112. The first field plate metal is formed by the first gate 105 forming one end near the first drain 107 and the source field plate of the enhancement-mode gallium nitride device region A1. The source field plate of the enhancement-mode gallium nitride device region A1 forms a Schottky contact with the passivation layer 112 and an ohmic contact with the first-level field plate dielectric 115. Both are used to further improve the device's withstand voltage capability.

[0081] Furthermore, as one implementation scheme, the thickness of the primary field plate dielectric 115 extending from the gate region to the drain region can be reduced or increased, thereby adjusting the morphology near the gate and subsequently forming a multi-level field plate through the gate metal, further improving the device's withstand voltage capability.

[0082] A secondary field plate dielectric 117 and a secondary field plate metal 118 are further grown above the primary field plate metal 116. The multi-stage field plate is used to further improve the device's withstand voltage capability. An insulating layer 119 is grown above the secondary field plate metal 118 and the secondary field plate dielectric 117. The secondary field plate dielectric 117 and the insulating layer 119 above the source and drain ohmic metals are etched to serve as metal interconnect vias.

[0083] Finally, interconnect metal is grown above the source-drain ohmic metal and the insulating layer 119. The interconnect metal includes a first source interconnect metal 120, which serves as the output terminal of the logic circuit as the external electrode of the first source 103; a second source interconnect metal 121, which serves as the ground terminal of the logic circuit as the external electrode of the second source 104; a first drain interconnect metal 122, which serves as the power input terminal of the logic circuit as the external electrode of the first drain 107; and a second drain interconnect metal 123, which serves as the output terminal of the logic circuit as the external electrode of the second drain 108.

[0084] Specifically, the gallium nitride integrated device provided in this application has the following advantages:

[0085] 1. The design of the first capping layer 109 allows the D-HEMT device region to form the first gate 105 without etching or thinning the passivation layer 112, thereby reducing the number of photomasks and avoiding damage to the surface of the barrier layer.

[0086] 2. By adjusting the size of the cutout, the threshold voltage of the D-HEMT device region can be controlled, thus preventing the threshold voltage of the D-HEMT device from being too positive or too negative.

[0087] 3. A multi-level field plate structure is formed near the gate, thereby improving the device's withstand voltage capability.

[0088] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A gallium nitride integrated device, characterized in that, include: Substrate; A semiconductor epitaxial layer is disposed on one side of the substrate; wherein the semiconductor epitaxial layer includes an enhancement-mode gallium nitride device region and a depletion-mode gallium nitride device region; The first source, the first gate, and the first drain are all disposed in the depletion-type gallium nitride device region and are spaced apart on the side of the semiconductor epitaxial layer away from the substrate; A first capping layer is disposed between the first gate and the semiconductor epitaxial layer; The first cap layer has a perforated portion.

2. The gallium nitride integrated device according to claim 1, characterized in that, The threshold voltage of the depletion-type gallium nitride device region is negatively correlated with the area of ​​the hollow portion in the first capping layer.

3. The gallium nitride integrated device according to claim 1, wherein the first source, the first gate, and the first drain are arranged at intervals along a first direction; the first gate, the first source, the first drain, and the first capping layer all extend along a second direction; the first direction, the second direction, and the thickness direction of the substrate all intersect each other; in, The first cap layer includes a plurality of sub-cap portions spaced apart along the second direction, and the orthographic projection of the first gate on the first cap layer covers the plurality of sub-cap portions and the interval region between two adjacent sub-cap portions.

4. The gallium nitride integrated device according to claim 3, characterized in that, The gallium nitride integrated device also includes: A passivation layer covers the semiconductor epitaxial layer; the passivation layer has a first opening corresponding to the first source and a second opening corresponding to the first drain, the first source is at least partially disposed in the first opening and in contact with the semiconductor epitaxial layer, the first drain is at least partially disposed in the second opening and in contact with the semiconductor epitaxial layer; the first gate is located on the side of the passivation layer away from the substrate; the first capping layer is in contact with the semiconductor epitaxial layer.

5. The gallium nitride integrated device according to claim 4, characterized in that, The passivation layer also covers each of the sub-cap portions to space the first gate from each of the sub-cap portions; Alternatively, the passivation layer has a third opening corresponding to the region of each of the sub-cap portions, and at least a portion of the first gate extends into the third opening and is connected to the sub-cap portion.

6. The gallium nitride integrated device according to claim 5, characterized in that, Each of the subcap portions has a first Schottky contact metal on the surface opposite to the substrate, and the first gate is connected to the subcap portion through the first Schottky metal.

7. The gallium nitride integrated device according to claim 4, characterized in that, The gallium nitride integrated device also includes: A primary field plate dielectric is disposed in the enhancement-mode gallium nitride device region and the depletion-mode gallium nitride device region, and is located on the surface of the passivation layer opposite to the substrate; A primary field plate metal is disposed in the enhancement-mode gallium nitride device region and the depletion-mode gallium nitride device region, and at least a portion of the projection of the primary field plate metal onto the substrate overlaps with at least a portion of the projection of the primary field plate dielectric onto the substrate.

8. The gallium nitride integrated device according to claim 7, characterized in that, The gallium nitride integrated device also includes: A secondary field plate dielectric is disposed in the enhancement-mode gallium nitride device region and the depletion-mode gallium nitride device region, and is disposed on the surface of the passivation layer opposite to the substrate, and covers the primary field plate dielectric and the primary field plate metal; A secondary field plate metal is disposed in the region of the enhanced gallium nitride device, and the secondary field plate metal, the secondary field plate dielectric, the primary field plate metal, and the primary field plate dielectric have a projected overlapping region on the substrate.

9. The gallium nitride integrated device according to claim 8, characterized in that, The enhanced gallium nitride device region is also provided with: The second source, the second gate, and the second drain are all disposed in the region of the enhanced gallium nitride device and are spaced apart on the side of the semiconductor epitaxial layer away from the substrate. The second capping layer is disposed between the second gate and the semiconductor epitaxial layer and is connected to the second gate, and the second source, the second gate, and the second drain are arranged at intervals along the first direction; the second source, the second gate, the second drain, and the second capping layer all extend along the second direction; The passivation layer has a fourth opening corresponding to the second source, a fifth opening corresponding to the second drain, and a sixth opening corresponding to the second capping layer. The second source electrode is at least partially disposed within the fourth opening and in contact with the semiconductor epitaxial layer; the second drain electrode is at least partially disposed within the fifth opening and in contact with the semiconductor epitaxial layer; the second capping layer is disposed within the sixth opening and in contact with the semiconductor epitaxial layer; and a second Schottky contact metal is disposed on the surface of the second capping layer facing away from the substrate; the second gate electrode is disposed on the side of the passivation layer facing away from the substrate; and the second gate electrode extends at least partially into the sixth opening and is connected to the second capping layer through the second Schottky metal.

10. The gallium nitride integrated device according to claim 9, characterized in that, The gallium nitride integrated device also includes: An insulating layer is disposed in the enhancement-mode gallium nitride device region and the depletion-mode gallium nitride device region, and is located on the side of the secondary field plate dielectric away from the substrate; A first source interconnect metal is disposed on the side of the insulating layer away from the substrate, and the first source interconnect metal is connected to the first source through a seventh opening that penetrates the insulating layer and the secondary field plate dielectric. The second source interconnect metal is disposed on the side of the insulating layer away from the substrate and spaced apart from the first source interconnect metal, and the second source interconnect metal is connected to the second source through an eighth opening that penetrates the insulating layer and the secondary field plate medium; The first drain interconnect metal is disposed on the side of the insulating layer away from the substrate and spaced apart from the first source interconnect metal and the second source interconnect metal, and the first drain interconnect metal is connected to the first drain through a ninth opening that penetrates the insulating layer and the secondary field plate dielectric. The second drain interconnect metal is disposed on the side of the insulating layer away from the substrate and spaced apart from the first drain interconnect metal and the second source interconnect metal, and the first drain interconnect metal is connected to the second drain through a tenth opening that penetrates the insulating layer and the secondary field plate dielectric.

11. The gallium nitride integrated device according to claim 10, characterized in that, The first source interconnect metal is shared with the second drain interconnect metal.

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