Array substrate and display panel

Abstract

Disclosed in the embodiments of the present application are an array substrate and a display panel. The array substrate comprises a thin-film transistor, a gate insulating layer of which comprises a first portion and a second portion, wherein the first portion covers an edge portion, and the second portion covers a body portion. The thin-film transistor is an N-type thin-film transistor, and the quantity of positive charges that the first portion has is less than the quantity of positive charges that the second portion has; or the thin-film transistor is a P-type thin-film transistor, and the quantity of negative charges that the first portion has is less than the quantity of negative charges that the second portion has.

Description

Array substrate and display panel Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are key components in the active drive and peripheral circuits of display devices such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). Currently, N-type LTPS exhibit a peak effect, with poor electrical properties in the subthreshold region, limiting the charging capability of high-specification products. The peak effect is caused by the fact that currently manufactured N-type LTPS can be considered as consisting of edge TFTs on both sides connected in parallel with a main TFT in the middle. The threshold voltage (Vth) of the edge TFTs is relatively negative compared to the main TFT, leading to an abnormally large increase in the subthreshold current of the main TFT. Invention Overview

[0003] This application provides an array substrate and a display panel that can reduce the risk of the hump effect in thin-film transistors.

[0004] On one hand, embodiments of this application provide an array substrate, which includes:

[0005] Substrate; and

[0006] A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The gate insulating layer covers the side of the active layer away from the substrate. The gate insulating layer includes a first portion and a second portion connected together. The first portion covers the edge portion, and the second portion covers the main body portion.

[0007] The gate is disposed on the side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion;

[0008] In a plan view of the array substrate, the first contact portion, the channel, and the second contact portion are arranged sequentially in a first direction; in a second direction perpendicular to the first direction, one of the edge portions is located on one side of the main body portion.

[0009] Wherein, the thin-film transistor is an N-type thin-film transistor, and the first part has fewer positive charges than the second part; or

[0010] The thin-film transistor is a P-type thin-film transistor, and the first part has fewer negative charges than the second part.

[0011] On the other hand, embodiments of this application also provide a display panel, which includes an array substrate as described in any of the above embodiments. Attached Figure Description

[0012] Figure 1 is a partial plan view of an array substrate provided in one or more embodiments of this application;

[0013] Figure 2 is a schematic cross-sectional view of the structure along line AA in Figure 1;

[0014] Figure 3 is a schematic cross-sectional view of the structure along line BB in Figure 1;

[0015] Figure 4 is a schematic diagram of step B1 of the array substrate fabrication method provided in the embodiment of this application;

[0016] Figure 5 is a schematic diagram of step B2 of the array substrate fabrication method provided in the embodiment of this application;

[0017] Figure 6 is a schematic diagram of step B3 of the array substrate fabrication method provided in the embodiment of this application;

[0018] Figure 7 is a schematic diagram of step B4 of the array substrate fabrication method provided in the embodiment of this application;

[0019] Figure 8 is a comparison of the transfer curves of thin-film transistors with drain voltage Vd=0.1V and drain voltage Vd=10V in Comparative Example 1, Comparative Example 2 and the experimental example of this application.

[0020] Figure 9 is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Embodiments of the present invention

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0022] On one hand, embodiments of this application provide an array substrate, which includes:

[0023] Substrate; and

[0024] A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The gate insulating layer covers the side of the active layer away from the substrate. The gate insulating layer includes a first portion and a second portion connected together. The first portion covers the edge portion, and the second portion covers the main body portion.

[0025] The gate is disposed on the side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion;

[0026] In a plan view of the array substrate, the first contact portion, the channel, and the second contact portion are arranged sequentially in a first direction; in a second direction perpendicular to the first direction, one of the edge portions is located on one side of the main body portion.

[0027] Wherein, the thin-film transistor is an N-type thin-film transistor, and the first part has fewer positive charges than the second part; or

[0028] The thin-film transistor is a P-type thin-film transistor, and the first part has fewer negative charges than the second part.

[0029] Optionally, in some embodiments of this application, the thin-film transistor is an N-type thin-film transistor, and the number of positive charges per unit area of ​​the second portion is greater than or equal to ten times the number of positive charges per unit area of ​​the first portion.

[0030] Optionally, in some embodiments of this application, the thickness of the first part is less than the thickness of the second part.

[0031] Optionally, in some embodiments of this application, the thickness difference between the first part and the second part is between 80 angstroms and 200 angstroms.

[0032] Optionally, in some embodiments of this application, the thickness of the second part is between 600 angstroms and 2000 angstroms.

[0033] Optionally, in some embodiments of this application, the slope angle of the edge portion is between 30 degrees and 80 degrees.

[0034] Optionally, in some embodiments of this application, the thickness of the main body is between 300 angstroms and 600 angstroms.

[0035] Optionally, in some embodiments of this application, the array substrate further includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer, and a pixel electrode. The light-shielding layer is located on the substrate, the buffer layer covers the light-shielding layer and the substrate, the active layer is disposed on the side of the buffer layer away from the substrate, the gate insulating layer covers the active layer, the interlayer dielectric layer covers the gate, the source and the drain are disposed on the side of the interlayer dielectric layer away from the substrate, the planarization layer covers the source and the drain, the pixel electrode is disposed on the side of the planarization layer away from the substrate, and the pixel electrode is connected to the source or the drain.

[0036] Optionally, in some embodiments of this application, the gate insulating layer further includes a third portion connected to one side of the first portion, the third portion directly covering the buffer layer, and the third portion having a greater number of positive charges than the first portion.

[0037] Optionally, in some embodiments of this application, the amount of positive charge in the first portion and the second portion decreases in the direction from the active layer toward the gate.

[0038] On the other hand, embodiments of this application also provide a display panel, which includes an array substrate as described in any of the above embodiments.

[0039] The array substrate of this application embodiment includes a thin-film transistor (TFT). The TFT includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion, and the edge portion has a slope angle of less than 90 degrees. The gate insulating layer at least covers the side of the channel away from the substrate. The gate insulating layer includes a first portion and a second portion connected together. The first portion covers the edge portion, and the second portion covers the main body portion. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion. The TFT is an N-type TFT, where the number of positive charges in the first portion is less than the number of positive charges in the second portion; or the TFT is a P-type TFT, where the number of negative charges in the first portion is less than the number of negative charges in the second portion.

[0040] In this embodiment, the charge amount of the first part of the gate insulating layer is less than that of the second part when the thin film transistor is turned on. Because the charge amount of the first part is less, the threshold voltage of the edge part shifts less in the negative or positive direction under the same gate voltage, while the threshold voltage of the corresponding main part shifts more in the negative or positive direction. This eliminates the difference in threshold voltage between the edge thin film transistor with the edge part and the main thin film transistor with the main part, thereby improving the hump effect of the thin film transistor.

[0041] This application provides an array substrate, a method for fabricating the same, and a display panel, which are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0042] Please refer to Figures 1 to 3. Figure 1 is a partial plan view of an array substrate provided in one or more embodiments of this application. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1.

[0043] In Figures 1 to 3, the first direction DR1 can be a direction parallel to one side of the array substrate 100 in a plan view, such as the longitudinal direction of the array substrate 100, but is not limited thereto. The second direction DR2 can be a direction parallel to the other side of the array substrate 100 in a plan view, such as the transverse direction of the array substrate 100, but is not limited thereto. The third direction DR3 can be the thickness direction of the array substrate 100.

[0044] One or more embodiments of this application provide an array substrate 100, which includes a substrate su and a thin-film transistor tft. The thin-film transistor tft is disposed on the substrate su.

[0045] The thin-film transistor (TFT) includes an active layer PY, a gate insulating layer GI, a gate GO1, a source SO1, and a drain DO1. The active layer PY includes a channel GD, a first contact P1, and a second contact P2. The channel GD includes a main body GD1 and an edge GD2. The edge GD2 has a slope angle α of less than 90 degrees.

[0046] The gate insulating layer gi covers the side of the active layer py away from the substrate su. The gate insulating layer gi includes a first part gi1 and a second part gi2 connected together. The first part gi1 covers the edge part gd2, and the second part gi2 covers the main part gd1.

[0047] The gate g01 is disposed on the side of the gate insulating layer gi away from the substrate su, the source s01 is connected to the first contact p1, and the drain d01 is connected to the second contact p2.

[0048] In a plan view of the array substrate 100, a first contact portion p1, a channel gd, and a second contact portion p2 are arranged sequentially on the first direction DR1; on the second direction DR2, which is perpendicular to the first direction DR1, an edge portion gd2 is located on one side of the main body portion gd1.

[0049] Among them, the thin-film transistor tft is an N-type thin-film transistor, and the first part gi1 has fewer positive charges than the second part gi2.

[0050] Alternatively, the thin-film transistor tft is a P-type thin-film transistor, where the first part gi1 has fewer negative charges than the second part gi2.

[0051] In the array substrate 100 of this application embodiment, the charge amount of the first part gi1 of the gate insulating layer gi is less than the charge amount of the second part gi2 in the same polarity charge. When the thin film transistor tft is turned on, since the charge amount of the first part gi1 is less, the negative or positive shift of the threshold voltage of the edge part gd2 is less under the same gate voltage, while the negative or positive shift of the threshold voltage of the corresponding main part gd1 is more. In this way, the difference in threshold voltage between the edge thin film transistor t2 with the edge part gd2 and the main thin film transistor t1 with the main part gd1 is eliminated, thereby achieving the effect of improving the camel hump effect of the thin film transistor tft.

[0052] For example, in one embodiment, the thin-film transistor tft is an N-type thin-film transistor. The amount of positive charge in the first part gi1 of the gate insulating layer gi is less than the amount of positive charge in the second part gi2. When the thin-film transistor tft is turned on, because the amount of positive charge in the first part gi1 is less, the threshold voltage of the edge part gd2 shifts less negatively under the same gate voltage, while the threshold voltage of the corresponding main part gd1 shifts more negatively. This eliminates the difference in threshold voltage between the edge thin-film transistor t2 with the edge part gd2 and the main thin-film transistor t1 with the main part gd1, thereby improving the camel hump effect of the thin-film transistor tft.

[0053] For example, in another embodiment, the thin-film transistor tft is a P-type thin-film transistor. The amount of negative charge in the first part gi1 of the gate insulating layer gi is less than the amount of negative charge in the second part gi2. When the thin-film transistor tft is turned on, because the amount of negative charge in the first part gi1 is less, the positive shift of the threshold voltage of the edge part gd2 is less under the same gate voltage, while the positive shift of the threshold voltage of the corresponding main part gd1 is more. This eliminates the difference in threshold voltage between the edge thin-film transistor t2 with the edge part gd2 and the main thin-film transistor t1 with the main part gd1, thereby improving the camel hump effect of the thin-film transistor tft.

[0054] It should be explained that the charge in the gate insulating layer gi can be measured by testing the CV (capacitance-gate voltage) curve of the thin-film transistor tft, and a fixed amount of charge can be extracted from the CV curve.

[0055] Among them, the flat band voltage V is obtained by using the CV curve. FB Then, using the formula: The amount of charge is calculated. Where Q f For a fixed number of charges, ∅ MS C represents the difference in work function between the metal and the semiconductor. OX It is a gate semiconductor capacitor.

[0056] The following text uses an N-type thin-film transistor (TFT) as an example for illustration.

[0057] Referring to Figure 1, the thin-film transistor TFT includes a main thin-film transistor t1 and edge thin-film transistors t2 located on both sides of the main thin-film transistor t1. The main thin-film transistor t1 and the edge thin-film transistor t2 share a common gate, common source, and common drain. The channel of the main thin-film transistor t1 is the main portion gd1, and the channel of the edge thin-film transistor t2 is the edge portion gd2.

[0058] It should be understood that the array substrate 100 in the embodiments of this application is used for a liquid crystal panel. The array substrate 100 in the embodiments of this application can be a driving architecture based on fringe field switching (FFS) technology, a driving architecture based on in-plane switching (IPS) technology, a driving architecture based on vertical alignment (VA) technology, and so on.

[0059] In some embodiments, the array substrate 100 can also be used for an electroluminescent display panel, such as an organic light-emitting diode display panel, a micro light-emitting diode display panel, a sub-millimeter-scale light-emitting diode display panel, or a quantum dot light-emitting diode display panel. Additionally, in other embodiments, the array substrate 100 can also be used for an electrophoretic panel, etc.

[0060] The array substrate 100 of the following application embodiment is described based on the FFS architecture, but is not limited thereto.

[0061] Referring to Figures 2 and 3, in one or more embodiments of this application, the array substrate 100 further includes a light-shielding layer Ls, a buffer layer buf, an interlayer dielectric layer Ld, a planarization layer Pn, and a pixel electrode pix.

[0062] A light-shielding layer Ls is located on the substrate su. A buffer layer buf covers the light-shielding layer Ls and the substrate su. An active layer py is disposed on the side of the buffer layer buf away from the substrate su. A gate insulating layer gi covers the active layer py, and an interlayer dielectric layer Ld covers the gate gi01. The source s01 and drain d01 are disposed on the side of the interlayer dielectric layer Ld away from the substrate su. A planarization layer Pn covers the source s01 and drain d01, and a pixel electrode pix is ​​disposed on the side of the planarization layer Pn away from the substrate su. The pixel electrode pix is ​​connected to either the source s01 or the drain d01.

[0063] Optionally, in one or more embodiments, the array substrate 100 may further include a common electrode layer com and a passivation layer Pv, wherein the common electrode layer com is disposed on the side of the planarization layer Pn away from the substrate su. The passivation layer Pv covers the common electrode layer com. Pixel electrodes pix are disposed on the side of the passivation layer Pv away from the substrate su.

[0064] Optionally, in some embodiments, the substrate su can be a rigid substrate or a flexible substrate. The material of the substrate su includes one of glass, sapphire, silicon, silica, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene dicarboxylate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefins, polyimide, or polyurethane.

[0065] In some embodiments, the material of the light-shielding layer Ls can be an inorganic metallic material, such as chromium, molybdenum, manganese, etc., or a metal oxide material, such as CrO. x MoO x MnO2, etc., or a mixed film layer formed by metals and metal oxides; it can also be an organic black resin material, such as black polystyrene, black photoresist, etc.

[0066] In some embodiments, the buffer layer buf, gate insulating layer gi, interlayer dielectric layer Ld, and passivation layer Pv can be formed from a plurality of inorganic layers stacked alternately. For example, the buffer layer buf, gate insulating layer gi, interlayer dielectric layer Ld, and passivation layer Pv can be formed as a bilayer by stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or as a multilayer by alternately stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, this disclosure is not limited thereto, and the buffer layer buf, gate insulating layer gi, interlayer dielectric layer Ld, and passivation layer Pv can be formed as a single inorganic layer comprising the aforementioned insulating material.

[0067] Furthermore, in one or more embodiments, the interlayer dielectric layer Ld may be made of an organic insulating material such as polyimide (PI).

[0068] Optionally, in one or more embodiments, the gate insulating layer gi further includes a third part gi3 connected to one side of the first part gi1, the third part gi3 directly covering the buffer layer buf, and the third part gi3 having more positive charges than the first part gi1.

[0069] It should be noted that the gate insulating layer gi completely covers the buffer layer bug. Therefore, the gate insulating layer gi not only directly covers the active layer py, but also extends to directly cover the buffer layer buf. Plasma injection, on the other hand, injects the entire gate insulating layer gi, thus fixing a positive charge on the entire gate insulating layer gi.

[0070] Since the gate insulating layer gi directly covering the buffer layer buf is a relatively flat buffer layer buf, the thickness of the third part gi3 is greater than the thickness of the first part gi1, and the amount of positive charge fixed in the third part gi3 is also greater than the amount of positive charge fixed in the first part gi1.

[0071] In some embodiments of this application, the number of positive charges in the first part gi1 and the second part gi2 decreases in the direction from the active layer py toward the gate g01, in order to further mitigate the risk of the hump effect.

[0072] In some embodiments, the active layer py may be made of polycrystalline silicon or monocrystalline silicon. The first contact p1 and the second contact p2 are N-type contacts. Both the first contact p1 and the second contact p2 include a heavily doped region and a lightly doped region. The heavily doped region is located on the side of the lightly doped region away from the channel gd. The source s01 is connected to the heavily doped region of the first contact p1, and the drain d01 is connected to the heavily doped region of the second contact p2.

[0073] In some embodiments, the gate g01, source s01, and drain d01 may be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy composed of any of the aforementioned metal elements, or an alloy combining any of the aforementioned metal elements. Furthermore, the gate, source, and drain may have a single-layer structure or a stacked structure of two or more layers.

[0074] In some embodiments, the material of the planarization layer Pn can be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0075] In some embodiments, the materials of the pixel electrode pix and the common electrode layer com can be oxides such as indium tin oxide and indium zinc oxide; they can also be metals, alloys and compounds and mixtures thereof with various conductivity properties, such as gold, silver or platinum, etc.

[0076] In one or more embodiments of this application, the thickness of the edge portion gd2 exhibits a gradual change, while the thickness of the main body portion gd1 exhibits a uniform change. The thickness of the edge portion gd2 increases from its edge towards the main body portion gd1.

[0077] It's important to understand that the increasing thickness of the edge portion gd2 does not mean a 100% increase in thickness. This is because, due to process limitations, the thickness of the edge portion gd2 cannot be 100% precise. Similarly, due to process limitations, the thickness of the main body portion gd1 tends to be uniform; that is, the thickness of the main body portion gd1 only needs to be roughly uniform.

[0078] Optionally, in one or more embodiments of this application, the thin-film transistor tft is an N-type thin-film transistor, and the number of positive charges in the second part gi2 per unit area is greater than or equal to twice the number of positive charges in the first part gi1 per unit area, for example, it can be 2 times, 2.5 times, 3 times, 3.5 times, 4 times, 4.5 times, 5 times, 5.5 times, 6 times, 6.5 times, 7 times, 7.5 times, 8 times, 8.5 times, 9 times, 9.5 times, 10 times, 10.5 times, 11 times, 11.5 times, 12 times, 12.5 times, 13 times, 13.5 times, 14 times, 14.5 times, 15 times, 15.5 times, 16 times, 16.5 times, 17 times, 17.5 times, 18 times, 18.5 times, 19 times, 19.5 times, or 20 times.

[0079] It is understandable that the fewer positive charges fixed in the first part gi1 and the more positive charges fixed in the second part gi2, the less the threshold voltage of the edge thin film transistor t2 shifts negatively under the same gate voltage, and the more the threshold voltage of the corresponding main thin film transistor t1 shifts negatively. Thus, the elimination effect of the threshold voltage difference between the two is better, so that the subthreshold region of the thin film transistor tft reflects the properties of the main thin film transistor t1, thereby improving the hump effect.

[0080] Optionally, the number of positive charges in the second part gi2 per unit area is greater than or equal to ten times the number of positive charges in the first part gi1 per unit area, so as to better eliminate the hump effect.

[0081] Optionally, in some embodiments of this application, the thickness d1 of the first part gi1 is smaller than the thickness d2 of the second part gi2.

[0082] Understandably, a smaller thickness d1 in the first part gi1 of the gate insulating layer gi results in a smaller number of positive charges that can be fixed in the first part gi1, facilitating a single ion implantation. Furthermore, a greater thickness difference between the first part gi1 and the second part gi2 leads to a greater difference in the amount of positive charges that can be fixed between them, making it easier to achieve a larger difference in the number of positive charges fixed between the first part gi1 and the second part gi2, thereby better mitigating the hump effect.

[0083] Optionally, the thickness difference between the first part gi1 and the second part gi2 is between 80 angstroms and 200 angstroms. For example, the thickness difference between the two can be 80 angstroms, 90 angstroms, 100 angstroms, 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms, 180 angstroms, 190 angstroms or 200 angstroms.

[0084] It is important to understand that the thickness difference between the first part gi1 and the second part gi2 is between 80 angstroms and 200 angstroms to avoid an excessive height difference between them.

[0085] Optionally, in one or more embodiments, the first part gi1 is a single film layer and the second part gi2 is a multi-film layer stacked structure.

[0086] For example, the second part gi2 includes a first film layer that directly covers the active layer py and a second film layer disposed on the first film layer away from the active layer py. The first part gi1 is made of the same material as the first film layer and is connected to it. The thickness of the first part gi1 is slightly less than the thickness of the first film layer, and the density of the second film layer is less than the density of the first film layer and the density of the first part gi1.

[0087] The first part, gi1, is a single-layer structure formed by deposition of the same material as the first film layer. Due to the slope angle of the edge part gd2, the thickness of the first part, gi1, is lower than that of the first film layer when the terrain is flat due to the sloping topography. The density of the second film layer is lower than that of the first film layer and the first part, gi1, making it easier for plasma to be injected into the second film layer to fix more positive charges.

[0088] Optionally, in one or more embodiments, the first part gi1 and the second part gi2 may both be single-layer structures, or the first part gi1 and the second part gi2 may both be multi-layer stacked structures.

[0089] Optionally, in one or more embodiments, the thickness d2 of the second part gi2 is between 600 angstroms and 2000 angstroms, for example, it can be 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1600 angstroms, 1700 angstroms, 1800 angstroms, 1900 angstroms or 2000 angstroms.

[0090] Optionally, in one or more embodiments, the slope angle α of the edge gd2 is between 30 degrees and 80 degrees.

[0091] It is understandable that the larger the slope angle α of the edge gd2, the steeper the edge gd2, and the smaller the projected area of ​​the edge gd2 based on the substrate su. Therefore, when the gate insulating layer gi is formed by vapor deposition, the thickness of the first part gi1 is smaller; and during ion implantation, the effective area of ​​the first part gi1 subjected to plasma implantation is also smaller. In other words, the smaller the thickness and effective area of ​​the first part gi1, the less positive charge can be fixed in the first part gi1.

[0092] The slope angle α of the edge part gd2 is between 30 degrees and 80 degrees. This takes into account the ability of the first part gi1 to fix the positive charge, avoids the thickness of the first part gi1 being too small, and even avoids the risk of the first part gi1 and the second part gi2 breaking apart due to the slope angle being too steep.

[0093] Optionally, the slope angle α of the edge gd2 can be 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees or 80 degrees.

[0094] Optionally, in one or more embodiments, the thickness of the body portion gd1 is between 300 angstroms and 600 angstroms, for example, it can be 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms or 600 angstroms.

[0095] It is understandable that, with a fixed slope angle α at the edge gd2, the greater the thickness of the main body gd1, the larger the effective area for ion implantation at the edge gd2. Therefore, the thickness of the main body gd1 is also a factor affecting the ability of the edge gd2 to fix positive charges.

[0096] On the other hand, this application embodiment also provides a method for fabricating an array substrate 100, which includes the following steps:

[0097] Step B1: An active layer p1 and a gate insulating layer g1 are sequentially formed on the substrate. The active layer p1 is N-type and includes a channel, a first contact portion, and a second contact portion. The channel g1 includes a main body portion g1 and an edge portion g2. The edge portion g2 has a slope angle of less than 90 degrees. The gate insulating layer g1 covers the side of the active layer p1 away from the substrate su. The gate insulating layer g1 includes a first portion g1 and a second portion g2 connected together. The first portion g1 covers the edge portion g2, and the second portion g2 covers the main body portion g1. In a plan view of the array substrate 100, the first contact portion p1, the channel g1, and the second contact portion p2 are sequentially arranged in a first direction. In a second direction DR2 perpendicular to the first direction DR1, an edge portion g2 is located on one side of the main body portion g1.

[0098] Step B2 involves ion implantation of the gate insulating layer gi to fix positive charges within it. The number of positive charges fixed in the first part gi1 is less than the number of positive charges fixed in the second part gi2.

[0099] In step B3, a gate electrode g01, an interlayer dielectric layer Ld, a source electrode s01, and a drain electrode d01 are sequentially formed on the gate insulating layer gi. The source electrode s01 is connected to the first contact portion p1, and the drain electrode d01 is connected to the second contact portion p2.

[0100] It should be understood that the array substrate 100 fabrication method of this application embodiment uses plasma injection to inject the entire surface of the gate insulating layer gi. Due to the influence of the edge gd2 terrain, the amount of positive charge fixed in the first part gi1 of the gate insulating layer gi is less than the amount of positive charge fixed in the second part gi2, thereby improving the risk of the hump effect.

[0101] The preparation method is described below based on the embodiments corresponding to Figures 1 to 3, but is not limited thereto.

[0102] Please refer to Figure 4, step B1.

[0103] Step B1: An active layer py and a gate insulating layer gi are sequentially formed on the substrate.

[0104] Optionally, the active layer py can be made of polycrystalline silicon.

[0105] Optionally, before forming the active layer py on the substrate su, the method further includes the step of forming a light-shielding layer LS and a buffer layer buf on the substrate su. The active layer py is formed on the buffer layer buf.

[0106] Then proceed to step B2.

[0107] Please refer to Figure 5, step B2, to perform ion implantation on the gate insulating layer gi to fix the positive charge within the gate insulating layer gi.

[0108] Optionally, plasma injection technology is used to process the gate insulating layer gi, wherein the gas source for plasma injection technology includes at least one of nitrous oxide (N2O) and nitrogen (N2). This application uses nitrous oxide as an example for illustration, but is not limited thereto.

[0109] During the plasma injection step, nitrous oxide is dissociated into plasma, which contains positively charged particles (NO). + Under the influence of a vertical electric field, the positively charged particles are injected into the gate insulating layer gi. Some of the positively charged particles also undergo charge replacement with the atoms in the gate insulating layer gi, so that the positive charge is fixed in the gate insulating layer gi.

[0110] During the plasma injection step, the pressure in the chamber is between 800 and 1400 mtorr, for example, it can be 800 mtorr, 900 mtorr, 1000 mtorr, 1100 mtorr, 1200 mtorr, 1300 mtorr or 140 mtorr.

[0111] The radio frequency power is between 3000 and 6000KW, for example, it can be 3000KW, 3500KW, 4000KW, 4500 KW, 5000 KW, 5500 KW or 6000 KW.

[0112] The chamber temperature is between 300 and 400 degrees Celsius, such as 300, 310, 320, 330, 340, 350, 360, 370, 380, 390 or 400 degrees Celsius.

[0113] The duration of plasma injection ranges from 10 to 90 seconds, such as 10, 20, 30, 40, 50, 60, 70, 80, or 90 seconds.

[0114] Then proceed to step B3.

[0115] Please refer to Figure 6, step B3, where a gate g01, an interlayer dielectric layer Ld, a source s01, and a drain d01 are sequentially formed on the gate insulating layer gi.

[0116] Optionally, step B3 includes: sequentially forming a gate g01 on the gate insulating layer g1; subsequently forming an interlayer dielectric layer Ld on the gate g01; and then forming a source s01 and a drain d01 on the interlayer dielectric layer Ld.

[0117] In addition, the method for fabricating the array substrate 100 in this embodiment of the application further includes the following steps:

[0118] Referring to Figure 7 and step B4, a planarization layer Pn, a common electrode layer com, a passivation layer pv, and a pixel electrode pix are sequentially formed on the source electrode s01 and the drain electrode d01. The pixel electrode pix is ​​connected to the drain electrode d01 through a via.

[0119] It should be noted that, please refer to Figure 8, which is a comparison graph of the transfer curves of thin-film transistors with drain voltage Vd=0.1V and drain voltage Vd=10V in the embodiments (experiments) of Comparative Example 1, Comparative Example 2 and the preparation method of this application.

[0120] The only difference between Comparative Example 1, Comparative Example 2, and the Experimental Example is whether plasma implantation of the gate insulating layer gi is used in the fabrication process. Specifically, the gate insulating layer of the low-temperature polycrystalline silicon thin-film transistor in Comparative Example 1 was not plasma implanted, the gate insulating layer of the low-temperature polycrystalline silicon thin-film transistor in Comparative Example 2 was implanted using oxygen plasma, and the Experimental Example is a low-temperature polycrystalline silicon thin-film transistor fabricated using the fabrication method of the array substrate 100 in this application embodiment, which was implanted using nitrous oxide (N2O) plasma.

[0121] As shown in Figure 8, compared to Comparative Example 1, Comparative Example 2, which uses oxygen plasma for injection, does not significantly improve the hump effect regardless of whether the drain voltage Vd = 0.1 V or Vd = 10 V; while the experimental example using nitrous oxide (N2O) plasma for injection shows a better improvement effect on the hump effect.

[0122] On the other hand, referring to FIG9, this application embodiment also provides a display panel 1000, which includes an array substrate as described in any of the above embodiments.

[0123] The display panel 1000 in the embodiments of this application can be one of a liquid crystal panel, an electroluminescent display panel, and an electrophoretic panel, such as an FFS liquid crystal display panel, an IPS liquid crystal display panel, a VA liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, a sub-millimeter-level light-emitting diode display panel, a quantum dot light-emitting diode display panel, or an electrophoretic panel, etc.

[0124] It should be noted that the structure of the thin-film transistor of the array substrate of the display panel in this application embodiment is similar to or the same as the structure of the thin-film transistor TFT of the array substrate 100 in any of the above embodiments.

[0125] Optionally, Figure 9 shows a display panel 1000 according to an embodiment of this application. The display panel 1000 is a liquid crystal panel. The display panel 1000 includes an array substrate 100, a counter substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.

[0126] The display panel of this application embodiment includes a thin-film transistor (TFT). The TFT includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion, and the edge portion has a slope angle of less than 90 degrees. The gate insulating layer at least covers the side of the channel away from the substrate. The gate insulating layer includes a first portion and a second portion connected together. The first portion covers the edge portion, and the second portion covers the main body portion. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion. The TFT is an N-type TFT, where the number of positive charges in the first portion is less than the number of positive charges in the second portion; or the TFT is a P-type TFT, where the number of negative charges in the first portion is less than the number of negative charges in the second portion.

[0127] In this embodiment, the charge amount of the first part of the gate insulating layer is less than that of the second part when the thin film transistor is turned on. Because the charge amount of the first part is less, the threshold voltage of the edge part shifts less in the negative or positive direction under the same gate voltage, while the threshold voltage of the corresponding main part shifts more in the negative or positive direction. This eliminates the difference in threshold voltage between the edge thin film transistor with the edge part and the main thin film transistor with the main part, thereby improving the hump effect of the thin film transistor.

[0128] The above provides a detailed description of an array substrate, its fabrication method, and a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, comprising: substrate; as well as A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The gate insulating layer covers the side of the active layer away from the substrate. The gate insulating layer includes a first portion and a second portion connected together. The first portion covers the edge portion, and the second portion covers the main body portion. The gate is disposed on the side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion; In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion; Wherein, the thin-film transistor is an N-type thin-film transistor, and the first part has fewer positive charges than the second part; or The thin-film transistor is a P-type thin-film transistor, and the first part has fewer negative charges than the second part.

2. The array substrate according to claim 1, wherein, The thin-film transistor is an N-type thin-film transistor, and the number of positive charges per unit area of ​​the second part is greater than or equal to ten times the number of positive charges per unit area of ​​the first part.

3. The array substrate according to claim 2, wherein, The amount of positive charge in the first portion and the second portion decreases in the direction from the active layer toward the gate.

4. The array substrate according to claim 1, wherein, The thickness of the first part is less than the thickness of the second part.

5. The array substrate according to claim 4, wherein, The thickness difference between the first part and the second part is between 80 angstroms and 200 angstroms.

6. The array substrate according to claim 5, wherein, The thickness of the second part is between 600 angstroms and 2000 angstroms.

7. The array substrate according to claim 4, wherein, The slope angle of the edge is between 30 degrees and 80 degrees.

8. The array substrate according to claim 7, wherein, The thickness of the main body is between 300 angstroms and 600 angstroms.

9. The array substrate according to claim 4, wherein, The first part is a single film layer, and the second part is a multi-film layer stacked structure.

10. The array substrate according to claim 9, wherein, The second part includes a first film layer that directly covers the active layer and a second film layer disposed on the first film layer away from the active layer. The first part is made of the same material as the first film layer and is connected to it. The density of the second film layer is less than the density of the first film layer and the density of the first part.

11. The array substrate according to claim 4, wherein, Both the first part and the second part are single-layer structures, or both the first part and the second part are multi-layer stacked structures.

12. The array substrate according to any one of claims 1 to 11, wherein, The array substrate further includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer, and a pixel electrode. The light-shielding layer is located on the substrate. The buffer layer covers the light-shielding layer and the substrate. The active layer is disposed on the side of the buffer layer away from the substrate. The gate insulating layer covers the active layer. The interlayer dielectric layer covers the gate. The source and the drain are disposed on the side of the interlayer dielectric layer away from the substrate. The planarization layer covers the source and the drain. The pixel electrode is disposed on the side of the planarization layer away from the substrate. The pixel electrode is connected to the source or the drain.

13. The array substrate according to claim 12, wherein, The gate insulating layer further includes a third portion connected to one side of the first portion, the third portion directly covering the buffer layer, and the third portion having a greater number of positive charges than the first portion.

14. The array substrate according to claim 12, wherein, The array substrate may further include the common electrode layer and the passivation layer, the common electrode layer being disposed on the side of the planarization layer away from the substrate, the passivation layer covering the common electrode layer, and the pixel electrode being disposed on the side of the passivation layer away from the substrate.

15. A display panel, comprising an array substrate, the array substrate comprising: substrate; as well as A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The gate insulating layer covers the side of the active layer away from the substrate. The gate insulating layer includes a first portion and a second portion connected together. The first portion covers the edge portion, and the second portion covers the main body portion. The gate is disposed on the side of the gate insulating layer away from the substrate, the source is connected to the first contact portion, and the drain is connected to the second contact portion; In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion; Wherein, the thin-film transistor is an N-type thin-film transistor, and the first part has fewer positive charges than the second part; or The thin-film transistor is a P-type thin-film transistor, and the first part has fewer negative charges than the second part.

16. The display panel according to claim 15, wherein, The thin-film transistor is an N-type thin-film transistor, and the number of positive charges per unit area of ​​the first part is greater than or equal to ten times the number of positive charges per unit area of ​​the second part.

17. The display panel according to claim 16, wherein, The amount of positive charge in the first portion and the second portion decreases in the direction from the active layer toward the gate.

18. The display panel according to claim 15, wherein, The thickness of the first part is less than the thickness of the second part.

19. The display panel according to claim 18, wherein, The thickness difference between the first part and the second part is between 80 angstroms and 200 angstroms.

20. The display panel according to claim 19, wherein, The thickness of the second part is between 600 angstroms and 2000 angstroms.

Images