Array substrate and preparation method therefor, and display panel

Abstract

Disclosed in the embodiments of the present application are an array substrate and a display panel. The array substrate comprises a thin film transistor, wherein the thin film transistor comprises an active layer, a gate insulating layer, a gate, a source and a drain; the active layer comprises a channel, a first contact portion and a second contact portion, and the channel comprises a main body portion and an edge portion; the source is connected to the first contact portion; the drain is connected to the second contact portion; and the edge portion has a slope angle less than 90 degrees; and the defect state density of the edge portion is greater than that of the main body portion.

Description

Array substrate and its fabrication method and display panel Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, its fabrication method, and a display panel. Background Technology

[0002] Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are key components in the active drive and peripheral circuits of display devices such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs). Currently, LTPS exhibit a peak effect, with poor electrical properties in the subthreshold region, limiting the charging capability of high-specification products. The peak effect is caused by the fact that LTPS manufactured using current processes can be considered as consisting of edge TFTs connected in parallel with a main TFT located in the middle. The threshold voltage (Vth) of the edge TFTs is relatively negative compared to the main TFT, leading to an abnormally large increase in the subthreshold current of the main TFT. Invention Overview

[0003] This application provides an array substrate, a method for fabricating the same, and a display panel, which can reduce the risk of the hump effect in thin-film transistors.

[0004] On one hand, embodiments of this application provide an array substrate, which includes:

[0005] Substrate; and

[0006] A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion.

[0007] In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion;

[0008] In the second direction, the edge portion has a slope angle of less than 90 degrees; the defect state density of the edge portion is greater than the defect state density of the main body portion.

[0009] On the other hand, embodiments of this application also provide a method for fabricating an array substrate, which includes the following steps:

[0010] A semiconductor layer and a photoresist layer are sequentially formed on the substrate;

[0011] The photoresist layer is patterned to form a photoresist pattern;

[0012] Using the photoresist pattern as a mask, the semiconductor layer is etched to form an active layer. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The main body portion is covered by the photoresist pattern, and the edge portion is exposed.

[0013] Using the photoresist pattern as a mask, ion bombardment is performed on the edge of the active layer to make the defect state density at the edge greater than the defect state density at the main body.

[0014] Remove the photoresist pattern, and sequentially form a gate insulating layer and a gate on the active layer. The gate insulating layer at least covers the side of the channel away from the substrate, and the gate is disposed on the side of the gate insulating layer away from the substrate.

[0015] A source and a drain are formed on the gate electrode, which are insulated from it. The source electrode is connected to the first contact portion, and the drain electrode is connected to the second contact portion.

[0016] In another aspect, embodiments of this application also provide a display panel, which includes an array substrate as described in any of the above embodiments. Attached Figure Description

[0017] Figure 1 is a partial plan view of an array substrate provided in one or more embodiments of this application;

[0018] Figure 2 is a schematic cross-sectional view of the structure along line AA in Figure 1;

[0019] Figure 3 is a schematic cross-sectional view of the structure along line BB in Figure 1;

[0020] Figure 4 is a schematic diagram of step B1 of the array substrate fabrication method provided in the embodiment of this application;

[0021] Figure 5 is a schematic diagram of step B2 of the array substrate fabrication method provided in the embodiment of this application;

[0022] Figure 6 is a schematic diagram of step B3 of the array substrate fabrication method provided in the embodiment of this application;

[0023] Figure 7 is a schematic diagram of step B4 of the array substrate fabrication method provided in the embodiment of this application;

[0024] Figure 8a is a schematic diagram of step B51 of the array substrate fabrication method provided in the embodiment of this application;

[0025] Figure 8b is a schematic diagram of step B52 of the array substrate fabrication method provided in the embodiment of this application;

[0026] Figure 8c is a schematic diagram of step B53 of the array substrate fabrication method provided in the embodiment of this application;

[0027] Figure 9 is a schematic diagram of step B6 of the array substrate fabrication method provided in the embodiment of this application;

[0028] Figure 10 is a schematic diagram of step B7 of the array substrate fabrication method provided in the embodiment of this application;

[0029] Figure 11 is a comparison of the transfer curves of thin-film transistors with drain voltage Vd = 0.1 V and drain voltage Vd = 10 V for Comparative Example 1, Comparative Example 2 and the experimental example of this application.

[0030] Figure 12 is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Embodiments of the present invention

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0032] On one hand, embodiments of this application provide an array substrate, which includes:

[0033] Substrate; and

[0034] A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion.

[0035] In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion;

[0036] In the second direction, the edge portion has a slope angle of less than 90 degrees; the defect state density of the edge portion is greater than the defect state density of the main body portion.

[0037] Optionally, in some embodiments of this application, the defect state density of the edge portion is greater than or equal to 5 times the defect state density of the main body portion.

[0038] Optionally, in some embodiments of this application, the defect state density of the main body is between 1×10⁻⁶. 20 Units / eV up to 3×10 20 Between 1 / eV.

[0039] Optionally, in some embodiments of this application, the carrier mobility of the edge portion is less than that of the main body portion.

[0040] Optionally, in some embodiments of this application, the material of the channel includes polycrystalline silicon, and the crystallinity of the edge portion is less than that of the body portion.

[0041] Optionally, in some embodiments of this application, the slope angle of the edge portion is between 30 degrees and 80 degrees.

[0042] Optionally, in some embodiments of this application, the thickness of the main body is between 300 angstroms and 600 angstroms.

[0043] Optionally, in some embodiments of this application, one of the edge portions is located on one side of the main body portion, and the other edge portion is located on the other side of the main body portion.

[0044] Optionally, in some embodiments of this application, in a plan view of the array substrate, the first contact portion, the channel, and the second contact portion are arranged sequentially in a first direction; in a second direction perpendicular to the first direction, one edge portion is located on one side of the main body portion, and the other edge portion is located on the other side of the main body portion.

[0045] Optionally, in some embodiments of this application, the array substrate further includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer, and a pixel electrode. The light-shielding layer is located on the substrate, the buffer layer covers the light-shielding layer and the substrate, the active layer is disposed on the side of the buffer layer away from the substrate, the gate insulating layer covers the active layer, the interlayer dielectric layer covers the gate, the source and the drain are disposed on the side of the interlayer dielectric layer away from the substrate, the planarization layer covers the source and the drain, the pixel electrode is disposed on the side of the planarization layer away from the substrate, and the pixel electrode is connected to the source or the drain.

[0046] On the other hand, embodiments of this application also provide a method for fabricating an array substrate, which includes the following steps:

[0047] A semiconductor layer and a photoresist layer are sequentially formed on the substrate;

[0048] The photoresist layer is patterned to form a photoresist pattern;

[0049] Using the photoresist pattern as a mask, the semiconductor layer is etched to form an active layer. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The main body portion is covered by the photoresist pattern, and the edge portion is exposed.

[0050] Using the photoresist pattern as a mask, ion bombardment is performed on the edge of the active layer to make the defect state density at the edge greater than the defect state density at the main body.

[0051] Remove the photoresist pattern, and sequentially form a gate insulating layer and a gate on the active layer. The gate insulating layer at least covers the side of the channel away from the substrate, and the gate is disposed on the side of the gate insulating layer away from the substrate.

[0052] A source and a drain are formed on the gate electrode, which are insulated from it. The source electrode is connected to the first contact portion, and the drain electrode is connected to the second contact portion.

[0053] Optionally, in some embodiments of this application, the reactivity of the ions is less than that of the oxygen plasma.

[0054] In another aspect, embodiments of this application also provide a display panel, which includes an array substrate as described in any of the above embodiments.

[0055] The array substrate of this application embodiment includes a thin-film transistor. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion. The edge portion has a slope angle of less than 90 degrees. The defect state density of the edge portion is greater than that of the main body portion.

[0056] In this embodiment, the defect state density at the edge is set to be greater than that at the main body. Because the defect state density at the edge is larger, it is more difficult for the edge to turn on under the same gate voltage, and the edge thin film transistor is suppressed, thereby achieving the effect of improving the hump effect of the thin film transistor.

[0057] This application provides an array substrate and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0058] Please refer to Figures 1 to 3. Figure 1 is a partial plan view of an array substrate provided in one or more embodiments of this application. Figure 2 is a cross-sectional view along line AA in Figure 1. Figure 3 is a cross-sectional view along line BB in Figure 1.

[0059] In Figures 1 to 3, the first direction DR1 can be a direction parallel to one side of the array substrate 100 in a plan view, such as the longitudinal direction of the array substrate 100, but is not limited thereto. The second direction DR2 can be a direction parallel to the other side of the array substrate 100 in a plan view, such as the transverse direction of the array substrate 100, but is not limited thereto. The third direction DR3 can be the thickness direction of the array substrate 100.

[0060] One or more embodiments of this application provide an array substrate 100, which includes a substrate su and a thin-film transistor tft. The thin-film transistor tft is disposed on the substrate su.

[0061] The thin-film transistor (TFT) includes an active layer PY, a gate insulating layer GI, a gate GO1, a source SO1, and a drain DO1. The active layer PY includes a channel GD, a first contact P1, and a second contact P2. The channel GD includes a main body GD1 and an edge portion GD2. The gate insulating layer GI at least covers the side of the channel GD away from the substrate SU. The gate GO1 is disposed on the side of the gate insulating layer GI away from the substrate SU. The source SO1 is connected to the first contact P1, and the drain DO1 is connected to the second contact P2.

[0062] Figure 1 shows only one plan view of an embodiment of this application, but is not limited thereto. Based on Figure 1, in the plan view of the array substrate 100, a first contact portion p1, a channel gd, and a second contact portion p2 are arranged sequentially in the first direction DR1; in the second direction DR2, which is perpendicular to the first direction DR1, an edge portion gd2 is located on one side of the main body portion gd1.

[0063] In the second direction DR2, the edge portion gd2 has a slope angle α of less than 90 degrees. The defect state density of the edge portion gd2 is greater than that of the main body portion gd1.

[0064] In this embodiment, the defect state density of the edge portion gd2 is set to be greater than that of the main portion gd1. Since the defect state density of the edge portion gd2 is larger, it is more difficult for the edge portion gd2 to turn on under the same gate voltage, and the edge thin film transistor is suppressed, thereby achieving the effect of improving the TFT hump effect of the thin film transistor.

[0065] It needs to be explained that the defect state density is a concept in the energy band theory of semiconductor physics. When a semiconductor deviates from an ideal crystal (due to various defects), electron orbitals (energy states) will be generated in the band gap. The state density refers to the number of energy states in a unit energy range within the energy band.

[0066] The defect state density can be measured by deep-level transient spectroscopy and charge pumping method, and can also be indirectly measured by X-ray diffraction to test crystallinity.

[0067] For example, the testing method for deep-level transient spectroscopy is as follows: first, non-equilibrium charge carriers are injected into a semiconductor material, and then the charge carriers are excited to the conduction band or valence band by photoexcitation or electric field excitation. The changes in the spectrum are then measured to study the electronic transition process and the properties of deep-level defects.

[0068] Another example is the charge-pumping technique, which can be found in the literature "Local oxide capacitance as a crucial parameter for characterization of hot-carrier degradation in long-channel n-MOSFETs".

[0069] Additionally, referring to Figure 1, the thin-film transistor TFT includes a main thin-film transistor t1 and edge thin-film transistors t2 located on both sides of the main thin-film transistor t1. The main thin-film transistor t1 and the edge thin-film transistor t2 share a common gate, common source, and common drain. The channel of the main thin-film transistor t1 is the main body portion gd1, and the channel of the edge thin-film transistor t2 is the edge portion gd2.

[0070] Optionally, the thin-film transistor tft can be an N-type thin-film transistor or a P-type thin-film transistor.

[0071] In the thin-film transistor (TFT) disclosed in the embodiments of this application, the embodiments of this application are illustrated by taking the gate g01 as a metal layer, the source s01 and the drain d01 as a metal layer in the same layer, but it is not limited to this. For example, the gate g01, the source s01 and the drain d01 can be set in the same layer, that is, they can be formed by using the same mask; or one of the source s01 and the drain d01 can be set in the same layer as the gate g01; or all three can be set in different layers.

[0072] It should be understood that the array substrate 100 in the embodiments of this application is used for a liquid crystal panel. The array substrate 100 in the embodiments of this application can be a driving architecture based on fringe field switching (FFS) technology, a driving architecture based on in-plane switching (IPS) technology, a driving architecture based on vertical alignment (VA) technology, and so on.

[0073] In some embodiments, the array substrate 100 can also be used for an electroluminescent display panel, such as an organic light-emitting diode display panel, a micro light-emitting diode display panel, a sub-millimeter-scale light-emitting diode display panel, or a quantum dot light-emitting diode display panel. Additionally, in other embodiments, the array substrate 100 can also be used for an electrophoretic panel, etc.

[0074] The array substrate 100 of the following application embodiment is described based on the FFS architecture, but is not limited thereto.

[0075] Referring to Figures 2 and 3, in one or more embodiments of this application, the array substrate 100 further includes a light-shielding layer Ls, a buffer layer buf, an interlayer dielectric layer Ld, a planarization layer Pn, and a pixel electrode pix.

[0076] A light-shielding layer Ls is located on the substrate su. A buffer layer buf covers the light-shielding layer Ls and the substrate su. An active layer py is disposed on the side of the buffer layer buf away from the substrate su. A gate insulating layer gi covers the active layer py, and an interlayer dielectric layer Ld covers the gate gi01. The source s01 and drain d01 are disposed on the side of the interlayer dielectric layer Ld away from the substrate su. A planarization layer Pn covers the source s01 and drain d01, and a pixel electrode pix is ​​disposed on the side of the planarization layer Pn away from the substrate su. The pixel electrode pix is ​​connected to either the source s01 or the drain d01.

[0077] Optionally, in one or more embodiments, the array substrate 100 may further include a common electrode layer com and a passivation layer Pv, wherein the common electrode layer com is disposed on the side of the planarization layer Pn away from the substrate su. The passivation layer Pv covers the common electrode layer com. Pixel electrodes pix are disposed on the side of the passivation layer Pv away from the substrate su.

[0078] Optionally, in some embodiments, the substrate su can be a rigid substrate or a flexible substrate. The material of the substrate su includes one of glass, sapphire, silicon, silica, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene dicarboxylate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefins, polyimide, or polyurethane.

[0079] In some embodiments, the material of the light-shielding layer Ls can be an inorganic metallic material, such as chromium, molybdenum, manganese, etc., or a metal oxide material, such as CrO. x MoO x MnO2, etc., or a mixed film layer formed by metals and metal oxides; it can also be an organic black resin material, such as black polystyrene, black photoresist, etc.

[0080] In some embodiments, the buffer layer buf, gate insulating layer gi, interlayer dielectric layer Ld, and passivation layer Pv can be formed from a plurality of inorganic layers stacked alternately. For example, the buffer layer buf, gate insulating layer gi, interlayer dielectric layer Ld, and passivation layer Pv can be formed as a bilayer by stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or as a multilayer by alternately stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, this disclosure is not limited thereto, and the buffer layer buf, gate insulating layer gi, interlayer dielectric layer Ld, and passivation layer Pv can be formed as a single inorganic layer comprising the aforementioned insulating material.

[0081] Furthermore, in one or more embodiments, the interlayer dielectric layer Ld may be made of an organic insulating material such as polyimide (PI).

[0082] In some embodiments, the active layer py may be made of polycrystalline silicon or monocrystalline silicon. The first contact p1 and the second contact p2 are N-type contacts. Both the first contact p1 and the second contact p2 include a heavily doped region and a lightly doped region. The heavily doped region is located on the side of the lightly doped region away from the channel gd. The source s01 is connected to the heavily doped region of the first contact p1, and the drain d01 is connected to the heavily doped region of the second contact p2.

[0083] In some embodiments, the gate g01, source s01, and drain d01 may be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, and cobalt, an alloy composed of any of the aforementioned metal elements, or an alloy combining any of the aforementioned metal elements. Furthermore, the gate, source, and drain may have a single-layer structure or a stacked structure of two or more layers.

[0084] In some embodiments, the material of the planarization layer Pn can be an organic transparent film layer, such as transparent photoresist, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0085] In some embodiments, the materials of the pixel electrode pix and the common electrode layer com can be oxides such as indium tin oxide and indium zinc oxide; they can also be metals, alloys and compounds and mixtures thereof with various conductivity properties, such as gold, silver or platinum, etc.

[0086] In one or more embodiments of this application, the thickness of the edge portion gd2 exhibits a gradual change, while the thickness of the main body portion gd1 exhibits a uniform change. The thickness of the edge portion gd2 increases from its edge towards the main body portion gd1.

[0087] It's important to understand that the increasing thickness of the edge portion gd2 does not mean a 100% increase in thickness. This is because, due to process limitations, the thickness of the edge portion gd2 cannot be 100% precise. Similarly, due to process limitations, the thickness of the main body portion gd1 tends to be uniform; that is, the thickness of the main body portion gd1 only needs to be roughly uniform.

[0088] In one or more embodiments of this application, the defect state density of the edge portion gd2 is greater than or equal to 5 times the defect state density of the main body portion gd1.

[0089] It is important to understand that the greater the defect state density of gd2 at the edge, the better the effect of suppressing the turn-on of the edge thin-film transistor t2, and thus the better the suppression of the hump effect; conversely, the smaller the defect state density, the worse the effect.

[0090] Therefore, in order to significantly suppress the hump effect, the defect state density of the edge part gd2 is selected to be greater than or equal to 5 times the defect state density of the main part gd1.

[0091] For example, the defect state density of the edge part gd2 can be 5, 6, 7, 8, 9 or 10 times that of the defect state density of the main part gd1.

[0092] In some embodiments of this application, the defect state density of the main body gd1 is between 1×10⁻⁶. 20 From 1 eV (electron volts) to 3 × 10⁻⁶ 20 Between units / eV, for example, it could be 1×10 20 Units / eV, 2×10 20 Units / eV or 3×10 20 per eV, etc.

[0093] In some embodiments of this application, the carrier mobility of the edge portion gd2 is less than that of the main body portion gd1.

[0094] It is understandable that the carrier mobility of the edge region gd2 is relatively small, which prolongs the time for carriers to cross the base region, reduces the switching speed of the thin film transistor, and thus suppresses the turn-on of the edge thin film transistor t2.

[0095] In some embodiments of this application, the material of the channel gd includes polycrystalline silicon, and the crystallinity of the edge portion gd2 is less than that of the body portion gd1.

[0096] It is understandable that the crystallinity of a channel refers to the degree of order in the arrangement of the crystal lattice structure within a polycrystalline silicon material. Low crystallinity implies the presence of numerous grain boundaries, defects, and disordered structures within the material.

[0097] In the embodiments of this application, the defect degree of the edge portion gd2 is greater than that of the main portion gd1. The increase in defects reduces the migration speed of the carrier channel, meaning that a larger gate voltage is required for control in the same amount of time. Therefore, the crystallinity of the edge portion gd2 is less than that of the main portion gd1, which can suppress the start-up of the edge thin-film transistor t2, thereby suppressing the hump effect of the thin-film transistor tft.

[0098] In some embodiments of this application, the thickness of the main body gd1 is between 300 angstroms and 600 angstroms, for example, it can be 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms or 600 angstroms.

[0099] Understandably, if the channel gd thickness is too thin, it will lead to uneven film formation, while if it is too thick, it will be difficult to crystallize, resulting in poor crystal quality of polycrystalline silicon. Therefore, based on the above considerations, the thickness of the channel gd is selected to be between 300 angstroms and 600 angstroms.

[0100] In some embodiments of this application, the slope angle α of the edge gd2 is between 30 degrees and 80 degrees.

[0101] It should be noted that, due to the relatively small thickness of the main body gd1 of the active layer py, if the slope angle α of the edge gd2 is too steep, it will be difficult for the edge gd2 to be hit by ions in the subsequent ion bombardment step, making it difficult to produce a large degree of defect on the side of the edge gd2 close to the gate g01. On the other hand, if the slope angle α is too gentle, it will occupy too much space.

[0102] Therefore, considering the ease of forming defects and space requirements of the edge gd2, the slope angle α of the edge gd2 is set between 30 degrees and 80 degrees, such as 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 65 degrees, 70 degrees, 75 degrees or 80 degrees.

[0103] In some embodiments of this application, in the second direction DR2, one edge portion gd2 is located on one side of the main body portion gd1, and the other edge portion gd2 is located on the other side of the main body portion gd1. Of course, in some embodiments, only one edge portion gd2 may be included.

[0104] Optionally, the slope angles of the two edge portions gd2 can be the same or different, and this application does not impose any restrictions.

[0105] In some embodiments, the main body gd1 includes a first portion and a second portion, with the first portion located between the second portion and the edge portion gd2. The defect state density of the first portion is between the defect state density of the edge portion gd2 and the defect state density of the second portion.

[0106] Understandably, the first part serves as a transition, reducing the risk of mutual interference between the edge thin-film transistor t2 and the main thin-film transistor t1 at the moment the thin-film transistor tft is turned on.

[0107] Optionally, as shown in Figure 3, the width of the first part is smaller than the width of the edge part gd2 to reduce the impact on the main thin-film transistor t1.

[0108] This application embodiment also provides a method for fabricating an array substrate 100, which includes the following steps:

[0109] Step B1: A semiconductor layer act and a photoresist layer pr are sequentially formed on the substrate su.

[0110] Step B2: Pattern the photoresist layer pr to form a photoresist pattern pr1.

[0111] Step B3: Using the photoresist pattern pr1 as a mask, the semiconductor layer act is etched to form the active layer py. The active layer py includes a channel gd, a first contact portion and a second contact portion. The channel gd includes a main portion gd1 and an edge portion gd2. The edge portion gd2 has a slope angle α of less than 90 degrees. The main portion gd1 is covered by the photoresist pattern pr1, and the edge portion gd2 is exposed.

[0112] Step B4: Using the photoresist pattern pr1 as a mask, ion bombardment is performed on the edge gd2 of the active layer py to make the defect state density of the edge gd2 greater than that of the main body gd1.

[0113] Step B5: Remove the photoresist pattern pr1, and sequentially form a gate insulating layer gi and a gate g01 on the active layer py. The gate insulating layer gi at least covers the side of the channel gd away from the substrate su, and the gate g01 is disposed on the side of the gate insulating layer gi away from the substrate su.

[0114] Step B6: A source electrode s01 and a drain electrode d01, which are insulated from the gate electrode g01, are formed on the gate electrode g01. The source electrode s01 is connected to the first contact portion p1, and the drain electrode d01 is connected to the second contact portion p2.

[0115] It should be understood that the fabrication method of the array substrate 100 in this embodiment of the application uses a photoresist pattern to protect the main body gd1 of the channel gd from ion bombardment, while simultaneously bombarding the edge gd2 of the channel gd with ions to increase the defect state density of the edge gd2. Since the defect state density of the edge gd2 is greater than that of the main body gd1, the turn-on of the edge thin-film transistor t2 can be suppressed under the same gate voltage, thereby suppressing the peak effect of the thin-film transistor tft.

[0116] The preparation method is described below based on the embodiments corresponding to Figures 1 to 3, but is not limited thereto.

[0117] Please refer to Figure 4, step B1, where a semiconductor layer act and a photoresist layer pr are sequentially formed on the substrate su.

[0118] Optionally, the material of the semiconductor layer act can be polycrystalline silicon.

[0119] Optionally, before forming the semiconductor layer act on the substrate su, the method further includes the step of forming a light-shielding layer Ls and a buffer layer buf on the substrate su. The semiconductor layer act is formed on the buffer layer buf.

[0120] Then proceed to step B2.

[0121] Please refer to Figure 5, step B2, pattern the photoresist layer pr to form the photoresist pattern pr1.

[0122] Among them, the photoresist pattern pr1 is used to form the subsequent active layer py.

[0123] Then proceed to step B3.

[0124] Referring to Figure 6, in step B3, using the photoresist pattern pr1 as a mask, the semiconductor layer act is etched to form the active layer py. The active layer py includes a channel gd, a first contact portion, and a second contact portion. The channel gd includes a main portion gd1 and an edge portion gd2. The edge portion gd2 has a slope angle α of less than 90 degrees. The main portion gd1 is covered by the photoresist pattern pr1, and the edge portion gd2 is exposed.

[0125] Optionally, during the etching of the semiconductor layer act, the side portion of the photoresist pattern pr1 is formed with a slope angle. The side of this side portion is flush with the side of the edge portion gd2.

[0126] Then proceed to step B4.

[0127] Please refer to Figure 7, step B4, using the photoresist pattern pr1 as a mask, bombard the edge gd2 of the active layer py with ions to make the defect state density of the edge gd2 greater than the defect state density of the main body gd1.

[0128] Optionally, the ions are less reactive than oxygen plasma ions. Examples include inert gases or less reactive gases such as Ar, Ne, Kr, Xe, or N2.

[0129] In this study, compared to the comparative example using oxygen plasma bombardment, oxygen plasma is more reactive and undergoes more chemical reactions with silicon. The experimental examples in this application use argon plasma (Ar). + Because Ar has a relatively large atomic mass, it is more effective in physical bombardment, which can quickly increase the defect state density of Gd2 at the edge and reduce the crystallinity of Gd2 at the edge. In addition, Ar is an inert gas and has virtually no chemical reaction with silicon, resulting in fewer side effects.

[0130] Furthermore, it should be understood that since the side portion of the photoresist pattern pr1 covers the side of the main body gd1 near the edge gd2, and the thickness of the side portion increases progressively, when plasma bombardment is performed, the plasma penetrates the thinner side portion and damages the first part of the main body gd1. The degree of damage to the first part of the main body gd1 decreases as the thickness of the side portion of the photoresist pattern pr1 increases. Based on this, the defect state density of the first part of the main body gd1 is between that of the edge gd2 and the second part of the main body gd1.

[0131] Of course, in some embodiments, the thickness of the side portion of the photoresist pattern pr1 is equal to the thickness of the other portions, that is, the photoresist pattern pr1 has no inclined slope angle.

[0132] Then proceed to step B5.

[0133] Please refer to Figures 8a to 8c. In step B5, remove the photoresist pattern pr1 and sequentially form a gate insulating layer gi and a gate g01 on the active layer py. The gate insulating layer gi at least covers the side of the channel gd away from the substrate su, and the gate g01 is disposed on the side of the gate insulating layer gi away from the substrate su.

[0134] Optionally, after removing the photoresist pattern pr1, step B5 further includes:

[0135] Please refer to Figure 8a, step B51, to perform the first light doping treatment on the entire surface of the active layer py.

[0136] Please refer to Figure 8b, step B52, to perform heavy doping treatment on the heavily doped region of the active layer py.

[0137] Referring to Figure 8c, in step B53, a gate insulating layer gi and a gate g01 are formed sequentially on the active layer py. Then, using the gate g01 as a mask, a second light doping treatment is performed on the lightly doped region of the active layer py to form the first contact p1, the second contact p2, and the channel gd.

[0138] Then proceed to step B6.

[0139] Referring to Figure 9, in step B6, a source electrode s01 and a drain electrode d01, which are insulated from the gate electrode g01, are formed on the gate electrode g01. The source electrode s01 is connected to the first contact portion p1, and the drain electrode d01 is connected to the second contact portion p2.

[0140] Optionally, step B6 includes: forming an interlayer dielectric layer Ld on the gate g01; subsequently, forming a source s01 and a drain d01 on the interlayer dielectric layer Ld.

[0141] In addition, the method for fabricating the array substrate 100 in this embodiment of the application further includes the following steps:

[0142] Referring to Figure 10 and step B7, a planarization layer Pn, a common electrode layer com, a passivation layer pv, and a pixel electrode pix are sequentially formed on the source electrode s01 and the drain electrode d01. The pixel electrode pix is ​​connected to the drain electrode d01 through a via.

[0143] It should be noted that, please refer to Figure 11, which is a comparison graph of the transfer curves of thin-film transistors with drain voltage Vd=0.1V and drain voltage Vd=10V in experimental embodiments of Comparative Example 1, Comparative Example 2 and the preparation method of this application.

[0144] The only difference between Comparative Example 1, Comparative Example 2, and the Experimental Example is whether plasma bombardment of the edge portion gd2 is used in the manufacturing process. That is, the low-temperature polycrystalline silicon thin-film transistor of Comparative Example 1 is a thin-film transistor without plasma bombardment, the low-temperature polycrystalline silicon thin-film transistor of Comparative Example 2 is a thin-film transistor bombarded with oxygen plasma, and the Experimental Example is a low-temperature polycrystalline silicon thin-film transistor TFT formed by the array substrate fabrication method of the present application embodiment, which is a thin-film transistor TFT bombarded with argon plasma.

[0145] As shown in Figure 11, compared with Comparative Example 1, under the conditions of drain voltage Vd=0.1V or drain voltage Vd=10V, Comparative Example 2, which uses oxygen plasma for bombardment, does not significantly improve the hump effect; while the experimental example using argon plasma for bombardment has a better improvement effect on the hump effect.

[0146] In another aspect, referring to FIG12, this application embodiment also provides a display panel 1000, which includes an array substrate as described in any of the above embodiments.

[0147] The display panel 1000 in the embodiments of this application can be one of a liquid crystal panel, an electroluminescent display panel, and an electrophoretic panel, such as an FFS liquid crystal display panel, an IPS liquid crystal display panel, a VA liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, a sub-millimeter-level light-emitting diode display panel, a quantum dot light-emitting diode display panel, or an electrophoretic panel, etc.

[0148] It should be noted that the structure of the thin-film transistor of the array substrate 100 of the display panel 1000 in this application embodiment is similar to or the same as the structure of the thin-film transistor TFT of the array substrate 100 in any of the above embodiments.

[0149] Optionally, Figure 12 shows a display panel 1000 according to an embodiment of this application. The display panel 1000 is a liquid crystal panel. The display panel 1000 includes an array substrate 100, a counter substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.

[0150] The display panel of this application embodiment includes a thin-film transistor. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion. The edge portion has a slope angle of less than 90 degrees. The defect state density of the edge portion is greater than that of the main body portion.

[0151] In this embodiment, the defect state density at the edge is set to be greater than that at the main body. Because the defect state density at the edge is larger, it is more difficult for the edge to turn on under the same gate voltage, and the edge thin film transistor is suppressed, thereby achieving the effect of improving the hump effect of the thin film transistor.

[0152] The above provides a detailed description of an array substrate, its fabrication method, and a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, comprising: substrate; as well as A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion. In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion; The edge portion has a slope angle of less than 90 degrees; the defect state density of the edge portion is greater than the defect state density of the main body portion.

2. The array substrate according to claim 1, wherein, The defect state density of the edge portion is greater than or equal to 5 times the defect state density of the main body portion.

3. The array substrate according to claim 2, wherein, The defect state density of the main body is between 1×10⁻⁶. 20 Units / eV up to 3×10 20 Between 1 / eV.

4. The array substrate according to claim 1, wherein, The carrier mobility at the edge is less than that at the main body.

5. The array substrate according to claim 1, wherein, The channel is made of polycrystalline silicon, and the crystallinity of the edge portion is less than that of the main body portion.

6. The array substrate according to any one of claims 1 to 5, wherein, The slope angle of the edge is between 30 degrees and 80 degrees.

7. The array substrate according to claim 6, wherein, The thickness of the main body is between 300 angstroms and 600 angstroms.

8. The array substrate according to claim 6, wherein, One of the edge portions is located on one side of the main body portion, and the other edge portion is located on the other side of the main body portion.

9. The array substrate according to claim 8, wherein, In a plan view of the array substrate, in a first direction, the first contact portion, the channel, and the second contact portion are arranged sequentially; in a second direction perpendicular to the first direction, one edge portion is located on one side of the main body portion, and the other edge portion is located on the other side of the main body portion.

10. The array substrate according to claim 9, wherein, The main body includes a first part and a second part, the first part being located between the second part and the edge part, and the defect state density of the first part being between the defect state density of the edge part and the defect state density of the second part.

11. The array substrate according to any one of claims 1 to 5, wherein, The array substrate further includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer, and a pixel electrode. The light-shielding layer is located on the substrate. The buffer layer covers the light-shielding layer and the substrate. The active layer is disposed on the side of the buffer layer away from the substrate. The gate insulating layer covers the active layer. The interlayer dielectric layer covers the gate. The source and the drain are disposed on the side of the interlayer dielectric layer away from the substrate. The planarization layer covers the source and the drain. The pixel electrode is disposed on the side of the planarization layer away from the substrate. The pixel electrode is connected to the source or the drain.

12. The array substrate according to claim 11, wherein, The array substrate may further include a common electrode layer and a passivation layer. The common electrode layer is disposed on the side of the planarization layer away from the substrate, and the passivation layer covers the common electrode layer. The pixel electrode is disposed on the side of the passivation layer away from the substrate.

13. A method for fabricating an array substrate, comprising the following steps: A semiconductor layer and a photoresist layer are sequentially formed on the substrate; The photoresist layer is patterned to form a photoresist pattern; Using the photoresist pattern as a mask, the semiconductor layer is etched to form an active layer. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main body portion and an edge portion. The edge portion has a slope angle of less than 90 degrees. The main body portion is covered by the photoresist pattern, and the edge portion is exposed. Using the photoresist pattern as a mask, ion bombardment is performed on the edge of the active layer to make the defect state density at the edge greater than the defect state density at the main body. Remove the photoresist pattern, and sequentially form a gate insulating layer and a gate on the active layer. The gate insulating layer at least covers the side of the channel away from the substrate, and the gate is disposed on the side of the gate insulating layer away from the substrate. A source and a drain are formed on the gate electrode, which are insulated from it. The source electrode is connected to the first contact portion, and the drain electrode is connected to the second contact portion.

14. The method for fabricating an array substrate according to claim 13, wherein, The reactivity of the ions is less than that of the oxygen plasma.

15. A display panel, comprising an array substrate, the array substrate comprising: substrate; as well as A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, a gate, a source, and a drain. The active layer includes a channel, a first contact portion, and a second contact portion. The channel includes a main portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The source is connected to the first contact portion, and the drain is connected to the second contact portion. In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion; The edge portion has a slope angle of less than 90 degrees; the defect state density of the edge portion is greater than the defect state density of the main body portion.

16. The display panel according to claim 15, wherein, The defect state density of the edge portion is greater than or equal to 5 times the defect state density of the main body portion.

17. The display panel according to claim 16, wherein, The defect state density of the main body is between 1×10⁻⁶. 20 Units / eV up to 3×10 20 Between 1 / eV.

18. The display panel according to claim 15, wherein, The carrier mobility at the edge is less than that at the main body.

19. The display panel according to claim 15, wherein, The channel is made of polycrystalline silicon, and the crystallinity of the edge portion is less than that of the main body portion.

20. The display panel according to any one of claims 15 to 19, wherein, The slope angle of the edge is between 30 degrees and 80 degrees.

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