Semiconductor device and method for forming same

Abstract

A semiconductor device and a method for forming same. The method comprises: forming a substrate; performing through-hole etching on the substrate with a first etching depth, so as to obtain a blind hole; performing pit etching on the substrate with a second etching depth, and simultaneously performing additional etching on the blind hole, so as to obtain a pit and a through hole, wherein the through hole is located in the pit; and forming an isolation material stack on the substrate, wherein the isolation material stack covers the surface of the substrate, the bottom surface and side wall surface of the pit, and the side wall surface of the through hole. The present invention can effectively reduce process limitations, reduce production costs, and improve the production efficiency.

Description

Semiconductor devices and their fabrication methods

[0001] This application claims priority to Chinese Patent Application No. CN202411220334X, filed on August 30, 2024, entitled "Semiconductor Device and Method of Forming the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0003] When manufacturing semiconductor devices, it is often necessary to form a pit on the substrate surface and then fabricate the circuit and other structures in the pit so that the top surface of the circuit structure is flush with the area outside the pit.

[0004] However, in the prior art, after forming the pit, it is necessary to form a via between the pit and the metal interconnect structure to form an electrically conductive structure. Since the pit is formed first and the via is formed later, the photoresist coating will be uneven in the etching process of the via, resulting in a vortex effect, which will affect continuous production.

[0005] In addition, an additional protective layer needs to be formed to protect the bottom surface of the pit before etching the through-hole, and the through-hole is etched using this protective layer as a mask. Summary of the Invention

[0006] This invention provides a semiconductor device and a method for forming the same, which can effectively reduce process limitations, lower production costs, and improve production efficiency.

[0007] One aspect of this invention relates to a method for forming a semiconductor device, comprising: forming a substrate; etching a through-hole in the substrate at a first etching depth to obtain a blind via; etching a pit in the substrate at a second etching depth, while simultaneously etching the blind via to obtain a pit and a through-hole, wherein the through-hole is located within the pit; and forming an isolation material stack on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and sidewall surface of the pit, and the sidewall surface of the through-hole.

[0008] Optionally, the insulating material stack includes one or more of the following stacked layers: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0009] Optionally, the silicon oxide layer is formed using an atomic layer deposition process.

[0010] Optionally, the step of using a second etching depth to perform pit etching on the substrate and simultaneously performing supplementary etching on the blind vias includes: using a plasma etching process to perform pit etching on the substrate and simultaneously performing supplementary etching on the blind vias; wherein the plasma etching process includes one or more of the following: the top power of the plasma etching process is higher than the standard top power, the standard top power being the top power used when performing pit etching on a sample substrate that does not contain the blind vias; the chamber pressure of the plasma etching process is lower than the standard chamber pressure, the standard chamber pressure being the chamber pressure used when performing pit etching on a sample substrate that does not contain the blind vias; the reaction temperature of the plasma etching process is lower than the standard reaction temperature, the standard reaction temperature being the reaction temperature used when performing pit etching on a sample substrate that does not contain the blind vias.

[0011] Optionally, the plasma etching process includes one or more of the following: the top power of the plasma etching process is selected from 800W-2000W; the chamber pressure of the plasma etching process is selected from 5mT-30mT; and the reaction temperature of the plasma etching process is selected from 30℃-70℃.

[0012] Optionally, the first etching depth is selected from 0.7μm-0.9μm.

[0013] Optionally, the second etching depth is selected from 0.8μm-0.9μm.

[0014] Optionally, the substrate has a logic circuit region and a pixel region, and the pit is formed on the back side of the substrate in the logic circuit region; the forming of the substrate includes: providing a semiconductor substrate; forming a front isolation structure in the semiconductor substrate in the pixel region and the logic circuit region from the front side of the semiconductor substrate; forming a photodiode in the semiconductor substrate in the pixel region, wherein the front isolation structure is used to isolate adjacent photodiodes.

[0015] Optionally, forming the substrate further includes: forming a semiconductor device structure on the semiconductor substrate in the pixel region; forming a metal interconnect structure on the semiconductor substrate in the pixel region and the logic circuit region; the metal interconnect structure in the pixel region being electrically connected to the semiconductor device structure; bonding the front side of the semiconductor substrate to a carrier wafer; and then thinning the semiconductor substrate from the back side to obtain the substrate.

[0016] Optionally, the projection of the via on the front side of the semiconductor substrate is located on the front isolation structure, and the via exposes the back side of the front isolation structure.

[0017] Optionally, after forming the substrate and before performing via etching on the substrate using the first etching depth, the method further includes: forming a grid-like back isolation trench from the back side of the substrate within the substrate in the pixel region, the back isolation trench being used to isolate adjacent photodiodes; and during the formation of the isolation material stack on the substrate, at least a portion of the isolation material stack filling the back isolation trench.

[0018] Optionally, the isolation material stack comprises a stack of linear oxide layer, aluminum oxide layer, and tantalum oxide layer formed sequentially; wherein the stack of linear oxide layer, aluminum oxide layer, and tantalum oxide layer fills the back isolation trench.

[0019] Optionally, the isolation material stack further includes a stack of silicon oxide and silicon nitride layers; the method further includes: using the stack of silicon oxide and silicon nitride layers as a protective layer, removing the front isolation structure exposed by the via from the back side of the substrate.

[0020] Optionally, the method further includes: forming a pad structure within the recess and the through hole, the pad structure being electrically coupled to the metal interconnect structure on the front side of the substrate in the logic circuit region.

[0021] Optionally, the pad structure is a multi-layer structure; the method further includes: forming a grid structure on the back side of the substrate in the pixel region, the grid structure being a multi-layer structure; wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

[0022] Optionally, at least a portion of the multi-layer structure of the grid structure and at least a portion of the multi-layer structure of the pad structure are formed using the same process.

[0023] Optionally, the method further includes: forming a filter within the grating structure of the pixel region; and forming a microlens structure on the grating structure of the pixel region and on a portion of the pad structure of the logic circuit region.

[0024] Another aspect of the present invention relates to a semiconductor device comprising: a substrate; a recess formed on the substrate; a via located within the recess; and an isolation material stack formed on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and sidewall surface of the recess, and the sidewall surface of the via.

[0025] Optionally, the insulating material stack includes one or more of the following stacked layers: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0026] Optionally, the substrate has a logic circuit region and a pixel region, and the pit is formed on the back side of the substrate in the logic circuit region; the substrate includes: a semiconductor substrate; a front isolation structure formed on the front side of the semiconductor substrate, within the semiconductor substrate of the pixel region and the logic circuit region; and a photodiode formed within the semiconductor substrate of the pixel region, wherein the front isolation structure is used to isolate adjacent photodiodes.

[0027] Optionally, the substrate further includes: a semiconductor device structure formed on the semiconductor substrate of the pixel region; a metal interconnect structure formed on the semiconductor substrate of the pixel region and the logic circuit region, wherein the metal interconnect structure of the pixel region is electrically connected to the semiconductor device structure; and a carrier wafer bonded to the front side of the semiconductor substrate.

[0028] Optionally, the projection of the via on the front side of the semiconductor substrate is located on the front isolation structure, and the via exposes the back side of the front isolation structure.

[0029] Optionally, the semiconductor device further includes: a grid-like back isolation trench formed on the back side of the substrate of the pixel region, the back isolation trench being used to isolate adjacent photodiodes; wherein at least a portion of the isolation material stack is filled into the back isolation trench.

[0030] Optionally, the isolation material stack comprises a stack of linear oxide layer, aluminum oxide layer, and tantalum oxide layer formed sequentially; wherein the stack of linear oxide layer, aluminum oxide layer, and tantalum oxide layer fills the back isolation trench.

[0031] Optionally, the semiconductor device further includes: a pad structure formed in the recess and the via, the pad structure being electrically coupled to the metal interconnect structure on the front side of the substrate in the logic circuit region.

[0032] Optionally, the pad structure is a multilayer structure; the semiconductor device further includes: a grid structure formed on the back side of the substrate of the pixel region, the grid structure being a multilayer structure; wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

[0033] Optionally, the semiconductor device further includes: a filter formed within the grid structure of the pixel region; a microlens structure formed on the grid structure of the pixel region and on a portion of the pad structure of the logic circuit region.

[0034] Optionally, the total thickness of the linear oxide layer, the alumina layer, and the tantalum oxide layer is selected from:

[0035] Optionally, the total thickness of the stacked layer of silicon oxide and silicon nitride is selected from:

[0036] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0037] In this embodiment of the invention, a first etching depth is used to perform through-hole etching on the substrate to obtain blind vias. Then, a second etching depth is used to perform pit etching on the substrate while simultaneously etching the blind vias to obtain both pits and through-holes. An isolation material stack is then formed to cover the surface of the substrate, the bottom and sidewall surfaces of the pits, and the sidewall surfaces of the through-holes. Using this method, by first etching the through-holes to form only the blind vias, and then etching the pits, the uniformity of photoresist coating is improved because the area of ​​the blind vias is smaller than the area of ​​the pits, effectively reducing the impact of cyclone effects. Furthermore, the through-holes are obtained by first etching the substrate at the first etching depth to obtain blind vias, and then using the second etching depth to etch the pits on the substrate while simultaneously etching the blind vias. The via etching process does not require the formation of an additional protective layer to protect the bottom surface of the pit. Compared to the approach of etching the pit first and then the via, which requires forming an additional protective layer during the via etching process, the solution of this embodiment reduces one layer of isolation material, thereby reducing production costs and accelerating product manufacturing. Furthermore, because no additional protective layer is needed during the formation of the pit and via, the isolation material stack can directly cover the sidewall surface of the via, effectively protecting the inner sidewall of the via and improving device quality.

[0038] Furthermore, the pit etching employs a plasma etching process. By utilizing a higher top power in the plasma etching process, a higher plasma concentration is formed, enhancing the etching reaction; the reaction is carried out under low pressure, increasing the mean free path of molecules and enhancing the bottom etching capability; the etching reaction is conducted at a low temperature, protecting the devices on the front side of the substrate. The top power of the plasma etching process is selected from 800W-2000W; the chamber pressure is selected from 5mT-30mT; and the reaction temperature is selected from 30℃-70℃. During the plasma etching process, the stepped shape of the pits and blind vias can be maintained.

[0039] Furthermore, the isolation material stack also includes a stack of silicon oxide and silicon nitride layers. Using the stack of silicon oxide and silicon nitride layers as a protective layer, the front isolation structure exposed by the via is removed from the back side of the substrate. By adopting the above solution, full-scale etching can be performed directly under the protection of the protective layer, thereby reducing one mask and its corresponding patterning etching steps, effectively improving production efficiency and reducing production costs. Attached Figure Description

[0040] Figures 1 to 5 are partial schematic diagrams of the cross-sectional structure of a semiconductor device corresponding to some steps in a method for forming a semiconductor device in the prior art;

[0041] Figure 6 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention;

[0042] Figures 7 to 14 are schematic diagrams of the cross-sectional structure of a semiconductor device in each step of a method for forming a semiconductor device according to an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures: 100: Semiconductor substrate; 101: Recess; 110: First protective layer; 120: Through-hole; 130: Second protective layer; 200: Semiconductor substrate; 201: Front isolation structure; 202: Photodiode; 203: Semiconductor device structure; 204: Metal interconnect structure; 205: Carrier wafer; 206: Back isolation trench; 210: First substrate protective layer; 211: First mask layer; 212: Blind via; D1: First etching depth; 220: Second substrate protective layer; 221: Second mask layer; 222: Recess; 223: Through-hole; D2: Second etching depth; 230: Isolation material stack; 240: Pad structure; 241: Grille structure. Detailed Implementation

[0044] In semiconductor device fabrication, it is often necessary to form pits on the substrate surface and then fabricate circuit structures within these pits to ensure that the top surface of the formed circuit structure is flush with the area outside the pit. In one prior art, pit etching is first performed on the substrate surface. Then, a first protective layer is formed on the surface of the substrate, the bottom surface of the pit, and the sidewall surfaces. Through-hole etching is then performed within the pit. Next, a second protective layer is formed on the surface of the substrate, the bottom surface and sidewall surfaces of the pit, and the sidewall surfaces of the through-hole. Finally, a full-scale etching process is performed to remove the substrate exposed within the through-hole.

[0045] Figures 1 to 5 are partial schematic diagrams of the cross-sectional structure of a semiconductor device corresponding to certain steps in a method for forming a semiconductor device in the prior art.

[0046] Referring to FIG1, a semiconductor substrate 100 is provided, and a pit 101 is formed by pit etching on the semiconductor substrate 100.

[0047] Referring to FIG2, a first protective layer 110 is formed on the semiconductor substrate 100. The first protective layer 110 covers the surface of the semiconductor substrate 100, the bottom surface of the pit 101, and the sidewall surface. The first protective layer 110 is used to reduce the damage to the semiconductor substrate 100 and the pit 101 formed during the etching of the via.

[0048] Referring to Figure 3, through-hole etching is performed on the semiconductor substrate 100 to form through-hole 120.

[0049] Referring to FIG4, a second protective layer 130 is formed on the semiconductor substrate 100. The second protective layer 130 covers the surface of the semiconductor substrate 100, the bottom surface and sidewall surface of the pit 101, and the sidewall surface of the via 120. The second protective layer 130 is used to reduce the damage to the semiconductor substrate 100, the pit 101, and the via 120 during the full etching.

[0050] Referring to FIG5, the semiconductor substrate 100 is fully etched to remove the substrate exposed within the via 120.

[0051] The inventors of this invention discovered through research that, in the prior art, the presence of pits leads to uneven photoresist coating during the via etching process, resulting in a swirling effect and impacting continuous production. Furthermore, an additional protective layer needs to be formed before via etching to protect the bottom and sidewall surfaces of the pits, and this protective layer is used as a mask for via etching, making the process complex and resulting in higher production costs.

[0052] In this embodiment of the invention, a substrate is formed; through-hole etching is performed on the substrate at a first etching depth to obtain blind vias; pit etching is performed on the substrate at a second etching depth, and the blind vias are simultaneously etched to obtain both pits and through-holes, wherein the through-holes are located within the pits; an isolation material stack is formed on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and sidewall surface of the pits, and the sidewall surface of the through-holes. By employing the above scheme, through-hole etching is performed first to form only the blind vias, followed by pit etching. Since the area of ​​the blind vias is smaller than the area of ​​the pits, the uniformity of photoresist coating is improved, effectively reducing the impact of cyclone effects. Furthermore, the through-holes are obtained by first etching the substrate at the first etching depth to obtain blind vias, and then etching the substrate at the second etching depth to form pits, while simultaneously etching the blind vias to obtain additional etching. The via etching process does not require the formation of an additional protective layer to protect the bottom surface of the pit. Compared to the approach of etching the pit first and then the via, which requires forming an additional protective layer during the via etching process, the solution of this embodiment reduces one layer of isolation material, thereby reducing production costs and accelerating product manufacturing. Furthermore, because no additional protective layer is needed during the formation of the pit and via, the isolation material stack can directly cover the sidewall surface of the via, effectively protecting the inner sidewall of the via and improving device quality.

[0053] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0054] Referring to Figure 6, which is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention, the method for forming the semiconductor device may include steps S61 to S64:

[0055] Step S61: Forming the substrate;

[0056] Step S62: Using the first etching depth, perform through-hole etching on the substrate to obtain blind holes;

[0057] Step S63: Using a second etching depth, perform pit etching on the substrate and simultaneously perform supplementary etching on the blind via to obtain pits and through holes, wherein the through holes are located within the pits;

[0058] Step S64: Form an isolation material stack on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and sidewall surface of the pit, and the sidewall surface of the through hole.

[0059] The steps described above are explained below with reference to Figures 7 to 11.

[0060] Figures 7 to 11 are schematic diagrams of the cross-sectional structure of a semiconductor device in each step of a method for forming a semiconductor device according to an embodiment of the present invention.

[0061] Referring to Figure 7, a substrate is formed, on which logic circuit regions and pixel regions are formed.

[0062] In some embodiments, the step of forming the substrate may include: providing a semiconductor substrate 200 having a front side and a back side.

[0063] In specific implementations, the semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 200 may also be a silicon substrate on an insulator surface or a germanium substrate on an insulator surface, or a substrate with an epitaxy layer (Epi layer) grown on it.

[0064] Preferably, the semiconductor substrate 200 is a lightly doped semiconductor substrate, and the doping type is opposite to that of the photodiode formed in the semiconductor substrate 200 in subsequent processes. If the dopant ions of the photodiode are N-type, then the dopant ions of the semiconductor substrate 200 are P-type ions, such as B, Ga, or In; conversely, if the dopant ions of the photodiode are P-type, then the dopant ions of the semiconductor substrate 200 are N-type ions, such as P, As, or Sb.

[0065] The step of forming the substrate may further include: forming a front isolation structure 201 from the front side of the semiconductor substrate 200 within the semiconductor substrate 200 in the pixel region and the logic circuit region.

[0066] Specifically, the front isolation structure 201 can be a shallow trench isolation (STI) structure, and its specific process includes: forming a shallow trench on a substrate, the shallow trench being used to isolate the active region on the substrate, the shallow trench being formed by an etching process; filling the shallow trench with a dielectric material and forming a dielectric layer on the substrate surface, the dielectric material being silicon oxide; annealing the dielectric material; and treating the dielectric layer with chemical mechanical polishing (CMP).

[0067] A photodiode 202 is formed within the semiconductor substrate 200 in the pixel region, wherein the front isolation structure 201 is used to isolate adjacent photodiodes 202.

[0068] Specifically, when the doping type of the photodiode 202 is N-type, the doping ions of the photodiode 202 can be set to include P, As, or Sb; when the doping type of the photodiode 202 is P-type, the doping ions of the photodiode 202 can be set to include B, Ga, or In.

[0069] Preferably, the doped ions of the photodiode 202 can be boron ions (P) or arsenic ions (As).

[0070] It should be noted that the thickness of the photodiode 202 can be greater than the depth of the front isolation structure 201, thereby obtaining a larger full-well capacity. The directions of both the depth of the front isolation structure 201 and the thickness of the photodiode 202 are perpendicular to the surface of the semiconductor substrate 200.

[0071] Then, a semiconductor device structure 203 can be formed on the semiconductor substrate 200 in the pixel region, and a metal interconnect structure 204 can be formed on the semiconductor substrate 200 in both the pixel region and the logic circuit region. The metal interconnect structure 204 in the pixel region is electrically connected to the semiconductor device structure 203. The front side of the semiconductor substrate 200 is bonded to the carrier wafer 205, and then the semiconductor substrate 200 is thinned from the back side to obtain the substrate.

[0072] The semiconductor component structure 203 may include logic devices in the logic circuit area and pixel devices in the pixel area (such as other semiconductor component structures besides photodiode 202).

[0073] It should be noted that, in this embodiment of the invention, the processing performed on the front side of the semiconductor substrate 200 may also include any conventional processing of existing image sensors, and this embodiment of the invention does not limit this.

[0074] After the substrate is formed, a grid-like back isolation trench 206 is formed from the back side of the substrate within the pixel region of the substrate. The back isolation trench 206 is used to isolate adjacent photodiodes 202.

[0075] Specifically, the back isolation trench 206 can be formed by an etching process.

[0076] Referring to FIG8, a first substrate protection layer 210 and a patterned first mask layer 211 are formed on the back side of the substrate and in the back isolation trench 206.

[0077] The material of the first substrate protective layer 210 can be an oxide layer, specifically, it can be formed by thermal oxidation process or by chemical vapor deposition process.

[0078] It should be noted that the material of the first substrate protective layer 210 can also be other suitable materials, such as nitride layers, etc.

[0079] The material of the first substrate protective layer 210 can be determined according to the material of the semiconductor substrate 200. For example, if the semiconductor substrate 200 is a silicon substrate, the material of the first substrate protective layer 210 can be silicon oxide; if the semiconductor substrate 200 is a germanium substrate, the material of the first substrate protective layer 210 can be germanium oxide.

[0080] The patterned first mask layer 211 can be a patterned first photoresist layer.

[0081] Referring to Figure 9, using the first mask layer 211 as a mask, a first etching depth D1 is used to perform via etching on the substrate to obtain a blind via 212.

[0082] It should be noted that in some embodiments, when the semiconductor device is an image sensor, after obtaining the via through-hole through subsequent etching, the via needs to expose the back side of the front isolation structure. Therefore, the first etching depth D1 should not be too small, otherwise it will be difficult to obtain a via with sufficient depth after the required pit depth is obtained through etching; the first etching depth D1 should not be too large, otherwise it will be difficult to obtain a pit with sufficient depth after obtaining the required via depth.

[0083] Furthermore, the first etching depth D1 can be the difference between the standard depth of the through hole and the standard depth of the pit.

[0084] The standard depth can be determined according to design rules and standard recipe flow.

[0085] In one specific embodiment, the first etching depth D1 can be selected from 0.7μm-0.9μm.

[0086] Referring to FIG10, a second substrate protection layer 220 and a patterned second mask layer 221 are formed on the back side of the substrate and in the back isolation trench 206.

[0087] For details regarding the materials, formation methods, and beneficial effects of the second substrate protective layer 220 and the second mask layer 221, please refer to the description above and Figure 8; further details will not be repeated here.

[0088] Referring to Figure 11, using the second mask layer 221 as a mask, the substrate is etched with a second etching depth D2 to create pits, and the blind via 212 is etched to obtain pits 222 and vias 223.

[0089] The recess 222 is formed on the back side of the substrate of the logic circuit region, and the via 223 is located within the recess 222. The projection of the via 223 on the front side of the semiconductor substrate 200 is located on the front isolation structure 201, and the via 223 exposes the back side of the front isolation structure 201.

[0090] In the above specific embodiment, the second etching depth D2 can be the standard depth of the etching process of the pit 222.

[0091] Specifically, the second etching depth D2 of the pit can be selected from 0.8μm-0.9μm.

[0092] Furthermore, the pit etching can be performed using a plasma etching process.

[0093] The plasma etching process includes one or more of the following: the top power of the plasma etching process is higher than the standard top power, where the standard top power is the top power used when performing pit etching on a sample substrate that does not contain the blind via; the chamber pressure of the plasma etching process is lower than the standard chamber pressure, where the standard chamber pressure is the chamber pressure used when performing pit etching on a sample substrate that does not contain the blind via; and the reaction temperature of the plasma etching process is lower than the standard reaction temperature, where the standard reaction temperature is the reaction temperature used when performing pit etching on a sample substrate that does not contain the blind via.

[0094] In some embodiments, by employing a higher top power in the plasma etching process, a higher concentration of plasma can be generated, enhancing the etching reaction.

[0095] In one specific embodiment, the top power of the plasma etching process can be selected from 800W-2000W, for example from 1200W-1600W, such as 1400W.

[0096] In some embodiments, etching at low pressure can increase the molecular mean free path and enhance bottom etching capability.

[0097] In one specific embodiment, the chamber pressure of the plasma etching process can be selected from 5mT-30mT, for example from 15mT-25mT.

[0098] In some embodiments, etching at low temperatures can protect the front-side devices of the substrate.

[0099] In one specific embodiment, the reaction temperature of the plasma etching process can be selected from 30℃-70℃, for example from 40℃-60℃, such as 50℃.

[0100] It should be noted that by employing one or more of the above process parameters, the stepped shape of the pits and blind holes can be maintained during the plasma etching process.

[0101] It should be noted that by first performing the through-hole etching and forming only the blind via 212, and then performing the pit etching, the uniformity of photoresist coating is improved because the area of ​​the blind via 212 is smaller than the area of ​​the pit 222, which can effectively reduce the influence of the cyclone effect. Furthermore, the through-hole 223 is obtained by using a first etching depth D1 to perform through-hole etching on the substrate to obtain the blind via 212, followed by pit etching on the substrate using a second etching depth D2, while simultaneously performing supplementary etching on the blind via 212. The through-hole etching does not require the formation of an additional protective layer to protect the bottom surface of the pit 222. Compared to the scheme of first etching the pit and then etching the through-hole, which requires forming an additional protective layer to protect the bottom surface of the pit 222 during the through-hole etching process, the scheme of this embodiment can reduce one layer of isolation material formation, reduce production costs, and accelerate product production speed.

[0102] Referring to FIG12, an isolation material stack 230 is formed on the substrate, the isolation material stack 230 covering the surface of the substrate, the bottom surface and sidewall surface of the pit 222, and the sidewall surface of the through hole 223.

[0103] Specifically, the isolation material stack 230 may include one or more of the following stacked layers: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0104] The linear oxide layer can be formed by a thermal oxidation process, and its material can be determined according to the material of the semiconductor substrate 200. For example, if the semiconductor substrate 200 is a silicon substrate, the material of the linear oxide layer can be silicon oxide; if the semiconductor substrate 200 is a germanium substrate, the material of the linear oxide layer can be germanium oxide.

[0105] It should be noted that the dielectric constant (K value) of alumina (Al2O3) is 39.922, while the dielectric constant (K value) of tantalum oxide (Ta2O5) can be adjusted between 11.6 and 34.3 as required. Therefore, when one or more of the alumina and tantalum oxide layers are used to form the insulating material stack, a high-K (HK) material layer can be obtained, which helps to achieve better thermal stability and lower leakage current.

[0106] Furthermore, the silicon oxide layer can be formed using atomic layer deposition (ALD) to improve the coverage and material density of the steps and sidewall surfaces.

[0107] It should be noted that the silicon oxide layer can also be formed using other suitable processes, such as chemical vapor deposition processes other than atomic layer deposition.

[0108] In some embodiments, the total thickness of the linear oxide layer, the alumina layer, and the tantalum oxide layer may be selected from: To achieve a better balance between process cost control and protective performance.

[0109] In some embodiments, the total thickness of the stacked layer of silicon oxide layer and silicon nitride layer is selected from: To achieve a better balance between process cost control and protective performance.

[0110] In this embodiment of the invention, the back isolation trench 206 is filled with a dielectric material, which is a stacked layer of linear oxide, aluminum oxide, and tantalum oxide. By filling the back isolation trench 206 with the dielectric material, an isolation structure for isolating the active region can be formed.

[0111] It should be noted that because no additional protective layer is needed during the formation of the pit 222 and the through hole 223, the isolation material stack 230 can directly cover the sidewall surface of the through hole 223, effectively protecting the inner sidewall of the through hole 223 and improving the device quality.

[0112] Referring to Figure 13, a full etching is performed from the back side of the substrate to remove the front isolation structure exposed by the via 223.

[0113] It is understood that, in another specific embodiment, a patterned mask layer can also be formed, and etching can be performed using the patterned mask layer as a mask.

[0114] It should be noted that when the isolation material stack 230 also includes a stack of silicon oxide and silicon nitride layers, the overall etching can use the stack of silicon oxide and silicon nitride layers formed in the prior process as a protective layer, and the substrate can be etched directly under the protection of the protective layer. Compared with the patterned etching process, this reduces the number of photomasks and photolithography processes, thus improving production efficiency.

[0115] It should be noted that after full etching, a portion of the thickness of the stacked silicon oxide and silicon nitride layers will be consumed, thereby protecting the HK material layer.

[0116] Referring to FIG14, a pad structure 240 is formed within the recess 222 and the through hole 223. The pad structure 240 is a multi-layer structure, and the pad structure 240 is electrically coupled to the metal interconnect structure 204 on the front side of the substrate in the logic circuit region. A grid structure 241 is formed on the back side of the substrate in the pixel region. The grid structure 241 is a multi-layer structure; wherein, on the back side of the substrate, the top surface of the pad structure 240 is flush with the top surface of the grid structure 241.

[0117] Specifically, at least a portion of the multi-layer structure of the grid structure 241 and at least a portion of the multi-layer structure of the pad structure 240 are formed sequentially using the same process.

[0118] Furthermore, a color filter is formed within the grid structure 241 in the pixel region; and a micro-lens structure is formed on the grid structure 241 in the pixel region and on a portion of the pad structure 240 in the logic circuit region.

[0119] It should be noted that by keeping the top surface of the pad structure 240 of the pixel area flush with the top surface of the grid structure 241, a better bottom base can be provided for the formation of the filter, which can effectively improve the swirling effect when coating photoresist.

[0120] It should be noted that, in the embodiments of the present invention, the processing technology performed on the substrate after forming the microlens structure can be any conventional processing technology of existing image sensors, and the embodiments of the present invention do not limit this.

[0121] In this embodiment of the invention, a semiconductor device is also provided. Referring to FIG14, the semiconductor device may include: a substrate; a recess 222 formed on the substrate; a through-hole 223 located within the recess 222; and an isolation material stack 230 formed on the substrate, the isolation material stack 230 covering the surface of the substrate, the bottom surface and sidewall surface of the recess 222, and the sidewall surface of the through-hole 223.

[0122] Furthermore, the insulating material stack 230 includes one or more of the following stacked layers: a linear oxide layer, an aluminum oxide layer, a tantalum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0123] Further, the substrate has a logic circuit region and a pixel region, and the pit 222 is formed on the back side of the substrate of the logic circuit region; the substrate includes: a semiconductor substrate 200; a front isolation structure 201 (refer to Figure 12) formed on the front side of the semiconductor substrate 200, within the semiconductor substrate 200 of the pixel region and the logic circuit region; and a photodiode 202 formed within the semiconductor substrate 200 of the pixel region, wherein the front isolation structure 201 is used to isolate adjacent photodiodes 202.

[0124] Furthermore, the substrate further includes: a semiconductor device structure 203 formed on the semiconductor substrate 200 in the pixel region; a metal interconnect structure 204 formed on the semiconductor substrate 200 in the pixel region and the logic circuit region, wherein the metal interconnect structure 204 in the pixel region is electrically connected to the semiconductor device structure 203; and a carrier wafer 205 bonded to the front side of the semiconductor substrate 200.

[0125] Furthermore, the projection of the via 223 on the front side of the semiconductor substrate 200 is located on the front isolation structure 201, and the via 223 exposes the back side of the front isolation structure 201.

[0126] Furthermore, the semiconductor device further includes: a grid-like back isolation trench 206 formed on the back side of the substrate of the pixel region, the back isolation trench 206 being used to isolate adjacent photodiodes 202; wherein at least a portion of the isolation material stack 230 is filled into the back isolation trench 206.

[0127] Furthermore, the isolation material stack 230 comprises a stack of linear oxide layer, aluminum oxide layer and tantalum oxide layer formed sequentially; wherein the stack of linear oxide layer, aluminum oxide layer and tantalum oxide layer fills the back isolation trench 206.

[0128] Furthermore, the semiconductor device further includes a pad structure 240 formed within the recess 222 and the via 223, the pad structure 240 being electrically coupled to the metal interconnect structure 204 on the front side of the substrate in the logic circuit region.

[0129] Furthermore, the pad structure 240 is a multilayer structure; the semiconductor device further includes: a grid structure 241 formed on the back side of the substrate of the pixel region, the grid structure 241 being a multilayer structure; wherein, on the back side of the substrate, the top surface of the pad structure 240 is flush with the top surface of the grid structure 241.

[0130] Furthermore, the semiconductor device further includes: a filter formed within the grid structure 241 of the pixel region; a microlens structure formed on the grid structure 241 of the pixel region and on a portion of the pad structure 240 of the logic circuit region.

[0131] Furthermore, the total thickness of the linear oxide layer, the alumina layer, and the tantalum oxide layer is selected from:

[0132] Furthermore, the total thickness of the stacked layer of silicon oxide and silicon nitride is selected from:

[0133] For the principles, specific implementation, and beneficial effects of this semiconductor device, please refer to the previous text and the relevant descriptions of the semiconductor device formation method shown in Figures 7 to 14, which will not be repeated here.

[0134] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. As used herein, unless explicitly stated otherwise, the term "or" covers all possible combinations unless impractical. For example, if a component is declared to include A or B, then unless explicitly stated otherwise or impractical, the component can include A, or B, or A and B. As a second example, if a component is declared to include A, B, or C, then unless explicitly stated otherwise or impractical, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0135] In the embodiments of this application, "multiple" refers to two or more.

[0136] Relational terms appearing in the embodiments of this application, such as "first," "second," etc., are used only to distinguish an entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the words "comprising," "having," and "including," as well as other similar forms, are intended to be equivalent in meaning and are open-ended; one or more items following any of these words do not imply an exhaustive list of such items or that they are limited to only the listed items.

[0137] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0138] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, include: Forming a base; Using a first etching depth, through-hole etching is performed on the substrate to obtain blind holes; Using a second etching depth, the substrate is etched with pits, and the blind vias are simultaneously etched to obtain pits and through holes, wherein the through holes are located within the pits; An isolation material stack is formed on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and sidewall surface of the pit, and the sidewall surface of the through hole.

2. The method according to claim 1, characterized in that, The insulating material stack comprises one or more of the following stacked layers: Linear oxide layer, aluminum oxide layer, tantalum oxide layer, silicon oxide layer and silicon nitride layer.

3. The method according to claim 2, characterized in that, The silicon oxide layer is formed using an atomic layer deposition process.

4. The method according to claim 1, characterized in that, The process of using a second etching depth to perform pit etching on the substrate and simultaneously performing fill etching on the blind vias includes: The substrate is etched with a plasma etching process to create pits, and the blind holes are simultaneously etched. The plasma etching process includes one or more of the following: The plasma etching process uses a higher top power than the standard top power, which is the top power used when performing pit etching on a sample substrate that does not contain the blind hole. The chamber pressure of the plasma etching process is lower than the standard chamber pressure, which is the chamber pressure used when performing pit etching on a sample substrate that does not contain the blind hole. The reaction temperature of the plasma etching process is lower than the standard reaction temperature, which is the reaction temperature used when performing pit etching on a sample substrate that does not contain the blind hole.

5. The method according to claim 4, characterized in that, The plasma etching process includes one or more of the following: The top power of the plasma etching process is selected from 800W-2000W; The chamber pressure of the plasma etching process is selected from 5mT-30mT; The reaction temperature of the plasma etching process is selected from 30℃-70℃.

6. The method according to claim 1, characterized in that, The first etching depth is selected from 0.7μm-0.9μm.

7. The method according to claim 1, characterized in that, The second etching depth is selected from 0.8μm-0.9μm.

8. The method according to claim 1, characterized in that, The substrate has a logic circuit region and a pixel region, and the pit is formed on the back side of the substrate of the logic circuit region; The formation of the substrate includes: Provide semiconductor substrates; A front-side isolation structure is formed within the semiconductor substrate from the front side of the semiconductor substrate, in the pixel region and the logic circuit region; A photodiode is formed within the semiconductor substrate in the pixel region, wherein the front isolation structure is used to isolate adjacent photodiodes.

9. The method according to claim 8, characterized in that, The formation of the substrate further includes: A semiconductor device structure is formed on the semiconductor substrate in the pixel region, and a metal interconnect structure is formed on the semiconductor substrate in the pixel region and the logic circuit region. The metal interconnect structure in the pixel region is electrically connected to the semiconductor device structure. The front side of the semiconductor substrate is bonded to the carrier wafer, and then the semiconductor substrate is thinned from the back side to obtain the substrate.

10. The method according to claim 8, characterized in that, The projection of the via on the front side of the semiconductor substrate is located on the front isolation structure, and the via exposes the back side of the front isolation structure.

11. The method according to claim 8, characterized in that, After the substrate is formed, and before the via etching is performed on the substrate using the first etching depth, the method further includes: Within the substrate of the pixel region, a grid-like back isolation trench is formed from the back side of the substrate, the back isolation trench being used to isolate adjacent photodiodes; During the process of forming the isolation material stack on the substrate, at least a portion of the isolation material stack fills the back isolation trench.

12. The method according to claim 11, characterized in that, The insulating material stack comprises a stack of linear oxide layer, aluminum oxide layer and tantalum oxide layer formed sequentially; The linear oxide layer, aluminum oxide layer, and tantalum oxide layer are stacked and filled into the back isolation trench.

13. The method according to claim 11, characterized in that, The isolation material stack also includes a stacked layer of silicon oxide layer and silicon nitride layer; The method further includes: Using the stacked layer of silicon oxide and silicon nitride as a protective layer, the front isolation structure exposed by the via is removed from the back side of the substrate.

14. The method according to claim 13, characterized in that, The method further includes: A pad structure is formed within the recess and the through hole, and the pad structure is electrically coupled to the metal interconnect structure on the front side of the substrate in the logic circuit region.

15. The method according to claim 14, characterized in that, The padding structure is a multi-layer structure; The method further includes: A grid structure is formed on the back surface of the substrate in the pixel region, and the grid structure is a multi-layer structure. Wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

16. The method according to claim 15, characterized in that, At least a portion of the multi-layer structure of the grid structure and at least a portion of the multi-layer structure of the padding structure are formed sequentially using the same process.

17. The method according to claim 15, characterized in that, The method further includes: A filter is formed within the grid structure of the pixel region; Microlens structures are formed on the grid structure in the pixel region and on a portion of the pad structure in the logic circuit region.

18. A semiconductor device, characterized in that, include: Base; A pit is formed on the substrate; A through hole, wherein the through hole is located within the recess; An isolation material stack is formed on the substrate, the isolation material stack covering the surface of the substrate, the bottom surface and sidewall surface of the pit, and the sidewall surface of the through hole.

19. The semiconductor device according to claim 18, characterized in that, The insulating material stack comprises one or more of the following stacked layers: Linear oxide layer, aluminum oxide layer, tantalum oxide layer, silicon oxide layer and silicon nitride layer.

20. The semiconductor device according to claim 18, characterized in that, The substrate has a logic circuit region and a pixel region, and the pit is formed on the back side of the substrate of the logic circuit region; The substrate includes: Semiconductor substrate; A front-side isolation structure is formed on the front side of the semiconductor substrate, within the semiconductor substrate of the pixel region and the logic circuit region; A photodiode is formed within the semiconductor substrate of the pixel region, wherein the front isolation structure is used to isolate adjacent photodiodes.

21. The semiconductor device according to claim 20, characterized in that, The substrate also includes: A semiconductor component structure is formed on the semiconductor substrate in the pixel region; A metal interconnect structure is formed on the semiconductor substrate of the pixel region and the logic circuit region, and the metal interconnect structure of the pixel region is electrically connected to the semiconductor device structure. The wafer is bonded to the front side of the semiconductor substrate.

22. The semiconductor device according to claim 20, characterized in that, The projection of the via on the front side of the semiconductor substrate is located on the front isolation structure, and the via exposes the back side of the front isolation structure.

23. The semiconductor device according to claim 20, characterized in that, The semiconductor device further includes: A grid-like back isolation trench is formed on the back side of the substrate of the pixel region, the back isolation trench being used to isolate adjacent photodiodes; At least a portion of the insulating material stack is filled into the back insulating groove.

24. The semiconductor device according to claim 23, characterized in that, The insulating material stack comprises a stack of linear oxide layer, aluminum oxide layer and tantalum oxide layer formed sequentially; The linear oxide layer, aluminum oxide layer, and tantalum oxide layer are stacked and filled into the back isolation trench.

25. The semiconductor device according to claim 23, characterized in that, The semiconductor device further includes: A pad structure is formed within the recess and the via, the pad structure being electrically coupled to the metal interconnect structure on the front side of the substrate in the logic circuit region.

26. The semiconductor device according to claim 25, characterized in that, The padding structure is a multi-layer structure; The semiconductor device further includes: A grid structure is formed on the back side of the substrate of the pixel region, and the grid structure is a multi-layer structure; Wherein, on the back side of the substrate, the top surface of the pad structure is flush with the top surface of the grid structure.

27. The semiconductor device according to claim 26, characterized in that, The semiconductor device further includes: A filter is formed within the grid structure of the pixel region; A microlens structure is formed on the grid structure of the pixel region and on a portion of the pad structure of the logic circuit region.

28. The semiconductor device according to claim 18, characterized in that, The total thickness of the linear oxide layer, the aluminum oxide layer, and the tantalum oxide layer is selected from:

29. The semiconductor device according to claim 18, characterized in that, The total thickness of the stacked layer of silicon oxide and silicon nitride is selected from:

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