Method and apparatus for software-hardware clock synchronization between multiple nodes in real-time simulation

Abstract

A method and apparatus for software-hardware clock synchronization between multiple nodes in real-time simulation, relating to the technical field of big data simulation. The method ensures the consistency of clock signals of a simulation system by performing clock synchronization on a clock signal of each computation step of hardware connected to each node in simulation software, and ensures software-hardware time step consistency by verifying the computation step between the hardware connected to each node and the software, omitting a clock synchronization mechanism between the software, reducing the difficulty of clock synchronization of the simulation system, preventing the accumulation of system clock errors, and improving joint real-time simulation performance between the multiple nodes.

Description

A method and apparatus for real-time simulation of software-hardware clock synchronization between multiple nodes

[0001] This application claims priority to Chinese Patent Application No. 202411210377.X, filed on August 30, 2024, entitled "A Method and Apparatus for Real-Time Simulation of Software-Hardware Clock Synchronization Between Multiple Nodes", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of big data simulation technology, and in particular to a method and apparatus for real-time simulation of software-hardware clock synchronization between multiple nodes. Background Technology

[0003] Real-time simulation of power systems is an effective means of understanding the characteristics of power systems, supporting power system research, planning, operation, production, equipment manufacturing, and ensuring the safe and reliable operation of power systems. With the rapid development of new power systems and the grid connection of massive amounts of new energy generating units and power electronic devices, the system scale has expanded dramatically, urgently requiring large-scale node parallel simulation. The clock synchronization method among multiple nodes is a crucial factor affecting parallel simulation. Existing clock synchronization methods correct the clocks of each node within a fixed period, causing clock errors between different nodes to accumulate within the correction period, which affects the joint real-time simulation performance among multiple nodes.

[0004] Currently, clock synchronization between multiple nodes is quite difficult in real-time simulation. Clock errors are hard to synchronize accurately, which can easily lead to the accumulation of clock errors and thus greatly reduce the performance of joint real-time simulation between multiple nodes. Summary of the Invention

[0005] This invention provides a method and apparatus for software-hardware clock synchronization between multiple nodes in real-time simulation, reducing the difficulty of clock synchronization between multiple nodes in real-time simulation. Accurate clock error synchronization avoids the accumulation of system clock errors, thereby improving the joint real-time simulation performance between multiple nodes.

[0006] In view of this, the first aspect of the present invention provides a real-time simulation method for software-hardware clock synchronization between multiple nodes, comprising:

[0007] In response to the clock synchronization request of the real-time simulation task, the clock signals of each calculation step of the hardware connected to each node in the simulation software are synchronized.

[0008] For each node in the simulation software, compare whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node;

[0009] When the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the first node continues to execute the next calculation task, updates the current number of calculation steps of the first node by 1, and proceeds to the step of comparing whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, until the calculation task of all calculation steps of the first node is completed.

[0010] Preferably, the step of synchronizing the clock signals of each calculation step of the hardware connected to each node in the simulation software includes:

[0011] The time synchronization server allocates a reference clock signal to each calculation step of the hardware connected to each node in the simulation software.

[0012] Based on the reference clock signals, the clock signals of each calculation step of the hardware connected to each node are clock-calibrated to synchronize the clock signals of each calculation step of the hardware with the reference clock signals allocated to each calculation step of the hardware.

[0013] Preferably, the step of comparing the number of computation steps of the first node with the number of computation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software includes:

[0014] When the first node completes the current computing task, it transmits the computing task data to the hardware connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task;

[0015] Compare whether the number of calculation steps corresponding to the completion of the current calculation task by the first node received by the hardware is consistent with the number of calculation steps corresponding to the current clock signal;

[0016] When the number of calculation steps corresponding to the completion of the current calculation task by the first node received by the hardware is consistent with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and sends the data of the next calculation task back to the simulation software running on the first node.

[0017] Compare the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node with the number of calculation steps when the first node executes the next calculation task;

[0018] When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is consistent with the number of calculation steps when the first node completes the next calculation task, it is determined that the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0019] Preferably, after the step of comparing whether the number of computation steps corresponding to the current computation task received by the hardware is consistent with the number of computation steps corresponding to the current clock signal, the method further includes:

[0020] If the number of computation steps corresponding to the completion of the current computation task by the first node received by the hardware is inconsistent with the number of computation steps corresponding to the current clock signal, then the simulation program run by the simulation software is terminated.

[0021] Preferably, after the step of comparing the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software, the method further includes:

[0022] If the number of calculation steps of the first node is not synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the simulation program run by the simulation software is terminated.

[0023] Preferably, the method further includes:

[0024] When the first node completes the current computing task, it transmits the computing task data to the second node connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task;

[0025] According to a preset verification period, the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is periodically compared with the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the second node.

[0026] When the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is consistent with the number of calculation steps received by the second node corresponding to the completion of the current calculation task, the second node executes the next calculation task.

[0027] If the number of computation steps received by the second node corresponding to the completion of the current computation task by the first node is inconsistent with the number of computation steps received by the second node corresponding to the completion of the current computation task by the second node, then the simulation program running by the simulation software is terminated.

[0028] Secondly, the present invention also provides a real-time simulation software-hardware clock synchronization device between multiple nodes, comprising:

[0029] The timing synchronization module is used to respond to clock synchronization requests for real-time simulation tasks and synchronize the clock signals of each calculation step of the hardware connected to each node in the simulation software.

[0030] The synchronization verification module is used to compare the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software.

[0031] The verification execution module is used to ensure that when the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the first node continues to execute the next calculation task and updates the current number of calculation steps of the first node by 1. The module then performs a comparison to see if the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, until the calculation tasks of all calculation steps of the first node are completed.

[0032] Thirdly, the present invention also provides an electronic device, the electronic device including a memory and a processor, the memory storing a computer program, the computer program being executed by the processor causing the processor to perform the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in the first aspect.

[0033] Fourthly, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed, implements the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in the first aspect.

[0034] Fifthly, the present invention also provides a computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein, when the program instructions are executed by a computer, the computer performs the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in the first aspect.

[0035] As can be seen from the above technical solutions, the present invention has the following advantages:

[0036] This invention ensures the consistency of the simulation system's clock signal by synchronizing the clock signals of each calculation step of the hardware connected to each node in the simulation software. By verifying the calculation steps between the hardware and software of each node, the software-hardware time step consistency is ensured. This eliminates the need for a clock synchronization mechanism between software, reduces the difficulty of synchronizing the simulation system's clock, avoids the accumulation of system clock errors, and thus improves the joint real-time simulation performance between multiple nodes. Attached Figure Description

[0037] Figure 1 is a schematic diagram of the electromagnetic transient simulation system provided in an embodiment of the present invention;

[0038] Figure 2 is a flowchart of a real-time simulation software-hardware clock synchronization method between multiple nodes provided by an embodiment of the present invention;

[0039] Figure 3 is a schematic diagram of a real-time simulation software-hardware clock synchronization device between multiple nodes provided in an embodiment of the present invention.

[0040] Figure 4 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] The real-time simulation multi-node software-hardware clock synchronization method provided in this application embodiment can be applied to the application environment of the electromagnetic transient simulation system shown in Figure 1. The electromagnetic transient simulation system includes a timing server 101, a signal amplifier 102, an FPGA timing card 103, hardware 104, and simulation software 105. The timing server 101 can be a BeiDou timing server, receiving BeiDou satellite signals to generate a reference clock signal, and sending the reference clock signal to the signal amplifier via a communication channel according to both 1PPS and TOD protocols, denoted as T. i The reference clock signal for the x-th calculation step is denoted as t. Signal amplifier 102 receives the reference clock signal sent by the timing server, amplifies and processes it to ensure it remains stable and unaffected during transmission. The reference clock signals for each calculation step are distributed to the FPGA timing cards 103 of different nodes to minimize clock errors. Multiple FPGA timing cards 103 are interconnected with the hardware of different nodes. Each timing card receives the amplified reference clock signal from signal amplifier 102 and then analyzes and processes it. The FPGA timing card 103 calibrates its own clock based on the received amplified reference clock signal to ensure synchronization with the clock of the timing server 101. This ensures that all hardware 104 in the network obtains accurate authorized clock information, maintaining time uniformity and synchronization throughout the network system. The clock signal for the x-th calculation step of the FPGA timing card 103 of the j-th node is denoted as t. jx , (x, j = 1, 2, ...).

[0043] In this context, a node refers to the smallest independent unit for simulation calculations in the simulation software, including a CPU, FPGA, and corresponding peripheral interfaces. In the electromagnetic transient simulation system, the nodes in the simulation software 105 are connected to corresponding hardware 104, such as various control and protection devices, rectifier / inverter equipment and protection devices for new energy sources, etc.

[0044] Based on this, as shown in Figure 2, this embodiment of the invention provides a real-time simulation software-hardware clock synchronization method between multiple nodes. The method provided by this embodiment of the invention can be executed by a real-time simulation software-hardware clock synchronization device between multiple nodes. This real-time simulation software-hardware clock synchronization device between multiple nodes can be implemented in hardware and / or software form, and can be configured in a computer device.

[0045] This invention provides a real-time simulation method for software-hardware clock synchronization between multiple nodes, comprising steps S1 to S3.

[0046] Step S1: In response to the clock synchronization request for the real-time simulation task, synchronize the clock signals of each calculation step of the hardware connected to each node in the simulation software.

[0047] In the application environment of the aforementioned electromagnetic transient simulation system, the FPGA timing card 103 is used to synchronize the clock signals of each calculation step of the hardware connected to each node in the simulation software. The clock signals of each calculation step of the hardware of each node can be synchronized with the clock of the Beidou timing server. At the same time, the synchronization of the clock signals of each calculation step of the hardware of each node can be completed before the simulation, ensuring the consistency of the clock signals of the simulation system.

[0048] Because software synchronization involves more complex steps, it requires synchronization of the execution instruction set. There are too many interfering factors (such as various operations and scheduling performed by the operating system), making it extremely difficult to implement. Therefore, this embodiment of the invention first synchronizes the clock signals of each calculation step of the hardware of each node, reducing the difficulty of clock synchronization in the simulation system.

[0049] Specifically, step S1 involves synchronizing the clock signals of the hardware connected to each node in the simulation software for each calculation step, including steps S101 to S102.

[0050] Step S101: Based on the time synchronization server, allocate reference clock signals to each calculation step of the hardware connected to each node in the simulation software.

[0051] Step S102: Based on each reference clock signal, perform clock calibration on the clock signals of each calculation step of the hardware connected to each node, so that the clock signals of each calculation step of the hardware are synchronized with the reference clock signals allocated to each calculation step of the hardware.

[0052] Step S2: For each node in the simulation software, compare whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0053] The first node can be any node in the simulation software.

[0054] During real-time simulation, multiple nodes in the simulation software run the simulation together. At the same time, based on the real-time synchronization relationship of the simulation, the number of calculation steps of the first node should be synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0055] If the number of steps calculated by the two programs is out of sync, it means that the number of steps in their simulation programs is inconsistent. The program needs to be forcibly stopped, and no further operation will be performed; instead, an error will be reported directly.

[0056] For example, when the number of calculation steps of the first node is not synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the simulation program running by the simulation software is terminated, thereby reporting an error to avoid the accumulation of system clock errors and thus improve the performance of electromagnetic transient joint real-time simulation between multiple nodes.

[0057] For example, the process of comparing whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node in step S2 includes steps S201 to S205.

[0058] in,

[0059] Step S201: When the first node completes the current computing task, it transmits the computing task data to the hardware connected to the first node. The computing task data includes the number of computing steps corresponding to the current computing task.

[0060] Among them, the computation task is the simulation task that the first node is running at the current computation step, such as various first-order and second-order computation tasks in electromagnetic transient simulation, arithmetic operations on various types of data, and matrix inversion.

[0061] When the first node completes the current computing task, it outputs the computing task data to the hardware connected to the first node. In addition to the computing result of the first node completing the current computing task, the computing task data should also include the number of computing steps corresponding to the current computing task, so that the hardware can verify it later.

[0062] Step S202: Compare the number of calculation steps corresponding to the completion of the current calculation task by the first node received by the hardware with the number of calculation steps corresponding to the current clock signal.

[0063] Step S203: When the number of calculation steps corresponding to the current calculation task completed by the first node received by the comparison hardware is consistent with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and sends the data of the next calculation task back to the simulation software running on the first node.

[0064] Similarly, when the number of calculation steps corresponding to the current calculation task completed by the first node received by the comparison hardware is inconsistent with the number of calculation steps corresponding to the current clock signal, the simulation program running by the simulation software is terminated and an error is reported. No further operation is performed to avoid the accumulation of system clock errors, thereby improving the performance of electromagnetic transient joint real-time simulation among multiple nodes.

[0065] When the number of computation steps corresponding to the completion of the current computation task by the first node received by the comparison hardware is consistent with the number of computation steps corresponding to the current clock signal, in order to make the software and hardware mutually reference each other, the embodiment of the present invention performs iterative verification of the number of computation steps, that is, the computation task data of the hardware executing the next step is sent back to the simulation software running on the first node, so that the simulation software can further verify the number of computation steps relative to the hardware. The computation task data sent back by the hardware to the simulation software should include the number of computation steps.

[0066] Step S204: Compare the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node with the number of calculation steps when the first node executes the next calculation task.

[0067] Step S205: When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is consistent with the number of calculation steps when the first node completes the next calculation task, it is determined that the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0068] When the hardware executes the next computational task data, the simulation software on the first node connected to the hardware should also execute the same number of computational steps as the hardware.

[0069] When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is inconsistent with the number of calculation steps when the first node completes the next calculation task, it is determined that the number of calculation steps of the first node is not synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node. The simulation program running by the simulation software is terminated and an error is reported. The next operation is not performed to avoid the accumulation of system clock error, thereby improving the performance of electromagnetic transient joint real-time simulation between multiple nodes.

[0070] Step S3: When the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the first node continues to execute the next calculation task and updates the current number of calculation steps of the first node by 1, and goes to step S2, until the calculation tasks of all calculation steps of the first node are completed.

[0071] In order to achieve software-hardware clock synchronization among all nodes in the simulation system, after synchronizing the clock for all computation steps of each node, it is necessary to synchronize the clock for all computation steps of the next node, until all computation steps of all nodes in the simulation system are completed and the clocks are synchronized.

[0072] The above steps can complete the software-hardware clock synchronization between all nodes in the simulation system. In real-time multi-node co-simulation, the software between multiple nodes should also be clock synchronized.

[0073] Therefore, in some embodiments, the method further includes steps S401 to S404.

[0074] Step S401: When the first node completes the current calculation task, it transmits the calculation task data to the second node connected to the first node. The calculation task data includes the number of calculation steps corresponding to the current calculation task.

[0075] Step S402: According to the preset verification period, periodically compare whether the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is consistent with the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the second node.

[0076] It should be noted that during multi-node co-simulation, the clock signals for the computation steps of each node experience delays, and verifying each step also affects simulation efficiency. Therefore, it is necessary to verify the computation steps between two nodes at regular intervals. Thus, the computation steps between two nodes need to be verified periodically according to a preset verification cycle. The verification cycle can be 100 steps, 1000 steps, etc., and is not limited here.

[0077] The verification period can be determined based on the crystal oscillator frequency f in the computing host of the first node. j To determine, i.e., the verification period n = f j / 100.

[0078] Step S403: When the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is consistent with the number of calculation steps received by the second node corresponding to the completion of the current calculation task, the second node executes the next calculation task.

[0079] Step S404: When the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is inconsistent with the number of calculation steps corresponding to the completion of the current calculation task by the second node, the simulation program run by the simulation software is terminated.

[0080] The following example illustrates the real-time simulation multi-node software-hardware clock synchronization method provided in this invention. The example includes:

[0081] 1) Determine the signal T received by the BeiDou timing server x The reference clock signal for calculating the x-th step is obtained by adjusting the reference clock signal T. x After amplification, the reference clock signal T for the x-th calculation step is... x FPGA timing cards are assigned to different nodes, where the x-th step clock signal of the FPGA timing card of the j-th node is t. jx (x, j = 1, 2, ...).

[0082] 2) The FPGA timing card receives the reference clock signal T x By calibrating its own clock signal, it can achieve time synchronization with the time service server.

[0083] 3) After starting the multi-node co-simulation task, the simulation software completes the m-th calculation task on the j-th node, and then transmits the calculation results to the external hardware device connected to node j and other nodes. The transmitted data is denoted as D. ojm (m, j = 1, 2, ...).

[0084] 4) The external hardware device connected to the j-th node receives data D ojm Then, with its own clock signal t jx If the number of calculation steps x equals the number of calculation steps m, then the hardware device executes the next calculation task and uses a sampling device to collect the hardware device's calculation task data D. ijx+1 The data is transmitted to the simulation software running on the j-th node; if x ≠ m, the simulation program is terminated.

[0085] 5) The simulation software on the j-th node receives the computational task data D transmitted by the hardware device connected to node j. ijx+1 Then, the data D executed by node j. ojm If x+1 = m+1, the simulation software continues the next calculation task at the j-th node and transmits the calculation result to the external hardware device connected to this node and other nodes. The transmitted data is denoted as D. ojm+1 If x+1≠m+1, then terminate the simulation program; if the program terminates, then stop the operation.

[0086] 6) Perform software step count comparison and verification every 1000 steps: After the simulation software completes the y-th step calculation task at the j-th node, the transmitted data D oky Give the data to the k-th node. The k-th node then passes the received data D. oky Data D transmitted between the simulation software and the node k after the (m-1)th step of the calculation task is completed. ojm-1 If y-1 = m-1, the simulation software continues the next calculation task at the k-th node; if y-1 ≠ m-1, the simulation program terminates.

[0087] It should be noted that this invention ensures the consistency of the simulation system's clock signal by synchronizing the clock signals of the calculation steps of the hardware connected to each node in the simulation software. By verifying the calculation steps between the hardware and software of each node, the software-hardware time step consistency is ensured, eliminating the need for a clock synchronization mechanism between software, reducing the difficulty of clock synchronization in the simulation system, avoiding the accumulation of system clock errors, and thus improving the joint real-time simulation performance between multiple nodes.

[0088] Based on the same inventive concept, this application also provides a real-time simulation multi-node software-hardware clock synchronization device for implementing the real-time simulation multi-node software-hardware clock synchronization method mentioned above.

[0089] The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more real-time simulation multi-node software-hardware clock synchronization device embodiments provided below can be found in the limitations of the real-time simulation multi-node software-hardware clock synchronization method above, and will not be repeated here.

[0090] As shown in Figure 3, this embodiment of the invention also provides a real-time simulation software-hardware clock synchronization device between multiple nodes, including:

[0091] The timing synchronization module 100 is used to synchronize the clock signals of each calculation step of the hardware connected to each node in the simulation software in response to the clock synchronization request of the real-time simulation task.

[0092] The synchronization verification module 200 is used to compare the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software.

[0093] The verification execution module 300 is used to verify whether the first node continues to execute the next calculation task when the calculation step count of the first node is synchronized with the calculation step count corresponding to the clock signal of the hardware connected to the first node, and updates the current calculation step count of the first node by 1. The module then compares whether the calculation step count of the first node is synchronized with the calculation step count corresponding to the clock signal of the hardware connected to the first node, until the calculation tasks of all calculation steps of the first node are completed.

[0094] In some embodiments, the timing synchronization module 100 is used to allocate a reference clock signal to each calculation step of the hardware connected to each node in the simulation software based on the timing server; and to perform clock calibration on the clock signal of each calculation step of the hardware connected to each node according to the reference clock signal, so that the clock signal of each calculation step of the hardware is synchronized with the reference clock signal allocated to each calculation step of the hardware.

[0095] In some embodiments, the verification and synchronization module 200 is used to transmit the computation task data to the hardware connected to the first node when the first node completes the current computation task, wherein the computation task data includes the number of computation steps corresponding to the current computation task; compare whether the number of computation steps corresponding to the completion of the current computation task by the first node received by the hardware is consistent with the number of computation steps corresponding to the current clock signal; when the number of computation steps corresponding to the completion of the current computation task by the first node received by the hardware is consistent with the number of computation steps corresponding to the current clock signal, the hardware executes the next computation task and sends the next computation task data back to the simulation software running on the first node; compare whether the number of computation steps corresponding to the next computation task data received by the simulation software on the first node is consistent with the number of computation steps when the first node executes the next computation task; when the number of computation steps corresponding to the next computation task data received by the simulation software on the first node is consistent with the number of computation steps when the first node completes the next computation task, it is determined that the number of computation steps of the first node is synchronized with the number of computation steps corresponding to the clock signal of the hardware connected to the first node.

[0096] In some embodiments, the verification synchronization module 200 is further configured to terminate the simulation program run by the simulation software when the number of calculation steps corresponding to the completion of the current calculation task by the first node received by the comparison hardware is inconsistent with the number of calculation steps corresponding to the current clock signal.

[0097] In some embodiments, the verification synchronization module 200 is further configured to terminate the simulation program run by the simulation software when the number of calculation steps of the first node is not synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

[0098] In some embodiments, the apparatus further includes:

[0099] The data transmission module is used to transmit the computation task data to the second node connected to the first node when the first node completes the current computation task. The computation task data includes the number of computation steps corresponding to the current computation task.

[0100] The node verification module is used to periodically compare the number of calculation steps received by the second node to complete the current calculation task with the number of calculation steps received by the first node to complete the current calculation task according to a preset verification period.

[0101] The first execution module is used to execute the next calculation task when the number of calculation steps received by the second node to complete the current calculation task of the first node is consistent with the number of calculation steps received by the second node to complete the current calculation task.

[0102] The second execution module is used to terminate the simulation program running by the simulation software when the number of calculation steps received by the second node to complete the current calculation task corresponding to the completion of the current calculation task by the first node is inconsistent with the number of calculation steps received by the second node to complete the current calculation task.

[0103] As shown in Figure 4, this embodiment of the invention also provides an electronic device. The electronic device 10 includes a memory 20 and a processor 30. The memory 20 stores a computer program. When the computer program is executed by the processor 30, the processor 30 performs the steps of the real-time simulation software-hardware clock synchronization method between multiple nodes as described in any of the above embodiments.

[0104] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed, implements the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in any of the above embodiments.

[0105] This invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, wherein when the program instructions are executed by a computer, the computer performs the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in any of the above embodiments.

[0106] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, electronic devices, computer storage media, and computer program products described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0107] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0108] In the several embodiments provided by this invention, it will be understood that each block in the flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the figures. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved.

[0109] In the embodiments provided by this invention, it should be understood that the disclosed systems, electronic devices, computer storage media, computer program products, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0110] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0112] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the methods described in the various embodiments of this invention through a computer device (which may be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0113] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A real-time simulation method for software-hardware clock synchronization between multiple nodes, characterized in that, include: In response to the clock synchronization request of the real-time simulation task, the clock signals of each calculation step of the hardware connected to each node in the simulation software are synchronized. For each node in the simulation software, compare whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node; When the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the first node continues to execute the next calculation task, updates the current number of calculation steps of the first node by 1, and proceeds to the step of comparing whether the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, until the calculation task of all calculation steps of the first node is completed.

2. The real-time simulation multi-node software-hardware clock synchronization method according to claim 1, characterized in that, The step of synchronizing the clock signals of each calculation step of the hardware connected to each node in the simulation software includes: The time synchronization server allocates a reference clock signal to each calculation step of the hardware connected to each node in the simulation software. Based on the reference clock signals, the clock signals of each calculation step of the hardware connected to each node are clock-calibrated to synchronize the clock signals of each calculation step of the hardware with the reference clock signals allocated to each calculation step of the hardware.

3. The real-time simulation multi-node software-hardware clock synchronization method according to claim 1, characterized in that, The step of comparing the number of computation steps of the first node with the number of computation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software includes: When the first node completes the current computing task, it transmits the computing task data to the hardware connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task; Compare whether the number of calculation steps corresponding to the completion of the current calculation task by the first node received by the hardware is consistent with the number of calculation steps corresponding to the current clock signal; When the number of calculation steps corresponding to the completion of the current calculation task by the first node received by the hardware is consistent with the number of calculation steps corresponding to the current clock signal, the hardware executes the next calculation task and sends the data of the next calculation task back to the simulation software running on the first node. Compare the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node with the number of calculation steps when the first node executes the next calculation task; When the number of calculation steps corresponding to the next calculation task data received by the simulation software on the first node is consistent with the number of calculation steps when the first node completes the next calculation task, it is determined that the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node.

4. The real-time simulation multi-node software-hardware clock synchronization method according to claim 3, characterized in that, After the step of comparing whether the number of computation steps corresponding to the current computation task received by the hardware is consistent with the number of computation steps corresponding to the current clock signal, the method further includes: If the number of computation steps corresponding to the completion of the current computation task by the first node received by the hardware is inconsistent with the number of computation steps corresponding to the current clock signal, then the simulation program run by the simulation software is terminated.

5. The real-time simulation software-hardware clock synchronization method among multiple nodes according to claim 1, characterized in that, After the step of comparing the number of computation steps of the first node with the number of computation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software, the method further includes: If the number of calculation steps of the first node is not synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the simulation program run by the simulation software is terminated.

6. The real-time simulation multi-node software-hardware clock synchronization method according to claim 1, characterized in that, The method further includes: When the first node completes the current computing task, it transmits the computing task data to the second node connected to the first node, wherein the computing task data includes the number of computing steps corresponding to the current computing task; According to a preset verification period, the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is periodically compared with the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the second node. When the number of calculation steps received by the second node corresponding to the completion of the current calculation task by the first node is consistent with the number of calculation steps received by the second node corresponding to the completion of the current calculation task, the second node executes the next calculation task. If the number of computation steps received by the second node corresponding to the completion of the current computation task by the first node is inconsistent with the number of computation steps received by the second node corresponding to the completion of the current computation task by the second node, then the simulation program running by the simulation software is terminated.

7. A real-time simulation software-hardware clock synchronization device for multiple nodes, characterized in that, include: The timing synchronization module is used to respond to clock synchronization requests for real-time simulation tasks and synchronize the clock signals of each calculation step of the hardware connected to each node in the simulation software. The synchronization verification module is used to compare the number of calculation steps of the first node with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node for each node in the simulation software. The verification execution module is used to ensure that when the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, the first node continues to execute the next calculation task and updates the current number of calculation steps of the first node by 1. The module then performs a comparison to see if the number of calculation steps of the first node is synchronized with the number of calculation steps corresponding to the clock signal of the hardware connected to the first node, until the calculation tasks of all calculation steps of the first node are completed.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the steps of the real-time simulation software-hardware clock synchronization method for multiple nodes as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, wherein when the program instructions are executed by a computer, the computer performs the steps of the real-time simulation multi-node software-hardware clock synchronization method as described in any one of claims 1 to 6.

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