Signal generation device

Abstract

A signal generation device comprises: a switching signal generator that generates a switching signal for turning a switching element that is included in a non-insulated DC / DC converter on or off, the DC converter operating in a switch mode; and a trigger generator that generates a trigger signal indicating the timing at which to measure the electrical characteristics of an inductor included in the DC / DC converter. The switching signal generator includes a phase compensator that determines the pulse width of the switching signal so that the output voltage of the DC / DC converter approaches a target voltage; and a first generation circuit that generates the switching signal having the pulse width. The trigger generator outputs the trigger signal when the pulse width satisfies a preset trigger condition.

Description

signal generator

[0001] The present disclosure relates to a signal generating device.

[0002] A DC / DC converter that converts an input voltage into a predetermined output voltage is known (see, for example, Patent Document 1). The DC / DC converter described in Patent Document 1 includes a first switch and a second switch connected in series between an input terminal to which the input voltage is applied and a reference power supply voltage, an inductor provided between a connection node of the first switch and the second switch and an output terminal from which an output voltage is output, and a control unit that controls the switching of the first switch and the second switch alternately at a predetermined switching period in accordance with an error between a target voltage and the output voltage.

[0003] JP 2010-273446 A

[0004] In the DC / DC converter described in Patent Document 1, the pulse width of the gate drive signal (switching signal) fluctuates depending on the load. Even when the load is constant, the pulse width may vary. Therefore, even if the electrical characteristics of the inductor are measured at the switching cycle, the measured electrical characteristics may not be sufficiently reproducible.

[0005] The present disclosure describes a signal generator capable of measuring the electrical properties of inductors with high reproducibility.

[0006] A signal generating device according to one aspect of the present disclosure includes: a switching signal generator that generates a switching signal that turns on and off a switching element included in a non-isolated DC / DC converter operating in switch mode; and a trigger generator that generates a trigger signal that indicates timing for measuring electrical characteristics of an inductor included in the DC / DC converter. The switching signal generator includes a phase compensator that determines a pulse width of the switching signal so that the output voltage of the DC / DC converter approaches a target voltage, and a first generating circuit that generates a switching signal having a pulse width. The trigger generator outputs the trigger signal when the pulse width satisfies a preset trigger condition.

[0007] In this signal generator, a trigger signal is output when the pulse width of the switching signal satisfies the trigger condition. Therefore, even if the pulse width of the switching signal varies, the electrical characteristics of the inductor are measured at a pulse width that satisfies the trigger condition. This makes it possible to measure the electrical characteristics of the inductor with high reproducibility.

[0008] The trigger generator may include a setting circuit that sets a pulse width setting value, a trigger detector that determines whether the pulse width satisfies a trigger condition, and a second generation circuit that generates a trigger signal in response to the determination that the pulse width satisfies the trigger condition. The trigger condition may include a range condition that the pulse width falls within a predetermined detection range that includes the setting value. In this case, the trigger signal is output when the pulse width falls within the predetermined detection range that includes the setting value. In other words, since the measurement timing is determined by the magnitude of the pulse width, it is possible to measure the electrical characteristics of the inductor with high reproducibility.

[0009] The trigger generator may further include a storage device that stores the maximum and minimum values ​​of the difference between each pulse width of successive switching signals and a preset value. The trigger condition may further include a transition condition in which, if a preset hysteresis width is a positive value, the maximum value stored in the storage device is greater than the hysteresis width, and, if the hysteresis width is a negative value, the minimum value stored in the storage device is smaller than the hysteresis width. With this configuration, if the hysteresis width is a positive value, the trigger signal is output when the maximum value exceeds the hysteresis width and the subsequent pulse width falls within the detection range. If the hysteresis width is a negative value, the trigger signal is output when the minimum value falls below the hysteresis width and the subsequent pulse width falls within the detection range. In other words, the measurement timing is determined by the direction (increase or decrease) of the pulse width transition and the magnitude of the pulse width. This enables measurement of the electrical characteristics of an inductor with higher reproducibility.

[0010] The storage device may reset the maximum and minimum values ​​in response to the output of the trigger signal. In this case, the maximum and minimum values ​​are reset each time the trigger condition is satisfied, making it possible to accurately determine whether the pulse width satisfies the trigger condition. This makes it possible to measure the electrical characteristics of the inductor with higher reproducibility.

[0011] The setting circuit may set the moving average value of the pulse width as the set value. In this case, a trigger signal is output when the pulse width falls within a detection range that includes the moving average value. For example, when the load is constant, the pulse width of the switching signal may vary around the moving average value. Therefore, by setting the moving average value as the set value, the static electrical characteristics of the inductor can be measured.

[0012] The setting circuit may set a value between the moving maximum and minimum values ​​of the pulse width as the set value. In this case, a trigger signal is output when the pulse width falls within a detection range that includes values ​​between the moving maximum and minimum values. For example, when the load fluctuates, the pulse width of the switching signal changes significantly. Therefore, if the moving average value of the pulse width is used as the set value, the pulse width may not fall within the detection range, making it impossible to measure the electrical characteristics of the inductor. In contrast, when a value between the moving maximum and minimum values ​​of the pulse width is set as the set value, the pulse width may fall within the detection range even if the pulse width changes significantly. Therefore, it is possible to measure the electrical characteristics of the inductor when the load fluctuates.

[0013] The setting circuit may include a selection circuit that selects a set value from among values ​​including a moving average value of the pulse width and a value between the moving maximum and minimum values ​​of the pulse width. In this case, the set value can be selected according to the measurement conditions, thereby improving measurement accuracy.

[0014] According to the present disclosure, it is possible to measure the electrical characteristics of an inductor with high reproducibility.

[0015] FIG. 1 is a circuit diagram showing an example of a DC / DC converter to which a signal generating device according to an embodiment is applied. FIG. 2 is a diagram showing an example of the configuration of a PWM (Pulse Width Modulation) controller shown in FIG. 1. FIG. 3 is a diagram showing an example of the configuration of a trigger generator shown in FIG. 2. FIG. 4 is a diagram showing changes over time in a current flowing through an inductor and a voltage between the terminals of the inductor shown in FIG. 1. FIG. 5 is a diagram for explaining variations in current and voltage when the load is constant. FIG. 6 is a diagram for explaining an example of generation of a trigger signal when the load is constant. FIG. 7 is a diagram showing changes in a switching signal and a current when the load fluctuates. FIG. 8 is a diagram for explaining an example of generation of a trigger signal when the load suddenly increases as shown in FIG. 7. FIG. 9 is a diagram for explaining an example of generation of a trigger signal when the load suddenly decreases as shown in FIG. 7. FIG. 10 is a circuit diagram showing another example of a DC / DC converter to which a signal generating device according to an embodiment is applied. FIG. 11 is a circuit diagram showing yet another example of a DC / DC converter to which a signal generating device according to an embodiment is applied.

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0017] An example of a DC / DC converter to which a signal generating device according to an embodiment is applied will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of a DC / DC converter to which a signal generating device according to an embodiment is applied.

[0018] The DC / DC converter 1 shown in FIG. 1 is a device that converts an input voltage Vin, which is a DC voltage, into an output voltage Vout, which is also a DC voltage. The DC / DC converter 1 is a non-isolated DC / DC converter that operates in switch mode. The DC / DC converter 1 has an input terminal T1, an input terminal T2, an output terminal T3, an output terminal T4, an input voltage line Lin, and a reference voltage line Lref. The input terminal T2 and the output terminal T4 are connected to the reference voltage line Lref, which supplies a reference voltage. The reference voltage is, for example, a ground voltage (0 V). The input terminal T1 receives the input voltage Vin. The input terminal T1 is connected to the input voltage line Lin, which also supplies the input voltage Vin. The output terminal T3 outputs the output voltage Vout. A load (not shown) is connected to the output terminals T3 and T4.

[0019] The DC / DC converter 1 includes, as circuit elements, a capacitor 11, a switching element 12, a switching element 13, an inverter 14, an inductor 15, a capacitor 16, and a PWM controller 17 (signal generating device).

[0020] The capacitor 11 is an input capacitor. The capacitor 11 is provided between the input voltage line Lin and the reference voltage line Lref. Specifically, one end of the capacitor 11 is connected to the input voltage line Lin, and the other end of the capacitor 11 is connected to the reference voltage line Lref.

[0021] The switching element 12 and the switching element 13 are connected in series between the input voltage line Lin and the reference voltage line Lref. Each switching element is a circuit element that can switch the electrical connection state between its two ends between a conductive state (ON state) and a cut-off state (OFF state). Examples of switching elements include metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). In this embodiment, N-channel MOSFETs are used as the switching elements 12 and 13.

[0022] The drain of the switching element 12 is connected to the input voltage line Lin. The source of the switching element 12 and the drain of the switching element 13 are connected to each other at a connection point Pc and to an output terminal T3 via an inductor 15. The source of the switching element 13 is connected to a reference voltage line Lref. A switching signal PWM_H is supplied to the gate of the switching element 12. The switching element 12 is switched between an ON state and an OFF state by the switching signal PWM_H. A switching signal PWM_L is supplied to the gate of the switching element 13. The switching element 13 is switched between an ON state and an OFF state by the switching signal PWM_L.

[0023] The switching signal PWM_H and the switching signal PWM_L are complementary signals having opposite polarities to each other. In this embodiment, the switching signal PWM_H is output from the PWM controller 17, and the switching signal PWM_L is generated by the inverter 14 inverting the switching signal PWM_H.

[0024] The inductor 15 is an output inductor whose electrical characteristics are to be measured. The inductor 15 is provided between the connection point Pc and the output terminal T3. Specifically, one end of the inductor 15 is connected to the connection point Pc, and the other end of the inductor 15 is connected to the output terminal T3. The capacitor 16 is an output capacitor. The capacitor 16 is provided between the output terminal T3 and the output terminal T4. Specifically, one end of the capacitor 16 is connected to the output terminal T3, and the other end of the capacitor 16 is connected to the output terminal T4 (reference voltage line Lref). The inductor 15 and the capacitor 16 form a filter circuit.

[0025] The PWM controller 17 is a circuit that uses PWM control to turn on and off the switching elements 12 and 13. Based on the output voltage Vout, the PWM controller 17 generates a switching signal PWM_H for alternately turning on and off the switching elements 12 and 13, and a trigger signal TG that indicates the timing for measuring the electrical characteristics of the inductor 15. Details of the PWM controller 17 will be described later.

[0026] The measuring device 2 is a device that measures electrical characteristics. An example of the measuring device 2 is an oscilloscope. The measuring device 2 has input ports 2a, 2b, and 2c. A current probe 3 is connected to the input port 2a. The current probe 3 is provided to measure the current IL flowing through the inductor 15. The current probe 3 is provided, for example, on the wiring connecting the connection point Pc and one end of the inductor 15. A differential probe 4 is connected to the input port 2b. The differential probe 4 is provided to measure the voltage VL between both terminals of the inductor 15.

[0027] A trigger signal TG is input to the input port 2c from the PWM controller 17. In response to the rising edge of the trigger signal TG, the measurement device 2 measures the current IL via the current probe 3 and measures the voltage VL via the differential probe 4. In other words, the measurement device 2 captures the waveforms of the current IL and the voltage VL in response to the rising edge of the trigger signal TG.

[0028] Next, the PWM controller 17 will be described in detail with reference to Figures 2 and 3. Figure 2 is a diagram showing an example of the configuration of the PWM controller shown in Figure 1. Figure 3 is a diagram showing an example of the configuration of the trigger generator shown in Figure 2.

[0029] 2, the PWM controller 17 has an input terminal 17a, an output terminal 17b, and an output terminal 17c. A controlled node is connected to the input terminal 17a. In this embodiment, the controlled node is the output terminal T3. Therefore, the output voltage Vout is input to the input terminal 17a. The output terminal 17b is connected to the gate of the switching element 12 and the input terminal of the inverter 14. The output terminal 17b outputs a switching signal PWM_H. The output terminal 17c is connected to the input port 2c. The output terminal 17c outputs a trigger signal TG.

[0030] The PWM controller 17 includes an oscillator 21 , a switching signal generator 22 , and a trigger generator 23 .

[0031] The oscillator 21 is a circuit that generates clock signals CL1 and CL2. The clock signal CL1 is supplied to the switching signal generator 22 and the trigger generator 23 and is used as a control clock signal. The clock signal CL2 is supplied to the switching signal generator 22 and is used for sampling the output voltage Vout. The frequency of the clock signal CL1 may be different from or the same as the frequency of the clock signal CL2. The oscillator 21 includes a master oscillator 31, a frequency divider 32, and a frequency divider 33.

[0032] The original oscillator 31 is a circuit that generates an original clock signal CL0. The original oscillator 31 is composed of a voltage controlled oscillator (VCO) and a phase locked loop (PLL). The frequency divider 32 is a circuit that outputs a clock signal CL1 by dividing the original clock signal CL0. The frequency divider 32 is configured so that the user can set the frequency division value. The frequency divider 32 divides the original clock signal CL0 by a frequency division value that is preset by the user.

[0033] The frequency divider 33 is a circuit that outputs a clock signal CL2 by dividing the frequency of the original clock signal CL0. The frequency divider 33 is configured so that the user can set the sampling period of the A / D converter 42 (described later). The frequency divider 33 generates a clock signal CL2 having a frequency that is the reciprocal of the sampling period preset by the user. In other words, the frequency divider 33 divides the frequency of the original clock signal CL0 by a division value obtained by multiplying the frequency of the original clock signal CL0 by the sampling period.

[0034] The switching signal generator 22 is a circuit that generates the switching signal PWM_H and includes a counter 41, an A / D converter 42, a subtractor 43, a phase compensator 44, a comparator 45, a comparator 46, and a flip-flop 47 (first generation circuit).

[0035] The counter 41 is a circuit that counts clock pulses of the clock signal CL1. The clock signal CL1 is supplied to a clock terminal of the counter 41. The counter 41 increments a count value C1 by one in synchronization with, for example, a rising edge of the clock signal CL1. The counter 41 outputs the count value C1 to the comparators 45 and 46. A start signal Str, which will be described later, is input to a reset terminal of the counter 41. When the counter 41 receives a high-level start signal Str from the comparator 45, it resets the count value C1 to 0.

[0036] The A / D converter 42 is a circuit that converts the output voltage Vout (analog value) input to the input terminal 17a into a digital value Dout. The A / D converter 42 samples the output voltage Vout at a sampling period in synchronization with the clock signal CL2, quantizes the sampled value, and normalizes (encodes) the quantized value to convert the output voltage Vout into the digital value Dout.

[0037] The subtractor 43 is a circuit that calculates the error Er between the target value and the digital value Dout. The target value can be set in advance by the user. The target value is a value that indicates a target voltage for the output voltage Vout. The subtractor 43 subtracts the digital value Dout from the target value and outputs the subtraction result to the phase compensator 44 as the error Er.

[0038] The phase compensator 44 is a circuit that determines the pulse width W of the switching signal PWM_H so that the output voltage Vout approaches the target voltage of the output voltage Vout. The pulse width W is the high-level period of the switching signal PWM_H and is expressed here as the number of clock signals CL1 corresponding to the high-level period of the switching signal PWM_H. Upon receiving the error Er from the subtractor 43, the phase compensator 44 determines the pulse width W based on the error Er. For example, the phase compensator 44 increases the pulse width W as the error Er increases and decreases the pulse width W as the error Er decreases. A known phase compensator may be used as the phase compensator 44, and detailed description thereof will be omitted. The phase compensator 44 outputs the pulse width W to the comparator 46 and the trigger generator 23.

[0039] The comparator 45 is a circuit that compares the count value C1 with the switching period Tcyc. The switching period Tcyc can be preset by the user. The switching period Tcyc is the duration of one cycle of the switching signal PWM_H, and is expressed here as the number of clock signals CL1 corresponding to one cycle of the switching signal PWM_H. The comparator 45 outputs a high-level start signal Str when the count value C1 matches the switching period Tcyc. The comparator 45 outputs the start signal Str to the trigger generator 23, the counter 41, and the flip-flop 47. Note that the comparator 45 outputs a low-level start signal Str when the count value C1 does not match the switching period Tcyc.

[0040] The comparator 46 is a circuit that compares the count value C1 with the pulse width W. When the count value C1 matches the pulse width W, the comparator 46 outputs a high-level reset signal Rset1. The comparator 46 outputs the reset signal Rset1 to the flip-flop 47. When the count value C1 does not match the pulse width W, the comparator 46 outputs a low-level reset signal Rset1.

[0041] The flip-flop 47 is a circuit that generates a switching signal PWM_H having a pulse width W. A clock signal CL1 is supplied to a clock terminal of the flip-flop 47. A start signal Str is input to a set terminal of the flip-flop 47. A reset signal Rset1 is input to a reset terminal of the flip-flop 47.

[0042] Therefore, the flip-flop 47 outputs a high level from the time when a high-level start signal Str is input to its set terminal until a high-level reset signal Rset1 is input to its reset terminal (i.e., for a period corresponding to the pulse width W), and outputs a low level from the time when a high-level reset signal Rset1 is input to its reset terminal until the next high-level start signal Str is input to its set terminal. This generates the switching signal PWM_H. The flip-flop 47 outputs the switching signal PWM_H to the outside of the PWM controller 17 via the output terminal 17b.

[0043] The trigger generator 23 is a circuit that generates a trigger signal TG. The trigger generator 23 outputs the trigger signal TG when the pulse width W satisfies a preset trigger condition.

[0044] 3, the trigger generator 23 has input terminals 23a, 23b, 23c, and an output terminal 23d. A start signal Str is input to the input terminal 23a. A pulse width W is input to the input terminal 23b. A clock signal CL1 is input to the input terminal 23c. The output terminal 23d outputs a trigger signal TG. The trigger generator 23 includes a setting circuit 51, a subtractor 52, a storage device 53, a trigger detector 54, an AND circuit 55, a counter 56, a comparator 57, and a flip-flop 58 (second generation circuit).

[0045] The setting circuit 51 is a circuit that sets a set value Wc of the pulse width W. The set value Wc is a value included in a detection range Rd (see FIG. 6) of the pulse width W. In this embodiment, the set value Wc is the median value of the detection range Rd. The setting circuit 51 includes a shift register 61, an arithmetic unit 62, an arithmetic unit 63, and a multiplexer 64 (selection circuit).

[0046] The shift register 61 is a circuit that stores N consecutive pulse widths W (e.g., 30 pulse widths W). The shift register 61 stores the pulse widths W for the most recent N switching periods Tcyc. The input terminal of the shift register 61 is connected to the input terminal 23b. The shift register 61 shifts the stored pulse widths W in synchronization with the start signal Str, and also takes in a new pulse width W input to the input terminal of the shift register 61. Note that, as the shift register 61 shifts, the oldest pulse width W of the N pulse widths W stored in the shift register 61 is discarded.

[0047] The calculator 62 is a circuit that calculates a moving average value V1 of the pulse width W. The calculator 62 calculates the average value (moving average value V1) of the N pulse widths W stored in the shift register 61, and outputs the moving average value V1 to the multiplexer 64.

[0048] The calculator 63 is a circuit that calculates a value V2 between the moving maximum and moving minimum values ​​of the pulse width W. The value V2 is a value within a range with the moving maximum value as the maximum value and the moving minimum value as the minimum value. The calculator 63 extracts the maximum value (moving maximum value) and the minimum value (moving minimum value) from the N pulse widths W stored in the shift register 61, and calculates the difference D by subtracting the moving minimum value from the moving maximum value. The calculator 63 calculates the value V2 by multiplying the difference D by a coefficient α and adding the result to the moving minimum value. The coefficient α is an arbitrary value within a range with 0 as the minimum value and 1 as the maximum value, and can be preset by the user. The calculator 63 outputs the value V2 to the multiplexer 64.

[0049] The multiplexer 64 is a circuit that selects the set value Wc from the moving average value V1, value V2, and immediate value V3. The multiplexer 64 outputs the value selected from the moving average value V1, value V2, and immediate value V3 as the set value Wc in response to a selection signal. A selection mode indicating which value of the moving average value V1, value V2, and immediate value V3 to use is selected by the user, and a selection signal is supplied to the multiplexer 64 in response to the selection mode selected by the user. The immediate value V3 is an arbitrary value that is directly set by the user. The multiplexer 64 outputs the set value Wc to the subtractor 52 and the trigger detector 54.

[0050] The subtractor 52 is a circuit that calculates the difference between the pulse width W and the set value Wc. The subtractor 52 subtracts the set value Wc from the pulse width W and outputs the result of the subtraction to the storage device 53.

[0051] The storage device 53 is a circuit (memory) that temporarily stores the maximum and minimum values ​​of the subtraction result. The storage device 53 receives the subtraction result output from the subtractor 52 in synchronization with the start signal Str and compares it with the maximum and minimum values ​​stored in the storage device 53. If the subtraction result is greater than the maximum value stored in the storage device 53, the storage device 53 updates the maximum value to the subtraction result. If the subtraction result is smaller than the minimum value stored in the storage device 53, the storage device 53 updates the minimum value to the subtraction result. In other words, the storage device 53 stores the maximum and minimum values ​​of the difference between each of the pulse widths W of the successive switching signals PWM_H and the set value Wc.

[0052] The storage device 53 is initialized by the set signal Set output from the AND circuit 55. That is, the maximum and minimum values ​​stored in the storage device 53 are reset by the set signal Set at a high level.

[0053] The trigger detector 54 is a circuit that determines whether the pulse width W satisfies a trigger condition. The trigger condition includes a range condition and a transition condition. The range condition is a condition that the pulse width W falls within a predetermined detection range Rd. The detection range Rd is a range that includes the set value Wc. In this embodiment, the detection range Rd is a range in which the value obtained by adding the error width We (see FIG. 6) to the set value Wc is the maximum value, and the value obtained by subtracting the error width We from the set value Wc is the minimum value. The error width We is the error of the pulse width W that is allowable for measurement and is expressed here as the number of clock signals CL1. The error width We can be set in advance by the user.

[0054] The transition condition is such that when the hysteresis width Δ is a positive value, the maximum value stored in the storage device 53 is greater than the hysteresis width Δ, and when the hysteresis width Δ is a negative value, the minimum value stored in the storage device 53 is smaller than the hysteresis width Δ. The hysteresis width Δ is used to determine the transition direction (increase or decrease) of the pulse width W. The hysteresis width Δ is set so that the absolute value of the hysteresis width Δ is greater than the error width We. The hysteresis width Δ can be set in advance by the user.

[0055] When both the range condition and the transition condition are satisfied, the trigger detector 54 determines that the pulse width W satisfies the trigger condition and outputs a high-level detection signal Det. When at least one of the range condition and the transition condition is not satisfied, the trigger detector 54 determines that the pulse width W does not satisfy the trigger condition and outputs a low-level detection signal Det.

[0056] The AND circuit 55 generates a set signal Set. The AND circuit 55 calculates the logical product of the start signal Str and the detection signal Det and outputs the result of the calculation as a set signal Set. The AND circuit 55 outputs the set signal Set to the storage device 53, the counter 56, and the flip-flop 58.

[0057] The counter 56 is a circuit that counts clock pulses of the clock signal CL1. The clock signal CL1 is supplied to a clock terminal of the counter 56. The counter 56 increments a count value C2 by one in synchronization with, for example, a rising edge of the clock signal CL1. The counter 56 outputs the count value C2 to the comparator 57. A set signal Set is input to a reset terminal of the counter 56. When the counter 56 receives a high-level set signal Set from the comparator 57, it resets the count value C2 to 0.

[0058] The comparator 57 is a circuit that compares the count value C2 with the trigger pulse width. The trigger pulse width can be preset by the user. The trigger pulse width is the high-level period of the trigger signal TG, and is expressed here as the number of clock signals CL1 corresponding to the high-level period of the trigger signal TG. The comparator 57 outputs a high-level reset signal Rset2 when the count value C2 matches the trigger pulse width. The comparator 57 outputs the reset signal Rset2 to the flip-flop 58. Note that the comparator 57 outputs a low-level reset signal Rset2 when the count value C2 does not match the trigger pulse width.

[0059] The flip-flop 58 is a circuit that generates a trigger signal TG in response to a determination that the pulse width W satisfies the trigger condition. A clock signal CL1 is supplied to a clock terminal of the flip-flop 58. A set signal Set is input to a set terminal of the flip-flop 58. A reset signal Rset2 is input to a reset terminal of the flip-flop 58.

[0060] Therefore, flip-flop 58 outputs a high level from the time a high-level set signal Set is input to its set terminal until a high-level reset signal Rset2 is input to its reset terminal (i.e., for a period corresponding to the trigger pulse width), and outputs a low level from the time a high-level reset signal Rset2 is input to its reset terminal until the next high-level set signal Set is input to its set terminal. This generates a trigger signal TG having a trigger pulse width. Flip-flop 58 outputs the trigger signal TG to the outside of PWM controller 17 via output terminals 23d and 17c.

[0061] Next, an example of the operation of the PWM controller 17 will be described with reference to Figures 4 to 6. Figure 4 is a diagram showing the time changes of the current flowing through the inductor and the voltage between the terminals of the inductor shown in Figure 1. Figure 5 is a diagram for explaining the variations in current and voltage when the load is constant. Figure 6 is a diagram for explaining an example of the generation of a trigger signal when the load is constant.

[0062] 4, the switching cycle Tcyc includes a period Ton and a period Toff. The period Ton is a period during which the switching element 12 is in an on state and the switching element 13 is in an off state. The period Toff is a period during which the switching element 12 is in an off state and the switching element 13 is in an on state.

[0063] During period Ton, current IL (on-current Ion) flows from input terminal T1 to output terminal T3, passing through switching element 12 and inductor 15 in this order, and energy is stored in inductor 15. Voltage VL is a voltage obtained by subtracting output voltage Vout from input voltage Vin, and current IL increases over time. During period Toff, current IL (off-current Ioff) flows from output terminal T4 to output terminal T3, passing through switching element 13 and inductor 15 in this order, and energy stored in inductor 15 is released via switching element 13. Voltage VL is a voltage obtained by subtracting output voltage Vout from a reference voltage, and current IL decreases over time.

[0064] The input voltage Vin is converted into the output voltage Vout by alternating between the periods Ton and Toff. By adjusting the width of the period Ton (the pulse width W of the switching signal PWM_H), the ratio (duty ratio) between the periods Ton and Toff is adjusted, and the output voltage Vout is controlled to the target voltage. Therefore, even if the load is constant and stable, the pulse width W is not constant and may vary. Therefore, as shown in FIG. 5 , the waveforms of the current IL and the voltage VL may fluctuate with each switching cycle. In this state, measuring the current IL and the voltage VL of the inductor 15 may not be sufficiently reproducible. Therefore, it may be impossible to extract representative electrical characteristics normalized by the switching cycle Tcyc.

[0065] In contrast, in the PWM controller 17, the user sets the selection mode and appropriately sets the error width We and hysteresis width Δ to set the trigger condition. In the example shown in Fig. 6, the selection mode is set so that the moving average value V1 is used as the set value Wc, and the hysteresis width Δ is set to a positive value. In this case, the trigger condition is that the maximum value stored in the storage device 53 is greater than the hysteresis width Δ, and the pulse width W is included in a detection range Rd whose minimum value is the value obtained by subtracting the error width We from the moving average value V1 and whose maximum value is the value obtained by adding the error width We to the moving average value V1.

[0066] In other words, after the previous trigger signal TG was output, the pulse width W exceeded the value obtained by adding the hysteresis width Δ to the moving average value V1, and the subsequent pulse width W entered the detection range Rd, and the trigger signal TG was output in response to this. In the example shown in Fig. 6, the pulse width W exceeded the value obtained by adding the hysteresis width Δ to the moving average value V1 in the second switching period, and the pulse width W entered the detection range Rd in the sixth switching period. Therefore, the trigger condition is satisfied in the sixth switching period, so the trigger signal TG is output at this timing, and the current IL and voltage VL are measured.

[0067] Next, another example of the operation of the PWM controller 17 will be described with reference to Figs. 7 to 9. Fig. 7 is a diagram showing changes in the switching signal and current during load fluctuations. Fig. 8 is a diagram for explaining an example of the generation of a trigger signal during a sudden load increase shown in Fig. 7. Fig. 9 is a diagram for explaining an example of the generation of a trigger signal during a sudden load decrease shown in Fig. 7.

[0068] 7, when the load current Iload suddenly increases, the current IL increases by increasing the pulse width W (duty ratio) of the switching signal PWM_H. On the other hand, when the load current Iload suddenly decreases, the current IL decreases by decreasing the pulse width W (duty ratio) of the switching signal PWM_H. Therefore, the waveforms of the current IL and the voltage VL may vary for each switching period.

[0069] 8, when the load suddenly increases, the selection mode is set so that value V2 (= difference D × coefficient α + moving minimum value) is used as the set value Wc, and the hysteresis width Δ is set to a negative value. In this case, the trigger condition is that the minimum value stored in the storage device 53 is smaller than the hysteresis width Δ, and the pulse width W is included in the detection range Rd whose minimum value is the value obtained by subtracting the error width We from value V2 and whose maximum value is the value obtained by adding the error width We to value V2.

[0070] In other words, after the previous trigger signal TG is output, the pulse width W falls below the value obtained by adding the hysteresis width Δ to the value V2, and the subsequent pulse width W falls within the detection range Rd, and the trigger signal TG is output in response to this. In the example shown in Figure 8, the pulse width W in the first switching period falls below the value obtained by adding the hysteresis width Δ to the value V2, and the pulse width W falls within the detection range Rd in the seventh switching period. Therefore, the trigger condition is satisfied in the seventh switching period, so the trigger signal TG is output at this timing, and the current IL and voltage VL are measured.

[0071] 9, when the load suddenly decreases, the selection mode is set so that value V2 (= difference D × coefficient α + moving minimum value) is used as the set value Wc, and the hysteresis width Δ is set to a positive value. In this case, the trigger condition is that the maximum value stored in the storage device 53 is greater than the hysteresis width Δ, and the pulse width W is included in the detection range Rd whose minimum value is the value obtained by subtracting the error width We from value V2 and whose maximum value is the value obtained by adding the error width We to value V2.

[0072] In other words, after the previous trigger signal TG was output, the pulse width W exceeded the value obtained by adding the hysteresis width Δ to the value V2, and the subsequent pulse width W entered the detection range Rd, and in response, the trigger signal TG is output. In the example shown in Fig. 9, the pulse width W in the first switching period exceeded the value obtained by adding the hysteresis width Δ to the value V2, and in the seventh switching period, the pulse width W entered the detection range Rd. Therefore, the trigger condition is satisfied in the seventh switching period, so the trigger signal TG is output at this timing, and the current IL and voltage VL are measured.

[0073] In the PWM controller 17 described above, the trigger signal TG is output when the pulse width W of the switching signal PWM_H satisfies the trigger condition. Therefore, even if there is variation in the pulse width W of the switching signal PWM_H, the electrical characteristics of the inductor 15 are measured at the pulse width W that satisfies the trigger condition. This makes it possible to measure the electrical characteristics with high reproducibility.

[0074] When the pulse width W is within a detection range Rd including the set value Wc, a trigger signal TG is output. In other words, the measurement timing is determined by the size of the pulse width W, making it possible to measure electrical characteristics with high reproducibility.

[0075] Furthermore, when the hysteresis width Δ is a positive value, the trigger signal TG is output when the maximum value stored in the storage device 53 exceeds the hysteresis width Δ and the subsequent pulse width W falls within the detection range Rd. When the hysteresis width Δ is a negative value, the trigger signal TG is output when the minimum value stored in the storage device 53 falls below the hysteresis width Δ and the subsequent pulse width W falls within the detection range Rd. In other words, the measurement timing is determined by the transition direction (increase or decrease) of the pulse width W and the magnitude of the pulse width W. This makes it possible to measure electrical characteristics with higher reproducibility.

[0076] The storage device 53 resets the maximum and minimum values ​​in response to the output of the trigger signal TG. Therefore, each time the trigger condition is satisfied, the maximum and minimum values ​​of the storage device 53 are reset. This makes it possible to accurately determine whether the pulse width W satisfies the trigger condition. This makes it possible to measure electrical characteristics with higher reproducibility.

[0077] When the setting circuit 51 sets the moving average value V1 as the set value Wc, a trigger signal TG is output in response to the pulse width W being included in the detection range Rd that includes the moving average value V1. For example, when the load (load current) connected to the DC / DC converter 1 is constant, the pulse width W of the switching signal PWM_H may vary around the moving average value V1. Therefore, by setting the moving average value V1 as the set value Wc, the static electrical characteristics of the inductor 15 can be measured.

[0078] When the setting circuit 51 sets the value V2 as the set value Wc, a trigger signal TG is output in response to the pulse width W falling within the detection range Rd that includes the value V2. For example, when the load (load current) fluctuates, the pulse width W of the switching signal PWM_H changes significantly. Therefore, when the moving average value V1 is used as the set value Wc, the pulse width W may not fall within the detection range Rd. In this case, the trigger signal TG is not output, and it may become impossible to measure the electrical characteristics of the inductor 15. In contrast, when the value V2 is set as the set value Wc, even if the pulse width W changes significantly, the pulse width W can be included within the detection range Rd by appropriately setting the coefficient α. Therefore, it is possible to measure the electrical characteristics of the inductor 15 during load fluctuations.

[0079] The multiplexer 64 selects the set value Wc from among the moving average value V1, the value V2, and the immediate value V3. In this case, the set value Wc can be selected according to the measurement conditions, which makes it possible to improve the measurement accuracy.

[0080] The signal generating device according to the present disclosure is not limited to the above embodiment.

[0081] The trigger condition may not include a transition condition, and may include only a range condition. For example, when the load is constant, the trigger signal TG may be output when the pulse width W is within the detection range Rd, regardless of whether the pulse width W is transitioning in an increasing or decreasing direction over time.

[0082] The setting circuit 51 may not include the calculator 63 and the multiplexer 64. In this case, the setting circuit 51 sets the moving average value V1 as the set value Wc. The setting circuit 51 may not include the subtractor 52 and the multiplexer 64. In this case, the setting circuit 51 sets the value V2 as the set value Wc. The setting circuit 51 may set the direct value V3 set by the user as the set value Wc. In this case, the setting circuit 51 may not include the shift register 61, the calculator 62, the calculator 63, and the multiplexer 64.

[0083] The multiplexer 64 may be able to select the set value Wc from among values ​​including the moving average value V1 and the value V2. For example, the multiplexer 64 may be able to select either the moving average value V1 or the value V2 as the set value Wc. The multiplexer 64 may be able to select another value instead of the immediate value V3.

[0084] In the above embodiment, the DC / DC converter 1 is a non-insulated step-down DC / DC converter that operates in switch mode, but the DC / DC converter to which the PWM controller 17 can be applied may be any non-insulated DC / DC converter that operates in switch mode.

[0085] For example, the PWM controller 17 can also be applied to a DC / DC converter 1A shown in FIG. 10 . The DC / DC converter 1A is a non-isolated step-up DC / DC converter that operates in switch mode. The DC / DC converter 1A differs from the DC / DC converter 1 mainly in the connections of the switching element 12, the switching element 13, and the inductor 15. Specifically, one end of the inductor 15 is connected to the input terminal T1, and the other end of the inductor 15 is connected to the drain of the switching element 12 and the source of the switching element 13. The source of the switching element 12 is connected to a reference voltage line Lref. The drain of the switching element 13 is connected to the output terminal T3. Note that the inverter 14 and the PWM controller 17 are not shown in FIG. 10 .

[0086] The PWM controller 17 can also be applied to a DC / DC converter 1B shown in FIG. 11 . The DC / DC converter 1B is a non-isolated inverting DC / DC converter that operates in switch mode. The DC / DC converter 1B differs from the DC / DC converter 1 mainly in the connection of the switching element 13 and the inductor 15. Specifically, one end of the inductor 15 is connected to the connection point Pc, and the other end of the inductor 15 is connected to the reference voltage line Lref. The source of the switching element 13 is connected to the output terminal T3. Note that the inverter 14 and the PWM controller 17 are not shown in FIG. 11 .

[0087] The DC / DC converters 1, 1A, and 1B do not have to be synchronous DC / DC converters. For example, the DC / DC converters 1, 1A, and 1B may include a diode instead of the switching element 13. In this case, the diode is connected so that the cathode of the diode corresponds to the drain of the switching element 13 and the anode of the diode corresponds to the source of the switching element 13. The PWM controller 17 turns the switching element 12 on and off by PWM control.

[0088] 1, 1A, 1B... DC / DC converter, 12... switching element, 13... switching element, 15... inductor, 17... PWM controller (signal generating device), 22... switching signal generator, 23... trigger generator, 44... phase compensator, 47... flip-flop (first generating circuit), 51... setting circuit, 53... storage device, 54... trigger detector, 58... flip-flop (second generating circuit), 64... multiplexer (selection circuit), Pc... connection point, T3... output terminal.

Claims

1. A signal generating device comprising: a switching signal generator that generates a switching signal that turns on and off a switching element included in a non-isolated DC / DC converter that operates in switch mode; and a trigger generator that generates a trigger signal that indicates the timing to measure the electrical characteristics of an inductor included in the DC / DC converter, wherein the switching signal generator comprises: a phase compensator that determines the pulse width of the switching signal so that the output voltage of the DC / DC converter approaches a target voltage; and a first generating circuit that generates the switching signal having the pulse width, and wherein the trigger generator outputs the trigger signal when the pulse width satisfies a preset trigger condition.

2. A signal generating device according to claim 1, wherein the trigger generator comprises: a setting circuit that sets a set value for the pulse width; a trigger detector that determines whether the pulse width satisfies the trigger condition; and a second generating circuit that generates the trigger signal in response to the determination that the pulse width satisfies the trigger condition, and wherein the trigger condition includes a range condition that the pulse width falls within a predetermined detection range that includes the set value.

3. A signal generating device according to claim 2, wherein the trigger generator further comprises a storage device that stores maximum and minimum values ​​of the difference between each of the pulse widths of successive switching signals and the set value, and the trigger condition further includes a transition condition in which, when a preset hysteresis width is a positive value, the maximum value stored in the storage device is greater than the hysteresis width, and, when the hysteresis width is a negative value, the minimum value stored in the storage device is smaller than the hysteresis width.

4. The signal generating device according to claim 3, wherein the storage device resets the maximum value and the minimum value in response to the output of the trigger signal.

5. A signal generating device according to any one of claims 2 to 4, wherein the setting circuit sets the moving average value of the pulse width as the set value.

6. A signal generating device according to any one of claims 2 to 4, wherein the setting circuit sets the set value to a value between the maximum and minimum moving values ​​of the pulse width.

7. A signal generating device according to any one of claims 2 to 4, wherein the setting circuit includes a selection circuit that selects the setting value from among values ​​including a moving average value of the pulse width and a value between the moving maximum value and moving minimum value of the pulse width.

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