Etching method and etching device

Abstract

An etching method according to the present disclosure comprises: a step for repeating a cycle which includes a first step for supplying a treatment gas into a treatment container that stores a substrate having a silicon oxide film formed on the front surface thereof and a silicon-containing film formed on the rear surface thereof, to generate a reaction product of the silicon oxide film and the treatment gas, and a second step for evacuating the treatment container in a state in which the supply of the treatment gas into the treatment container is stopped, to remove the reaction product; and a step for performing the first step in a first cycle among the respective cycles under treatment conditions different from those of the first step in a subsequent cycle, in order to remove an oxidized layer formed by oxidizing the silicon-containing film.

Description

Etching method and etching apparatus

[0001] The present disclosure relates to an etching method and an etching apparatus.

[0002] In manufacturing semiconductor devices, etching is performed on a film formed on the surface of a semiconductor wafer (hereinafter referred to as a wafer), which is a substrate. Patent Document 1 describes a method for performing ashing to remove a carbon-containing film adhering to the backside of the peripheral edge of the substrate during etching, without adhering the wafer to an electrostatic chuck and without supplying a heat transfer gas that transfers heat from the electrostatic chuck to the backside of the wafer. This method promotes the ashing gas supplied to the front side of the wafer to reach the peripheral edge of the backside of the wafer. Patent Document 2 describes an apparatus for forming a local plasma in a region extending from the peripheral edge of the front side of the wafer, across the side, to the peripheral edge of the backside of the wafer, and removing a film formed in that region.

[0003] JP 2006-93558 A JP 2006-120875 A

[0004] The present disclosure provides a technique that can etch a silicon oxide film formed on a front surface of a substrate while suppressing etching of a silicon-containing film formed on the rear surface of the substrate.

[0005] The etching method of the present disclosure includes a step of repeating a cycle including a first step of supplying a process gas into a process vessel storing substrates each having a silicon oxide film formed on a front surface and a silicon-containing film formed on a back surface, to generate a reaction product between the silicon oxide film and the process gas, and a second step of evacuating the process vessel while stopping the supply of the process gas into the process vessel to remove the reaction product; and a step of performing the first step in a first cycle of the cycles under process conditions different from those of the first step in a subsequent cycle, in order to remove an oxide layer formed by oxidizing the silicon-containing film.

[0006] The present disclosure makes it possible to etch a silicon oxide film formed on a front surface of a substrate while suppressing etching of a silicon-containing film formed on a rear surface of the substrate.

[0007] FIG. 1 is a longitudinal side view of an etching module performing an etching process according to an embodiment of the present disclosure; FIG. 2 is a longitudinal side view of a wafer processed in the etching module; FIG. 3 is a longitudinal side view showing the configuration of the front surface side of the wafer; FIG. 4 is a chart showing a processing flow in a comparative example; FIG. 5 is a schematic view showing a wafer that changes in the comparative example; FIG. 6 is a schematic view of a wafer after processing in the comparative example; FIG. 7 is a chart showing a processing flow in an example; FIG. 8 is a process diagram showing a wafer processing process in the example; FIG. 9 is a longitudinal side view of a wafer after processing in the example; FIG. 10 is a chart for explaining the state inside a processing container in the processing of the example; FIG. 11 is a plan view of a substrate processing apparatus including an etching module; and FIG. 12 is a graph showing the results of an evaluation test.

[0008] In one embodiment of the etching method of the present disclosure, SiO formed on the surface of a wafer W is ２ The wafer W is etched by using a processing gas containing HF (hydrogen fluoride) gas and a basic gas such as NH 3 as a processing gas. ３ By supplying ammonia gas, these gases and SiO ２ A reaction product with the film is generated, and this reaction product is vaporized and removed by etching called COR (Chemical Oxide Removal).

[0009] FIG. 1 is a longitudinal side view of an etching module 1, which is an example of an etching apparatus for performing the COR process. Reference numeral 11 in the figure denotes a processing chamber constituting the etching module 1. Reference numeral 12 denotes a wafer W transfer port opening in the sidewall of the processing chamber 11 and opened and closed by a gate valve 13. A stage 21 for supporting the wafer W is provided within the processing chamber 11. A plurality of protruding pins 22 are distributed on the upper surface of the stage 21, and the backside of the wafer W is supported by each of the pins 22. Support by the pins 22 reduces the contact area of ​​the backside of the wafer W with the stage 21, thereby suppressing the adhesion of foreign matter to the backside. A gap is formed between an area on the upper surface of the stage 21 where the pins 22 are not formed and an area on the backside of the wafer W that is not in contact with the pins 22. The stage 21 is provided with a support member (not shown) that is raised and lowered by a lifting mechanism. The wafer W is transferred between the stage 21 and a second substrate transfer mechanism 72 (described later) via the support member.

[0010] A temperature adjustment unit 23 is embedded in the stage 21, and the wafer W placed on the stage 21 is maintained at a predetermined temperature, for example, a temperature of 50° C. or higher. The temperature adjustment unit 23 is configured as a flow path that forms part of a circulation path through which a temperature adjustment fluid, such as water, flows, and adjusts the temperature of the wafer W by heat exchange with the fluid. However, the temperature adjustment unit 23 is not limited to being a flow path for such a fluid, and may be configured as, for example, a heater for resistance heating.

[0011] One end of an exhaust pipe 14 opens into the processing vessel 11, and the other end of the exhaust pipe 14 is connected to an exhaust mechanism 16, which is constituted by, for example, a vacuum pump, via a valve 15, which is a pressure change mechanism. By adjusting the opening of the valve 15, the pressure inside the processing vessel 11 is set to a pressure range described below, and processing is performed.

[0012] A gas shower head 17 is provided at the upper side of the processing vessel 11 so as to face the stage 21, and the gas shower head 17 discharges gas toward the surface of the wafer W on the stage 21. The downstream sides of gas supply paths 31 to 34 are connected to the gas shower head 17, and the upstream sides of the gas supply paths 31 to 34 are connected to gas supply sources 36 to 39 via flow rate adjusters 35, respectively. Each flow rate adjuster 35 includes a valve and a mass flow controller. The gas supplied from the gas supply sources 36 to 39 is supplied downstream and cut off by opening and closing the valves included in the flow rate adjuster 35.

[0013] Gas sources 36, 37, 38, and 39 supply HF gas, NH ３ Gas, N ２ Therefore, the HF gas, NH (nitrogen) gas, and Ar (argon) gas are supplied into the processing chamber 11 from the gas shower head 17. ３ Gas, N ２ The gas supply sources 36 and 37 and the flow rate adjusting units 35 provided in the gas supply paths 31 and 32 correspond to a process gas supply mechanism. ２ The gas is a carrier gas, and the processing gas is HF gas and NH ３ The N ２ The HF gas and Ar gas are supplied after the supply of the processing gas into the processing vessel 11 is stopped, and also function as purge gases for purging the processing gas remaining in the processing vessel 11 from the processing vessel 11. In the following description, the flow rate of the HF gas supplied into the processing vessel 11 is set to the flow rate of the NH ３ The value divided by the gas flow rate (i.e., the NH ３ The ratio of the flow rate of HF gas supplied into the processing chamber 11 to the flow rate of NH ３ It may be expressed as the gas flow rate.

[0014] 2 shows a vertical cross-sectional side view of the wafer W placed on the stage 21 before processing by the etching module 1. The front surface of the wafer W faces upward. More specifically, this front surface (top surface) is the device formation surface on which semiconductor devices are formed. This surface is provided with the SiO ２ While the film 41 is formed, a silicon-containing film, that is, a silicon nitride (SiN) film 42, is formed on the rear surface (lower surface) of the wafer W. The surface layer of the SiN film 42 is oxidized to form an oxide layer 43. The oxide layer 43 is formed by, for example, natural oxidation or processing of the wafer W before processing in the etching module 1.

[0015] 3 is a vertical cross-sectional side view showing an example of the structure of the surface of a wafer W, with the upper side of FIG. 3 showing the wafer W before processing by the etching module 1 and the lower side of FIG. 3 showing the wafer W after processing by the etching module 1. A plurality of recesses 46 are formed in a layer 45 made of, for example, Si (silicon) provided on the surface of the wafer W. The recesses 46 have different widths, and a narrow recess 46 may be referred to as recess 46A and a wide recess 46 may be referred to as recess 46B. Each recess 46 is provided with a SiO ２ The membrane 41 is buried.

[0016] SiO ２ When etching the film 41, it is required to suppress etching of the SiN film 42. As will be shown in the evaluation tests described later, the process of this embodiment (hereinafter, sometimes referred to as the process of the example) can meet this requirement. ２ The film 41 is etched so that a part of it remains in each recess 46. When etching is performed so as to leave a part of it, the remaining SiO ２ It is required that the height of the film 41 is uniform. ２ It is required that the flatness of the upper surface of the film 41 is high. In addition, it is required that the etching amount is uniform between the recesses 46A and 46B having different widths. As will be described in the evaluation test, according to the treatment of the example, such SiO ２It is also possible to meet the demand for improving the state of the film 41 after etching. ２ The film 41 is shown as having been etched so that its post-etch condition is good.

[0017] In order to clearly show the effect of suppressing etching of the SiN film 42 in the process of the embodiment, the process of the comparative example will be described first with reference to Fig. 4 and Figs. 5 to 6. Fig. 4 is a flowchart of the process of the comparative example. Figs. 5 to 6 are schematic diagrams showing the wafer W on the stage 21 that changes with the process of the comparative example. In Figs. 5 and 6, HF gas is used as 51, NH ３ The gas is shown as 52. In addition, these processing gases (HF gas 51 and NH ３ The sublimate of the reaction product between the gas 52 and the film on the wafer W is shown as 50 .

[0018] 2 is placed on the stage 21 and heated to a predetermined temperature, and the inside of the processing chamber 11 is maintained at a predetermined vacuum pressure. ３ Gas 52, N ２ The SiO gas and Ar gas are supplied into the processing chamber 11 at predetermined flow rates (step S11, left side of FIG. 5). ２ The film 41 reacts with the SiO ２ The surface layer of the film 41 is an altered layer 44 containing AFS, which is a reaction product.

[0019] While the surface of the wafer W is changing in this way, a gap is formed between the back surface of the wafer W supported by the pins 22 and the stage 21, so that the HF gas 51 and the NH ３ The gas 52 flows from the front surface to the rear surface of the wafer W and reacts with the oxide layer 43. The oxide layer 43 is then transformed into an altered layer 44 containing AFS. The altered layer 44 on the front surface side and the altered layer 44 on the rear surface side are made of SiO ２ Since the layers are formed from oxides of the film 41 and the SiN film 42, they may contain different components. However, for convenience, they are not distinguished from each other and are referred to as the same altered layer 44.

[0020] The HF gas 51 and NH３ Since the amount of gas 52 supplied is large, the amount of change to the above-mentioned altered layer 44 is large. A large amount of AFS is generated at the peripheral portion of the rear surface of the wafer W. Since AFS is reactive with the SiN film 42, the portion of the SiN film 42 at the peripheral portion of the rear surface of the wafer W is also altered to form the altered layer 44.

[0021] HF gas 51 and NH ３ After a predetermined time has elapsed since the start of supplying the gas 52 into the processing vessel 11, the HF gas 51 and the NH ３ The supply of gas 52 into the processing vessel 11 is stopped. N ２ The HF gas and NH gas remaining in the processing vessel 11 are supplied as purge gases. ３ The gas is purged (step S12, center of FIG. 5). The altered layers 44 formed on the front and back surfaces of the wafer W are sublimated and removed by the action of the exhaust flow of the purge gas in the processing chamber 11 and the heating by the stage 21. Therefore, the SiO ２ Not only the film 41 but also the SiN film 42 on the periphery of the rear surface of the wafer W is etched.

[0022] HF gas 51 and NH ３ After a predetermined time has elapsed since the supply of the gas 52 into the processing vessel 11 was stopped, the HF gas 51 and the NH ３ The supply of the gas 52 into the processing chamber 11 is resumed. That is, step S11 is performed again. Thereafter, the HF gas 51 and the NH ３ The supply of gas 52 is stopped, and step S12 is performed again. Thereafter, the cycle consisting of steps S11 and S12 is repeated, and SiO ２ While the etching of the film 41 progresses, the etching of the SiN film 42 at the peripheral portion of the rear surface of the wafer W progresses.

[0023] When the control unit 100, which controls the operation of the etching module 1 described below, determines that the cycle consisting of steps S11 and S12 has been performed a predetermined number of times (step S13), the repetition of steps S11 and S12 stops, and the wafer W is unloaded from the processing vessel 11. The wafer W is then transferred to a heat treatment module 70 described below, where it is subjected to a heat treatment at a relatively high temperature, and the affected layer 44 remaining on the wafer W is removed as a sublimate 50 (step S14, right side of FIG. 5). FIG. 6 shows the wafer W after step S14 is completed.

[0024] As described above, the oxide layer 43 formed on the rear surface of the wafer W is formed by etching the SiO ２ Since the film 41 contains silicon and oxygen, the processing gas (HF gas and NH ３ The SiN film 42 reacts with the processing gas (gas) to generate reaction products, and these reaction products react with the SiN film 42 to alter the SiN film 42. As a result, the amount of etching of the SiN film 42 becomes relatively large at the peripheral portion of the wafer W where a large amount of processing gas is supplied.

[0025] Therefore, in the treatment of the embodiment, the treatment conditions suitable for removing the oxide layer 43 are set and the treatment is performed, and then the treatment conditions are changed to remove SiO ２ The film 41 is removed. The process of the embodiment will be described below with reference to FIGS. 7 to 11. FIG. 7 is a flow chart showing the process flow of the embodiment, and FIGS. 8 to 10 are schematic diagrams showing the wafer W on the stage 21 that change with the process of the embodiment. FIG. 11 shows the process flow of the embodiment with the processing gas (HF gas and NH ３ The timing of supplying the HF gas / NH ３ 1 is a timing chart showing gas flow rates and steps performed;

[0026] The wafer W shown in FIG. 2 is placed on the stage 21 and heated to a predetermined temperature. The pressure inside the processing chamber 11 is set to a relatively low pressure of A1 Torr to increase the gas diffusibility. This pressure A1 Torr is determined based on an evaluation test described later and is specifically set to, for example, 11 Torr (1.47×10 ３The pressure is lower than 3 Torr (400 Pa), more specifically, for example, 3 Torr (400 Pa) or less. ３ Gas 52, N ２ The Ar gas and the Ar gas are supplied into the processing chamber 11 at predetermined flow rates of D1 sccm, D2 sccm, D3 sccm, and D4 sccm, respectively (step S1, time t1).

[0027] SiO on the surface of the wafer W ２ For the film 41, the process gas (HF gas 51 and NH ３ The oxide layer 43 reacts with the gas 52) and its surface becomes an altered layer 44. On the other hand, because the pressure inside the processing vessel 11 is low, a relatively large amount of the processing gas supplied to the front surface of the wafer W flows around to the rear surface of the wafer W and is supplied not only to the peripheral portion of the wafer W but also to the center portion. As a result, the processing gas is sufficiently supplied to the entire rear surface of the wafer W, and the entire oxide layer 43 becomes an altered layer 44 (left side of FIG. 8 ).

[0028] At time t2, when a predetermined time has elapsed since time t1, the processing gas (HF gas 51 and NH ３ The supply of gas 52 is stopped and the pressure is reduced from A1 Torr to A2 Torr (step S2). ２ The Ar gas continues to be supplied into the processing vessel 11 as a purge gas. The action of the exhaust flow in the processing vessel 11 caused by this purge gas and the heating by the stage 21 sublimates and removes the affected layers 44 on the front and back surfaces of the wafer W (right side of FIG. 8). Since the pressure in the processing vessel 11 is relatively low, the affected layers 44 are removed efficiently. This step S2 is performed for a sufficiently long time so that the affected layer 44 on the back surface of the wafer W is completely removed.

[0029] At time t3, when a predetermined time has elapsed since time t2, the processing gas (HF gas 51 and NH ３ The supply of HF gas 51, NH gas 52, and the pressure inside the processing chamber 11 is increased to A3 Torr, which is higher than A1 Torr, thereby completing step S2 and starting step S3. The above-mentioned A3 Torr is, for example, 11 Torr or higher. In step S3, HF gas 51, NH gas 53, and the like are supplied. ３ Gas 52, N２ In step S1, the Ar gas and the Ar gas are supplied into the processing chamber 11 at predetermined flow rates of E1 sccm, E2 sccm, E3 sccm, and E4 sccm, respectively. The flow rates of these gases are greater than the flow rates of the gases in step S1 so that the pressure inside the processing chamber 11 becomes relatively high. That is, E1>D1, E2>D2, E3>D3, and E4>D4.

[0030] The process in step S3 is the same as step S11 described in the comparative example, and involves removing SiO ２ The surface layer of the film 41 changes into an altered layer 44 (left side of FIG. 9). However, in step S3, unlike step S11, the oxide layer 43 on the rear surface of the wafer W has been removed, so that even if the processing gas reaches the rear surface of the wafer W, a new altered layer 44 is prevented from being generated on the rear surface. Therefore, the SiN film 42 is prevented from reacting with the altered layer 44 and becoming the altered layer 44.

[0031] At time t4, when a predetermined time has elapsed since time t3, the HF gas 51 and the NH ３ The supply of gas 52 is stopped, and the purge gas (N ２ The affected layer 44 on the front surface of the wafer W is removed by the action of the exhaust flow in the processing chamber 11 due to the Ar gas (Ar gas) and the heating by the stage 21 (step S4, center of FIG. 9). The pressure in the processing chamber 11 in step S4 is set to, for example, A3 Torr, the same as in step S3. The process in step S4 is the same as step S12 described in the comparative example. However, since the affected layer 44 is not formed on the rear surface of the wafer W, sublimation of the affected layer 44 from the rear surface of the wafer W does not occur.

[0032] At time t5, when a predetermined time has elapsed since time t4, the HF gas 51 and NH ３ The supply of gas 52 is resumed, and step S3 is resumed. After step S3, step S4 is performed again. Steps S3 and S4 are then repeated.

[0033] Here, the processes of steps S1 to S4 will be explained in more detail. As will be explained later in the evaluation test, SiO ２The film 41 is in a good condition after etching (SiO ２ In order to increase the flatness of the upper surface of the film 41 and suppress the difference in the amount of etching between the recesses 46A and 46B, the flow rate of the HF gas 51 (E1 sccm) / NH ３ It is preferable that the flow rate (E2 sccm) of the gas 52 is set to a relatively high value. Specifically, E1 / E2 in step S3 is set to, for example, 8 or more. However, the processing gas is SiO ２ It has the effect of reacting with and altering not only the film 41 but also the SiN film 42. ３ The greater the value of the flow rate of the gas 52, the higher the reactivity of the processing gas with the SiN film 42. Therefore, in step S1, where the pressure is set to a relatively low level so that the gas can reach the rear surface of the wafer W, the flow rate of the HF gas 51 / NH ３ It is preferable that the flow rate of the gas 52 be set to a relatively low value so as to suppress etching of the SiN film 42. Therefore, the flow rate of the HF gas 51 / NH ３ The flow rate of the HF gas 51 / NH ３ When comparing the flow rate of the gas 52 (=E1 / E2), it is preferable to set D1 / D2 to be smaller.

[0034] Furthermore, as described above, the processing gas alters the SiN film 42. As will be shown later in the evaluation test, increasing the pressure in the processing vessel 11 prevents the processing gas that has reached the backside of the wafer W from flowing toward the center, thereby preventing the SiN film 42 in the center from being altered and ultimately removed. Therefore, the pressure in the processing vessel 11 is set relatively high in step S3. Therefore, the pressure A1 in the processing vessel 11 in step S1, which allows the processing gas to sufficiently flow around the backside of the wafer W to remove the oxide layer 43, is lower than the pressure A3 in the processing vessel 11 in step S3. In other words, setting the pressure A1 in step S1 lower than the pressure A3 in step S3 is preferable because it allows the oxide layer 43 to be removed more reliably in step S1 and also prevents etching of the SiN film in the center of the wafer W in step S3.

[0035] Even if the pressure in the processing chamber 11 is increased in step S3, the SiN film 42 is more easily etched at the peripheral portion of the wafer W than at the center of the wafer W. The execution time of step S3 (times t3 to t4) is set relatively short to suppress etching of the SiN film 42 at the peripheral portion. On the other hand, in step S1, a sufficient execution time (times t1 to t2) must be ensured to reliably convert the oxide layer 43 into the altered layer 44 and remove it. For these reasons, the execution time (the supply time of the processing gas) of step S1 is set longer than that of step S3, for example. In other words, by making the execution time of step S1 longer than that of step S3, the oxide layer 43 can be removed more reliably in step S1, and etching of the SiN film 42 can be suppressed in step S3, which is preferable. Based on the evaluation test described below, the execution time of step S3 is preferably set to, for example, 3 seconds or less.

[0036] Furthermore, if the altered layer 44 remains on the back surface of the wafer W, it will alter the SiN film 42, so to reliably prevent this, the implementation time of step S2 (times t2 to t3) is made longer than the implementation time of step S4 (times t4 to t5). For example, if the implementation time of step S4 is L1, the implementation time of step S2 is, for example, at least twice L1, and more specifically, at least six times L1.

[0037] When the control unit 100 determines that steps S3 and S4 have been performed a predetermined number of times (step S5), the repeated cycle of steps S3 and S4 stops, and the wafer W is unloaded from the processing chamber 11 and transferred to the heat treatment module 70 where it is subjected to a heat treatment at a relatively high temperature. As a result, the affected layer 44 remaining on the wafer W is removed as a sublimate 50 (step S6, right side of FIG. 9). FIG. 10 shows the wafer W after step S6 is completed.

[0038] As described above, in the process of the embodiment, a cycle consisting of supplying the process gas into the process vessel 11 and exhausting the inside of the process vessel 11 without supplying the process gas is repeated. The process conditions during the process gas supply period (step S1) in the first cycle are different from the process conditions during the process gas supply period (step S3) in each cycle from the second onwards, and are set as process conditions for removing the entire oxide layer 43. Therefore, from the second cycle onwards, SiO ２ Since the film 41 is etched, etching of the SiN film 42 by the altered layer 44 formed from the oxide layer 43 is prevented. Therefore, etching of the SiN film 42 is suppressed. In particular, etching of the SiN film 42 is suppressed at the peripheral portion of the wafer W where a large amount of processing gas is supplied due to the wraparound from the surface.

[0039] Furthermore, if the period during which the processing vessel 11 is evacuated without supplying processing gas is defined as a purge period, when the above-described cycle is repeated, the processing conditions for the purge period (step S2) in the first cycle are set to be different from the processing conditions for the purge period (step S4) in each cycle thereafter. Specifically, the processing conditions are set to be different with respect to the length of the purge period and the pressure inside the processing vessel 11. By setting different processing conditions in this manner, the altered layer 44 on the backside of the wafer W is removed with high reliability in step S2, and the execution time of step S4 is prevented from being longer than necessary.

[0040] As described above, steps S3 and S4 are SiO ２This is a process for etching the film 41, and the process performed in step S3 thereafter may be referred to as the main etching. Steps S1 and S2 are pre-processing steps for this main etching, and the process performed in step S1 thereafter may be referred to as the pre-etching. The process performed in step S11 of the comparative example may also be referred to as the main etching. Steps S1 and S3 are the first process, and steps S2 and S4 are the second process. The implementation time of step S1 or S3 (the length of the processing gas supply period) corresponds to the implementation time of the first process, and the implementation time of step S2 or S4 (the length of the purge period) corresponds to the implementation time of the second process. In the above process example, both the pressure in the processing vessel 11 and the implementation time are different between steps S2 and S4 to more reliably remove the altered layer 44, but only one of these may be different.

[0041] In the above processing example, the processing conditions for the pre-etching and main etching are the pressure in the processing vessel 11, the flow rate of the HF gas 51 / NH ３ Although the flow rate of the gas 52 and the length of the supply period of the processing gas (i.e., the length of time for performing steps S1 and S3) are made different, it is not necessary to make all of these elements different. For example, only the pressure inside the processing vessel 11 may be made different. Even in this case, it is possible to remove the oxide layer 43 in step S1 and to prevent the gas from flowing around to the backside of the wafer W in step S3.

[0042] Furthermore, although the processing conditions for each of the processing gas supply period and the purge period are changed between the first cycle and the second and subsequent cycles, this is not a limitation. The processing conditions for the processing gas supply period or the purge period may be different between the first cycle to the Nth cycle and the (N+1)th cycle to the final cycle. N is an integer of 2 or greater. That is, the removal of the oxide layer 43 described above may not end in the first cycle, but may be performed over multiple cycles. Therefore, for example, after steps S1 and S2 are repeated, step S3 and subsequent steps may be performed. As described above, in this technology, the processing conditions are different between the first cycle and the cycles subsequent to the first, but the subsequent cycles are not limited to the second cycle. Note that the final cycle may be the (N+1)th cycle. That is, the SiO to be etched may be removed. ２ Depending on the target etching amount of the film 41, steps S3 and S4 may be performed only once after changing the processing conditions, rather than being repeated.

[0043] Next, a substrate processing apparatus 6, which is one embodiment of an apparatus including the etching module 1 and performing steps S1 to S6, will be described with reference to the plan view of Fig. 12. The substrate processing apparatus 6 includes a load / unload section 61 for loading and unloading wafers W, two load lock chambers 71 provided adjacent to the load / unload section 61, two heat treatment modules 70 provided adjacent to each of the two load lock chambers 71, and two etching modules 1 provided adjacent to each of the two heat treatment modules 70.

[0044] The load / unload section 61 includes an atmospheric pressure transfer chamber 63 in which a first substrate transfer mechanism 62 is installed and which is kept under atmospheric pressure, and a carrier mounting table 65 on the side of the atmospheric pressure transfer chamber 63 on which a carrier 64 for accommodating a wafer W is mounted. In the drawing, reference numeral 66 denotes an aligner adjacent to the atmospheric pressure transfer chamber 63, which is provided to rotate the wafer W to optically determine the amount of eccentricity and to align the wafer W with the first substrate transfer mechanism 62. The first substrate transfer mechanism 62 transfers the wafer W between the carrier 64 on the carrier mounting table 65, the aligner 66, and the load lock chamber 71.

[0045] A second substrate transfer mechanism 72 having, for example, an articulated arm structure is provided within each load lock chamber 71, and the second substrate transfer mechanism 72 transfers wafers W between the load lock chamber 71, the heat treatment module 70, and the etching module 1. The interior of the processing vessel constituting the heat treatment module 70 is in a vacuum atmosphere, similar to the interior of the processing vessel 11 constituting the etching module 1, and the interior of the load lock chamber 71 can be switched between an atmospheric pressure atmosphere and a vacuum atmosphere so that wafers W can be transferred between these vacuum atmosphere processing vessels and the atmospheric pressure transfer chamber 63.

[0046] In the figure, reference numeral 73 denotes openable and closable gate valves, which are respectively provided between the atmospheric pressure transfer chamber 63 and the load lock chamber 71, between the load lock chamber 71 and the heat treatment module 70, and between the heat treatment module 70 and the etching module 1. The gate valve 73 provided between the heat treatment module 70 and the etching module 1 corresponds to the gate valve 13 shown in Fig. 1. The heat treatment module 70 includes the above-mentioned processing vessel, an exhaust mechanism for evacuating the processing vessel to form a vacuum atmosphere, and a stage provided within the processing vessel and capable of heating the wafer W placed thereon, and is configured to be able to perform the heat treatment of step S6 described above under vacuum pressure.

[0047] The transfer path of the wafer W in the substrate processing apparatus 6 will now be described. As described in FIG. 2, the carrier 64 storing the wafer W on which each film has been formed is placed on the carrier mounting table 65. The wafer W is then transferred in the order of atmospheric pressure transfer chamber 63 → aligner 66 → atmospheric pressure transfer chamber 63 → load lock chamber 71, and then transferred to the etching module 1 via the heat treatment module 70. Steps S1 to S4 are then performed as described in the flow chart of FIG. 7. Subsequently, after the determination in step S5, the wafer W is transferred to the heat treatment module 70, where sublimation is performed in step S6.

[0048] The substrate processing apparatus 6 also includes a control unit 100, which is a computer. The control unit 100 includes a program, a memory, and a CPU. The program includes instructions (steps) for processing the wafer W and transporting the wafer W as described above. The program is stored on a storage medium, such as a compact disc, a hard disk, a magneto-optical disc, or a DVD, and is installed in the control unit 100. The control unit 100 outputs control signals to each component of the substrate processing apparatus 6 based on the program, thereby controlling the operation of each component. Specifically, the operations of the substrate processing apparatus 6 controlled in this manner include, for example, adjusting the temperature of the fluid supplied to the stage 21 (i.e., the processing temperature of the wafer W), supplying each gas from the gas supply sources 36 to 39 to the processing chamber 11, switching between supplying and stopping each gas to the processing chamber 11 and adjusting the flow rate by each flow rate adjuster 35, adjusting the exhaust flow rate by the valve 15 (i.e., adjusting the pressure inside the processing chamber 11), and operating the first substrate transport mechanism 62 and the second substrate transport mechanism 72.

[0049] In the process described in the flow chart of FIG. 7 , the wafer W remains in the same processing vessel 11 from the start of step S1 through the repeated steps S3 and S4 until the final step S4 is completed, and the wafer W is not unloaded from the processing vessel 11. However, the wafer W is not limited to remaining in the same processing vessel 11 in this manner. For example, after the completion of step S2, the wafer W is unloaded from the processing vessel 11 and heated in the thermal processing module 70 to remove the damaged layer 44 on the backside of the wafer W. The wafer W may then be transferred back to the etching module 1 for steps S3 and S4. However, from the viewpoint of preventing a decrease in the throughput of the apparatus, it is preferable to perform the processing by remaining the wafer W in the same processing vessel 11 from step S1 to the final step S4, as in the process described in the flow chart of FIG. 7 . To enable the processing in the same processing vessel 11 in this manner, different processing conditions are set for step S2 than for step S4, thereby ensuring the removal of the damaged layer 44 from the backside of the wafer W.

[0050] The silicon-containing film formed on the rear surface of the wafer W is not limited to the SiN film 42, but may be any other silicon-containing film. Even when a silicon-containing film other than the SiN film is formed, if the film is oxidized to form the oxide layer 43, the SiO ２ When etching the film 41, the oxide layer 43 may become an altered layer 44, which may etch the silicon-containing film, and therefore, it is effective to apply this technology. Note that the term "silicon-containing" in the silicon-containing film does not mean that the silicon-containing film contains silicon as an impurity that is unavoidable, but means that the silicon-containing film contains silicon as a constituent component.

[0051] In the process of the above embodiment, HF gas and NH 4 are introduced into the processing vessel 11 in step S1 (pre-etching) and step S3 (main etching). ３ Although the timings at which the gas supply starts and ends are synchronized, the gas supply is not limited to this. ３ There may be a difference between the timing of starting the supply of HF gas and the timing of stopping the supply of NH ３There may be a difference in timing between when the gas supply ends and when the gas supply ends.

[0052] The same gas is used as the processing gas for the pre-etching and the main etching. However, the halogen-containing gas is not limited to HF gas. HCl, HBr, HI, SF, etc. may be used instead of HF gas. ４ It is possible to use a gas of a compound containing a halogen such as NH 3 . Note that the term "containing a halogen" does not mean that the halogen is contained as an impurity, but that the halogen is contained as a constituent component. In addition, the basic gas among the processing gases is NH 3 . ３ It is not limited to using gas, but the NH ３ Instead of the gas, various amine compound gases such as trimethylamine, dimethylamine, dimethylethylamine, diethylamine, triethylamine, mono-tertiary butylamine, pyrrolidine, pyridine, etc. As other specific examples of the amine compound, various amine gases such as compounds in which some or all of the C-H bonds of the above compounds are replaced with C-F bonds (e.g., 1,1,1-trifluorodimethylamine) can be used.

[0053] Although the foregoing description has been given using wafers as an example of the substrate to be processed, substrates processed in the processing chamber 11 include, in addition to wafers, substrates for manufacturing flat panel displays, substrates for manufacturing exposure masks used in photolithography, and dummy substrates processed for the purpose of testing or setting processing parameters in the substrate processing apparatus. Furthermore, the embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The above-described embodiments may be omitted, substituted, modified, or combined in various ways without departing from the scope and spirit of the appended claims.

[0054] [Evaluation Tests] Evaluation tests performed in connection with this embodiment will be described. Evaluation Test 1 In Evaluation Test 1-1, the wafer W described in FIG. 2 was transported to the etching module 1, and the process described as the example was performed. That is, pre-etching (step S1), purging after pre-etching (step S2), main etching (step S3), and purging after main etching (step S4) were performed, and steps S3 and S4 were repeated a predetermined number of times. Then, after the heating process of step S6 was performed, the etching amount of the SiN film 42 at each in-plane portion on the back surface of the wafer W was measured.

[0055] As evaluation test 1-2, a test similar to evaluation test 1-1 was conducted, except that only pre-etching and purging after pre-etching were conducted. Therefore, in evaluation test 1-2, the processes of steps S3 and S4 were not conducted. Furthermore, as evaluation test 1-3, a test similar to evaluation test 1-1 was conducted, except that only main etching and purging after main etching were conducted. Therefore, in evaluation test 1-3, the process of the comparative example described in FIG. 4 was conducted, and the processes of steps S1 and S2 were not conducted.

[0056] The results of Evaluation Test 1 will now be described. The average values ​​of the measured etching amounts of the SiN film 42, normalized by dividing each by a predetermined value, were 0.52 for Evaluation Test 1-1, 0.46 for Evaluation Test 1-2, and 2.38 for Evaluation Test 1-3. The larger the normalized value, the larger the measured etching amount. Therefore, in Evaluation Tests 1-1 and 1-2, in which pre-etching was performed, the etching amount of the SiN film 42 within the surface of the wafer W was reduced compared to the evaluation test in which pre-etching was not performed. Note that in the explanation of the evaluation tests that follows, all etching amounts are normalized.

[0057] In each of Evaluation Tests 1-1 to 1-3, the etching amount of the SiN film 42 at the center of the wafer W was 0 or approximately 0, and the etching amount of the SiN film 42 at the peripheral portion of the wafer W was greater than that at the center. Figure 13 is a graph showing the etching amount of the SiN film 42 at each position along the diameter of the wafer W for Evaluation Tests 1-1 to 1-3. The horizontal axis of the graph represents the distance from the center of the wafer W, and the vertical axis of the graph represents the normalized etching amount of the SiN film 42.

[0058] The waveforms of the graphs are substantially the same in Evaluation Tests 1-1 and 1-2. Furthermore, with respect to the peripheral portion of the wafer W, the etching amount of the SiN film 42 in the peripheral portion is reduced in Evaluation Tests 1-1 and 1-2, in which steps S1 and S2 are performed, compared to Evaluation Test 1-3, in which steps S1 and S2 are not performed. The results of Evaluation Test 1 above show that the processing in steps S1 and S2 can reduce the etching amount of the SiN film 42 in the peripheral portion of the back surface of the wafer W more than the processing in steps S3 and S4. Furthermore, it was shown that when steps S1 and S2 are performed followed by steps S3 and S4, the etching amount of the SiN film 42 in the peripheral portion of the back surface of the wafer W can be reduced. Therefore, Evaluation Test 1 confirmed the effectiveness of the processing in the example.

[0059] Evaluation Test 2 In Evaluation Test 2, the wafer W described in FIG. 2 was subjected to the process described as the comparative example using the etching module 1, and then the heating process of step S6 was performed. Then, as in Evaluation Test 1, the etching amount of the SiN film 42 at each portion of the rear surface of the wafer W was measured. The processing conditions for the main etching (step S11) were changed for each wafer W.

[0060] In this evaluation test 2, the pressure in the processing vessel 11 was set to 3 Torr, and the flow rate of HF gas / NH ３ The gas flow rate was set to 5 / 1, and the supply time of the processing gas (the execution time of step S11) was set to 10 seconds. ３The gas flow rate was set to 2 / 1, and the processing gas supply time (the time for performing step S11) was set to 10.8 seconds, which was designated as evaluation test 2-2. The number of cycles of steps S11 and S12 performed was the same between evaluation tests 2-1 and 2-2, and the wafer W temperature was also the same.

[0061] The results of Evaluation Tests 2-1 and 2-2 show that the etching amount of the SiN film 42 in each portion of the wafer W was 0.40 to 2.78 in Evaluation Test 2-1 and 0.04 to 5.69 in Evaluation Test 2-2. In Evaluation Test 2-1, the etching amount of the SiN film 42 was greater at the peripheral portion of the wafer W than at the center, but the center was also etched relatively largely. In Evaluation Test 2-2, the etching amount of the SiN film 42 at the center of the wafer W was reduced compared to Evaluation Test 2-1, but the SiN film 42 was etched relatively largely in a relatively narrow range at the peripheral portion of the wafer W. Comparing the etching amount of the SiN film 42 at the peripheral portion of the wafer W, Evaluation Test 2-2 was found to be greater than Evaluation Test 2-1.

[0062] As described above, the results of evaluation test 2, in which pre-etching was not performed, confirmed that by relatively increasing the pressure within the processing vessel 11, it is possible to suppress the process gas from flowing around to the backside of the wafer W and thereby suppress the amount of etching at the center of the wafer W, but that the SiN film 42 is etched relatively largely at the peripheral portion of the wafer W. Furthermore, evaluation test 2-2 showed a small amount of etching at the center of the wafer W, while evaluation test 2-1 showed a large amount of etching at the center of the wafer W. In view of these results, when pre-etching is performed, it is preferable to set the pressure within the processing vessel 11 in step S1 to, for example, lower than 11 Torr, and more preferably 3 Torr or less, in order to remove the entire oxide layer 43.

[0063] Evaluation Test 3 Evaluation Tests 3-1 and 3-2 were conducted in the same manner as Evaluation Test 2, except that the processing conditions for the main etching (step S11) were different. In Evaluation Tests 3-1 and 3-2, in order to prevent the processing gas from leaking around to the backside of the wafer W, the pressure inside the processing vessel 11 in step S11 was set to 11 Torr, as in Evaluation Test 2-2, and the execution time of step S11 was shorter than that of Evaluation Test 2-2. Specifically, in Evaluation Tests 3-1 and 3-3, the execution time of step S11 was 3 seconds. Regarding other processing conditions, in Evaluation Test 3-1, the flow rate of HF gas / NH ３ In evaluation test 3-2, the flow rate of HF gas / NH ３ The gas flow rate was 8 / 1. The number of cycles of steps S11 and S12 was set to be greater than the number of cycles in evaluation test 2, and the number of cycles in evaluation test 3-1 was set to be slightly greater than the number of cycles in evaluation test 3-2. The temperature of the wafer W was the same between evaluation tests 3-1 and 3-2.

[0064] As a result of the evaluation test 3-1, the etching amount of the SiN film 42 in each part of the surface of the wafer W was 0.05 to 0.62. That is, in the evaluation test 3-1, although the number of cycles was greater than the result of the evaluation test 2-2 described above, the etching amount of the SiN film 42 in the peripheral part of the rear surface of the wafer W was suppressed, which was a desirable result. However, the SiO remaining in the recess 46 on the surface of the wafer W as described in FIG. ２ The flatness of the upper surface of the film 41 and the SiO ２ The results indicated that the variation in the amount of etching of the film 41 needs to be improved.

[0065] As a result of the evaluation test 3-2, the etching amount of the SiN film 42 in each part of the surface of the wafer W was 0.06 to 4.71. ３ In this evaluation test 3-2 in which the gas flow rate was set to a relatively high value as described above, the amount of SiO remaining in the recesses 46 on the surface of the wafer W was smaller than in the evaluation test 3-1. ２ The upper surface of the film 41 has high flatness, and the SiO ２The variation in the amount of etching of the SiN film 41 was suppressed. However, the amount of etching of the SiN film 42 at the peripheral portion of the wafer W was larger than that in Evaluation Test 3-1. As described above, the results of Evaluation Test 3 show that when only main etching is performed, the amount of etching of the SiO ２ It is considered difficult to achieve both a good state of the film 41 after etching and a reduced amount of etching of the peripheral edge of the SiN film 42 on the rear surface of the wafer W.

[0066] Evaluation Test 4: The processing of the example was carried out as Evaluation Test 4. In Evaluation Test 4, wafers W were processed in the same manner as in Evaluation Test 3-2, except that pre-etching (Step S1) was carried out before the main etching (Step S3) and that purging in Step S2 was carried out in conjunction with the pre-etching. The processing conditions for pre-etching in Evaluation Test 4 were: flow rate of HF gas / NH ３ The gas flow rate was set to 5, the execution time of step S1 (time t1 to t2 in FIG. 11) was set to 5.5 seconds, and the pressure inside the processing vessel was set to 3 Torr. The execution time of step S2 (time t2 to t3 in FIG. 11) was set to 120 seconds, which was six times longer than the execution time of step S4 (time t4 to t5 in FIG. 11).

[0067] The results of Evaluation Test 4 showed that the etching amount of the SiN film 42 in each part of the surface of the wafer W was 0.07 to 0.97. In other words, the etching amount of the SiN film 42 was relatively small over the entire surface of the wafer W, and the etching amount of the SiN film 42 in the peripheral part of the wafer W was suppressed compared to Evaluation Test 3-2. Note that within the above etching amount range (0.07 to 0.97), the area where the etching amount was relatively large was limited to a relatively narrow area on the peripheral part of the wafer W. In other words, the processing gas was prevented from flowing around to the back surface of the wafer W and moving toward the center during the main etching. Furthermore, in Evaluation Test 3-1, where etching of the SiN film 42 was suppressed, and in Evaluation Test 3-2, the etching amount of the SiN film 42 in the peripheral part of the wafer W was suppressed compared to Evaluation Test 3-2. ２ When the state of the film 41 after etching was compared, the state in this evaluation test 4 was better.

[0068] The results of the above evaluation test 4 confirmed the effect of the present technology in that it is possible to suppress etching of the SiN film 42 on the rear surface of the wafer W. Furthermore, according to the present technology, while suppressing etching of the SiN film 42 in this way, the SiO 2 remaining on the surface of the wafer W after processing can be suppressed. ２ It was confirmed that the flatness of the upper surface of the film 41 could be increased and the difference in the amount of etching between the recesses 46A and 46B could be reduced.

[0069] W wafer 41 silicon oxide film (SiO ２ film) 42 silicon nitride film (SiN film) 43 oxide layer 44 altered layer 51 HF (hydrogen fluoride) gas 52 NH ３ (ammonia) gas

Claims

1. An etching method comprising: a step of repeating a cycle consisting of a first step of supplying a process gas into a process vessel storing substrates each having a silicon oxide film formed on its front surface and a silicon-containing film formed on its back surface, to generate a reaction product between the silicon oxide film and the process gas; and a second step of evacuating the process vessel while stopping the supply of the process gas into the process vessel, to remove the reaction product; and a step of performing the first step in a first of the cycles under different process conditions from those of the first step in a subsequent cycle, in order to remove an oxide layer formed by oxidizing the silicon-containing film.

2. The etching method according to claim 1, wherein the step of repeating the cycle is performed without removing the substrate from the processing chamber.

3. The etching method according to claim 2, wherein the second step of the first cycle is performed under different processing conditions from the second step of the subsequent cycle.

4. The etching method according to claim 3, wherein the processing conditions that differ between the second step of the first cycle and the second step of the subsequent cycle include at least one of the duration of the second step and the pressure within the processing vessel, and the pressure within the processing vessel during the second step of the first cycle is lower than the pressure within the processing vessel during the second step of the subsequent cycle, or the duration of the second step of the first cycle is longer than the duration of the second step of the subsequent cycle.

5. The etching method according to claim 4, wherein the subsequent cycle is the second or subsequent cycle.

6. The etching method according to claim 5, wherein the processing conditions that differ between the first step of the first cycle and the first step of the subsequent cycle include at least the pressure inside the processing vessel, and the pressure inside the processing vessel in the first step of the first cycle is lower than the pressure inside the processing vessel in the first step of the subsequent cycle.

7. The etching method according to claim 6, wherein the processing conditions that differ between the first step of the first cycle and the first step of the subsequent cycle include an implementation time of the first step, and the implementation time of the first step of the first cycle is longer than the implementation time of the first step of the subsequent cycle.

8. The etching method according to claim 6, wherein the processing gas contains a halogen-containing gas and a basic gas, and the processing conditions that differ between the first step of the first cycle and the first step of the subsequent cycle include a ratio of the flow rate of the halogen-containing gas supplied into the processing vessel to the flow rate of the basic gas supplied into the processing vessel, and the ratio in the first cycle is lower than the ratio in the subsequent cycle.

9. The etching method according to claim 8, wherein said halogen-containing gas is hydrogen fluoride gas and said basic gas is ammonia gas.

10. The etching method according to claim 1, wherein the silicon-containing film is a silicon nitride film.

11. An etching apparatus comprising: a processing vessel that stores therein a substrate having a silicon oxide film formed on its front surface and a silicon-containing film formed on its back surface; a processing gas supply mechanism that supplies into the processing vessel a processing gas that reacts with the silicon oxide film to generate a reaction product; an exhaust mechanism that evacuates the processing vessel; and a control unit that repeats a cycle consisting of a first step of supplying the processing gas into the processing vessel to generate the reaction product and a second step of evacuating the processing vessel while stopping the supply of the processing gas into the processing vessel, and that outputs a control signal to perform the first step in a first of the cycles under different processing conditions than the first step in subsequent cycles in order to remove an oxide layer formed by oxidizing the silicon-containing film.

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