Circuit board and semiconductor package

Abstract

This circuit board comprises: a build-up layer including an insulating layer stacked along the vertical direction; and a metal layer penetrating at least a portion of the build-up layer. The metal layer includes a first portion overlapping the build-up layer along the horizontal direction, and a second portion disposed on the first portion and misaligned with the build-up layer along the horizontal direction. The upper surface of the second portion includes a concave groove along the vertical direction.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] A circuit board is a board with a printed circuit printed on an insulating substrate using conductive material.

[0004] Circuit boards are structured to densely mount various types of devices on a flat surface, by determining the mounting location of each device and fixing the circuit pattern connecting the devices by printing it on the flat surface, or by having an embedded structure in which the devices are embedded inside the printed circuit board.

[0005] Recently, in order to realize miniaturization and multi-functionality of electronic components, circuit boards are being used in a multilayer structure that allows for high-density integration, and when components such as PA (Power Amplifier) ​​are built in, circuit boards with a coreless structure are being used for miniaturization and efficient heat dissipation.

[0006] The circuit board of the coreless structure is formed with a stack via structure connected from the upper layer to the lower layer to facilitate heat dissipation, and a metal layer for heat dissipation can be placed within the stack via.

[0007]

[0008] The present embodiment provides a circuit board and semiconductor package capable of uniformly forming the surface of a circuit board by controlling the surface of a metal layer arranged in a via hole and having improved bonding between different layers.

[0009]

[0010] A circuit board according to the present embodiment comprises a build-up layer including an insulating layer laminated along a vertical direction; and a metal layer penetrating at least a portion of the build-up layer, wherein the metal layer comprises a first portion that overlaps the build-up layer along a horizontal direction, and a second portion that is disposed on the first portion and is misaligned from the build-up layer along the horizontal direction, and an upper surface of the second portion includes a concave groove along the vertical direction.

[0011] The above home can be vertically overlapped with the first part.

[0012] The metal layer may include a hairline forming a gap between crystal grains constituting the metal layer.

[0013] The above hairline can be connected to the above home.

[0014] The above hairline may be spaced apart from the above home.

[0015] At least some of the plurality of crystals facing the hairline may have different crystal orientations.

[0016] At least some of the crystals among the plurality of crystals facing each other in a horizontal direction based on the above hairline may have different crystal orientations.

[0017] The second portion includes a first region vertically overlapping the first portion and a second region extending horizontally from the first region, and the upper surface of the first region may include a plurality of stepped regions.

[0018] The upper surface of the first region may include a first surface having a first height in a vertical direction from the upper surface of the build-up layer, and a second surface having a second height smaller than the first height.

[0019] A semiconductor package according to the present embodiment comprises a build-up layer including an insulating layer stacked along a vertical direction; a metal layer penetrating at least a portion of the build-up layer; and a semiconductor element disposed on the metal layer, wherein the metal layer includes a first portion that overlaps the build-up layer along a horizontal direction, and a second portion that is disposed on the first portion and is misaligned from the build-up layer along the horizontal direction, and an upper surface of the second portion includes a concave groove along the vertical direction.

[0020]

[0021] According to this embodiment, the surface of the metal layer to which the semiconductor chip is bonded is formed flat without a burr phenomenon such as a protruding area, thereby maintaining a strong bonding force with the semiconductor chip, and thus has the advantage of improving heat dissipation efficiency.

[0022] Additionally, there is an advantage in that the durability of the metal layer can be improved through the hairline, particle size, and crystal direction within the metal layer.

[0023]

[0024] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0025] Figure 2 is a cross-sectional view showing the bonding structure of a build-up layer and a metal layer according to an embodiment of the present invention.

[0026] Figure 3 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0027] Figure 4 is an enlarged view of a part of Figure 3.

[0028] FIG. 5 is a drawing of a crystal of a metal layer in a hairline arrangement area according to an embodiment of the present invention.

[0029] Figure 6 is a photograph of a metal layer crystal according to an embodiment of the present invention.

[0030] FIG. 7 and FIG. 8 are drawings for explaining a manufacturing process of a circuit board according to an embodiment of the present invention.

[0031] FIG. 9 is a cross-sectional view of a circuit board having a protective layer bonded thereto according to an embodiment of the present invention.

[0032] FIG. 10 is a drawing showing a modified example of the upper surface of a metal layer according to an embodiment of the present invention.

[0033] Figure 11 is a plan view showing the upper surface of a circuit board according to an embodiment of the present invention.

[0034] Figure 12 is a drawing illustrating a manufacturing process of a circuit board according to a comparative example.

[0035] Fig. 13 is a perspective view of a semiconductor package according to an embodiment of the present invention.

[0036] Fig. 14 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0037]

[0038] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0039] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0040] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0041] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0042] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0043] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0044] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0045] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0046] Additionally, the expression that configuration A is positioned between configurations B and C should also include the meaning that configuration A is positioned so that it overlaps configurations B and C at least partially in the horizontal and / or vertical directions.

[0047] Expressions referring to directions include horizontal directions, vertical directions, and include a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. These are referred to as a first horizontal direction (X-axis), a second horizontal direction (Y-axis), and a vertical direction (Z-axis) according to the Cartesian coordinate system, and the meaning of overlapping along the horizontal direction should also include the meaning of overlapping along the first horizontal direction and / or overlapping along the second horizontal direction.

[0048] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0049] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0050] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0051] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a bonding structure of a build-up layer and a metal layer according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 4 is an enlarged view of a part of FIG. 3, FIG. 5 is a view showing crystals of a metal layer in a hairline arrangement area according to an embodiment of the present invention, FIG. 6 is a view showing crystals of a metal layer according to an embodiment of the present invention, FIGS. 7 and 8 are views for explaining a manufacturing process of a circuit board according to an embodiment of the present invention, FIG. 9 is a cross-sectional view of a circuit board to which a protective layer is bonded according to an embodiment of the present invention, FIG. 10 is a view showing a modified example of the upper surface of a metal layer according to an embodiment of the present invention, and FIG. 11 is a plan view showing the upper surface of a circuit board according to an embodiment of the present invention.

[0052] Referring to FIGS. 1 to 11, a circuit board (10) according to an embodiment of the present invention may include a build-up layer (100), a protective layer, a plurality of wiring portions, a plurality of via portions, and a metal layer (150).

[0053] The build-up layer (100) may include a plurality of insulating layers arranged in a vertical direction. For example, the build-up layer (100) may include a first insulating layer (101), a second insulating layer (102) arranged on the lower surface of the first insulating layer (101), a third insulating layer (103) arranged on the lower surface of the second insulating layer (102), a fourth insulating layer (104) arranged on the lower surface of the third insulating layer (103), a fifth insulating layer (105) arranged on the lower surface of the fourth insulating layer (104), and a sixth insulating layer (106) arranged on the lower surface of the fifth insulating layer (105). The number of insulating layers constituting the build-up layer (100) is exemplary, and the build-up layer (100) may include a greater or lesser number of insulating layers.

[0054] The first to sixth insulating layers (101, 102, 103, 104, 105, 106) may each be any insulator, such as photocurable and / or thermosetting. As the thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and a prepreg (PPG) including glass fibers in a resin may be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be provided with a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material provided with glass fibers or aramid fibers may be included. When the first to sixth insulating layers (101, 102, 103, 104, 105, 106) are photocurable insulators, the first to sixth insulating layers (101, 102, 103, 104, 105, 106) may each be a PID (Photo Imageable Dielectric). In addition, some of the plurality of insulating layers may be formed of the same material as the protective layer.

[0055] The build-up layer (100) may include a hole (140). The hole (140) may have a shape that penetrates the build-up layer (100). The hole (140) may have a shape that penetrates from one surface to the other surface of the build-up layer (100). A metal layer (150) may be arranged in the hole (140).

[0056] The hole (140) may include an upper region (141) having a shape in which a horizontal width gradually decreases downward from the upper surface of the build-up layer (100), and a lower region (142) having a shape in which a horizontal width gradually decreases upward from the lower surface of the build-up layer (100). The lower end of the upper region (141) and the upper end of the lower region (142) may be connected. By the upper region (141) and the lower region (142), the hole (140) may have a cross-sectional shape of an hourglass shape. For example, the upper region (141) may be defined from the upper surface of the first insulating layer (101) to the lower surface of the third insulating layer (103), and the lower region (142) may be defined from the lower surface of the third insulating layer (103) to the lower surface of the sixth insulating layer (106).

[0057] The horizontal width of the hole (140) may be greater than the horizontal width of each of the plurality of vias or the plurality of wiring portions. Accordingly, the arrangement area of ​​the metal layer (150) within the circuit board (10) can be secured widely.

[0058] The cross-sectional shape of the hole (140) may be square, but may also be circular.

[0059] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (191) and a second protective layer (192). The first protective layer (191) may be disposed on the upper surface of the build-up layer (100). The first protective layer (191) may be disposed on the upper surface of the first insulating layer (101). The second protective layer (192) may be disposed on the lower surface of the build-up layer (100). The second protective layer (192) may be disposed on the lower surface of the sixth insulating layer (106). The first protective layer (191) and the second protective layer (192) may perform a function of preventing short circuits between solders due to low wettability with solder when semiconductor elements are disposed on the surface of the circuit board (10) using a material such as solder. The first protective layer (191) and the second protective layer (192) may each use a photocurable insulating material. For example, the first protective layer (191) and the second protective layer (192) may be solder resist or PID (Photo Imageable Dielectric).

[0060] A circuit board (10) may include a circuit pattern. A plurality of wiring portions and a plurality of via portions may be arranged on the circuit board (10).

[0061] A plurality of wiring sections may be arranged on the surfaces of the plurality of insulating layers, respectively. Here, "arranged on the surface" may also mean that at least a portion of the plurality of wiring sections are embedded within the plurality of insulating layers or protective layers and exposed to the outside from the surface. The wiring sections may also be referred to as pad sections.

[0062] The plurality of wiring portions may include a first wiring portion (111) arranged on the lower surface of the first insulating layer (101), a second wiring portion (112) arranged on the lower surface of the second insulating layer (102), a third wiring portion (113) arranged on the lower surface of the third insulating layer (103), a fourth wiring portion (114) arranged on the lower surface of the fourth insulating layer (104), and a fifth wiring portion (115) arranged on the lower surface of the fifth insulating layer (105). The first to fifth wiring portions (111, 112, 113, 114, 115) may each have a predetermined width in the horizontal direction within the build-up layer (100) and may be arranged along the vertical direction.

[0063] The circuit board (10) may include a pad portion. The pad portion may include a first pad portion (131) disposed on an upper surface of the build-up layer (100) and a second pad portion (132) disposed on a lower surface of the build-up layer (100). The first pad portion (131) may be disposed on an upper surface of the first insulating layer (101). The second pad portion (132) may be disposed on a lower surface of the sixth insulating layer (106). The first pad portion (131) may be embedded in the first protective layer (191). The second pad portion (132) may be embedded in the second protective layer (192). The first pad portion (131) and the second pad portion (132) may have a horizontal width longer than the horizontal width of each of the first to fifth wiring portions (111, 112, 113, 114, 115). Accordingly, a wide space for coupling with electronic components can be secured.

[0064] The via portion may be a metal material arranged in a via hole formed in each of a plurality of insulating layers to connect different wiring portions arranged in a vertical direction. Here, the via hole may have a shape that vertically penetrates each of the plurality of insulating layers.

[0065] The via portion may include a first via portion (125) penetrating the first insulating layer (101), a second via portion (121) penetrating the second insulating layer (102), a third via portion (122) penetrating the third insulating layer (103), a fourth via portion (123) penetrating the fourth insulating layer (104), a fifth via portion (124) penetrating the fifth insulating layer (105), and a sixth via portion (126) penetrating the sixth insulating layer (106).

[0066] The first via (125) can connect the first pad (131) and the first wiring portion (111). The second via (121) can electrically connect the first wiring portion (111) and the second wiring portion (112). The third via (122) can electrically connect the second wiring portion (112) and the third wiring portion (113). The fourth via (123) can electrically connect the third wiring portion (113) and the fourth wiring portion (114). The fifth via (124) can electrically connect the fourth wiring portion (114) and the fifth wiring portion (115). The sixth via (126) can electrically connect the fifth wiring portion (115) and the second pad portion (132).

[0067] The first to third via sections (125, 121, 122) may each have a shape in which the horizontal width gradually decreases as they go downward. The fourth to sixth via sections (123, 124, 126) may each have a shape in which the horizontal width gradually increases as they go downward.

[0068] Among the plurality of vias, the vertical length of the fourth via (123) may be longer than the vertical length of any one of the first to third vias (125, 121, 122), the fifth via (124), and the sixth via (126). This is in consideration of the fact that the third wiring portion (113) and the fourth wiring portion (114) are arranged on the upper and lower surfaces, respectively, with respect to the fourth insulating layer (104), and the plating portion (160) to be described later can be supported through the fourth insulating layer (104).

[0069] The circuit board (10) may include a metal layer (150). The metal layer (150) may be a metal material. The metal layer (150) may be arranged to penetrate at least a portion of the build-up layer (100). The metal layer (150) may be arranged to penetrate a hole (140) of the build-up layer (100). A semiconductor chip (300, see FIG. 12), which will be described later, is arranged on the metal layer (150), and thus, heat generated by the operation of the semiconductor chip (300) may be dissipated through the metal layer (150). The metal layer (150) may be referred to as a heat dissipation unit.

[0070] The metal layer (150) may include a first portion (151) and a second portion (155) arranged above and below the first portion (151). The first portion (151) may be arranged to overlap the build-up layer (100) in a horizontal direction. The second portion (155) may be arranged to be offset from the build-up layer (100) in a horizontal direction.

[0071] The first portion (151) may be disposed in the hole (140). Since it is disposed in the hole (140), the first portion (151) may also be referred to as a penetrating portion. The first portion (151) may include a first-first portion (152) disposed in an upper region (141) of the hole (140), and a first-second portion (153) disposed in a lower region (142) of the hole (140). The first-first portion (152) may have a shape in which the width gradually decreases downward, corresponding to the shape of the upper region (141). The first-second portion (153) may have a shape in which the width gradually increases downward, corresponding to the shape of the lower region (142). The first-first portion (152) may be disposed to penetrate the first to third insulating layers (101, 102, 103). The first-second section (153) may be arranged to penetrate the fourth to sixth insulating layers (104, 105, 106). The horizontal widths of the first-first section (152) and the first-second section (153) may be greater than the horizontal widths of each of the plurality of wiring sections or the plurality of via sections.

[0072] The second portion (155) may be positioned on the upper and lower portions of the first portion (151), respectively. The second portion (155) may also be referred to as a protrusion since it protrudes from the first portion (151). The second portion (155) may be positioned on the upper and lower surfaces of the build-up layer (100), respectively. The second portion (155) may include a first protrusion positioned on the first insulating layer (101) and a second protrusion positioned on the lower surface of the sixth insulating layer (106). The first protrusion and the second protrusion may each be embedded in the protective layer (191, 192) on the surface of the build-up layer (100).

[0073] The second portion (155) may have a rectangular cross-sectional shape. This is in consideration of the arrangement of the semiconductor chip (300) described later, and the semiconductor chip (300) may be arranged on the second portion (155). However, this is not limited, and the cross-sectional shape of the second portion (155) may be circular.

[0074] The horizontal width of the second portion (155) may be greater than the horizontal width of the first portion (151) or the horizontal width of the hole (140). Accordingly, the second portion (155) disposed at both ends of the first portion (151) may be firmly bonded to the build-up layer (100). The horizontal width of the second portion (155) may be greater than the horizontal width of the first pad portion (131) or the second pad portion (132).

[0075] The circuit board (10) may include a plating portion (160). The plating portion (160) may function as a seed layer for forming a metal layer (150). The plating portion (160) may be disposed between the first-first portion (152) and the first-second portion (153). The plating portion (160) may be embedded in the third insulating layer (103) or the fourth insulating layer (104). The plating portion (160) may be disposed such that at least a portion thereof horizontally overlaps the third wiring portion (113). The horizontal length of the plating portion (160) may be longer than the horizontal length of the first portion (151) or the second portion (155). Not only is the plating process of the metal layer (150) performed through the plating portion (160), but the strength of the metal layer (150) may also be reinforced within the build-up layer (100). In addition, the plating portion (160) is positioned in the vertical center within the build-up layer (100), so that warping of the circuit board (10) can be minimized.

[0076] The circuit board (10) may include a plurality of power vias and power wiring portions that provide current to the plating portion (160). The plurality of power vias and power wiring portions may be electrically connected to the plating portion (160). Accordingly, current for plating the metal layer (150) may be provided to the plating portion (160).

[0077] A plurality of power vias and power wiring sections can be electrically separated from the first and second pad sections (131, 132), the first to sixth via sections (125, 121, 122, 123, 124, 126), and the first to fifth wiring sections (111, 112, 113, 114, 115) described above.

[0078] The plurality of power wiring sections may include a first power wiring section (161) disposed on a first insulating layer (101), a second power wiring section (162) disposed on a second insulating layer (102), a third power wiring section (163) disposed on a third insulating layer (103), a fourth power wiring section (164) disposed on a lower surface of a fourth insulating layer (104), a fifth power wiring section (165) disposed on a lower surface of a fifth insulating layer (105), and a sixth power wiring section (166) disposed on a lower surface of a sixth insulating layer (106). Among these, the first power wiring section (161) disposed on the first insulating layer (101) and the sixth power wiring section (166) disposed on the lower surface of the sixth insulating layer (106) can be connected to the second section (155) of the metal layer (150) to be described later. The surfaces of the first power wiring section (161) and the sixth power wiring section (166) are disposed so as to form the same plane as the surface of the second section (155), and accordingly, a wider space for arranging semiconductor chips on the surface of the circuit board (10) can be secured.

[0079] The plurality of power vias may include a first power via (171) penetrating at least a portion of a first insulating layer (101), a second power via (172) penetrating at least a portion of a second insulating layer (102), a third power via (173) penetrating at least a portion of a third insulating layer (103), a fourth power via (174) penetrating at least a portion of a fourth insulating layer (104), a fifth power via (175) penetrating at least a portion of a fifth insulating layer (105), and a sixth power via (176) penetrating at least a portion of a sixth insulating layer (106).

[0080] The first power via (171) can electrically connect the first power wiring portion (161) and the second power wiring portion (162). The second power via (172) can electrically connect the second power wiring portion (162) and the third power wiring portion (163). The third power via (173) can electrically connect the third power wiring portion (163) and the plating portion (160). The fourth power via (174) can electrically connect the plating portion (160) and the fourth power wiring portion (164). The fifth power via (175) can electrically connect the fourth power wiring portion (164) and the fifth power wiring portion (165). The sixth power via section (176) can electrically connect the fifth power wiring section (165) and the sixth power wiring section (166).

[0081] In Fig. 2, Fig. 7, and Fig. 12, the power via section and power wiring section within the circuit board are excluded from the drawings.

[0082] As illustrated in FIGS. 2 to 4, a groove (170) may be arranged on the upper surface of the metal layer (150). The groove (170) may be arranged on the upper surface of the second portion (155). The groove (170) may have a concave shape in a vertical direction from the upper surface of the second portion (155). At least a portion of the groove (170) may overlap with the first pad portion (131) or the second pad portion (132) in a horizontal direction. The groove (170) may be arranged to overlap with the first portion (151) in a vertical direction. The groove (170) may be arranged to overlap with the hole (140) of the build-up layer (100) in a vertical direction. The groove (170) may be arranged to overlap with the semiconductor chip (300, see FIG. 12) in a vertical direction. Based on the horizontal direction, the home (170) can be placed closer to the inner wall of the hole (140) than the center of the hole (140) of the build-up layer (100).

[0083] The groove (170) is formed during the process of arranging the metal layer (150), and as the area protruding from the surface of the metal layer (150) through the groove (170) is removed through a process such as polishing, warping of the semiconductor chip (300) can be minimized when the semiconductor chip (300) is coupled. In addition, by forming a gap with the semiconductor chip (300) through the groove (170), the heat transfer path can be efficiently controlled, thereby improving heat dissipation efficiency. In addition, by dividing the arrangement area of ​​the semiconductor chip through the groove (170), the positional alignment can be made more precise when arranging the semiconductor chip.

[0084] As illustrated in FIG. 11, a closed-loop-shaped groove (170) may be implemented on the upper surface of the second portion (155) disposed on the upper surface of the build-up layer (100) and on the lower surface of the second portion (155) disposed on the lower surface of the build-up layer (100). The groove (170) may be formed along the edge of the second portion (155) on the upper and lower surfaces of the metal layer (150), respectively. The groove (170) may have a cross-sectional shape corresponding to the cross-sectional shape of the hole (140) of the build-up layer (100). Accordingly, the bonding between the semiconductor chip (300) and the metal layer (150) may be more stably achieved.

[0085] The vertical length of the groove (170) may be shorter than the vertical length of the second portion (155). Accordingly, the support structure of the semiconductor chip (300) through the groove (170) can be maintained while minimizing the deterioration of the durability of the metal layer (150).

[0086] Meanwhile, in the present embodiment, it is illustrated as an example that the groove (170) vertically overlaps with the hole (140) of the build-up layer (100) and does not vertically overlap with the insulating layer within the build-up layer (100), based on the vertical direction, but this is not limited thereto, and the groove (170) may vertically overlap at least partly with the insulating layer in consideration of the shape of the hole (140). In this case, durability may be reinforced by the insulating layer in the vertical direction in the groove (170) formation area.

[0087] Figure 12 is a drawing illustrating a manufacturing process of a circuit board according to a comparative example.

[0088] Referring to Fig. 12, the circuit board according to the comparative example has a problem in that, during the process of forming the metal layer (30) through the plating portion (24) and seed layer (26) arranged in the hole in the build-up layer (22), unnecessary plating areas are formed in areas other than the hole due to isotropic growth of the plating area. That is, as shown in the right drawing of Fig. 12, since there is no structure for preventing the growth of the plating area on the metal layer (30) beyond necessity, protruding areas (32) that protrude above the upper surface of the protective layer (28) may be formed on the upper surface of the metal layer (30). Accordingly, there is a problem in that the flatness of the upper surface of the metal layer (30) forming the arrangement area of ​​the electronic component is reduced.

[0089] According to this embodiment, as illustrated in FIG. 7, before the plating process for forming the metal layer (150), a mask (210) and a protective layer (220) are placed on the build-up layer (100), and then the flatness of the surface of the metal layer (150) can be controlled through a process such as polishing.

[0090] In detail, the mask (210) may include a mask hole (212) that vertically overlaps with the hole (140) of the build-up layer (100). A protective layer (220) may be disposed on the mask (210), and a protective portion (224) may be disposed such that an end surface thereof extends inwardly from an end surface of the mask (210) so that at least a portion thereof vertically overlaps with the hole (140) of the build-up layer (100). In other words, the protective portion (224) includes a protective layer hole (222), and a cross-sectional area of ​​the protective layer hole (222) is formed to be smaller than the cross-sectional area of ​​the mask hole (212), so that at least a portion of the protective layer (220) vertically overlaps with the hole (140) of the build-up layer (100) and the plating portion (160).

[0091] The circuit board (10) may include a seed layer for forming a metal layer (150). The seed layer may include, by region, a first layer (232) disposed on the upper and lower surfaces of the build-up layer (100), a second layer (234) disposed on the upper and lower surfaces of the plating portion (160), and a connection layer (236) disposed on the inner wall of the hole (140) and connecting the first layer (232) and the second layer (234). The first layer (232), the second layer (234), and the connection layer (236) each have a predetermined thickness, and may be disposed on the surface of the build-up layer (100), the inner wall of the hole (140), and the surface of the plating portion (160).

[0092] Accordingly, after the mask (210) and the protective layer (220) are bonded to the surface of the build-up layer (100), during the plating process through the seed layer, the growth of the plating area can be prevented from expanding excessively through the protective portion (224) of the protective layer (220) that vertically overlaps the hole (140). That is, the plating area can be prevented from protruding upwards and downwards, thereby forming a protruding area as in the comparative example. Accordingly, the flatness of the metal layer (150) can be improved.

[0093] Meanwhile, as illustrated in FIG. 8, the protective layer (220) is attached to the surface of the build-up layer (100) and the mask (210) through heat and pressure, and during the attachment process, deformation of the surface of the seed layer occurs due to contact between the protective layer (220) and the upper portion of the connection layer (236) within the seed layer or the end portion of the first layer (232). Accordingly, a groove (170) can be implemented between the upper portion of the connection layer (236) and the plating area for forming the metal layer (150).

[0094] Referring to FIG. 9, the second portion (155) of the metal layer (150) may include a first region (155A) that vertically overlaps the first portion (151), and a second region (155B) that extends horizontally from the first region (155A). The first region (155A) may vertically overlap the first portion (151) and the hole (140) of the build-up layer (100). The second region (155B) may vertically overlap a plurality of insulating layers within the build-up layer (100).

[0095] The upper surface of the first region (155A) and the upper surface of the second region (155B) may be arranged with a vertical step. For example, based on the second part (155) arranged on the upper surface of the build-up layer (100), the upper surface of the second region (155B) may be arranged with a lower step than the upper surface of the first region (155A). This is because the first region (155A) is plated with a thickness of the mask (210) during the manufacturing process of the circuit board (10) described above. Accordingly, there is an advantage in that heat dissipation efficiency is improved due to an increase in the vertical thickness of the metal layer (150) through the first region (155A), and a predetermined distance can be vertically spaced from the semiconductor chip (300) through the second region (155B).

[0096] The upper surface of the first region (155A) may include a first surface (156) and a second surface (157). The first surface (156) may be disposed at the center of the first region (155A), and the second surface (157) may be disposed along the edge of the first region (155A). The first surface (156) may have a first height along a direction perpendicular to the upper surface of the build-up layer (100). The second surface (157) may have a second height smaller than the first height along a direction perpendicular to the upper surface of the build-up layer (100). Accordingly, not only can a heat dissipation area be secured thickly by concentrating on the center of the metal layer (150), but also a plating area for forming the metal layer (150) can be reduced.

[0097] A third surface (158) may be arranged on the upper surface of the second region (155B). Based on the hole of the build-up layer (100), the second surface (157) may be arranged on the outer side of the first surface (156), and the third surface (158) may be arranged on the outer side of the second surface (157). The first to third surfaces (156, 157, 158) may be arranged sequentially along the horizontal direction. Here, the groove (170) may be arranged between the second surface (157) and the third surface (158), which are between the first region (155A) and the second region (155B).

[0098] The third height in the vertical direction between the upper surface of the third surface (158) of the second area (155B) and the upper surface of the build-up layer (100) may be smaller than the first height and the second height described above.

[0099] However, this is exemplary, and with reference to the modified example of FIG. 10, the second vertical height between the second surface (157) and the upper surface of the build-up layer (100) may be greater than the first vertical height between the first surface (156) and the upper surface of the build-up layer (100) or the third vertical height between the third surface (158) and the upper surface of the build-up layer (100). In this case, a heat dissipation structure through an air gap between the semiconductor chip (300) and the first surface (156) can be implemented by a structure in which the first surface (156) is stepped downwards more than the second surface (157). In addition, the lower surface of the semiconductor chip (300) can be stably supported by the concave structure of the first surface (156).

[0100] As illustrated in FIGS. 9 and 10, protective layers may be disposed on the upper and lower surfaces of the build-up layer (100), respectively. Based on the upper surface of the build-up layer (100), the first protective layer (191) may be disposed to vertically overlap the third surface (158) and the second surface (157), and to be vertically misaligned with the first surface (156). Accordingly, the first surface (156) for arranging the semiconductor chip (300) may be exposed above the protective layer.

[0101] As a variation, the first protective layer (191) may overlap at least partly vertically with the first surface (156), in which case the protective structure through the protective layer within the surface of the build-up layer (100) may be secured more widely.

[0102] As illustrated in FIGS. 4 and 5, the metal layer (150) may include a hairline (180). The hairline (180) may be a void in which bonding between grains constituting the metal layer (150) is not formed. The metal layer (150) may include a region separated in a horizontal or vertical direction by the hairline (180). The hairline (180) may have a shape extending vertically from the groove (170). Accordingly, a portion of the metal layer (150) may be separated in a horizontal direction by the hairline (180) extending from the groove (170).

[0103] As a variation, the hairline (180) may be separated from the groove (170). The hairline (180) may not be connected to the groove (170). In this case, the hairline (180) and the groove (180) may overlap at least partially in the vertical direction.

[0104] By forming an air gap through the hairline (180), the heat dissipation efficiency through the metal layer (150) can be improved. That is, since the metal layer (150) is divided into multiple regions in the horizontal direction through the hairline (180), heat generated from the semiconductor chip (300) can be conducted in the vertical direction while minimizing conduction to regions other than the set region in the horizontal direction. In addition, with the air gap formation structure through the hairline (180), the metal layer (150) can implement an additional heat dissipation structure.

[0105] The vertical length of the hairline (180) may be less than or equal to twice the vertical thickness of each of the plurality of insulating layers. Accordingly, the hairline (180) may overlap horizontally with at least one of the first insulating layer (101), the second insulating layer (102), the fifth insulating layer (105), and the sixth insulating layer (106) among the plurality of insulating layers, but may not overlap horizontally with the third insulating layer (103) and the fourth insulating layer (104) arranged in the center of the vertical direction. The hairline (180) may not overlap horizontally with the plating portion (160). Accordingly, while having the aforementioned heat dissipation effect, the deterioration of the durability of the metal layer (150) through the hairline (180) may be minimized.

[0106] Referring to the EBSD (Electron Backcatter Diffraction) illustrated in FIG. 5, crystals within the metal layer (150) forming the boundary with the hairline (180) may be arranged in multiple different crystal directions. That is, the metal layer (150) may include multiple crystals that face the hairline (180) in a horizontal direction, and the multiple crystals may have different crystal directions, such as (001), (101), and (111). In addition, among the multiple crystals that overlap in the horizontal or vertical direction with respect to the hairline (180), at least two or more crystals may have different crystal directions. Accordingly, at the interface where the hairline (180) is formed, the strength within the metal layer (150) may be increased through the multiple crystals having different crystal directions.

[0107] The circuit board (10) may include a seed layer. The seed layer is for forming a metal layer (150), and the metal layer (150) may be formed through plating on the surface of the seed layer. As described above, the seed layer may include a first layer (232) disposed on the upper and lower surfaces of the build-up layer (100), a second layer (234) disposed on the upper and lower surfaces of the plating portion (160), and a connection layer (236) disposed on the inner wall of the hole (140) and connecting the first layer (232) and the second layer (234).

[0108] The seed layer may be disposed on the surface of the plating portion (160). The drawing illustrated in FIG. 6 is a drawing taken by EBSD (Electron Backscatter-Diffraction) of a portion of the metal layer (150), and shows the size of the crystal grains of the metal layer (150) and the crystal direction of each crystal grain. As in A and B of FIG. 6, the size of the crystal grains constituting the seed layer may be smaller than the size of the crystal grains forming the plating portion (160) or the metal layer (150). Accordingly, at the interface where the plating portion (160) and the metal layer (150) are joined, the plating portion (160) and the metal layer (150) may be more densely joined to each other through the seed layer having a relatively small crystal grain size.

[0109] As illustrated in FIG. 6, the seed layer is disposed along the surface of the plating portion (160), and at least a portion of the seed layer may be disposed between the surface of the plating portion (160) and the insulating layer. According to the prior art, the seed layer is disposed to extend in a vertical direction along the inner wall of the through hole of the insulating layer. Thereafter, the metal layer (150) is disposed through a plating process. However, according to the prior art, during the plating process, plating is performed isotropically on the seed layer disposed on the inner wall and on the plating portion (160), which causes a problem in that voids are generated inside the metal layer (150), concave dimples are generated on the upper surface of the metal layer (150), or the protruding area (32) illustrated in FIG. 12 is disposed to be excessively large.

[0110] According to the present embodiment, the above-described problem can be prevented by not forming a seed layer on the inner wall of the hole (140) of the build-up layer (100). That is, by preventing A and B shown in FIG. 6 from being formed on the inner wall of the insulating layer and arranging the size of the crystal grains of the plating portion (160) to be larger than the crystal grains on the upper side of A and / or the lower side of B in FIG. 6, the flatness of the upper surface of the metal layer (1250) can be controlled, which has the advantage of being possible.

[0111] FIG. 13 is a perspective view of a semiconductor package according to an embodiment of the present invention, and FIG. 14 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0112] Referring to FIGS. 1, 13, and 14, a semiconductor package according to an embodiment of the present invention may include a semiconductor chip (300) coupled to a circuit board (10). The semiconductor chip (300) is placed on a first protective layer (191) and may be electrically connected to a first pad (131) via a wire (310).

[0113] As described above, the semiconductor chip (300) may be arranged to vertically overlap with the hole (140) of the circuit board (10). The semiconductor chip (300) may be arranged to vertically overlap with the metal layer (150). The semiconductor chip (300) may be arranged to vertically overlap with the groove (170) of the metal layer (150). Due to the cross-sectional shape of the groove (170), the lower surface of the semiconductor chip (300) may form an overlapping structure with the groove (170) along the periphery.

[0114] The lower surface of the semiconductor chip (300) is supported by the upper surface of the metal layer (150), and thus, heat generated by the operation of the semiconductor chip (300) can be dissipated through the metal layer (150).

[0115] Meanwhile, a plurality of semiconductor chips (300) may be provided and arranged on a circuit board (10). In this case, as illustrated in FIG. 11, the circuit board (10) may be provided with a plurality of holes (140) and metal layers (150) corresponding to the number of semiconductor chips (300).

[0116] A semiconductor package may include a molding portion (400) disposed on a circuit board (10). A semiconductor chip (300) including a wire (310) may be embedded within the molding portion (400). The molding portion (400) may be bonded to the surface of a protective layer. Accordingly, the bonding state of the semiconductor chip (300) on the circuit board (10) may be firmly maintained.

[0117] According to the structure described above, the surface of the metal layer to which the semiconductor chip is bonded can be formed flat without a burr phenomenon such as a protruding area, thereby maintaining a strong bonding force with the semiconductor chip, and thus, there is an advantage in that heat dissipation efficiency can be improved.

[0118] Additionally, there is an advantage in that the durability of the metal layer can be improved through the hairline, particle size, and crystal direction within the metal layer.

[0119] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0120] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

[0121] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0122] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A build-up layer including an insulating layer laminated along the vertical direction; and Comprising a metal layer penetrating at least a portion of the above build-up layer, The metal layer includes a first portion that overlaps the build-up layer in a horizontal direction, and a second portion that is disposed on the first portion and is misaligned with the build-up layer in the horizontal direction. The upper surface of the second part is a circuit board including a concave groove along the vertical direction.

2. In paragraph 1, The above home is a circuit board that overlaps the first part in a vertical direction.

3. In paragraph 1, A circuit board in which the metal layer includes a hairline forming a gap between crystal grains constituting the metal layer.

4. In paragraph 3, The above hairline is a circuit board connected to the above home.

5. In paragraph 3, The above hairline is a circuit board spaced apart from the above home.

6. In paragraph 3, A circuit board in which a plurality of crystals facing the hairline have at least some different crystal orientations.

7. In paragraph 3, A circuit board in which at least some of the crystals among a plurality of crystals facing each other in a horizontal direction based on the hairline have different crystal orientations.

8. In paragraph 1, The second part includes a first region vertically overlapping the first part, and a second region extending horizontally from the first region, A circuit board having a top surface of the first region including a plurality of stepped regions.

9. In paragraph 8, A circuit board including a first surface having a first height in a vertical direction from the upper surface of the build-up layer and a second surface having a second height smaller than the first height, wherein the upper surface of the first region is a first surface.

10. Build-up layer including insulation layer laminated along vertical direction; a metal layer penetrating at least a portion of the above build-up layer; and It includes a semiconductor element disposed on the metal layer, The metal layer includes a first portion that overlaps the build-up layer in a horizontal direction, and a second portion that is disposed on the first portion and is misaligned with the build-up layer in the horizontal direction. A semiconductor package including a concave groove along the vertical direction on the upper surface of the second part.

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