Progressive parallel simulation

Abstract

This patent application discloses a computing system to perform an unbalanced partitioning of a circuit design describing an electronic device and to simulate the unbalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system. The computing system can merge performance data extracted from the parallel simulation of unbalanced partitions of the circuit design into a representation corresponding to a single core simulation, perform a balanced partitioning of the circuit design based, at least in part, on the merged performance data, and simulate the balanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system. The computing system also can iteratively merge newly extracted parallel simulation performance data, and repartition the circuit design.

Description

202410658 PROGRESSIVE PARALLEL SIMULATION TECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, morespecifically, to progressive parallel simulation.BACKGROUND

[0002] Designing and fabricating electronic systems typically involves many steps, knownas a “design flow.” The particular steps of a design flow often are dependent upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system from a design. Initially, a specification for a new electronic system can be transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic system. With this logical design, the electronic system can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as SystemVerilog or Very high speed integrated circuit Hardware Design Language (VHDL).

[0003] The logic of the electronic system can be analyzed to confirm that it will accuratelyperform the functions desired for the electronic system, sometimes referred to as “functional verification.” Design verification tools can perform functional verification202410658 operations, such as simulating, emulating, and / or prototyping the logical design. For example, when a design verification tool simulates the logical design, the design verification tool can provide transactions or sets of test vectors, for example, generated by a simulated test bench, to the simulated logical design. The design verification tools can determine how the simulated logical design responded to the transactions or test vectors, and verify, from that response, that the logical design describes circuitry to accurately perform functions.

[0004] As the logical designs increase in size and verification runtime becomes longer, onetechnique used to speed-up functional verification includes implementing multiple processing device or multi-core parallel simulation. Applying multi-core parallel processing in functional simulation, however, can be difficult given the varying nature of logical designs, cache or memory activity levels during parallel simulation, or the like. This added difficulty can translate into time and effort to set up a design environment to be able to run multi-core parallel simulation on a logical design that was traditionally been run on single- core. While some logical designs can be sped-up with parallel simulation, parallel simulation solutions often suffer from an unbalanced design partitioning or an unbalanced design activity distribution, which can obviate simulation improvements. For example, when performing design partitioning during compilation of the logical design, a compiler may have insufficient simulation knowledge to appropriately balance the partitions so that each partition can run faster by running simultaneously with other cores. Simulation activity distribution also can be sensitive to the test bench applied to the logical design, as each testbench can have prompt the logical design to perform different activities and / or with a different distribution.202410658 SUMMARY

[0005] This application discloses a computing system to perform an unbalancedpartitioning of a circuit design describing an electronic device and to simulate the unbalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system. The computing system can merge performance data extracted from the parallel simulation of unbalanced partitions of the circuit design into a representation corresponding to a single core simulation, perform a balanced partitioning of the circuit design based, at least in part, on the merged performance data, and simulate the balanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

[0006] The computing system also can progressively alter the parallel simulation of thebalanced partitions of the circuit design by extracting performance data from the parallel simulation with balanced partitions, merging balanced performance data into another representation corresponding to the single core simulation, performing rebalanced partitioning of the circuit design based, at least in part, on the merged balanced performance data, and simulating the rebalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system. Embodiments will be described in greater detail below. DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 and 2 illustrate an example of a computer system of the type that may beused to implement various embodiments.202410658

[0008] Figure 3 illustrates an example design verification system 300 that implementsprogression parallel simulation according to various embodiments.

[0009] Figure 4 illustrates an example parallel simulation qualification system to partitiona circuit design for parallel simulation, which may be implemented according to variousembodiments.

[0010] Figure 5 illustrates an example flowchart implementing progressive parallelsimulation, which may be implemented according to various embodiments. DETAILED DESCRIPTION Illustrative Operating Environment

[0011] Various embodiments may be implemented through the execution of softwareinstructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processing unit 105 and a system memory 107. The processing unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processing unit 105.202410658

[0012] The processing unit 105 and the system memory 107 are connected, either directlyor indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 117-123. For example, the processing unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processing unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 117-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 117-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0013] With some implementations, the computing unit 103 may be directly or indirectlyconnected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a202410658 modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0014] It should be appreciated that the computing device 101 is illustrated as an exampleonly, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0015] With some implementations, the processor unit 105 can have more than oneprocessor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its202410658 corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0016] Each processor core 201A and 201B is connected to an interconnect 207. Theparticular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments. Progressive Parallel Simulation

[0017] Figure 3 illustrates an example design verification system 300 that implementsprogression parallel simulation according to various embodiments. Figure 5 illustrates an202410658 example flowchart implementing progressive parallel simulation, which may be implemented according to various embodiments. Referring to Figures 3 and 5, the design verification system 300 can include a progressive simulation system 310 and a simulator 320, for example, each capable of being implemented with computing system, such as a computer network 101 described above with reference to Figure 1. The progressive simulation system 310 and the simulator 320 can work together to perform progressive parallel simulation on a circuit design 301 describing an electronic device, which can implement a balanced parallel simulation of the circuit design 301 based on at least one prior parallel simulation of the circuit design 301. The circuit design 301 can describe the electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device. The circuit design 301 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as SystemVerilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.

[0018] The progressive simulation system 310 can include a compiler 312 to compile thecircuit design 301 and a test bench 302 into a format compatible for execution during parallel simulation by the simulator 320. The compilation of the circuit design 301 and test bench 302 can vary depending on a number of processing devices, such as different processors, or different processing cores, different computers, or the like, which the simulator 320 intends to utilize during parallel simulation. The parallel simulation balancing system 400, in a block 501 of Figure 5, can perform unbalanced partitioning of202410658 the circuit design 301 and the compiler 312 can compile the unbalanced partitions of the circuit design 301 to generate a plurality of design partitions 303 of the circuit design 301.

[0019] The simulator 320, in a block 502 of Figure 5, can simulate the design partitions 303corresponding to unbalanced partitions of the circuit design 301 at least partially in parallel with multiple processing cores of a computing system. During the simulation of the design partitions 303, the simulator 320 can utilize the test bench 302 to generate test stimulus during functional verification operations, such as clock signals, activation signals, power signals, control signals, data signals or the like. The test stimulus, when grouped, may form test bench transactions capable of prompting operation of the design partitions 303 being functionally verified by the simulator 320. In some embodiments, the test bench 302 can be written in an object-oriented programming language, for example, SystemVerilog or the like, which, when executed during elaboration, can dynamically generate test bench components for verification of the circuit design. A methodology library, for example, a Universal Verification Methodology (UVM) library, an Open Verification Methodology (OVM) library, an Advanced Verification Methodology (AVM) library, a Verification Methodology Manual (VMM) library, or the like, can be utilized as a base for creating the test bench. The simulator 320 can generate output corresponding to the operations of the design partitions 303 in response to the test stimulus during the functional verification operations, which can be compared to expected output of the circuit design 301.

[0020] The parallel simulation balancing system 400, in a block 503 of Figure 5, can extractperformance data 305 for the parallel simulation of the design partitions 303 of the circuit design 301. The parallel simulation balancing system 400 can, in some examples, send at202410658 least one extraction request 304 to the simulator 320, which can prompt the simulator 320 to provide the performance data 305 to the progressive simulation system 310. The parallel simulation balancing system 400 can extract performance data 305 for each design partition 303 being simulated in parallel simulation and, for example, store the performance data 305 in separate databases.

[0021] The performance data 305 can include design activity during the parallel simulationfor each design partition 303 of the circuit design 301, concurrency information between the design partitions 303 of the circuit design 301, communications between the design partitions 303 of the circuit design 301, synchronization between the design partitions 303 of the circuit design 301, or the like. In some embodiments, the design activity can include instance trees can include information on the instances of the design partitions 303 having activity during the simulation and include simulation activity, such as an activation of processes or implementation of triggers in each of the design partitions 303 of the circuit design 301. In some embodiments, the processes can correspond to one or more design blocks in the circuit design 301, while the triggers can correspond to change activity in the circuit design 301, such as a change in an output value or change of state in the circuit design 301, for example, which can prompt evaluation of one or more of the processes. The concurrency information between the design partitions 303 of the circuit design 301 can include information corresponding to an overlap of design activity during the parallel simulation between the design partitions 303 of the circuit design 301. The communications between the design partitions 303 of the circuit design 301 can correspond to the data and / or signals exchanged between design partitions 303 of the circuit design 301 during the parallel simulation. In some embodiments, the communications between the202410658 design partitions 303 of the circuit design 301 also can identify hierarchical references between the design partitions 303, a processing overhead associated with the communicates between design partitions 303 of the circuit design 301, the synchronization between the design partitions 303 of the circuit design 301, or the like.

[0022] The parallel simulation balancing system 400, in a block 504 of Figure 5, can mergethe performance data 305 for the parallel simulation into a representation corresponding to a single core simulation. In some embodiments, the merger of the performance data 305 can correspond to a merging of the performance data 305 from the separate databases for each design partition 303, so that the resulting database of performance data 305 appears as though it was from a non-parallel or serial simulation of the circuit design 301. The merged performance data also can include the concurrency information between the design partitions 303 of the circuit design 301, communications between the design partitions 303 of the circuit design 301, synchronization between the design partitions 303 of the circuit design 301, or the like.

[0023] The parallel simulation balancing system 400, in a block 505 of Figure 5, canperform balanced partitioning of the circuit design 301 based, at least in part, on the merged performance data associated with a non-parallel simulation of the circuit design 301. In some embodiments, the parallel simulation balancing system 400 can perform balanced partitioning of the circuit design 301 based on the simulation activity of different portions of the circuit design 301, concurrency information between the design partitions 303 of the circuit design 301, communications between the design partitions 303 of the circuit design 301, synchronization between the design partitions 303 of the circuit design202410658 301, or the like. By performing the partitioning of the circuit design 301 after the performing an unbalanced parallel simulation, the parallel simulation balancing system 400 can perform a balanced partition the circuit design 301 based on the communication, synchronization, concurrency, hierarchical references, or the like, between different partitions in the unbalances parallel simulation. Embodiments of the parallel simulation balancing system 400 will be described below with reference to Figure 4 in greater detail.

[0024] Figure 4 illustrates an example parallel simulation balancing system 400, whichmay be implemented according to various embodiments. Referring to Figure 4, the parallel simulation balancing system 400 can receive a circuit design 401 describing an electronic device both in terms of an exchange of data signals between components in the electronic device, such as hardware registers, flip-flops, combinational logic, or the like, and in terms of logical operations that can be performed on the data signals in the electronic device. The circuit design 401 can model the electronic device at a register transfer level (RTL), for example, with code in a hardware description language (HDL), such as SystemVerilog, Very high speed integrated circuit Hardware Design Language (VHDL), System C, or the like.

[0025] The parallel simulation balancing system 400 can include a performance profiler 410to extract performance data 402, which can include information about the circuit design 401, for example, collected during parallel simulation of partitions of the circuit design 401 using multiple processing devices of a computing system. In some embodiments, the performance data 402 can correspond to unbalanced partitions of the circuit design 401 or balanced partitions of the circuit design 401. The data collected during the parallel simulation can include an instance tree, activity in event queues during the simulation,202410658 execution frequency processes and triggers, execution concurrency of processes and triggers, and ports between the partitions of circuit design 401, along with concurrency information between the partitions of the circuit design 401, communications between the partitions of the circuit design 401, synchronization between the partitions of the circuit design 401, or the like.

[0026] The parallel simulation balancing system 400 can include a merging system 420 tomerge the performance data 402 for the parallel simulation into a representation corresponding to a single core simulation. The merged performance data can aggregate the simulation activity data for each partition, such that the simulation activity corresponds to a non-parallel simulation of the circuit design 401, while also including the concurrency information, communication information, synchronization information, or the like, that occurred between the partitions of the circuit design 401 when simulated in parallel.

[0027] The parallel simulation balancing system 400 can include a design partitioningsystem 430 to perform balanced partitioning of the circuit design 401 based, at least in part, on the merged performance data associated with a representation of a non-parallel simulation of the circuit design 401. In some embodiments, the parallel simulation balancing system 400 can perform balanced partitioning of the circuit design 401 based on the simulation activity of different portions of the circuit design 401, concurrency information between the partitions of the circuit design 401, communications between the partitions of the circuit design 401, synchronization between the partitions of the circuit design 401, or the like. The performance of balanced partitioning of the circuit design 401 by design partitioning system 430 can generate design partitions 403 corresponding to202410658 balanced partitions of the circuit design 401. The design partitioning system 430 can output the design partitions 403 to a simulator having multiple processing devices or cores to simulate the design partitions 403 at least partially in parallel.

[0028] Referring back to Figures 3 and 5, the parallel simulation balancing system 400 canprovide the balanced partitions of the circuit design 301, as design partitions 303, to the simulator 320 for parallel simulation. The simulator 320, in a block 506 of Figure 5, can simulate the balanced partitions of the circuit design 301 at least partially in parallel with the multiple processing cores or processing devices of the computing system. By simulating the unbalanced partitions of the circuit design 301 to identify inter-partition communication, inter-partition concurrency, and inter-partition synchronization, the parallel simulation balancing system 400 can repartition the circuit design 301 to optimize the parallel simulation of the circuit design by the simulator 320.

[0029] In some embodiments, execution can return to the block 503, where the parallelsimulation balancing system 400 can repartition the circuit design 301 by extracting performance data for the parallel simulation of the balanced partitions, merging the performance data for the parallel simulation of the balanced partitions into a representation corresponding to a single core simulation, and then reperform balanced partitioning of the circuit design based, at least in part, on the merged performance data. This iterative repartitioning of the circuit design 301 can occur after each simulation run performed by the simulator 320, after modifications have been made to the circuit design 301, or the like, which can allow the design verification system 300 to adapt, optimize,202410658 and / or improve the parallel simulation through the development process for the circuit design 301.

[0030] The system and apparatus described above may use dedicated processor systems,micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0031] The processing device may execute instructions or "code" stored in memory. Thememory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0032] The processor memory may be integrated together with the processing device, forexample RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing202410658 device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine- readable" and may be readable by a processing device.

[0033] Operating instructions or commands may be implemented or embodied in tangibleforms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer- readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0034] A program stored in a computer-readable storage medium may comprise a computerprogram product. For example, a storage medium may be used as a convenient means to202410658 store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries. Conclusion

[0035] While the application describes specific examples of carrying out embodiments,those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while some of the specific terminology has been employed above to refer to electronic design automation processes, it should be appreciated that various examples may be implemented using any electronic system.

[0036] One of skill in the art will also recognize that the concepts taught herein can betailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0037] Although the specification may refer to “an”, “one”, “another”, or “some” example(s)in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

202410658 CLAIMS 1. A method comprising: performing, by a computing system, an unbalanced partitioning of a circuit design describing an electronic device for simulation at least partially in parallel with multiple processing cores of a computing system merging, by the computing system, performance data extracted from the parallel simulation of unbalanced partitions of the circuit design into a representation corresponding to a single core simulation; performing, by the computing system, a balanced partitioning of the circuit design based, at least in part, on the merged performance data; and simulating, by the computing system, the balanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

2. The method of claim 1, further comprising: merging, by the computing system, balanced performance data extracted from the parallel simulation of balanced partitions of the circuit design into another representation corresponding to the single core simulation; performing, by the computing system, rebalanced partitioning of the circuit design based, at least in part, on the merged balanced performance data; and simulating, by the computing system, the rebalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.202410658 3. The method of claim 1, further comprising compiling, by the computing system, the circuit design for the simulation, which identifies the unbalanced partitions of the circuit design, wherein performing the unbalanced partitioning of the circuit design is based, at least in part, on the compilation of the circuit design.

4. The method of claim 1, wherein the extracted performance data includes one or more of an instance tree for each partition of the circuit design, concurrency information between the partitions of the circuit design, communications between the partitions of the circuit design, and synchronization between the partitions of the circuit design.

5. The method of claim 4, wherein performing the balanced partitioning of the circuit design is based, at least in part, on an aggregation of the instance trees corresponding to design activity of the partitions, and at least one of the concurrency information between the partitions of the circuit design, the communications between the partitions of the circuit design, and the synchronization between the partitions of the circuit design.

6. The method of claim 1, further comprising simulating, by the computing system, the unbalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

7. The method of claim 1, wherein each of the partitions of the circuit design is simulated on a different processing core of the computing system.202410658 8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising: performing an unbalanced partitioning of a circuit design describing an electronic device for simulation at least partially in parallel with multiple processing cores of a computing system merging performance data extracted from the parallel simulation of unbalanced partitions of the circuit design into a representation corresponding to a single core simulation; performing a balanced partitioning of the circuit design based, at least in part, on the merged performance data; and simulating the balanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

9. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising: merging balanced performance data extracted from the parallel simulation of balanced partitions of the circuit design into another representation corresponding to the single core simulation; performing rebalanced partitioning of the circuit design based, at least in part, on the merged balanced performance data; and simulating the rebalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.202410658 10. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising compiling the circuit design for the simulation, which identifies the unbalanced partitions of the circuit design, wherein performing the unbalanced partitioning of the circuit design is based, at least in part, on the compilation of the circuit design.

11. The apparatus of claim 8, wherein the extracted performance data includes one or more of an instance tree for each partition of the circuit design, concurrency information between the partitions of the circuit design, communications between the partitions of the circuit design, and synchronization between the partitions of the circuit design.

12. The apparatus of claim 11, wherein performing the balanced partitioning of the circuit design is based, at least in part, on an aggregation of the instance trees corresponding to design activity of the partitions, and at least one of the concurrency information between the partitions of the circuit design, the communications between the partitions of the circuit design, and the synchronization between the partitions of the circuit design.

13. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising simulating the unbalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.202410658 14. The apparatus of claim 8, wherein each of the partitions of the circuit design is simulated on a different processing core of the computing system.

15. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: perform an unbalanced partitioning of a circuit design describing an electronic device for simulation at least partially in parallel with multiple processing cores of a computing system merge performance data extracted from the parallel simulation of unbalanced partitions of the circuit design into a representation corresponding to a single core simulation; perform a balanced partitioning of the circuit design based, at least in part, on the merged performance data; and simulate the balanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

16. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:202410658 merge balanced performance data extracted from the parallel simulation of balanced partitions of the circuit design into another representation corresponding to the single core simulation; perform rebalanced partitioning of the circuit design based, at least in part, on the merged balanced performance data; and simulate the rebalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

17. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to compile the circuit design for the simulation, which identifies the unbalanced partitions of the circuit design, wherein performing the unbalanced partitioning of the circuit design is based, at least in part, on the compilation of the circuit design.

18. The system of claim 15, wherein the extracted performance data includes one or more of an instance tree for each partition of the circuit design, concurrency information between the partitions of the circuit design, communications between the partitions of the circuit design, and synchronization between the partitions of the circuit design.

19. The system of claim 18, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to perform the balanced partitioning of the circuit design based, at least in part, on an aggregation of the instance trees corresponding to design activity of the partitions, and at least one of the concurrency202410658 information between the partitions of the circuit design, the communications between the partitions of the circuit design, and the synchronization between the partitions of the circuit design.

20. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to simulate the unbalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system.

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