In-plane controllably grown germanium nanowire, preparation method therefor, and use thereof

Abstract

Disclosed in the present application are an in-plane controllably grown germanium nanowire, a preparation method therefor, and the use thereof. The method comprises: obtaining a strip-shaped platform structure on a silicon germanium substrate; pretreating the silicon germanium substrate having the strip-shaped platform structure; and using a molecular beam epitaxy growth technique to sequentially grow a silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cap layer on the silicon germanium substrate having the strip-shaped platform structure, so as to prepare a germanium nanowire. The problem of a germanium nanowire grown by means of self-assembling having excessively high contact resistance and reduced material mobility due to inter-diffusion of materials is overcome; and good ohmic contact can be formed with contact metal at a low temperature, and a thousand-level low-temperature mobility is achieved, which are conducive to the extension of quantum dot devices and the increase in the number of spin bits.

Description

In-plane controllable growth germanium nanowire and preparation method and application thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of nanowire materials, in particular to an in-plane controllable growth germanium nanowire and a preparation method and application thereof. BACKGROUND

[0002] Nanomaterials can realize the confinement of charges in different dimensions. Nanowires with one-dimensional structure have separated energy levels, low charge density and effective mass, and produce different charge transport properties from bulk materials. The transport and regulation of charges are limited in the one-dimensional nanowire conductive channel, and the nanowires have better photoelectric performance than bulk materials, so the nanowires are more researched and applied in the fields of lasers, ring-gate FETs and flexible sensors.

[0003] Since the successful preparation of germanium nanowires, it has been considered that the germanium nanowires will be important in the field of semiconductor integrated circuits. On the one hand, germanium material has the highest hole mobility among conventional semiconductor materials, and its electron mobility is more than twice that of silicon, which is an important high-mobility channel material in the semiconductor industry. On the other hand, the nanowire structure limits the transport of carriers in a one-dimensional channel, which fundamentally isolates the leakage current to the substrate and is a natural transistor channel.

[0004] For the research of semiconductor quantum computing, germanium nanowires also have important applications. The quantum bits defined by the spin properties of holes in germanium material have long decoherence time and fast manipulation speed, which is an important technical route for semiconductor quantum computing. It is worth noting that the preparation of the first bit in germanium is based on germanium nanowire material, and the fastest manipulation speed of the semiconductor bit is also maintained by the germanium nanowire material.

[0005] The traditional synthesis method of germanium nanowires is the gas-liquid-solid method. In this method, metal particles are used as catalysts, and germanium-based gas molecules are introduced into the liquid eutectic alloy formed by the metal under suitable growth conditions, and then the solid single crystal is precipitated from the supersaturated solution. However, this method inevitably introduces metal atom doping, forms deep level traps, and contaminates the germanium nanowires. In addition, the germanium nanowires synthesized by this method have a non-in-plane growth geometry, and the preparation of electrical devices requires transfer and arrangement, which is difficult to meet the demand for device integration for logic operation. Recently, through the method of selective epitaxy, a planar network structure of germanium nanowires has been successfully prepared on the surface of a silicon wafer. However, due to the more than 4% lattice mismatch between germanium and silicon, there are still high-density crystal defects in the germanium nanowires grown by the selective epitaxy method, and the mobility is an order of magnitude lower than the former. SUMMARY

[0006] In order to solve the above problems existing in the prior art, the application aims to provide a germanium nanowire with controllable in-plane growth and a preparation method and application thereof.

[0007] According to an aspect of the application, a preparation method of a germanium nanowire with controllable in-plane growth is provided, comprising:

[0008] obtaining a strip-shaped platform structure on a silicon germanium substrate;

[0009] preprocessing the silicon germanium substrate with the strip-shaped platform structure;

[0010] growing a silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cap layer on the strip-shaped platform structure of the silicon germanium substrate in sequence by using a molecular beam epitaxy growth technique to obtain the germanium nanowire.

[0011] According to some embodiments of the application, the silicon germanium substrate is obtained by epitaxially growing a silicon germanium substrate layer on a silicon substrate;

[0012] wherein the germanium content in the silicon germanium substrate layer is 20wt%-50wt%, and optionally 25wt%-45wt%.

[0013] According to some embodiments of the application, the strip-shaped platform structure is obtained on the silicon germanium substrate by using a micro-nano processing technique;

[0014] wherein the micro-nano processing technique comprises:

[0015] spin-coating an etching-resistant agent on the surface of the silicon germanium substrate;

[0016] forming a strip-shaped platform structure on the etching-resistant agent by using electron beam exposure;

[0017] transferring the strip-shaped platform structure to the silicon germanium substrate by using a reactive ion etching technique; and

[0018] removing the residual etching-resistant agent on the surface.

[0019] According to some embodiments of the application, the preprocessing of the silicon germanium substrate with the strip-shaped platform structure comprises:

[0020] immersing and cleaning the silicon germanium substrate with the strip-shaped platform structure in piranha solution and hydrofluoric acid solution in sequence, and performing in-situ heat treatment on the silicon germanium substrate with the strip-shaped platform structure in a molecular beam epitaxy cavity.

[0021] According to some embodiments of the application, the germanium nanowire is obtained by growing a silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cap layer on the strip-shaped platform structure of the silicon germanium substrate in sequence by using a molecular beam epitaxy growth technique, comprising:

[0022] growing a silicon germanium buffer layer on the silicon germanium substrate by using a molecular beam epitaxy growth technique;

[0023] a silicon spacer layer is grown on the silicon germanium buffer layer by using a molecular beam epitaxy growth technique;

[0024] a pure germanium layer is grown on the silicon spacer layer by using a molecular beam epitaxy growth technique;

[0025] a silicon cap layer is grown on the pure germanium layer by using a molecular beam epitaxy growth technique.

[0026] According to some embodiments of the present application, the temperature for growing the silicon germanium buffer layer is 300-450℃;

[0027] Optionally, the temperature for growing the silicon spacer layer is 300-450℃;

[0028] Optionally, the temperature for growing the pure germanium layer is 280-420℃, and further optionally 290-350℃;

[0029] Optionally, the rate for growing the pure germanium layer is 0.1-0.3μm / min. Further optionally, the rate for growing the pure germanium layer is 0.1-0.3μm / min.

[0030] Optionally, the temperature for growing the silicon cap layer is 250-350℃.

[0031] According to some embodiments of the present application, the piranha solution is a mixed solution of a concentrated sulfuric acid solution with a mass fraction of 98% and a hydrogen peroxide solution with a mass fraction of 30% in a volume ratio of 3:1; the soaking cleaning time of the piranha solution is 5-10min.

[0032] The concentration of the hydrofluoric acid solution is 5%, and the soaking cleaning time is 20-120s.

[0033] According to some embodiments of the present application, the in-situ heat treatment comprises: annealing the silicon germanium substrate with a strip terrace structure at 400℃ for 5-20min, and then annealing the sample at 600℃ for 5-20min.

[0034] According to another aspect of the present application, a germanium nanowire controllably grown in a plane is also provided, comprising: a silicon germanium substrate and, from bottom to top, a silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cap layer arranged in sequence above the silicon germanium substrate;

[0035] The silicon germanium substrate comprises a silicon substrate and a silicon germanium substrate layer; the silicon germanium substrate layer has a strip terrace structure.

[0036] According to some embodiments of the present application, the germanium content in the silicon germanium substrate layer is 20wt%-50wt%, and optionally 25wt%-45wt%;

[0037] Optionally, the germanium content in the silicon germanium buffer layer is 20-50wt%, and further optionally 25-45wt%;

[0038] Optionally, the thickness of the silicon germanium buffer layer is 30-200 nm, and further optionally 50-150 nm;

[0039] Optionally, the thickness of the silicon spacer layer is 2-10 nm, and further optionally 3-7 nm;

[0040] Optionally, the thickness of the pure germanium layer is 1-6 nm, and further optionally 2-4 nm;

[0041] Optionally, the thickness of the silicon cap layer is 1-5 nm, and further optionally 2-4 nm.

[0042] According to some embodiments of the present application, the height of the strip platform structure is 40-200 nm, and optionally 50-150 nm;

[0043] Optionally, the width of the strip platform structure is 40-150 nm, and further optionally 60-100 nm;

[0044] Optionally, the direction of the strip platform structure is

[0100] or

[0010] direction.

[0045] According to still another aspect of the present application, the germanium nanowire prepared by the above preparation method, and / or the above germanium nanowire, has an application in semiconductor spin quantum bits and topological quantum bits.

[0046] Compared with the prior art, the present application at least includes the following beneficial effects:

[0047] The present application provides a germanium nanowire material, which is a pure germanium nanowire arranged on a silicon germanium substrate, and can overcome the technical difficulties in current synthesis methods of germanium nanowires, such as the simultaneous consideration of material crystal quality, material purity, and compatibility with device integration. At the same time, the field effect mobility of the germanium nanowire of the present application is more than 7000 cm 2 Vs.

[0048] The present application also provides a preparation method of a germanium nanowire, which can controllably grow a high-crystal-quality pure germanium nanowire on a silicon germanium substrate. The present application selects a strain-relaxed silicon germanium virtual substrate as a substrate for the growth of the germanium nanowire instead of a silicon substrate, and overcomes the problems of crystal defects and discontinuity of the germanium nanowire caused by lattice mismatch.

[0049] The present application uses a pre-prepared silicon germanium strip structure as a mask substrate for inducing the growth of the germanium nanowire, effectively reduces the growth temperature of the germanium nanowire, overcomes the problem of reduced material purity caused by the high-temperature process in the growth, and realizes a nanowire composed of pure germanium material. In combination with the flexibility of the exposure process, the germanium nanowire prepared by the present application can be arranged in an addressable manner on the surface of the substrate, and meets the integration and expansion requirements of transistor devices and quantum dot devices. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 is a schematic diagram of a germanium nanowire structure according to an example embodiment of the present application.

[0051] Figure 2 is a flow chart of a process for fabricating a germanium nanowire according to an example embodiment of the present application.

[0052] Figure 3 is a scanning electron microscope image of a strip platform structure fabricated on a silicon germanium substrate using micro-nano processing techniques according to Example 1 of the present application.

[0053] Figure 4 is a scanning electron microscope image of a germanium nanowire structure according to Example 1 of the present application.

[0054] Figure 5 is a cross-sectional atom resolution scanning transmission electron microscope image of a germanium nanowire according to Example 2 of the present application.

[0055] Figure 6 is a cross-sectional atom resolution scanning transmission electron microscope image of a germanium nanowire according to Example 3 of the present application.

[0056] Figure 7 is an electron energy loss spectrum of a germanium nanowire according to Example 3 of the present application, showing that the nanowire is composed of pure germanium material.

[0057] Figure 8 is a low temperature field effect transfer characteristic curve of a transistor device fabricated using a germanium nanowire according to Example 4 of the present application.

[0058] Figure 9 is an electron energy loss spectrum of a nanowire according to an example comparative example of the present application, showing that the nanowire is composed of silicon germanium alloy.

[0059] Figure 10 is a low temperature field effect transfer characteristic curve of a transistor device fabricated using a nanowire according to an example comparative example of the present application. DETAILED DESCRIPTION

[0060] The technical solutions of the present application will be described clearly and completely below in conjunction with the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making any creative effort fall within the scope of the present application.

[0061] It is particularly pointed out that similar substitutions and modifications made to the present application are obvious to those skilled in the art, and they are considered to be included in the present application. The relevant personnel can obviously make changes or appropriate changes and combinations to the methods and applications described herein without departing from the content, spirit and scope of the present application, to realize and apply the technology of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments of the present application.

[0062] Unless otherwise specified, the present application is carried out under conventional conditions or manufacturer's recommended conditions, and the raw materials or excipients used, and the reagents or instruments used, are not specified, are conventional products that can be obtained on the market.

[0063] The present application will be described in detail below.

[0064] Germanium silicon materials have been widely concerned and researched by scientific research and industry, and have been applied in heterojunction bipolar transistors, optical waveguides, photoelectric detection and other fields, and are key materials for high-performance system on a chip. Germanium nanowires have been considered to have important applications in the field of semiconductor integrated circuits since their successful preparation.

[0065] In order to overcome the difficulty that the current synthesis method of germanium nanowires cannot simultaneously consider the compatibility of material crystal quality, material purity and device integration, the present application provides a preparation method of germanium nanowires, comprising:

[0066] Obtaining a strip platform structure on a silicon germanium substrate: spin-coating an etch-resistant agent (methyl isobutyl ketone, HSQ) on the surface of the silicon germanium substrate, forming a strip platform structure on the etch-resistant agent by electron beam exposure, then transferring the strip platform structure to the silicon germanium substrate by using a reactive ion etching technology, and finally removing the residual etch-resistant agent on the surface by using a hydrofluoric acid aqueous solution.

[0067] Pre-treatment of the sample before epitaxy (i.e. the silicon germanium substrate with a strip platform structure): cleaning the sample by using an arowana solution, removing the natural oxide layer on the surface of the sample by soaking in a hydrofluoric acid solution, and in-situ heat treating the sample in a molecular beam epitaxy chamber. After each solution treatment, the sample needs to be rinsed with deionized water for 2 minutes.

[0068] Epitaxial growth of germanium nanowires on the strip platform structure of the silicon germanium substrate: growing a silicon germanium buffer layer and covering a silicon spacer layer on the silicon germanium substrate by using a molecular beam epitaxy growth technology, growing a pure germanium layer on the silicon spacer layer, and depositing a silicon cap layer on the pure germanium layer.

[0069] The arowana solution is a mixed solution of a concentrated sulfuric acid solution with a concentration of 98% and a hydrogen peroxide solution with a concentration of 30% in a volume ratio of 3:1.

[0070] Optionally, the arowana solution treats the sample for 10 minutes. The concentration of the hydrofluoric acid solution is 5%, and the treatment time is 1 minute.

[0071] The in-situ heat treatment of the sample in the molecular beam epitaxy chamber includes: annealing the sample at 400℃ for 15 minutes, and then annealing the sample at 600℃ for 10 minutes.

[0072] The growth temperature of the silicon germanium buffer layer is 300-450℃.

[0073] The growth temperature of the pure germanium layer is 280-420℃, and can be 290-350℃.

[0074] The growth rate of the pure germanium layer is and can be

[0075] The growth temperature of the silicon cap layer is 250-350℃.

[0076] The germanium nanowire of the present application can be applied to semiconductor spin quantum bits and topological quantum bits.

[0077] The germanium nanowire of the present application has a silicon germanium substrate with a strip-shaped platform structure, and a silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cap layer on the silicon germanium substrate.

[0078] The silicon germanium substrate is a strain-relaxed silicon germanium substrate layer epitaxially grown on a silicon (001) substrate, and the germanium content in the silicon germanium substrate layer is 20-50wt%, and can be 25-45wt%.

[0079] The height of the strip-shaped platform structure is 40-200nm, and can be 50-150nm. The width of the strip-shaped platform structure is 40-150nm, and can be 60-100nm. The direction of the strip-shaped platform structure is

[0100] or

[0010] direction.

[0080] The germanium content in the silicon germanium buffer layer is 20-50wt%, and can be 25-45wt%. The thickness of the silicon germanium buffer layer is 30-200nm, and can be 50-150nm.

[0081] The thickness of the silicon spacer layer is 2-10nm, and can be 3-7nm.

[0082] The thickness of the pure germanium layer is 1-6nm, and can be 2-4nm.

[0083] The thickness of the silicon cap layer is 1-5nm, and can be 2-4nm.

[0084] The technical solutions of the present application are further described below in combination with specific embodiments.

[0085] Embodiment 1

[0086] A silicon germanium layer with a germanium content of 20wt% is epitaxially grown on a silicon substrate; a strip-shaped platform structure along

[0100] or

[0010] direction with a height of 200nm and a width of 100nm is prepared on the surface of the silicon substrate by using a Wiener processing technology.

[0087] The sample is soaked in piranha solution for 10 minutes to remove residual organic matter and other impurities, rinsed in deionized water for 2 minutes, soaked in hydrofluoric acid solution for 1 minute to remove the natural oxide layer, and rinsed in deionized water for 2 minutes. The sample is transferred into a molecular beam epitaxy cavity, and annealed at 400°C for 15 minutes and at 600°C for 10 minutes in sequence.

[0088] The silicon germanium buffer layer has a content of 20wt%, a thickness of 200nm, and a growth temperature of 450°C; the silicon spacer layer has a thickness of 10nm and a growth temperature of 450°C; the pure germanium layer has a thickness of 1.5nm, a growth temperature of 420°C, and a growth rate of 0.1nm / s; and the silicon cap layer has a thickness of 5nm and a growth temperature of 350°C. The silicon cap layer has a thickness of 5nm and a growth temperature of 350°C.

[0089] FIG. 3 is a scanning electron microscope image of a strip-shaped platform with a height of 200nm and a width of 100nm prepared on a silicon substrate by using the micro-nano processing technology in the embodiment; and FIG. 4 is a scanning electron microscope image of a germanium nanowire in the embodiment. As shown in FIG. 4, the prepared strip-shaped platform is uniform in size and flat in surface, and the prepared germanium nanowire is positioned and grown on the top of the strip-shaped platform, and the structure is continuous without fracture.

[0090] Embodiment 2

[0091] A silicon germanium layer with a content of 35wt% of strain relaxed germanium is epitaxially grown on a silicon substrate; and a strip-shaped platform structure with a height of 30nm and a width of 40nm along the

[0100] or

[0010] direction is prepared on the surface of the silicon substrate by using the micro-nano processing technology.

[0092] The sample is soaked in piranha solution for 10 minutes to remove residual organic matter and other impurities, rinsed in deionized water for 2 minutes, soaked in hydrofluoric acid solution for 1 minute to remove the natural oxide layer, and rinsed in deionized water for 2 minutes. The sample is transferred into a molecular beam epitaxy cavity, and annealed at 400°C for 15 minutes and at 600°C for 10 minutes in sequence.

[0093] The silicon germanium buffer layer has a content of 20wt%, a thickness of 200nm, and a growth temperature of 450°C; the silicon spacer layer has a thickness of 10nm and a growth temperature of 450°C; the pure germanium layer has a thickness of 1.5nm, a growth temperature of 420°C, and a growth rate of 0.1nm / s; and the silicon cap layer has a thickness of 5nm and a growth temperature of 350°C. The silicon cap layer has a thickness of 3nm and a growth temperature of 300°C.

[0094] Figure 5 is a cross-sectional atomic resolution scanning transmission electron microscopy image of the germanium nanowire of the present embodiment. As shown in Figure 5, the germanium nanowire, the top silicon cap layer and the bottom silicon spacer layer are lattice-ordered with the silicon germanium buffer layer without mismatch dislocation, indicating that the germanium nanowire prepared by the present embodiment has excellent crystal quality.

[0095] Embodiment 3

[0096] A silicon germanium layer with a strain relaxed germanium content of 30wt% is epitaxially grown on a silicon substrate; a strip-shaped platform structure with a height of 80nm and a width of 90nm along the

[0100] or

[0010] direction is prepared on the surface of the silicon substrate by using the Viner processing technology.

[0097] The sample is soaked in the piranha solution for 10 minutes to remove residual organic matter and other impurities, rinsed in deionized water for 2 minutes, soaked in a hydrofluoric acid solution for 1 minute to remove the natural oxide layer, and rinsed in deionized water for 2 minutes. The sample is transferred into a molecular beam epitaxy chamber and annealed at 400℃ for 15 minutes and at 600℃ for 10 minutes in sequence.

[0098] A silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cap layer are epitaxially grown on the surface of the pre-processed strip-shaped platform structure in sequence by using the molecular beam epitaxy growth technology. The silicon germanium buffer layer has a content of 30wt%, a thickness of 60nm and a growth temperature of 400℃; the silicon spacer layer has a thickness of 4nm and a growth temperature of 400℃; the pure germanium layer has a thickness of 3.5nm and a growth temperature of 290℃, and a growth rate of 0.1A / s; and the silicon cap layer has a thickness of 3nm and a growth temperature of 290℃.

[0099] Figure 6 is a cross-sectional atomic resolution scanning transmission electron microscopy image of the germanium nanowire of the present embodiment 3. As shown in Figure 6, the germanium nanowire, the top silicon cap layer and the bottom silicon spacer layer are lattice-ordered with the silicon germanium buffer layer without mismatch dislocation, indicating that the germanium nanowire prepared by the present embodiment has excellent crystal quality.

[0100] Embodiment 4

[0101] A silicon germanium layer with a strain relaxed germanium content of 50wt% is epitaxially grown on a silicon substrate; a strip-shaped platform structure with a height of 100nm and a width of 150nm along the

[0100] or

[0010] direction is prepared on the surface of the silicon substrate by using the Viner processing technology.

[0102] The sample is soaked in the piranha solution for 10 minutes to remove residual organic matter and other impurities, rinsed in deionized water for 2 minutes, soaked in a hydrofluoric acid solution for 1 minute to remove the natural oxide layer, and rinsed in deionized water for 2 minutes. The sample is transferred into a molecular beam epitaxy chamber and annealed at 400℃ for 15 minutes and at 600℃ for 10 minutes in sequence.

[0103] ​The silicon germanium buffer layer has a content of 50wt%, a thickness of 100nm, and a growth temperature of 300°C; the silicon cap layer has a thickness of 2nm and a growth temperature of 300°C; and the pure germanium layer has a thickness of 6nm, a growth temperature of 250°C, and a growth rate of 0.1A / s. The silicon cap layer has a thickness of 1nm and a growth temperature of 250°C.

[0104] Figure 7 is an electron energy loss spectrum (EELS) of the germanium nanowire epitaxially grown in Example 4. The silicon germanium content is obtained by extracting the Ge-L peak and Si-K peak intensity. In Figure 7, the silicon and germanium elements are marked with red and green colors respectively. It can be confirmed from the data in Figure 7 that the nanowire is composed of pure germanium material.

[0105] Figure 8 is a low-temperature field effect transfer characteristic curve of a transistor device of the germanium nanowire epitaxially grown in Example 4. The horizontal axis is the device gate voltage, in volts; and the vertical axis is the device conductance, in quantum conductance. The device channel length is 1μm, the excitation voltage is 10mV, and the test temperature is 2K. The device capacitance is calculated by finite element to be 300aF. According to the formula The field effect mobility of the device is more than 7000cm 2 / Vs.

[0106] Comparative Example 1

[0107] The silicon (001) substrate is soaked in the piranha solution for 10 minutes to remove residual organic impurities, rinsed in deionized water for 2 minutes, soaked in a hydrofluoric acid solution for 1 minute to remove the natural oxide layer, and rinsed in deionized water for 2 minutes. The sample is transferred into a molecular beam epitaxy cavity and annealed at 400°C for 15 minutes and at 600°C for 10 minutes in sequence.

[0108] The silicon buffer layer has a total thickness of 100nm and is grown in three sections: (1) a silicon buffer layer with a thickness of 40nm and a growth temperature of 400°C; (2) a silicon buffer layer with a thickness of 30nm and a growth temperature of 400°C-550°C; and (3) a silicon buffer layer with a thickness of 30nm and a growth temperature of 50°C. The pure germanium layer has a thickness of 0.8nm, a growth temperature of 560°C, and a growth rate of 0.1A / s. The growth needs to be annealed at 540°C for 2 hours; the silicon cap layer has a thickness of 3nm and a growth temperature of 330°C; and the growth rate is 0.1A / s.

[0109] Figure 9 is an electron energy loss spectrum line scanning spectrum of the germanium nanowire epitaxially grown in Comparative Example 1.

[0110] The green line region in the upper graph indicates the region tested, and the lower graph is a corresponding line scan spectrum. The silicon germanium content is obtained by extracting the Ge-L peak and Si-K peak intensity. It can be confirmed from the data in Figure 9 that the nanowire is composed of a silicon germanium alloy material, and the peak value of the germanium content is less than 70%.

[0111] Figure 10 is a transistor device low-temperature field effect transfer characteristic curve of the germanium nanowire epitaxially grown in the comparative example 1. The horizontal axis is the device gate voltage, in volts; the vertical axis is the device source-drain current, in nanoamperes. The device channel length is 100 nm, the excitation voltage is 5 mV, 10 mV and 15 mV respectively, and the test temperature is 4.2 kelvin. According to the formula , the mobility thereof can be calculated to be 780 cm 2 / Vs.

[0112] In the comparative examples of the present application, although pure germanium material is deposited, the nanowire obtained is actually a germanium silicon alloy. This is because the self-assembly of the nanowire requires a high-temperature growth and a high-temperature annealing process. The high-temperature process provides sufficient kinetic energy for the germanium atoms to migrate to the groove edge to nucleate and grow, but at the same time, it also aggravates the material interdiffusion between germanium and silicon, forming an alloy material.

[0113] Compared with pure germanium material, the material mobility of the silicon germanium alloy nanowire is significantly reduced, which is not conducive to the preparation of high-performance transistor devices and quantum dot devices. The high work function metal forms a contact with the germanium material, and the work function thereof is pinned near the valence band top of germanium, which can form a good ohmic contact. However, the introduction of silicon material in the germanium nanowire will hinder the work function pinning effect, causing serious contact resistance problems. In addition, the distribution of germanium silicon content in the nanowire is not uniform, and the corresponding stress distribution is also not uniform. This will aggravate the complexity of the characteristic physical parameters in the nanowire and the dispersion of the characteristic physical parameters between samples, which is not conducive to the improvement of device yield.

[0114] The pure germanium nanowire positioned and arranged on the silicon germanium substrate of the present application overcomes the problems of high contact resistance and reduced material mobility caused by material interdiffusion of the self-assembled grown germanium nanowire; can form a good ohmic contact with the contact metal at low temperature, and the low-temperature mobility breaks through the order of magnitude (cm 2 / Vs), which is helpful for the expansion of quantum dot devices and the improvement of spin bit number.

[0115] The germanium nanowire of the present application has strong spin-orbit interaction, and there is a superconducting near-neighbor induction effect with conventional superconductors, which meets the physical properties of constructing topological quantum computing. The germanium nanowire of the present application can be positioned and arranged, which is helpful for realizing the weaving operation between topological bits.

[0116] The above description of the embodiments is only used to help understand the method and its core idea of the application. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the application without departing from the principles of the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

Claims

1. A method for preparing a germanium nanowire with in-plane controllable growth, characterized in that, The application relates to a preparation method of a germanium nanowire. A strip-shaped platform structure is obtained on a silicon germanium substrate; The silicon germanium substrate with the strip-shaped platform structure is pretreated; A silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cover layer are sequentially grown above the strip-shaped platform structure of the silicon germanium substrate by using a molecular beam epitaxy growth technology, so that the germanium nanowire is prepared.

2. The production method according to claim 1, characterized by, The silicon germanium substrate is obtained by epitaxially growing a silicon germanium substrate layer on a silicon substrate; The germanium content in the silicon germanium substrate layer is 20wt%-50wt%, and the germanium content is optionally 25wt%-45wt%. Optionally, the strip-shaped platform structure is obtained on the silicon germanium substrate by using a micro-nano processing technology; Further optionally, the micro-nano processing technology comprises the following steps: The strip-shaped platform structure is formed on the anti-etching agent by using electron beam exposure; The strip-shaped platform structure is transferred to the silicon germanium substrate by using a reactive ion etching technology; and The residual anti-etching agent on the surface is removed. The pretreatment of the silicon germanium substrate with the strip-shaped platform structure comprises the following steps:

3. The preparation method according to claim 1, characterized in that, The silicon germanium substrate with the strip-shaped platform structure is immersed and cleaned by using an aiptasia solution and a hydrofluoric acid solution in sequence, and the silicon germanium substrate with the strip-shaped platform structure is in-situ heat-treated in a molecular beam epitaxy cavity. The silicon germanium buffer layer is grown on the silicon germanium substrate by using the molecular beam epitaxy growth technology; 4. The method of claim 1, wherein, The silicon spacer layer is grown on the surface of the silicon germanium buffer layer by using the molecular beam epitaxy growth technology; The pure germanium layer is grown above the silicon spacer layer by using the molecular beam epitaxy growth technology; The silicon cover layer is grown above the pure germanium layer by using the molecular beam epitaxy growth technology. The temperature for growing the silicon germanium buffer layer is 300-450 DEG C; Optionally, the temperature for growing the silicon spacer layer is 300-450 DEG C; 5. The preparation method according to claim 4, characterized in that, Optionally, the temperature for growing the pure germanium layer is 280-420 DEG C, and the temperature is further optionally 290-350 DEG C; Optionally, the temperature for growing the silicon cover layer is 250-350 DEG C. The aiptasia solution is a mixed solution prepared by mixing a concentrated sulfuric acid solution with a mass fraction of 98% and a hydrogen peroxide solution with a mass fraction of 30% in a volume ratio of 3:1; the immersion cleaning time of the aiptasia solution is 5-10 min; Optionally, the rate of growing the pure germanium layer is Further optionally The concentration of the hydrofluoric acid solution is 5%, and the immersion cleaning time is 20-120 s; 6. The preparation method according to claim 3, characterized in that, Optionally, the in-situ heat treatment comprises the following steps: the silicon germanium substrate with the strip-shaped platform structure is heated to 400 DEG C and annealed for 5-20 min, and then the sample is heated to 600 DEG C and annealed for 5-20 min. The application relates to a preparation method of a germanium nanowire. A silicon germanium substrate and a silicon germanium buffer layer, a silicon spacer layer, a pure germanium layer and a silicon cover layer arranged above the silicon germanium substrate in sequence from bottom to top; 7. A germanium nanowire with in-plane controllable growth, characterized by, The silicon germanium substrate comprises a silicon substrate and a silicon germanium substrate layer; and the silicon germanium substrate layer has a strip-shaped platform structure. The germanium content in the silicon germanium substrate layer is 20wt%-50wt%, and the germanium content is optionally 25wt%-45wt%. ​ 8. The germanium nanowire of claim 7, wherein, ​ Optionally, the Ge content in the SiGe buffer layer is 20-50 wt%, further optionally 25-45 wt%; Optionally, the thickness of the SiGe buffer layer is 30-200 nm, further optionally 50-150 nm; Optionally, the thickness of the Si spacer layer is 2-10 nm, further optionally 3-7 nm; Optionally, the thickness of the pure Ge layer is 1-6 nm, further optionally 2-4 nm; Optionally, the thickness of the Si cap layer is 1-5 nm, further optionally 2-4 nm.

9. The germanium nanowire of claim 7, wherein, The height of the strip platform structure is 40-200 nm, optionally 50-150 nm; Optionally, the width of the strip platform structure is 40-150 nm, further optionally 60-100 nm; Optionally, the direction of the strip platform structure is [100] or [010] direction.

10. The Ge nanowire prepared by the preparation method of any one of claims 1-6, and / or the Ge nanowire of any one of claims 7-9, for use in semiconductor spin qubits and topological qubits.

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