Array substrate, display panel, and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel, and a display apparatus. The array substrate comprises: a base substrate, the base substrate comprising a pixel opening area; a transistor, the transistor and the pixel opening area not overlapping one another; an insulating layer, comprising a via hole, the orthographic projection of the via hole on the base substrate overlapping the orthographic projection of a first electrode of the transistor on the base substrate; and a pixel electrode, comprising a first pixel electrode portion, a second pixel electrode portion, and at least one connecting portion. The first pixel electrode portion is electrically connected to the first electrode of the transistor by means of the via hole. The second pixel electrode portion at least partially covers the pixel opening area, and the second pixel electrode portion comprises a first edge close to one side of the first pixel electrode portion. The at least one connecting portion is connected to the first pixel electrode portion, and the at least one connecting portion is connected to a part of the first edge.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high image quality, no radiation and portability, and has been rapidly developed in recent years, and has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual reality displays, etc.

[0003] SUMMARY

[0004] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions.

[0005] In one aspect, the present disclosure provides an array substrate, comprising:

[0006] a substrate substrate, the substrate substrate comprising a pixel opening area;

[0007] a transistor, the transistor and the pixel opening area do not overlap each other;

[0008] an insulating layer comprising a via, a normal projection of the via on the substrate substrate and a normal projection of a first electrode of the transistor on the substrate substrate overlap each other;

[0009] a pixel electrode comprising a first pixel electrode part, a second pixel electrode part and at least one connecting part; wherein the first pixel electrode part is electrically connected with the first electrode of the transistor through the via; the second pixel electrode part at least partially covers the pixel opening area, the second pixel electrode part comprises a first edge close to a side of the first pixel electrode part; the at least one connecting part is connected with the first pixel electrode part, and the at least one connecting part is connected with part of the first edge.

[0010] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises the data line, and the first edge comprises a first end portion away from the data line.

[0011] The at least one connecting portion comprises a first connecting portion, which is extended from a side of the first pixel electrode portion away from the data line to the first end portion.

[0012] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises the data line, and the first edge comprises a second end portion close to the data line.

[0013] The at least one connecting portion comprises a second connecting portion, which is extended from a side of the first pixel electrode portion close to the second pixel electrode portion towards the data line and then is bent to connect to the second end portion.

[0014] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises the data line, and the first edge comprises a first end portion away from the data line, a second end portion close to the data line, and an intermediate portion between the first end portion and the second end portion.

[0015] The at least one connecting portion comprises a third connecting portion, which is directly extended from a side of the first pixel electrode portion close to the second pixel electrode portion to the intermediate portion.

[0016] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line, and a projection of the first common electrode line on the substrate substrate overlaps with a projection of the first electrode of the transistor on the substrate substrate.

[0017] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a first common electrode line, and a projection of the first common electrode line on the substrate substrate overlaps with a projection of the first electrode of the transistor on the substrate substrate.

[0018] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises the data line, and the second pixel electrode portion comprises a second edge close to a side of the data line and a third edge away from a side of the data line.

[0019] The projection of the first common electrode line on the substrate substrate overlaps with a projection of the second edge on the substrate substrate, and / or the projection of the first common electrode line on the substrate substrate overlaps with a projection of the third edge on the substrate substrate.

[0020] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a data line and a second common electrode line in the same layer as the pixel electrode.

[0021] The orthogonal projection of the second common electrode line on the substrate substrate and the orthogonal projection of the data line on the substrate substrate overlap each other.

[0022] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a gate line and a third common electrode line in the same layer as the pixel electrode.

[0023] The third common electrode line is electrically connected to the second common electrode line, and the orthogonal projection of the third common electrode line on the substrate substrate and the orthogonal projection of the gate line on the substrate substrate overlap each other.

[0024] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a red pixel opening area, a blue pixel opening area, and a green pixel opening area.

[0025] The transistor electrically connected to the pixel electrode overlapping the red pixel opening area is a first transistor, the transistor electrically connected to the pixel electrode overlapping the green pixel opening area is a second transistor, and the transistor electrically connected to the pixel electrode overlapping the blue pixel opening area is a third transistor.

[0026] The orthogonal projection area of the first electrode of the first transistor on the substrate substrate is substantially the same as the orthogonal projection area of the first electrode of the second transistor on the substrate substrate, and the orthogonal projection area of the first electrode of the first transistor on the substrate substrate is greater than the orthogonal projection area of the first electrode of the third transistor on the substrate substrate.

[0027] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a second pixel electrode part in a block shape.

[0028] The array substrate further comprises an alignment layer, and the alignment layer has a plurality of alignments in the pixel opening area.

[0029] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a second pixel electrode part in a slit shape, and the slits of the slit electrode have a plurality of extension directions in the pixel opening area.

[0030] In another aspect, the embodiments of the present disclosure provide a display panel comprising an array substrate and a counter substrate opposite to each other, wherein the array substrate is the array substrate provided by the embodiments of the present disclosure.

[0031] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the opposite substrate comprises a black matrix and a common electrode located on the side of the black matrix facing the array substrate; wherein the common electrode is arranged opposite to at least the second pixel electrode part, and the orthographic projection of the black matrix on the substrate substrate covers the via hole.

[0032] In another aspect, the embodiments of the present disclosure provide a display device comprising the display panel provided in the embodiments of the present disclosure and a backlight module located on the light-incident side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0033] FIG. 1 is a structural schematic diagram of a VA-type liquid crystal display panel;

[0034] FIG. 2 is a structural schematic diagram of a VA-type liquid crystal display panel under external force extrusion;

[0035] FIG. 3 is a trace Mura actual diagram caused by a finger or a hard object sliding across a VA-type liquid crystal display panel;

[0036] FIG. 4 is a dark line display effect diagram of an unpressed pixel;

[0037] FIG. 5 is a dark line display effect diagram of a pressed pixel;

[0038] FIG. 6 is a structural schematic diagram of a pixel electrode in the VA-type liquid crystal display panel shown in FIG. 1;

[0039] FIG. 7 is a structural schematic diagram of one sub-pixel in an array substrate provided in the embodiments of the present disclosure;

[0040] FIG. 8 is an enlarged structural schematic diagram of a Z1 region in FIG. 7;

[0041] FIG. 9 is a cross-sectional structural schematic diagram along line I-I' in FIG. 7;

[0042] FIG. 10 is a light efficiency simulation diagram of the sub-pixel shown in FIG. 7;

[0043] FIG. 11 is another structural schematic diagram of one sub-pixel in an array substrate provided in the embodiments of the present disclosure;

[0044] FIG. 12 is an enlarged structural schematic diagram of a Z3 region in FIG. 11;

[0045] FIG. 13 is a light efficiency simulation diagram of the sub-pixel shown in FIG. 11;

[0046] FIG. 14 is another structural schematic diagram of one sub-pixel in an array substrate provided in the embodiments of the present disclosure;

[0047] FIG. 15 is an enlarged structural schematic diagram of a Z4 region in FIG. 14;

[0048] FIG. 16 is a schematic view of another structure of one sub-pixel in an array substrate according to an embodiment of the present disclosure;

[0049] FIG. 17 is a schematic view of an enlarged structure of a region Z5 in FIG. 16;

[0050] FIG. 18 is a schematic view of a structure of 2*2 sub-pixels in an array substrate according to an embodiment of the present disclosure;

[0051] FIG. 19 is a schematic view of a structure of a layer in which gate lines are located in FIG. 18;

[0052] FIG. 20 is a schematic view of a structure of an active layer in FIG. 18;

[0053] FIG. 21a is a schematic view of a structure of a layer in which data lines are located in FIG. 18;

[0054] FIG. 21b is a schematic view of another structure of a layer in which data lines are located according to an embodiment of the present disclosure;

[0055] FIG. 22 is a schematic view of a structure of a layer in which a via is located in FIG. 18;

[0056] FIG. 23 is a schematic view of a structure of a layer in which a pixel electrode is located in FIG. 18;

[0057] FIG. 24 is a schematic view of a structure of a display panel according to an embodiment of the present disclosure;

[0058] FIG. 25 is a schematic view of a structure of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that, in the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated but are to include deviations in shapes that result from, for example, manufacturing. For example, an region illustrated or described as a flat surface can typically have rough and / or nonlinear features. Similarly, an illustrated sharp corner can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not reflective of true scale, the purpose of which is to illustrate the embodiments of the present disclosure. Like numbers refer to like or similar elements throughout. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and configurations incorporated herein will be omitted.

[0060] Unless otherwise defined, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein and the claims section of the instant disclosure are not intended to be limiting of the scope of the present disclosure. Rather, the terminology used is intended to convey, in a specific but non-limiting sense, the present disclosure. Unless specified otherwise, the various technical stages described herein are not meant to be sequential but can be performed in any order. For simplicity, the terms "first", "second", etc., are used in the description and the claims section of the instant disclosure not to denote any sequential or chronological order, but to distinguish different components having the same or similar functions. The terms "comprises", "comprising", "includes", "including" and the like can be used in the description and the claims section of the instant disclosure. Such terms are like a "speaking clause" to the effect that the modifications of a claimed element can include additional, not specifically named elements, or elements instead of the additional. The terms "connected" and "coupled" and the like, as used in the description and the claims section of the instant disclosure, are intended to be interpreted broadly to encompass a mechanical connection or a connection via a medium, whether direct or indirect. The terms "inner", "outer", "upper", "lower", and the like, are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0061] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "disposed on a side of" another element or layer, it can be directly on a side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there is no intervening element or layer. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] VA type liquid crystal display panel is a liquid crystal vertical alignment display panel, due to its higher contrast ratio and high transmittance and other advantages in TV TV and display MNT product application more and more widely, common VA vertical alignment technology has PSVA, UV2A, MVA, and so on, vertical alignment of liquid crystal display section diagram as shown in figure 1. Due to the vertical alignment of the display panel, the display screen is subjected to the pressing or extrusion of external force will produce concave, then the array substrate 001 and the spacing gap of the opposite substrate 002 is small, its liquid crystal layer 003 is very easy to be subjected to the change of liquid crystal cell thickness and produce alignment disorder, reflected to the liquid crystal display is extruded at the place of light and other location different, resulting in display trace Mura, as shown in figure 2, but with the opposite substrate 002 recovery, liquid crystal cell thickness restores the initial, with the liquid crystal also restores the initial state, trace Mura disappears. Therefore, the vertical alignment of liquid crystal panel is very sensitive to the change of liquid crystal cell thickness, especially in MNT display product use distance from the user distance is close (≈50cm), so that the display is easy to be subjected to the pressing of external force and produce trace Mura problem, in ≤5s recovery is considered normal, >5s recovery is considered to exist trace Mura display panel.

[0063] The display panel using the UV2A vertical alignment technology generates trace Mura after a finger or a hard object is swiped across the display panel, and the trace Mura does not disappear within 5 seconds, as shown in FIG. 3. The actual trace Mura generated after the finger is swiped. By microscopically observing the pixel display effect, it is found that the display alignment of the pixels at the trace Mura position is obviously abnormal. FIG. 4 is a dark line display of normal liquid crystal alignment, which presents a swastika shape. FIG. 5 is a dark line display of abnormal liquid crystal alignment after pressing, and it can be obviously seen that the dark lines of the pixels in the dashed line are abnormally distributed, which causes the pixels at the position to display differently from other pixels and form trace Mura defects. FIG. 6 is a related pixel electrode design. As shown in FIG. 6, in the pixel electrode, the first pixel electrode part P1 can be electrically connected with the drain of the transistor through a pixel via hole V, and the first pixel electrode part P1 and the second pixel electrode part P2 of the pixel opening area are connected as a whole through a block part C'. Because of the via hole V design, the film thickness at the first pixel electrode part P1 is smaller than that at the second pixel electrode part P2, which causes the liquid crystal at the pixel via hole to have a different azimuth angle than the normally aligned liquid crystal in the pixel opening area when the liquid crystal is aligned. When an external force is pressed, the cell gap at the pressed position is reduced, and the liquid crystal will flow under the pressure. The liquid crystal in the via hole V is squeezed into the pixel opening area. When the azimuth angle of the disordered liquid crystal in the via hole V is opposite to that of the liquid crystal in the pixel opening area, the liquid crystal in the pixel opening area will be abnormally oriented and appear disordered dark lines. When the external force is removed, the cell gap of the liquid crystal is restored, and the liquid crystal is redistributed and filled. However, the existence of the block part C' causes the liquid crystal alignment in the pixel opening area to be easily affected by the unstable electric field in the disordered liquid crystal area, so that the disordered dark lines in the pixel opening area do not disappear for a long time, causing display problems after pressing and causing trace Mura defects.

[0064] To improve the above technical problems, an array substrate is provided in the embodiments of the present disclosure. FIG. 7 is a structure schematic diagram of one sub-pixel in the array substrate provided by the embodiments of the present disclosure. FIG. 8 is an enlarged structure schematic diagram of the Z1 area in FIG. 7. FIG. 9 is a cross-sectional structure schematic diagram along the I-I' line in FIG. 7. FIG. 10 is a light efficiency simulation diagram of the sub-pixel shown in FIG. 7. As shown in FIGS. 7 to 9, in the array substrate provided by the embodiments of the present disclosure, the array substrate can include:

[0065] The substrate 101 includes a pixel opening area O, which can include a red sub-pixel opening R corresponding to a red sub-pixel, a green sub-pixel opening G corresponding to a green sub-pixel, a blue sub-pixel opening B corresponding to a blue sub-pixel, and the like. Optionally, the red sub-pixel, the green sub-pixel, and the blue sub-pixel constitute one pixel, and the pixel can be arranged in a row direction X or a column direction Y, and the like. In some embodiments, the substrate 101 can be a substrate allowing visible light to pass through, such as a glass, quartz, plastic, or the like.

[0066] The transistor 102, which does not overlap the pixel opening region O, can be a bottom-gate transistor, a top-gate transistor or a dual-gate transistor, and the active layer material of the transistor 102 can be single-crystal silicon a-si, polycrystalline silicon poly, indium gallium zinc oxide IGZO, etc.

[0067] The insulating layer 103 includes a via V, and the orthogonal projection of the via V on the substrate substrate 101 overlaps the orthogonal projection of the first electrode d of the transistor 102 on the substrate substrate 101; in some embodiments, the insulating layer 103 can include an organic insulating layer 1031 and an interlayer dielectric layer 1032, and in other embodiments, the insulating layer 103 can include an organic insulating layer 1031, an interlayer dielectric layer 1032 and a color resistance layer 1033; in some embodiments, the color resistance layer 1033 can also be located on the opposite substrate. The first electrode d of the transistor 102 can be a source electrode or a drain electrode, and to enhance the electrical connection effect, the orthogonal projection of the via V on the substrate substrate 101 can be located within the orthogonal projection of the first electrode d of the transistor 102 on the substrate substrate 101.

[0068] The pixel electrode 104 includes a first pixel electrode part P1, a second pixel electrode part P2 and at least one connecting part C; wherein the first pixel electrode part C1 is electrically connected to the first electrode d of the transistor 103 through the via V; the second pixel electrode part P2 at least partially covers the pixel opening region O, and the second pixel electrode part P2 includes a first edge P21 close to the first pixel electrode part P1; the at least one connecting part C is connected to the first pixel electrode part P1, and the at least one connecting part C is connected to part of the first edge P21. Optionally, the material of the pixel electrode 104 includes but is not limited to at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO).

[0069] In the related embodiments shown in FIG. 6, the first pixel electrode part P1 and the second pixel electrode P2 are connected through the whole part C', which will cause the liquid crystal alignment of the first pixel electrode part P2 to contact more with the liquid crystal alignment of the second pixel electrode part P2. The embodiments of the present disclosure separate the first pixel electrode part P1 and the second pixel electrode part P2, and connect them using the at least one connecting part C in the form of a trace, which reduces the contact between the liquid crystal alignment of the second pixel electrode part P2 and the abnormal alignment liquid crystal of the first pixel electrode part P1, as shown in FIG. 9, there is no pixel electrode pattern in the Z2 region (here the black matrix BM on the opposite substrate side blocks light, and there is no worry about light leakage), which avoids the influence of the change of the electric field in the liquid crystal turbulence area at the pixel via V on the normal alignment of the liquid crystal in the pixel opening region O when the box thickness changes due to pressing, so that the liquid crystal in the pixel opening region O can quickly recover to the initial state without being affected by other electric field forces when the box thickness recovers, thereby avoiding trace Mura defects.

[0070] In addition, the present disclosure simulates the dark line relationship between the first pixel electrode part P1 and the second pixel electrode part P2 by optical simulation, as shown in FIG. 10. As shown in FIG. 10, in the present disclosure, the pixel liquid crystal disordered area is not in direct contact with the vertical dark line, but is first converted into a horizontal direction and then into a vertical direction. This avoids the influence of the disordered area electric field on the vertical dark line of the pixel opening area O when an external force is applied, ensures that the dark line of the pressed pixel opening area O is similar to or even the same as the dark line of the unpressed pixel opening area O, and thus avoids the abnormal dark line of the pressed pixel opening area O leading to trace Mura defects in pixel display.

[0071] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, FIG. 11 is another schematic structural diagram of one sub-pixel in the array substrate provided by the embodiments of the present disclosure, FIG. 12 is an enlarged schematic structural diagram of the Z3 area in FIG. 11, FIG. 13 is a light efficiency simulation diagram of the sub-pixel shown in FIG. 11, FIG. 14 is another schematic structural diagram of one sub-pixel in the array substrate provided by the embodiments of the present disclosure, FIG. 15 is an enlarged schematic structural diagram of the Z4 area in FIG. 14, FIG. 16 is another schematic structural diagram of one sub-pixel in the array substrate provided by the embodiments of the present disclosure, and FIG. 17 is an enlarged schematic structural diagram of the Z5 area in FIG. 16.

[0072] As shown in FIGS. 11 to 17, in the array substrate provided by the embodiments of the present disclosure, a data line 105 extending along the column direction Y can also be included, and the data line 105 is electrically connected with the second electrode s of the transistor 102. The first edge P21 of the second pixel electrode part P2 can include a first end portion ED1 away from the data line 105, a second end portion ED2 close to the data line 105, and a middle portion MD between the first end portion ED1 and the second end portion ED2. At least one connecting portion C can connect the first pixel electrode part P1 and part of the first edge P21 of the second pixel electrode part P2 in proximity. Optionally, the at least one connecting portion C includes at least one of a first connecting portion C1, a second connecting portion C2, and a third connecting portion C3, wherein the first connecting portion C1 extends from one side of the first pixel electrode part P1 away from the data line 105 to the first end portion ED1, the second connecting portion C2 extends from one side of the first pixel electrode part P1 close to the second pixel electrode part P2 towards the data line 105 and then turns to the second end portion ED2, and the third connecting portion C3 directly extends from one side of the first pixel electrode part P1 close to the second pixel electrode part P2 to the middle portion MD. As shown in the light efficiency simulation diagram in FIG. 13, the vertical dark line of the pixel opening area O is not directly connected with the disordered alignment liquid crystal at the via V, which reduces the influence of the disordered electric field on the vertical dark line, and thus trace Mura defects can be improved.

[0073] In some embodiments, FIG. 18 shows a structure diagram of 2*2 sub-pixels in an array substrate provided by embodiments of the present disclosure, FIG. 19 shows a structure diagram of a layer where a gate line is located in FIG. 18, FIG. 20 shows a structure diagram of an active layer in FIG. 18, FIG. 21a shows a structure diagram of a layer where a data line is located in FIG. 18, FIG. 21b shows another structure diagram of a layer where a data line is located provided by embodiments of the present disclosure, FIG. 22 shows a structure diagram of a layer where a via is located in FIG. 18, and FIG. 23 shows a structure diagram of a layer where a pixel electrode is located in FIG. 18. As shown in FIGS. 18 to 20, 21a, 21b, 22 and 23, in the above-mentioned array substrate provided by embodiments of the present disclosure, a first common electrode line 106 can also be included, which can be arranged in the same layer and of the same material as the gate line 107. Optionally, the orthogonal projection of the first common electrode line 106 on the substrate 101 and the orthogonal projection of the first electrode d of the transistor 102 on the substrate 101 have an overlapping area OL, so that the first common electrode line 106 and the first electrode d of the transistor 102 form a storage capacitor Cst at the overlapping area OL. In some embodiments, in order to increase the storage capacitor Cst, the overlapping area OL and the orthogonal projection of the first pixel electrode part P1 on the substrate 101 can be overlapped with each other, and the orthogonal projection of the overlapping area OL and the connection part C on the substrate 101 can be overlapped with each other.

[0074] In some embodiments, in the above-mentioned array substrate provided by embodiments of the present disclosure, as shown in FIGS. 18, 19, 21a, 21b and 23, the second pixel electrode part P2 includes a second edge P22 close to one side of the data line 105 and a third edge P23 away from the other side of the data line 105; the orthogonal projection of the first common electrode line 106 on the substrate 101 and the orthogonal projection of the second edge P22 on the substrate 101 can be overlapped with each other, and / or the orthogonal projection of the first common electrode line 106 on the substrate 101 and the orthogonal projection of the third edge P23 on the substrate 101 can be overlapped with each other, so that the first common electrode line 106 and the second edge P22 and / or the third edge P23 of the second pixel electrode part P2 form a storage capacitor Cst. In this way, the storage capacitor Cst of the present disclosure can include the first common electrode line 106 and the first electrode d of the transistor 102, the first common electrode line 106 and the second edge P22 of the second pixel electrode part P2, and / or the first common electrode line 106 and the third edge P23 of the second pixel electrode part P2.

[0075] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 18, 21a, 21b and 23, a second common electrode line 108 which is in the same layer and made of the same material as the pixel electrode 104 can also be included; the orthogonal projection of the second common electrode line 108 on the substrate 101 and the orthogonal projection of the data line 105 on the substrate 101 overlap with each other, for example, the orthogonal projection of the second common electrode line 108 on the substrate 101 covers the orthogonal projection of the data line 105 on the substrate 101 between adjacent pixel opening regions O in the row direction X, so as to shield the interference of the data line 105 on the pixel electrode 104 through the second common electrode line 108, and improve the horizontal stripe defect.

[0076] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 18, 19 and 23, a third common electrode line 109 which is in the same layer and made of the same material as the pixel electrode 104 can also be included; the third common electrode line 109 is electrically connected with the second common electrode line 108, and the orthogonal projection of the third common electrode line 109 on the substrate 101 and the orthogonal projection of the gate line 107 on the substrate 101 overlap with each other. The second common electrode line 108 and the third common electrode line 109 cross with each other to form a mesh structure, which can effectively improve the uniformity of the common voltage, improve the shielding effect, and effectively improve the horizontal stripe defect. In some embodiments, the first common electrode line 106 and the mesh common electrode line (including the second common electrode line 108 and the third common electrode line 109) are not connected with each other in the display area AA, and the first common electrode line 106 and the mesh common electrode line (including the second common electrode line 108 and the third common electrode line 109) can be loaded with a common voltage signal through the wiring in the frame area.

[0077] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 18 and FIG. 21a, the transistor 102 electrically connected to the pixel electrode 104 overlapping the red pixel opening region R is the first transistor TR, the transistor 102 electrically connected to the pixel electrode 104 overlapping the green pixel opening region G is the second transistor TG, and the transistor 102 electrically connected to the pixel electrode 104 overlapping the blue pixel opening region B is the third transistor TB; optionally, the first electrode d of the first transistor TR can have a projection area on the substrate 101 that is substantially the same as the first electrode d of the second transistor TG, and the first electrode d of the first transistor TR can have a projection area on the substrate 101 that is larger than the first electrode d of the third transistor TB. In this way, the storage capacitance Cst of the blue sub-pixel can be made smaller than the storage capacitance Cst of the red sub-pixel or the storage capacitance Cst of the green sub-pixel, thereby reducing the brightness of blue light and improving color cast defects. In some embodiments, the storage capacitance can also be reduced by reducing the overlapping area of the first common electrode line 106 and the second pixel electrode portion P2, and at this time, to simplify the manufacturing process, the first electrode d of the first transistor TR, the first electrode d of the second transistor TG, and the first electrode d of the third transistor TB can have the same pattern, as shown in FIG. 21b.

[0078] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 23, the second pixel electrode portion P2 can be a block electrode; the array substrate can further include a first alignment layer 110, and the first alignment layer 110 can have multiple alignments in the pixel opening region O, so that the pixel opening region O forms multiple domains with different alignments of liquid crystal molecules. In other embodiments, the second pixel electrode portion P2 can be a slit electrode, and the slits of the slit electrode can have multiple extension directions in the pixel opening region O, thereby forming domains with different alignments in the pixel opening region O.

[0079] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 9, the array substrate can further include a second inorganic insulating layer 111 between the layer where the first electrode d of the transistor 102 is located and the layer where the first common electrode line 106 is located. The other indispensable components of the array substrate should be understood by those skilled in the art, and will not be described here again, nor should it be regarded as a limitation on the present disclosure.

[0080] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure is shown in FIG. 24, which comprises an array substrate 001 and a counter substrate 002 opposite to each other, wherein the array substrate 001 is the array substrate 001 provided by the embodiments of the present disclosure. Since the principle of solving the problem of the display panel is similar to that of the array substrate 001, the implementation of the display panel can refer to the above-mentioned embodiments of the array substrate, and the repeated parts will not be described here.

[0081] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the counter substrate 002 comprises a substrate 202 and a black matrix 202 covering the area outside the pixel opening region O and the via V; optionally, the counter substrate 002 can further comprise a common electrode 203 located on the side of the black matrix 202 facing the array substrate 001, and the common electrode 203 is arranged opposite to at least the second pixel electrode part P2, for example, the common electrode 203 can be arranged on the entire display area AA. In addition, the display panel can further comprise a liquid crystal layer 003 arranged between the array substrate 001 and the counter substrate 002, a first alignment layer 110 arranged on the side of the array substrate 001 facing the counter substrate 002, a first polarizer 004 arranged on the side of the array substrate 001 away from the counter substrate 002, a second alignment layer 204 arranged on the side of the counter substrate 002 facing the array substrate 001, and a second polarizer 005 arranged on the side of the counter substrate 002 away from the array substrate 001, wherein the first alignment layer 110 and the second alignment layer 204 can align the liquid crystal molecules in the plurality of domain regions, and the polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. The other indispensable components of the display panel should be understood by those skilled in the art, which will not be described here and should not be regarded as a limitation of the present disclosure.

[0082] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure is shown in FIG. 25, which comprises the above-mentioned display panel PNL provided by the embodiments of the present disclosure and a backlight module BLU located on the light entering side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can comprise a lamp strip, a reflection sheet, a light guide plate, a diffusion sheet, a prism group and the like arranged in a stack, and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can comprise a matrix light source, a reflection sheet, a diffusion plate and a brightness enhancement film arranged in a stack on the light emitting side of the matrix light source, and the reflection sheet comprises an opening corresponding to the position of each lamp bead in the matrix light source. The lamp bead in the lamp strip and the lamp bead in the matrix light source can be a light emitting device (LED), such as a quantum dot light emitting device (QLED), a micro light emitting device (such as Mini LED, Micro LED) and the like.

[0083] Among them, the micro light emitting device of sub-millimeter level or even micron level is also a self-luminous device like the organic light emitting device (OLED). It has a series of advantages such as high brightness, ultra-low delay, ultra-large viewing angle, etc. like the organic light emitting device. And because the inorganic light emitting device emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared with the organic light emitting device based on organic matter. When the micro light emitting device is used as a backlight source, it can realize more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the light and dark areas of the screen, and optimize the visual experience.

[0084] In some embodiments, the display device provided by the embodiments of the present disclosure can be a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any product or component with display function. Optionally, the display device provided by the present disclosure includes but is not limited to radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip, etc. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), etc. For example, the control chip can also include a memory, and can also include a power module, etc., and realizes the power supply and signal input and output functions through the additionally arranged wires, signal lines, etc. For example, the control chip can also include hardware circuit and computer executable code, etc. The hardware circuit can include conventional very large scale integration (VLSI) circuit or gate array, and existing semiconductors such as logic chips, transistors, or other discrete elements; the hardware circuit can also include field programmable gate array, programmable array logic, programmable logic device, etc. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or different component arrangements.

[0085] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0086] It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that such changes and modifications be included within the scope of the present disclosure.

Claims

1. An array substrate, wherein, Comprising: a substrate substrate comprising a pixel opening region; a transistor, the transistor and the pixel opening region not overlapping each other; an insulating layer comprising a via, a projection of the via on the substrate substrate and a projection of a first electrode of the transistor on the substrate substrate overlapping each other; a pixel electrode comprising a first pixel electrode part, a second pixel electrode part and at least one connecting part; wherein the first pixel electrode part is electrically connected to the first electrode of the transistor through the via; the second pixel electrode part at least partially covers the pixel opening region, the second pixel electrode part comprises a first edge close to a side of the first pixel electrode part; the at least one connecting part is connected to the first pixel electrode part, and the at least one connecting part is connected to part of the first edge.

2. The array substrate of claim 1, wherein, Further comprising the data line, the first edge comprises a first end portion away from the data line; The at least one connecting part comprises a first connecting part, the first connecting part extends from a side of the first pixel electrode part away from the data line to be connected to the first end portion.

3. The array substrate of claim 1 or 2, wherein, Further comprising the data line, the first edge comprises a second end portion close to the data line; The at least one connecting part comprises a second connecting part, the second connecting part extends from a side of the first pixel electrode part close to the second pixel electrode part towards the data line and then turns to be connected to the second end portion.

4. The array substrate according to any one of claims 1 to 3, wherein, Further comprising the data line, the first edge comprises a first end portion away from the data line, a second end portion close to the data line, and an intermediate portion between the first end portion and the second end portion; The at least one connecting part comprises a third connecting part, the third connecting part directly extends from a side of the first pixel electrode part close to the second pixel electrode part to be connected to the intermediate portion.

5. The array substrate according to any one of claims 1 to 4, wherein, Further comprising a first common electrode line, a projection of the first common electrode line on the substrate substrate and a projection of the first electrode of the transistor on the substrate substrate have an overlapping area.

6. The array substrate of claim 5, wherein, The overlapping area and a projection of the first pixel electrode part on the substrate substrate overlap each other, and the overlapping area and a projection of the at least one connecting part on the substrate substrate overlap each other.

7. The array substrate of claim 5 or 6, wherein, Further comprising the data line, the second pixel electrode part comprises a second edge close to a side of the data line, and a third edge away from a side of the data line; The projection of the first common electrode line on the substrate substrate and the projection of the second edge on the substrate substrate overlap each other, and / or the projection of the first common electrode line on the substrate substrate and the projection of the third edge on the substrate substrate overlap each other.

8. The array substrate according to any one of claims 1 to 7, wherein, Further comprising a data line and a second common electrode line in the same layer as the pixel electrode; The projection of the second common electrode line on the substrate substrate and the projection of the data line on the substrate substrate overlap each other.

9. The array substrate of claim 8, wherein, Further comprising a gate line and a third common electrode line in the same layer as the pixel electrode; The third common electrode line is electrically connected with the second common electrode line, and a projection of the third common electrode line on the substrate substrate overlaps with a projection of the gate line on the substrate substrate.

10. The array substrate according to any one of claims 1 to 9, wherein, The pixel opening region comprises a red pixel opening region, a blue pixel opening region and a green pixel opening region. The transistor electrically connected with the pixel electrode overlapping with the red pixel opening region is a first transistor, the transistor electrically connected with the pixel electrode overlapping with the green pixel opening region is a second transistor, and the transistor electrically connected with the pixel electrode overlapping with the blue pixel opening region is a third transistor. The first electrode of the first transistor has a projection area on the substrate substrate which is substantially the same as a projection area of the first electrode of the second transistor on the substrate substrate, and the first electrode of the first transistor has a projection area on the substrate substrate which is larger than a projection area of the first electrode of the third transistor on the substrate substrate.

11. The array substrate according to any one of claims 1 to 10, wherein, The second pixel electrode part is a block electrode. The array substrate further comprises an alignment layer, and the alignment layer has a plurality of alignments in the pixel opening region.

12. The array substrate of any one of claims 1 to 10, wherein, The second pixel electrode part is a slit electrode, and the slit of the slit electrode has a plurality of extension directions in the pixel opening region.

13. A display panel, wherein, The display panel comprises the array substrate and the opposite substrate.

14. The display panel of claim 13, wherein, The opposite substrate comprises a black matrix and a common electrode on a side of the black matrix facing the array substrate, wherein the common electrode is arranged opposite to at least the second pixel electrode part, and a projection of the black matrix on the substrate substrate covers the via hole.

15. A display device, wherein, The display panel comprises the display panel and a backlight module on a light-incident side of the display panel.

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