Display substrate and electronic paper display apparatus

Abstract

A display substrate and an electronic paper display apparatus. The display substrate comprises a base substrate (10), a plurality of gate lines (Gate), a plurality of data lines (Data), and a plurality of pixel units arranged in an array. The plurality of pixel units are divided into a plurality of groups, each group comprising two rows of pixel units. Gate lines (Gate) connected to the two rows of pixel units located in a same group are configured to be loaded with a same scanning signal. The pixel units located in a same column are provided with data signals by two data lines (Data), and the pixel units which are located in the same column and the connected gate lines (Gate) of which are loaded with the same scanning signal are provided data signals by different data lines (Data). For pixel units located in the same column and the two data lines (Data) providing data signals for the pixel units in said column, the orthographic projections of the pixel units on the base substrate (10) overlap with the orthographic projection of one of the two data lines (Data) on the base substrate (10) and do not overlap with the orthographic projection of the other of the two data lines (Data) on the base substrate (10).

Description

Display substrate and electronic paper display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate and an electronic paper display device. BACKGROUND

[0002] With the development of electronic paper display devices, electronic paper display devices have gradually integrated into daily life. Since electronic paper display devices have the advantages of convenient reading, convenient carrying, resource saving, low energy consumption, fast transmission speed and the like, the electronic paper display devices have broad development prospects.

[0003] SUMMARY

[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display substrate and an electronic paper display device.

[0005] The display substrate provided by the present disclosure comprises a substrate, a plurality of gate lines and a plurality of data lines arranged on the substrate, and a plurality of pixel units arranged in an array; the plurality of gate lines are arranged side by side and spaced apart along the column direction, and each extends along the row direction; the plurality of data lines are arranged side by side and spaced apart along the row direction, and the main body part of each data line extends along the column direction.

[0006] The plurality of pixel units are divided into a plurality of groups, each group comprising two rows of pixel units, and the gate lines connected to the two rows of pixel units in the same group are configured to load the same scanning signal; the pixel units in the same column are provided with data signals by two data lines, and the data lines providing data signals for the pixel units in the same column and loaded with the same scanning signal are different; wherein for the pixel units in the same column and the two data lines providing data signals for the pixel units in the column, the pixel units and one of the two data lines have overlapping projections on the substrate, and the other one has no overlapping projection on the substrate.

[0007] In some examples, the pixel electrodes in the pixel units in the same column are equal in size, and the projections of the pixel electrodes on the substrate each comprise a first side edge and a second side edge arranged opposite along the row direction; the extension lines of the first side edges of the pixel units in the same column coincide, and the extension lines of the second side edges of the pixel units in the same column coincide.

[0008] In some examples, the data lines include first data line segments and second data line segments arranged alternately and spaced apart along the column direction, and connecting segments connecting the first data line segments and the second data line segments arranged adjacently; the first data line segments and the second data line segments of the data lines have a certain spacing; for two data lines arranged adjacently and a column of pixel units provided with data line voltages by the two data lines, two pixel units in the same group and in different rows have a pixel electrode in one of the pixel units overlapping a normal projection on the substrate of the first data line segment of one of the data lines, and a pixel electrode in the other of the pixel units overlapping a normal projection on the substrate of the second data line segment of the other of the data lines.

[0009] In some examples, the pixel electrodes in the pixel units in the same column have equal sizes, and the normal projections of the pixel electrodes on the substrate include first side edges and second side edges arranged oppositely along the row direction; the first side edges of at least some of the pixel units in the same column have a certain spacing between the extensions of the first side edges; the second side edges of at least some of the pixel units in the same column have a certain spacing between the extensions of the second side edges.

[0010] In some examples, for two data lines arranged adjacently and a column of pixel units provided with data line voltages by the two data lines, the extensions of the first side edges of the pixel electrodes of the pixel units provided with data signals by one of the data lines coincide, and the extensions of the second side edges of the pixel electrodes of the pixel units provided with data signals by the other of the data lines coincide.

[0011] In some examples, two rows of the pixel units in the same group are arranged adjacently.

[0012] In some examples, two rows of the pixel units in the same group are spaced apart by one row of the pixel units.

[0013] In some examples, the display substrate further includes a gate drive circuit; two gate lines providing scan signals for the pixel units in the same group are connected to the gate drive circuit through the same signal lead line.

[0014] In some examples, the gate lines have first ends and second ends arranged oppositely, and part of the signal lead lines are connected to the first ends of the gate lines, and part of the signal lead lines are connected to the second ends of the gate lines.

[0015] In some examples, a first end of the gate line providing a scanning signal to the pixel unit in the odd number array is connected to the signal lead; and a second end of the gate line providing a scanning signal to the pixel unit in the odd number array is connected to the signal lead.

[0016] In some examples, the pixel unit further comprises a common electrode located on a side of the pixel electrode close to the substrate, and a normal projection of the common electrode and the pixel electrode on the substrate at least partially overlaps.

[0017] In some examples, the pixel unit comprises a thin film transistor, a gate of the thin film transistor is connected to the gate line, a source of the thin film transistor is connected to the data line, and a drain of the thin film transistor is connected to the pixel electrode.

[0018] In some examples, the gate of the thin film transistor is connected to the gate line as an integral structure, and is arranged in the same layer as the common electrode.

[0019] In some examples, the source, the drain and the data line of the thin film transistor are arranged in the same layer, and an interlayer insulating layer is arranged on a side of the layer where the source, the drain and the data line of the thin film transistor are located away from the substrate, and the pixel electrode is connected to the pixel electrode through a via hole penetrating through the interlayer insulating layer.

[0020] Embodiments of the present disclosure provide an electronic paper display device comprising the display substrate as described above. BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1 is a schematic diagram of an example display substrate.

[0022] FIG. 2 is a partial top view of an example display substrate.

[0023] FIG. 3 is a cross-sectional view of A-A' of FIG. 2.

[0024] FIG. 4 is a partial top view of a display substrate according to an embodiment of the present disclosure.

[0025] FIG. 5 is a top view of a pixel unit of a display substrate according to an embodiment of the present disclosure.

[0026] FIG. 6 is a schematic diagram of a first conductive layer of a display substrate according to an embodiment of the present disclosure.

[0027] FIG. 7 is a schematic diagram of a semiconductor layer of a display substrate according to an embodiment of the present disclosure.

[0028] FIG. 8 is a schematic diagram of a second conductive layer of a display substrate according to an embodiment of the present disclosure.

[0029] FIG. 9 is a schematic diagram of a third conductive layer of a display substrate according to an embodiment of the present disclosure.

[0030] FIG. 10 is a schematic view of a display substrate according to an embodiment of the present disclosure.

[0031] FIG. 11 is a top view of a pixel electrode and a data line according to a first example of an embodiment of the present disclosure.

[0032] FIG. 12 is a partial top view of a display substrate according to the first example of an embodiment of the present disclosure.

[0033] FIG. 13 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 12.

[0034] FIG. 14 is a partial top view of a display substrate according to a second example of an embodiment of the present disclosure.

[0035] FIG. 15 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 14.

[0036] FIG. 16 is a partial top view of another display substrate according to the second example of an embodiment of the present disclosure.

[0037] FIG. 17 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 16.

[0038] FIG. 18 is a partial top view of a display substrate according to a third example of an embodiment of the present disclosure.

[0039] FIG. 19 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 18.

[0040] FIG. 20 is a partial top view of another display substrate according to the third example of an embodiment of the present disclosure.

[0041] FIG. 21 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 20.

[0042] FIG. 22 is a partial top view of a display substrate according to a fourth example of an embodiment of the present disclosure.

[0043] FIG. 23 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 22.

[0044] FIG. 24 is a partial top view of another display substrate according to the fourth example of an embodiment of the present disclosure.

[0045] FIG. 25 is a top view of a pixel electrode and a data line of the display substrate shown in FIG. 24. DETAILED DESCRIPTION

[0046] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0047] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0048] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure shall have the ordinary meanings understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0049] As used herein, "parallel", "perpendicular" includes the stated case and the case similar to the stated case within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of a specific quantity (i.e., the limitation of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular can also be, for example, within 5°. It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0050] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and for purposes of illustration only. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of the regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0051] FIG. 1 is a schematic view of an exemplary display substrate, FIG. 2 is a partial plan view of an exemplary display substrate, and FIG. 3 is a cross-sectional view of A-A' of FIG. 2. As shown in FIGS. 1-3, the display substrate can be applied to an electronic paper display device. The display substrate in the example can specifically include a substrate 10, a plurality of gate lines Gate, a plurality of data lines Data, and a plurality of pixel units provided on the substrate 10. Each pixel unit includes a thin film transistor 1, a pixel electrode 2, and a common electrode 3.

[0052] The plurality of pixel units are arranged in an array and divided into a plurality of groups arranged side by side in a column direction Y, each group including two rows of pixel units arranged in the column direction Y. In FIGS. 1 and 2, only every two adjacent rows of pixel units are taken as a group. Among them, the pixel units in the same row are connected to the same gate line Gate, and the gate lines Gate connected to the pixel units in the same group are connected to the gate drive circuit 200 through the same signal lead 100. The pixel units in the same column are connected to the same data line Data, and the pixel units in the same column and provided with the same scanning signal by the same signal lead 100 are connected to different data lines Data. Specifically, for each pixel unit, the gate of the thin film transistor 1 is connected to the corresponding gate line Gate, the source 15 of the thin film transistor 1 is connected to the corresponding data line Data, and the drain 16 of the thin film transistor 1 is connected to the pixel electrode 2. It should be noted that only the plan views of four pixel units are shown in FIG. 2, which are respectively denoted as P1, P2, P3, and P4. In addition, two data lines Data and four gate lines Gate corresponding to the four pixel units are shown in FIG. 2, the two data lines Data are respectively denoted as D1 and D2, and the four gate lines Gate are respectively denoted as G1, G2, G3, and G4. The four gate lines Gate are respectively denoted as G1, G2, G3, and G4 only to represent that they respectively correspond to four rows of pixel units, among which G1 and G2 are connected together, and G3 and G4 are connected together.

[0053] The thin film transistor 1 of each pixel unit can be a top-gate thin film transistor 1 or a bottom-gate thin film transistor 1. The thin film transistor 1 can be selected from any one of a single-gate thin film transistor 1, a double-gate thin film transistor 1, a horizontal thin film transistor 1, a vertical thin film transistor 1, and the like. The types of the thin film transistor 1 in each pixel unit can be the same or different. In the embodiments of the present disclosure, only the case where the thin film transistor 1 is selected from a double-gate thin film transistor 1 is taken as an example. Specifically, referring to FIG. 3, the thin film transistor 1 includes a first gate 11 and a second gate 12 disposed on a substrate 10, a first active layer 13 and a second active layer 14, a source 15, a drain 16, and a connection electrode 17. The first active layer 13 and the second active layer 14 are disposed on a side of the first gate 11 and the second gate 12 away from the substrate 10. The first gate 11 and the second gate 12 are disposed in the same layer, and the first active layer 13 and the second active layer 14 are disposed in the same layer. A gate insulating layer GI is disposed between the layer in which the first gate 11 and the second gate 12 are disposed and the layer in which the first active layer 13 and the second active layer 14 are disposed. The orthographic projection of the first active layer 13 and the first gate 11 on the substrate 10 at least partially overlaps, and the orthographic projection of the second active layer 14 and the second gate 12 on the substrate 10 at least partially overlaps. The source 15, the drain 16, and the connection electrode 17 are disposed in the same layer on a side of the active layer away from the substrate 10. The source 15 is connected to the first active layer 13, the drain 16 is connected to the second active layer 14, and the connection electrode 17 connects the first active layer 13 and the second active layer 14.

[0054] The first gate 11 and the second gate 12 of the thin film transistor 1 in each pixel unit are connected to a gate line Gate. The source 15 of the thin film transistor 1 is connected to a data line Data, and the drain 16 of the thin film transistor 1 is connected to a pixel electrode 2. The pixel electrode 2 is usually disposed on a side of the layer in which the source 15 and the drain 16 of the thin film transistor 1 are disposed away from the substrate 10. An interlayer insulating layer 4 is disposed between the layer in which the source 15 and the drain 16 of the thin film transistor 1 are disposed and the layer in which the pixel electrode 2 is disposed. The interlayer insulating layer 4 includes a passivation layer PVX and a planarization layer PLN stacked in sequence away from the substrate 10. The pixel electrode 2 in each pixel unit is connected to the drain 16 of the thin film transistor 1 through a via hole penetrating the passivation layer PVX and the planarization layer PLN.

[0055] Continuing to refer to FIG. 2, in order to improve display uniformity and facilitate wiring, a gate line Gate is arranged on the side of the pixel unit in the current row close to the pixel unit in the next row, and a column of pixel units is correspondingly arranged between the two data lines Data. For the two data lines Data arranged adjacently and the column of pixel units correspondingly arranged therebetween, the orthogonal projection of the pixel electrode 2 in the pixel unit on the substrate 10 overlaps the orthogonal projection of the two data lines Data on the substrate 10. In this way, the data line Data and the pixel electrode 2 will form a coupling capacitance, resulting in a large load capacitance of the pixel unit and a large power consumption.

[0056] FIG. 4 is a partial top view of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 4, the display substrate according to the embodiment of the present disclosure includes a substrate 10, a plurality of gate lines Gate and a plurality of data lines Data arranged on the substrate 10, and a plurality of pixel units arranged in an array. The plurality of gate lines Gate are arranged side by side and spaced apart along the column direction Y and extend along the row direction X. The plurality of data lines Data are arranged side by side and spaced apart along the row direction X, and the main body portions of the data lines Data extend along the column direction Y. It should be noted that only the top views of four pixel units are shown in FIG. 4, which are denoted as P1, P2, P3, and P4. In addition, two data lines Data and four gate lines Gate corresponding to the four pixel units are shown in FIG. 4, which are denoted as D1 and D2, and G1, G2, G3, and G4, respectively. The four gate lines G1, G2, G3, and G4 are only used to represent that they correspond to four rows of pixel units, respectively. In FIG. 4, G1 and G2 are connected together, and G3 and G4 are connected together. The plurality of pixel units are divided into a plurality of groups, each group including two rows of pixel units, and the gate lines Gate connected to the two rows of pixel units in the same group are configured to load the same scanning signal. The pixel units in the same column are provided with data signals by two data lines Data, and the data lines Data providing data signals for the pixel units in the same column and the gate lines Gate connected to the pixel units are loaded with the same scanning signal are different. In the embodiment of the present disclosure, for the pixel units in the same column and the two data lines Data providing data signals for the pixel units, the orthogonal projection of the pixel unit on the substrate 10 overlaps one of the two data lines Data, and does not overlap the other data line Data.

[0057] That is, a column of pixel units is arranged between two adjacent data lines Data, for each pixel electrode 2 in the column of pixel units, only one of the two data lines Data has an intersection with the orthogonal projection of the pixel electrode 2 on the substrate 10, so that the coupling capacitance formed by the pixel electrode 2 and the data line Data in each pixel unit can be reduced, thereby reducing the overall load capacitance of the pixel and reducing power consumption.

[0058] In some examples, FIG. 5 is a top view of a pixel unit of a display substrate according to an embodiment of the present disclosure; as shown in FIGS. 4 and 5, the pixel unit in the embodiment of the present disclosure not only includes the pixel electrode 2 described above, but also includes a thin film transistor 1 and a common electrode 3. The gate of the thin film transistor 1 in each pixel unit is connected to a gate line Gate, the source 15 is connected to a data line Data, and the drain 16 is connected to the pixel electrode 2. The common electrode 3 is located on the side of the pixel electrode 2 close to the substrate 10, and at least partially overlaps the orthogonal projection of the pixel electrode 2 on the substrate 10, at which point the pixel electrode 2 and the common electrode 3 form an overlapping capacitance at the overlapping position.

[0059] Specifically, the thin film transistor 1 in the embodiment of the present disclosure can adopt the same thin film transistor 1 as in FIG. 3, of course, it can also adopt a different type of thin film transistor 1 from FIG. 3, and in the embodiment of the present disclosure, only the thin film transistor 1 is taken as an example to illustrate the same thin film transistor 1 as in FIG. 3. FIG. 6 is a schematic view of a first conductive layer of a display substrate according to an embodiment of the present disclosure, FIG. 7 is a schematic view of a semiconductor layer of a display substrate according to an embodiment of the present disclosure, FIG. 8 is a schematic view of a second conductive layer of a display substrate according to an embodiment of the present disclosure, and FIG. 9 is a schematic view of a third conductive layer of a display substrate according to an embodiment of the present disclosure; as shown in FIGS. 5-9, the display substrate specifically includes a first conductive layer, a gate insulating layer GI, a semiconductor layer, a second conductive layer, an interlayer insulating layer 4 composed of a passivation layer PVX and a planarization layer PLN, and a third conductive layer arranged in sequence away from the substrate 10. The first conductive layer includes the first gate line Gate and the second gate 12 of each thin film transistor 1, and the gate line Gate and the common electrode 3; the first gate line Gate and the second gate 12 are connected as an integral structure with the gate line Gate. The semiconductor layer includes the first active layer 13 and the second active layer 14 of the thin film transistor 1. The second conductive layer includes the source 15, the drain 16, the connection electrode 17, and the data line Data of the thin film transistor 1; the data line Data and the source 15 of the thin film transistor 1 are connected as an integral structure, the source 15 is connected to the first active layer 13, the drain 16 is connected to the second active layer 14, and the connection electrode 17 connects the first active layer 13 and the second active layer 14. The third conductive layer can be a transparent conductive layer, and the third conductive layer includes the pixel electrode 2; the pixel electrode 2 in each pixel unit is connected to the drain 16 of the thin film transistor 1 through a via hole penetrating the passivation layer PVX and the planarization layer PLN.

[0060] Further, with continued reference to FIG. 8, the second conductive layer can further include a common electrode line 30 for connecting the common electrodes 3. By loading the common electrode line 30 with a common voltage signal, the common electrodes 3 of the respective pixel units are caused to be applied with the same voltage signal.

[0061] In some examples, the material of the first conductive layer and the second conductive layer can be gold (Au), an alloy of gold, silver (Ag), an alloy of silver, aluminum (Al), an alloy of aluminum, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), an alloy of copper, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), an alloy of molybdenum, titanium (Ti), titanium nitride (TiNx), platinum (Pt), etc. The first conductive layer and the second conductive layer can each be a single layer or a multi-layer film layer structure.

[0062] In some examples, the material of the third conductive layer can be indium tin oxide (ITO), etc.

[0063] In some examples, the semiconductor layer can be an inorganic semiconductor material (e.g., polysilicon, amorphous silicon, etc.), an organic semiconductor material, an oxide semiconductor material (e.g., indium gallium zinc oxide, etc.).

[0064] In some examples, the material of the gate insulating layer GI can be silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbonitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI can be a single layer or a multi-layer film layer structure.

[0065] In some examples, the passivation layer PVX can be the same material as the gate insulating layer GI, and the planarization layer PLN can be an organic material.

[0066] In some examples, the display substrate not only includes the above structure, but also includes a gate driving circuit 200, two gate lines Gate providing scanning signals for the same group of pixel units, and the two gate lines Gate are connected to the gate driving circuit 200 through the same signal lead 100. That is, the gate lines Gate connected by the pixel units in the same group are connected to the gate driving circuit 200 through the same signal lead 100. Further, the gate lines Gate include oppositely arranged first ends and second ends, in order to narrow the display panel of the display substrate applying the embodiment of the present disclosure, part of the signal leads 100 are connected to the first ends of the gate lines Gate, and part of the signal leads 100 are connected to the second ends of the gate lines Gate. Further, the first ends of the gate lines Gate providing scanning signals for the pixel units in the odd group are connected to the signal leads 100; and the second ends of the gate lines Gate providing scanning signals for the pixel units in the odd group are connected to the signal leads 100.

[0067] In one example, the gate driving circuit 200 can be an integrated chip, in which case, a connection pad can be arranged on the substrate 10, the signal lead 100 is connected to the connection pad, and the chip is connected to the connection pad by bonding, to provide scanning signals for the gate lines Gate. In another example, the gate driving circuit 200 can be directly formed on the substrate 10, and is composed of a plurality of cascaded shift registers, the output end of each shift register is connected to a corresponding signal lead 100 to provide scanning signals for the gate lines Gate.

[0068] In some examples, the two rows of pixel units in the same group are arranged adjacently, that is, the same as the connection mode in FIG. 1. That is, every two rows of adjacently arranged pixel units form a group. For example, the first row of pixel units and the second row of pixel units form a group, and the third row of pixel units and the fourth row of pixel units form a group. In this case, wiring is facilitated.

[0069] In another example, FIG. 10 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 10, for each group of two rows of pixel units, the two rows of pixel units are separated by one row of pixel units. That is, the two rows of pixel units in each group are not adjacent. For example, the first row of pixel units and the third row of pixel units form a group, and the second row of pixel units and the fourth row of pixel units form a group. Since a coupling capacitance is generated between the pixel electrode 2 in the pixel unit and the gate line Gate when a scanning signal is written to the gate line Gate, when the two rows of pixel units in each group are arranged separately, the pixel electrode 2 of each pixel unit only forms a parasitic capacitance with one gate line Gate. At this time, the sizes of the parasitic capacitances are equal or approximately equal, so that there is no difference in the jump voltage of each pixel unit, thereby avoiding the occurrence of horizontal stripe defects in the refresh process. In FIG. 10, only four pixel units in the same column are labeled, which are P1, P2, P3, and P4. In addition, FIG. 10 schematically shows two data lines Data and four gate lines Gate corresponding to the four pixel units. The four gate lines Gate are represented by G1, G2, G3, and G4. The four gate lines Gate are represented by G1, G2, G3, and G4 only to represent that they correspond to four rows of pixel units, respectively. Among them, G1 and G3 are connected together, and G2 and G4 are connected together. In the embodiment of the present disclosure, in order to achieve that each pixel electrode 2 only overlaps with the orthogonal projection of one data line Data on the substrate 10, the relative positions between the pixel electrodes 2 can be changed without changing the pixel aperture ratio, or the line type of the data line Data can be changed. The following will be described in combination with specific examples.

[0070] The first example: in the display substrate in this example, every two rows of adjacent pixel units form a group, and the pixel units in the same column are provided with data voltage signals by two data lines Data. For ease of understanding, only four rows of pixel units in one column are described. In this case, two data lines Data and four gate lines Gate are provided. The scanning signals written to the gate lines Gate connected to the pixel units in the same group are the same, and the data lines Data connected to the pixel units in the same group are different.

[0071] Fig. 11 is a top view of the pixel electrode 2 and the data line Data in the first example of the embodiment of the present disclosure; as shown in Figs. 4 and 11, the shape and area of the pixel electrode 2 in each pixel unit are equal, and in Figs. 4 and 11, only the pixel electrode 2 in the shape of a rectangle is taken as an example. Each pixel electrode 2 includes a first side edge and a second side edge arranged opposite along the row direction X. The extension lines of the first side edges of the pixel electrodes 2 in the pixel units in the same column coincide, and the extension lines of the second side edges of the pixel electrodes 2 in the pixel units in the same column coincide. That is, the pixel electrodes 2 are arranged in an array. Each data line Data includes first data line D1 segments and second data line D2 segments arranged alternately and spaced apart, and a connection segment connecting the first data line D1 segment and the second data line D2 segment arranged adjacent to each other. The extension line of the first data line D1 segment and the extension line of the second data line D2 segment of the data line Data have a certain spacing.

[0072] In one example, as shown in Figs. 4 and 11, for the pixel units in the same column and the two data lines Data providing data signals for the pixel units, the pixel electrodes 2 of the pixel units in the odd number are arranged one by one with the first data line D1 segments of one of the two data lines Data, and the pixel electrodes 2 and the first data line D1 segments arranged correspondingly have overlapping projections on the substrate 10. The pixel electrodes 2 of the pixel units in the even number are arranged one by one with the second data line D2 segments of the other of the two data lines Data, and the pixel electrodes 2 and the second data line D2 segments arranged correspondingly have overlapping projections on the substrate 10.

[0073] For example, referring to Figs. 4 and 11, the two data lines Data are referred to as the first data line D1 and the second data line D2 for convenience of description. For the first pixel unit and the second pixel unit in the same group, the pixel electrode 2 of the first pixel unit has overlapping projections on the substrate 10 with the first data line D1 segments of the first data line D1 and has no overlapping projections on the substrate 10 with the first data line D1 segments of the second data line D2; the pixel electrode 2 of the second pixel unit has overlapping projections on the substrate 10 with the second data line D2 segments of the first data line D1 and has no overlapping projections on the substrate 10 with the second data line D2 segments of the second data line D2.

[0074] In another example, FIG. 12 is a partial top view of a display substrate according to a first example of embodiments of the present disclosure; FIG. 13 is a top view of pixel electrodes 2 and data lines Data of the display substrate shown in FIG. 12; as shown in FIGS. 12 and 13, for pixel units located in the same column and two data lines Data providing data signals for the pixel units, pixel electrodes 2 of pixel units located at even positions are arranged in one-to-one correspondence with a first data line D1 segment of one of the two data lines Data, and the corresponding pixel electrodes 2 and first data line D1 segment have overlapping projections on the substrate 10; pixel electrodes 2 of pixel units located at odd positions are arranged in one-to-one correspondence with a second data line D2 segment of the other of the two data lines Data, and the corresponding pixel electrodes 2 and second data line D2 segment have overlapping projections on the substrate 10.

[0075] For example, referring to FIGS. 12 and 13, the two data lines Data are referred to as a first data line D1 and a second data line D2 for ease of description. For a first pixel unit and a second pixel unit located in the same group, the pixel electrode 2 of the first pixel unit has overlapping projections on the substrate 10 with a first data line D1 segment of the second data line D2 and no overlapping projections on the substrate 10 with a first data line D1 segment of the first data line D1; the pixel electrode 2 of the second pixel unit has overlapping projections on the substrate 10 with a second data line D2 segment of the second data line D2 and no overlapping projections on the substrate 10 with a second data line D2 segment of the first data line D1.

[0076] For the above two examples, in short, for two pixel electrodes 2 arranged adjacent to each other in the column direction Y, one of the pixel electrodes has overlapping projections on the substrate 10 with a first data line D1 segment of one of the data lines Data, and the other of the pixel electrodes has overlapping projections on the substrate 10 with a second data line D2 segment of the other of the data lines Data.

[0077] In some examples, the connection segments of the data lines Data can extend in the same direction as the gate lines Gate, i.e., in the row direction X. The source 15 of the thin film transistor 1 can be connected to one of the connection segments as an integral structure.

[0078] Second example: Fig. 14 is a partial top view of a display substrate according to a second example of the present disclosure; Fig. 15 is a top view of the pixel electrode 2 and the data line Data of the display substrate shown in Fig. 14; Fig. 16 is a partial top view of another display substrate according to the second example of the present disclosure; Fig. 17 is a top view of the pixel electrode 2 and the data line Data of the display substrate shown in Fig. 16. As shown in Figs. 14-17, this example is substantially the same as the structure of the first example, and the difference is that in this example, the data lines Data of the display substrate all extend along the column direction Y, and the shape and area of the pixel electrode 2 in each pixel unit are equal, and in Figs. 14-17, only the case where the pixel electrode 2 is rectangular is taken as an example. Each pixel electrode 2 includes a first side edge and a second side edge arranged opposite along the row direction X. For pixel units located in the same column, the extension lines of the first side edges of the pixel electrodes 2 of some pixel units have a certain spacing, and the extension lines of the second side edges of the pixel electrodes 2 of some pixel units have a certain spacing, that is, at least part of the pixel electrodes 2 of the pixel units located in the same column are misaligned. By changing the relative positions of the pixel electrodes 2, the pixel electrodes 2 only overlap with the orthogonal projection of one data line Data on the substrate 10.

[0079] In some examples, for pixel units located in the same column, the extension lines of the first side edges of the pixel electrodes 2 of the pixel units located in odd-numbered pixel units coincide, and the extension lines of the first side edges of the pixel electrodes 2 of the pixel units located in even-numbered pixel units coincide. That is, for two pixel units located in the same column and arranged adjacent to each other, the pixel electrodes 2 of the two pixel units are staggered. In this case, the pixel electrodes 2 on the entire display substrate can be spliced with each other without loss of display resolution and aperture ratio.

[0080] For example: with reference to Figs. 14 and 15, the pixel electrode 2 of the first pixel unit overlaps with the orthogonal projection of the first data line D1 on the substrate 10, and does not overlap with the orthogonal projection of the second data line D2 on the substrate 10; the pixel electrode 2 of the second pixel unit overlaps with the orthogonal projection of the second data line D2 on the substrate 10, and does not overlap with the orthogonal projection of the first data line D1 on the substrate 10.

[0081] For example: with reference to Figs. 14 and 15, the pixel electrode 2 of the first pixel unit overlaps with the orthogonal projection of the first data line D1 on the substrate 10, and does not overlap with the orthogonal projection of the second data line D2 on the substrate 10; the pixel electrode 2 of the second pixel unit overlaps with the orthogonal projection of the second data line D2 on the substrate 10, and does not overlap with the orthogonal projection of the first data line D1 on the substrate 10.

[0082] The third example: Fig. 18 is a partial top view of a display substrate of a third example of an embodiment of the present disclosure; Fig. 19 is a top view of the pixel electrode 2 and the data line Data of the display substrate shown in Fig. 18; Fig. 20 is a partial top view of another display substrate of the third example of an embodiment of the present disclosure; Fig. 21 is a top view of the pixel electrode 2 and the data line Data of the display substrate shown in Fig. 20; as shown in Figs. 18-21, the difference between this example and the first example is that in the display substrate of this example, there is one row of pixel units between two rows of pixel units in the same group. The same as the first example is that the pixel units in the same column are provided with data voltage signals by two data lines Data. For the convenience of understanding, only one column of four rows of pixel units is described. In this case, two data lines Data and four gate lines Gate are correspondingly provided, the scanning signals written by the gate lines Gate connected by the pixel units in the same group are the same, and the data lines Data connected by the pixel units in the same group are different. Among them, the first row of pixel units and the third row of pixel units are a group, and the second row of pixel units and the fourth row of pixel units are a group.

[0083] The shape and area of the pixel electrode 2 in each pixel unit are equal, and in Figs. 18-21, only the pixel electrode 2 is taken as an example of a rectangle. Each pixel electrode 2 includes a first side edge and a second side edge arranged opposite along the row direction X. The extension lines of the first side edges of the pixel electrodes 2 in the pixel units in the same column coincide, and the extension lines of the second side edges of the pixel electrodes 2 in the pixel units in the same column coincide. That is, each pixel electrode 2 is arranged in an array. Each data line Data includes a first data line D1 segment and a second data line D2 segment arranged alternately and spaced apart, and a connection segment connecting the first data line D1 segment and the second data line D2 segment arranged adjacent to each other. The extension line of the first data line D1 segment and the extension line of the second data line D2 segment of the data line Data have a certain spacing.

[0084] In some examples, for one data line Data, the first data line D1 segment and the second data line D2 segment arranged adjacent to each other are correspondingly provided with four pixel units in the same column and divided into two groups, wherein the first data line D1 segment is correspondingly provided with two pixel units in the same column and in different groups, and the second data line D2 segment is correspondingly provided with another two pixel units in the same column and in different groups. Referring to Figs. 18-21, the first pixel unit and the second pixel unit are correspondingly provided with the first data line D1 segment, and the third pixel unit and the fourth pixel unit are correspondingly provided with the second data line D2 segment.

[0085] Further, for two adjacent data lines Data, and a column of pixel units provided with data line Data voltage by the two data lines Data, for the pixel unit provided corresponding to the first data line D1 segment, the normal projection of the pixel electrode 2 and the first data line D1 segment of one of the two data lines Data on the substrate 10 exists overlap, for the pixel unit provided corresponding to the second data line D2 segment, the normal projection of the pixel electrode 2 and the second data line D2 segment of the other of the two data lines Data on the substrate 10 exists overlap.

[0086] For example: referring to Figures 18 and 19, the pixel electrode 2 of the first pixel unit and the pixel electrode 2 of the second pixel unit both exist overlap with the normal projection of the first data line D1 segment of the second data line D2 on the substrate 10, and the normal projection of the first data line D1 segment of the first data line D1 on the substrate 10. The pixel electrode 2 of the third pixel unit and the pixel electrode 2 of the fourth pixel unit both exist overlap with the normal projection of the second data line D2 segment of the first data line D1 on the substrate 10, and the normal projection of the second data line D2 segment of the second data line D2 on the substrate 10.

[0087] For example: referring to Figures 18 and 19, the pixel electrode 2 of the first pixel unit and the pixel electrode 2 of the second pixel unit both exist overlap with the normal projection of the first data line D1 segment of the second data line D2 on the substrate 10, and the normal projection of the first data line D1 segment of the first data line D1 on the substrate 10. The pixel electrode 2 of the third pixel unit and the pixel electrode 2 of the fourth pixel unit both exist overlap with the normal projection of the second data line D2 segment of the first data line D1 on the substrate 10, and the normal projection of the second data line D2 segment of the second data line D2 on the substrate 10.

[0088] The fourth example: Fig. 22 is a partial top view of a display substrate of a fourth example of an embodiment of the present disclosure; Fig. 23 is a top view of the pixel electrode 2 and the data line Data of the display substrate shown in Fig. 22; Fig. 24 is a partial top view of another display substrate of the fourth example of an embodiment of the present disclosure; Fig. 25 is a top view of the pixel electrode 2 and the data line Data of the display substrate shown in Fig. 24; as shown in Figs. 22-25, the example is substantially the same as the structure of the third example, and the difference is that in the example, the data lines Data of the display substrate all extend along the column direction Y, the shape and area of the pixel electrode 2 in each pixel unit are equal, and in Figs. 22-25, only the case where the pixel electrode 2 is rectangular is taken as an example. Each pixel electrode 2 includes a first side edge and a second side edge arranged opposite along the row direction X. For the pixel units located in the same column, there is a certain spacing between the extension lines of the first side edges of the pixel electrodes 2 of some pixel units, and there is a certain spacing between the extension lines of the second side edges of the pixel electrodes 2 of some pixel units, that is, at least part of the pixel electrodes 2 of the pixel units located in the same column are arranged in a staggered manner. By changing the relative positions of the pixel electrodes 2, the pixel electrodes 2 only overlap with the orthographic projection of one data line Data on the substrate 10.

[0089] In some examples, for two data lines Data arranged adjacent to each other, and a column of pixel units provided with data line Data voltages by the two data lines Data, among two pixel units located in the same group and in different rows, the pixel electrode 2 in one pixel unit overlaps with the orthographic projection of a first data line D1 segment of one data line Data on the substrate 10, and the pixel electrode 2 in the other pixel unit overlaps with the orthographic projection of a second data line D2 segment of the other data line Data on the substrate 10.

[0090] For example: with reference to Figs. 22 and 23, the first pixel unit overlaps with the orthographic projection of the first data line D1 on the substrate 10, and the third pixel unit located in the same group as the first pixel unit overlaps with the orthographic projection of the second data line D2 on the substrate 10. The second pixel unit overlaps with the orthographic projection of the first data line D1 on the substrate 10, and the fourth pixel unit located in the same group as the second pixel unit overlaps with the orthographic projection of the second data line D2 on the substrate 10.

[0091] For example, referring to FIGS. 24 and 25, the first pixel unit overlaps the normal projection of the second data line D2 on the substrate 10, and the third pixel unit in the same group as the first pixel unit overlaps the normal projection of the first data line D1 on the substrate 10. The second pixel unit overlaps the normal projection of the second data line D2 on the substrate 10, and the fourth pixel unit in the same group as the second pixel unit overlaps the normal projection of the first data line D1 on the substrate 10.

[0092] Further, for two adjacent data lines Data and a column of pixel units provided with data line Data voltages by the two data lines Data, the extension line of the first side of the pixel electrode 2 of each pixel unit provided with a data signal by one of the data lines Data coincides, and the extension line of the second side of the pixel electrode 2 of each pixel unit provided with a data signal by the other of the data lines Data coincides.

[0093] For example, referring to FIGS. 22-25, the extension line of the first side of the first pixel unit coincides with the extension line of the first side of the second pixel unit, and the extension line of the second side of the first pixel unit coincides with the extension line of the second side of the second pixel unit. The extension line of the first side of the third pixel unit coincides with the extension line of the first side of the fourth pixel unit, and the extension line of the second side of the third pixel unit coincides with the extension line of the second side of the fourth pixel unit.

[0094] The above only gives several exemplary structures of the display substrate, and any modification or similar arrangement of the above structure is within the protection scope of the embodiments of the present disclosure.

[0095] The embodiments of the present disclosure also provide an electronic paper display device including any one of the above display substrates. Of course, the electronic paper display device can also include a counter substrate arranged opposite to the display substrate, the counter substrate having a reference electrode opposite to the pixel electrode 2, and a plurality of microcapsules arranged between the layer where the reference electrode is located and the layer where the pixel electrode 2 is located. The microcapsules encapsulate electrophoretic particles.

[0096] For example, the electrophoretic particles include positively charged black particles and yellow particles and negatively charged white particles. When the black particles are driven to move to the top end of the microcapsule by controlling the electric field generated between the pixel electrode 2 and the reference electrode, the microcapsule displays black; when the white particles are driven to move to the top end of the microcapsule by the electric field generated between the pixel electrode 2 and the reference electrode, the microcapsule displays white; and when the yellow particles are driven to move to the top end of the microcapsule by the electric field generated between the pixel electrode 2 and the reference electrode, the microcapsule displays yellow. Based on this, different colors are displayed by controlling the plurality of microcapsules, thereby realizing display.

[0097] It is understood that the above embodiments are only exemplary for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A display substrate, comprising a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of pixel units arranged in an array; the plurality of gate lines are disposed side by side and spaced apart along a column direction, and each extends along a row direction; the plurality of data lines are disposed side by side and spaced apart along the row direction, and a main body portion of each of the data lines extends along the column direction; for the pixel units in the same column and two data lines providing data signals for the pixel units in the column, the pixel units and one of the two data lines have overlapping orthographic projections on the substrate, and the pixel units and the other of the two data lines have no overlapping orthographic projections on the substrate. The plurality of pixel units are divided into groups, each group including two rows of the pixel units, and the gate lines connected to the pixel units in the same group are configured to load the same scanning signal, the pixel units in the same column are provided with data signals by two data lines, and the data lines providing data signals for the pixel units in the same column and connected to the gate lines loaded with the same scanning signal are different; wherein, The pixel electrodes in the pixel units in the same column are equal in size, and orthographic projections of the pixel electrodes on the substrate each include a first side edge and a second side edge disposed opposite along the row direction; extension lines of the first side edges of the pixel units in the same column coincide, and extension lines of the second side edges of the pixel units in the same column coincide. 2.The display substrate of claim 1, wherein, The data lines include first data line segments and second data line segments disposed alternately and spaced apart along the column direction, and connecting segments connecting the first data line segments and the second data line segments disposed alternately; the extension lines of the first data line segments and the second data line segments of the data lines have a certain interval; for two data lines disposed alternately and a column of the pixel units provided with data line voltages by the two data lines, two of the pixel units in the same group and in different rows, the pixel electrode in one of the pixel units and the first data line segment of one of the data lines have overlapping orthographic projections on the substrate, and the pixel electrode in the other of the pixel units and the second data line segment of the other of the data lines have overlapping orthographic projections on the substrate. 3.The display substrate of claim 2, wherein, The pixel electrodes in the pixel units in the same column are equal in size, and orthographic projections of the pixel electrodes on the substrate each include a first side edge and a second side edge disposed opposite along the row direction; the extension lines of the first side edges of at least some of the pixel units in the same column have a certain interval; the extension lines of the second side edges of at least some of the pixel units in the same column have a certain interval. 4.The display substrate of claim 1, wherein, For two data lines disposed alternately and a column of the pixel units provided with data line voltages by the two data lines, the extension lines of the first side edges of the pixel electrodes of each of the pixel units provided with data signals by one of the data lines coincide, and the extension lines of the second side edges of the pixel electrodes of each of the pixel units provided with data signals by the other of the data lines coincide. 5.The display substrate of claim 4, wherein, Two rows of the pixel units in the same group are disposed alternately. 6.The display substrate according to any one of claims 1-5, wherein, Two rows of the pixel units in the same group are spaced apart by one row of the pixel units. 7.The display substrate according to any one of claims 1-5, wherein, The display substrate further comprises a gate drive circuit; two of the gate lines providing scan signals for the pixel units in the same group are connected to the gate drive circuit through the same signal lead. 8.The display substrate according to any one of claims 1-5, wherein, ​ 9.The display substrate of claim 8, wherein, The gate lines have oppositely arranged first ends and second ends, and part of the signal leads are connected to the first ends of the gate lines, and part of the signal leads are connected to the second ends of the gate lines. 10.The display substrate of claim 9, wherein, The first ends of the gate lines providing scanning signals for the pixel units in the odd-numbered group are connected to the signal leads, and the second ends of the gate lines providing scanning signals for the pixel units in the odd-numbered group are connected to the signal leads. 11.The display substrate of any one of claims 1-5, wherein, The pixel unit further comprises a common electrode located on the side of the pixel electrode close to the substrate, and the orthogonal projection of the common electrode and the pixel electrode on the substrate substrate at least partially overlaps. 12.The display substrate of claim 11, wherein, The pixel unit comprises a thin film transistor, the gate of the thin film transistor is connected to the gate line, the source of the thin film transistor is connected to the data line, and the drain of the thin film transistor is connected to the pixel electrode. 13.The display substrate of claim 12, wherein, The gate of the thin film transistor is connected to the gate line in an integrated structure, and is arranged in the same layer as the common electrode. 14.The display substrate of claim 12, wherein, The source and the drain of the thin film transistor are arranged in the same layer as the data line, and an interlayer insulation layer is arranged on the side of the layer where the source and the drain of the thin film transistor are located away from the substrate, and the pixel electrode is connected to the pixel electrode through a via hole penetrating through the interlayer insulation layer.

15. An electronic paper display device comprising the display substrate according to any one of claims 1-14.

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