Transistor, preparation method therefor and use thereof

Abstract

The present invention relates to the technical field of semiconductor manufacturing, and specifically to a transistor. The transistor comprises a channel layer, a barrier layer, an ion-implanted region, a passivation layer, and an ohmic electrode. The barrier layer is disposed on the channel layer; a first region of the ion-implanted region extends from the upper surface of the barrier layer toward the channel layer and extends into the channel layer, and the first region has a groove; a second region of the ion-implanted region is located in the channel layer and in communication with the first region; the passivation layer is disposed on the barrier layer and has an opening; and the ohmic electrode is disposed on the passivation layer and is connected to the first region through the opening and the groove, wherein the peak ion concentration of the first region is greater than that of the second region. With such arrangements, the transistor can avoid crystal damage and reduce dislocation defects while thinning the channel layer, thereby improving the performance of the transistor.

Description

Transistor and method of manufacturing and using the same TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a transistor, a method for manufacturing the transistor, a radio frequency amplifier comprising the transistor, and a communication device comprising the radio frequency amplifier. BACKGROUND

[0002] High electron mobility transistor (HEMT) has the advantages of high frequency, high voltage, high temperature, etc., and is the future development direction of solid-state microwave power devices and power electronic devices.

[0003] In a conventional AlGaN / GaN HEMT power device, the thickness of the gallium nitride channel layer is usually 1-2 microns, and if it can be further thinned to 300-800 nm, the voltage resistance characteristics of the HEMT device can be greatly improved, and it can be applied to higher voltage scenarios to obtain greater output power and efficiency. However, as the gallium nitride channel layer is thinned, more dislocation defects are generated, and in the process of preparing the ohmic electrode of the HEMT device, the entire crystal is more susceptible to damage, and the dislocation defects are further amplified, resulting in a decrease in the electron concentration and other properties of the channel of the HEMT device, a decrease in the output saturation current, and a more serious current collapse effect. Therefore, how to avoid damage to the crystal and reduce dislocation defects while thinning the gallium nitride channel layer has become one of the technical difficulties that technicians in the field urgently need to solve.

[0004] It should be noted that the information disclosed in this background section is only intended to increase the understanding of the overall background of the present application and should not be considered as acknowledging or implying in any form that this information constitutes prior art known to those of ordinary skill in the art. TECHNICAL SOLUTION

[0005] The present application provides a transistor, which comprises a channel layer, a barrier layer, an ion implantation region, a passivation layer, and an ohmic electrode. The barrier layer is disposed on the channel layer. The ion implantation region comprises a first region and a second region. The first region of the ion implantation region extends from the upper surface of the barrier layer to the channel layer and extends to the channel layer, and the first region has a groove. The second region of the ion implantation region is located in the channel layer and is in communication with the first region. The passivation layer is disposed on the barrier layer and has an opening. The ohmic electrode is disposed on the passivation layer and is connected to the first region through the opening and the groove. Wherein, the peak ion concentration of the first region is greater than the peak ion concentration of the second region.

[0006] The application further provides a preparation method of the transistor, comprising the following steps: sequentially growing a channel layer and a barrier layer on a substrate; growing a passivation layer on the barrier layer, and performing opening on the passivation layer to expose a source region and a drain region; performing ion implantation on the source region and the drain region to form a first region and a second region, the first region extending from an upper surface of the barrier layer to the channel layer, and the second region being located in the channel layer and communicating with the first region, wherein a peak ion concentration of the first region is greater than a peak ion concentration of the second region; etching a groove at the first region, and then arranging an ohmic electrode at the source region and the drain region, the ohmic electrode being connected with the first region through the groove. Advantages

[0007] The application provides a transistor and a preparation method and application thereof, by arranging a first region with a higher concentration on the barrier layer and the channel layer, and arranging a second region with a lower concentration in the channel layer, a low ohmic contact resistance is formed, so that the transistor can avoid damage to the crystal and reduce dislocation defects in the case of thinning the channel layer, thereby improving the performance of the transistor.

[0008] Other features and advantages of the application will be illustrated in the following description, and some technical features and advantages can be obtained from the description, or can be understood by implementing the application. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, some of the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0010] Fig. 1 is a structural schematic diagram of a transistor provided by a first embodiment of the application;

[0011] Fig. 2 is a structural schematic diagram of a transistor provided by a second embodiment of the application;

[0012] Figs. 3 to 7 are structural schematic diagrams of the transistor in each stage of the preparation process provided by an embodiment of the application.

[0013] Reference signs:

[0014] 11 - channel layer; 12 - barrier layer; 13 - passivation layer; 14 - ohmic electrode; 15 - gate; 16 - substrate; 17 - nucleation layer; 21 - first region of ion implantation region; 22 - second region of ion implantation region; 30 - recess; H1 - thickness of the first region; H2 - thickness of the second region; H3 - thickness of the channel layer; S1 - shortest distance from the lower boundary of the second region to the lower surface of the channel layer; L1, L2 - shortest distances; dl - vertical distance; d2 - thickness of the barrier layer. Embodiments of the present application

[0015] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. As long as there is no conflict, the technical features designed in the different embodiments of the present application can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0016] In the description of the present application, it should be understood that the terms "center", "transverse", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or component referred to must have a particular orientation, or be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, the term "comprising" and any variation thereof means "at least including".

[0017] Referring to FIG. 1, FIG. 1 is a structural schematic diagram of a transistor provided by the first embodiment of the present application. In order to achieve at least one of the described advantages or other advantages, an embodiment of the present application provides a transistor. As shown in the figure, the transistor can include a channel layer 11, a barrier layer 12, a first region 21 of an ion implantation region, a second region 22 of the ion implantation region, a passivation layer 13 and an ohmic electrode 14. That is, the transistor includes an ion implantation region, which includes the first region 21 and the second region 22.

[0018] The channel layer 11 is preferably a non-intentionally doped gallium nitride layer. The thickness H3 of the channel layer 11 ranges from 200 to 640 nm, thereby greatly improving the voltage resistance of the transistor device, allowing the transistor to be applied in a higher voltage scenario, and achieving greater output power and efficiency.

[0019] The barrier layer 12 is disposed on the channel layer 11. The material of the barrier layer 12 can include AlGaN.

[0020] The passivation layer 13 is disposed on the barrier layer 12 and has an opening. The material of the passivation layer 13 can include silicon nitride.

[0021] The ohmic electrode 14 is disposed on the passivation layer 13 and connected to the first region 21 through the opening. The ohmic electrode 14 can be a source electrode or a drain electrode, or both the source electrode and the drain electrode can be used to connect the first region 21. In some embodiments, the lower surface of the ohmic electrode 14 is within the channel layer 11 and does not directly contact the second region 22. The ohmic electrode 14 can be a laminated metal structure such as Ti, Al, Ni, and Au, or a laminated metal structure such as Ti, Pt, and Au. Optionally, the thickness of the ohmic electrode 14 ranges from 500 to 600 nm.

[0022] The first region 21 extends from the upper surface of the barrier layer 12 to the channel layer 11 and extends into the channel layer 11. The first region 21 has a recess 30, which can be formed by collapsing from the upper surface of the barrier layer 12 to the channel layer 11. The ohmic electrode 14 is connected to the first region 21 through the recess 30, i.e., the ohmic electrode 14 fills the recess 30. The second region 22 is located within the channel layer 11 and communicates with the first region 21. The peak ion concentration of the first region 21 is greater than the peak ion concentration of the second region 22. Taking the first region 21 as an example, the peak ion concentration refers to the highest ion concentration value within the first region 21. In some embodiments, the average ion concentration of the first region 21 is greater than the average ion concentration of the second region 22.

[0023] The present application forms a low ohmic contact resistance by gradient concentration implantation, i.e., disposing the first region 21 with a higher concentration on the barrier layer 12 and the channel layer 11, and disposing the second region 22 with a lower concentration within the channel layer 11, thereby avoiding damage to the crystal and reducing dislocation defects when thinning the channel layer 11, and improving the performance of the transistor.

[0024] In some embodiments, silicon ions are implanted in the first region 21, and the silicon concentration in the first region 21 ranges from 1E18 to 5E20 Atom / cm 3The silicon concentration in the first region 21 increases first and then decreases along the direction from the barrier layer 12 to the channel layer 11, that is, the silicon concentration of the first region 21 gradually increases to the maximum concentration and then decreases downward along the direction from top to bottom in the figure. Silicon ions are implanted in the second region 22, and the silicon concentration in the second region 22 ranges from 1E17 to 1E18 Atom / cm 3 The second region 22 is a transition region, and the ion concentration gradient in the second region 22 decreases to 1E17-1E18 Atom / cm 3 The shortest distance S1 from the lower boundary of the second region 22 to the lower surface of the channel layer 11 is formed in the range of 50-150 nm, which reduces the current collapse effect of the device. The closer to the lower part of the channel layer 11, the higher the crystal dislocation density and the relatively poor crystal quality. The second region 22 is arranged in the lower half of the channel layer 11, and the corresponding concentration is designed to be 1E17-1E18 Atom / cm 3 The current collapse effect of the device can be effectively reduced.

[0025] The silicon concentration in the second region 22 gradually decreases along the direction from the barrier layer 12 to the channel layer 11. In some embodiments, other ions can be implanted in the first region 21 and the second region 22. In some embodiments, the concentration of the first region 21 at its upper boundary is higher than that at its lower boundary; and the concentration of the second region 22 at its upper boundary is higher than that at its lower boundary.

[0026] It should be noted that the ohmic electrodes 14 on the left and right sides in the figure are both provided with the first region 21 and the second region 22 below them, but the present application is not limited thereto, and the first region 21 and the second region 22 can also be arranged below one of the ohmic electrodes 14 to achieve the corresponding effect. Considering that it is not convenient to define and distinguish the first region 21 and the second region 22 in actual situations, the definition of the first region 21 can be made by the concentration change of the first region 21, for example, the region where the concentration of the first region 21 increases first and then decreases from the upper surface of the barrier layer 12 downward in the range of 1E18-5E20 Atom / cm 3 It should be noted that the concentration increase and decrease are not linear concentration changes, but the overall trend of the concentration increases or decreases, for example, in the process of concentration increase, each wave peak can be higher than the previous one in a wave shape; similarly, in the process of concentration decrease, each wave peak can be lower than the previous one in a wave shape. The definition of the second region 22 can be made by the concentration change of the second region 22, for example, the concentration of the second region 21 decreases from the upper surface of the barrier layer 12 downward in the range of 1E17-1E18 Atom / cm 3The region where the concentration decreases from the first region 21 to below 1E17 is the second region 22, and the change in the decrease in the concentration is not a linear concentration change, but the overall trend of the concentration shows a decrease, for example, in the process of the decrease in the concentration, it can be wavy, and each wave peak is lower than the previous one.

[0027] In some embodiments, the thickness H1 of the first region 21 is greater than the thickness H2 of the second region 22, so that the region 200 nm from the upper surface 100 of the barrier layer 12 can be heavily doped to form an ohmic, so that the region is in full contact with the two-dimensional electron gas of the device, and the ohmic contact resistivity is reduced. Optionally, the thickness H1 of the first region 21 ranges from 100 to 200 nm. Optionally, the thickness H2 of the second region 22 ranges from 85 to 300 nm.

[0028] In some embodiments, for the channel layer 11 with a thickness H3 of 200-640 nm, the channel layer 11 can be made of gallium nitride epitaxial material, and the shortest distance S1 from the lower boundary of the second region 22 to the lower surface of the channel layer 11 ranges from 50 to 150 nm.

[0029] Table 1

[0030]

[0031] As shown in Table 1, for the ratio relationship between S1 and H3 of the values of the present application in different value cases, preferably, the ratio relationship between S1 and H3 is: 1 / 12 < S1 / H3 <1 / 2.

[0032] When S1 / H3 <1 / 12, the silicon concentration ranges from 1E17 to 1E18 Atom / cm 3 The second region 22 with a silicon concentration of 1E17-1E18 Atom / cm 3 can be significantly different from the silicon concentration of other regions in the channel layer 11, so that the lower side of the silicon concentration range is taken as the lower boundary.

[0033] When S1 / H3>1 / 2 (for example, S1>150 nm), the lower boundary of the second region 22 is too high, so that part of the channel hot electrons in the S1 range area are captured by the hole-like defects in the region when the device is working, the current density is reduced, and the output power is reduced. Therefore, by means of implantation, the size of the region is controlled, and then the drain current and current collapse performance of the device are adjusted, which is particularly important for preparing gallium nitride transistors.

[0034] In a further more preferred solution, when the thickness H3 of the channel layer 11 is in the range of 200-640 nm, the ratio of S1 to H3 can be: 1 / 8 < S1 / H3 <1 / 4. On the one hand, the cross-sectional area of the ion implantation region is relatively large, and the surface area of the groove formed in the channel layer 11 is relatively large, which can improve the ohmic contact area of the source or drain, thereby improving the ohmic contact performance of the source or drain; on the other hand, it can make the groove 30 easier to manufacture, thereby improving the consistency of the device, and the crystal at the lower part of the channel layer 11 can avoid the bombardment of silicon ion implantation.

[0035] In some embodiments, the shortest distance from the contact point of the ohmic electrode 14 on the upper surface of the barrier layer 12 to the side boundary of the first region 21 to the contact point of the barrier layer 12 on the upper surface is L1, and L1 is in the range of 0.5-0.7 μm, which is beneficial to the formation of ohmic contact. Considering that in actual situations, the side boundary of the first region 21 is not easy to determine, the silicon concentration range of 1E18-5E20 Atom / cm 3 will be significantly different from the silicon concentration of other regions in the barrier layer 12, so that the side boundary is taken as the side where the contact point of the ohmic electrode 14 is located. In some embodiments, the angle between the ohmic electrode 14 and the upper surface of the barrier layer 12 is in the range of 70-80°, which is beneficial to the formation of ohmic contact.

[0036] In some embodiments, the vertical distance from the lower surface of the ohmic electrode 14 to the upper surface of the barrier layer 12 is d1, and the thickness of the barrier layer 12 is d2, 5 nm+d2≤d1≤100 nm, which ensures the vertical longitudinal region of the ohmic electrode, and the barrier layer is replaced by metal filling. On the one hand, the crystal defects of the part of the barrier region are increased or amplified after implantation, so that the current collapse is serious when the device is working, and on the other hand, the metal is directly in contact with the two-dimensional electron gas, which is beneficial to the formation of low ohmic contact resistance; ensure the formation of ohmic contact. The value range of d2 can be 10-35 nm.

[0037] In some embodiments, the transistor can further include a gate 15 disposed on the passivation layer 13 and connected to the barrier layer 12. In some embodiments, the shortest distance between the contact point on the upper surface of the barrier layer 12 to the side boundary of the first region 21 is L2, and L2 is in the range of 0.6-1.5 μm, which is conducive to the preparation of the gate.

[0038] It should be noted that the transistor device provided by the present application can include other structures in addition to the above structure, and the conventional setting mode in the prior art can be used, such as an insertion layer between the channel layer and the barrier layer, the insertion layer being an AlN layer, and a GaN cap layer being further provided on the barrier layer. Therefore, the present embodiment will not be described here. In addition, the epitaxial structure of the transistor provided by the present embodiment can also be applied to the HEMT structure of other material systems.

[0039] Referring to FIG. 2, FIG. 2 is a structural schematic diagram of a transistor provided by a second embodiment of the present application. Compared with the transistor shown in FIG. 1, the difference of the present embodiment mainly lies in that the transistor further includes a substrate 16 and a nucleation layer 17. The nucleation layer 17 is disposed on the substrate 16. The channel layer 11 is disposed on the nucleation layer 17. The material of the substrate 16 can include silicon carbide, silicon, or any other suitable substrate 16 for epitaxial growth of GaN material known to those skilled in the art, which is not specifically limited in the present application. The material of the nucleation layer 17 can include aluminum nitride. By setting the shortest distance S1 between the lower boundary of the second region 22 to the lower surface of the channel layer 11 in the range of 50-100 nm, the influence of the bombardment of silicon ion implantation on the nucleation layer 17 can also be reduced, thereby avoiding the decline in crystal quality and seriously affecting the current collapse performance.

[0040] Referring to FIGS. 3-7, FIGS. 3-7 are structural schematic diagrams of the transistor at each stage in the preparation process according to an embodiment of the present application. An embodiment of the present application further provides a preparation method of a transistor, which includes the following steps:

[0041] First, as shown in FIG. 3, the channel layer 11 and the barrier layer 12 are sequentially grown on the substrate 16. Specifically, a MOCVD machine can be used to grow a thin GaN channel layer 11 and an AlGaN barrier layer 12 on a SiC substrate 16.

[0042] Second, as shown in FIG. 4, the passivation layer 13 is grown on the barrier layer 12, and the passivation layer 13 is opened to expose the source region and the drain region. Specifically, the SIN passivation layer 13 can be grown by using LPCVD (low pressure chemical vapor deposition method), the growth temperature is 780°C, and NH3 and DCS gases (the ratio of the two is 27:280 sccm) are used; the thickness can be controlled in the range of 18-22 nm. Then, the source region and the drain region are prepared by using a step lithography machine through coating, developing and exposing.

[0043] Then, as shown in FIG. 5, ion implantation is performed on the source region and the drain region to form the first region 21 and the second region 22, the first region 21 extending from the upper surface of the barrier layer 12 to the channel layer 11, and the second region 22 being located in the channel layer 11 and communicating with the first region 21, wherein the peak ion concentration of the first region 21 is greater than the peak ion concentration of the second region 22. Specifically, silicon ion implantation is performed on the source region and the drain region, and a low-energy large-beam implantation machine is used, and the beam current of the implantation machine is tens of milliamperes. Twice ion implantation can be used, the first ion implantation has an implantation energy of 100 keV, and the implantation dose ranges from 1E17 to 1E18 Atom / cm 3 , and the second ion implantation has an implantation energy of 50 keV, and the implantation dose ranges from 1E18 to 5E20 Atom / cm 3 . The first region 21 and the second region 22 are formed by the twice ion implantation to ensure that the silicon concentration of the source region and the drain region is gradiently distributed in the vertical direction, and to ensure that the region 50-100 nm above the lower surface of the channel layer 11 is not subjected to silicon ion implantation, so as to reduce the bombardment caused by silicon ion implantation, thereby reducing the crystal quality and affecting the current collapse performance. However, the present application is not limited thereto, and in some embodiments, a single ion implantation or three times ion implantation or more times ion implantation can be used to form the first region 21 and the second region 22.

[0044] Then, as shown in FIG. 6, a groove 30 is etched at the first region 21, and then an ohmic electrode 14 is arranged at the source region and the drain region, and the ohmic electrode 14 is connected to the first region 21 through the groove 30. Specifically, the plasma etching method can be used to etch the groove 30 shape by gas proportioning (such as CF4, N2, O2, BCl3, etc.), and then the ohmic electrode 14 is formed by the electron beam evaporation machine.

[0045] Finally, as shown in FIG. 7, a slot is opened at the preset gate region of the passivation layer 13, and then a gate 15 is arranged at the gate region.

[0046] The above preparation steps are used to show a preparation method of the transistor, and the present application is not limited thereto.

[0047] In some embodiments, the step of performing ion implantation on the source region and the drain region includes twice ion implantation, the implantation energy of the first ion implantation is greater than the implantation energy of the second ion implantation, and the energy difference between the implantation energy of the first ion implantation and the implantation energy of the second ion implantation is greater than or equal to 10 keV. The implantation energy of the first ion implantation ranges from 65 to 110 keV, and the implantation dose of the first ion implantation ranges from 1E18 to 5E20 Atom / cm 3The second ion implantation has an implantation energy of 45-60 keV, and the second ion implantation has an implantation dose in a range of 1E17-1E18 Atom / cm 3 .

[0048] Correspondingly, the present application also provides a radio frequency amplifier, which comprises the transistor of any one of the above embodiments. The present application also provides a communication device, and the radio frequency amplifier can be applied to a microwave system, a radar, a wireless communication module, a network device, and the like.

[0049] To sum up, the present application provides a transistor and a preparation method and application thereof. By arranging the first area 21 with high concentration in the barrier layer 12 and the channel layer 11 and the second area 22 with low concentration in the channel layer 11, a low ohmic contact resistance is formed, so that the transistor can avoid crystal damage and reduce dislocation defects in the case of thinning the channel layer 11, thereby improving the performance of the transistor.

[0050] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present application can only be improved in one or several aspects, and it is not necessary to solve all the technical problems listed in the prior art or background art at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be regarded as a limitation of the claim.

[0051] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A transistor, characterized by: The transistor comprises: a channel layer; a barrier layer disposed on the channel layer; an ion implantation region, the ion implantation region comprising a first region and a second region; the first region extending from an upper surface of the barrier layer to the channel layer, the first region having a recess; the second region being located in the channel layer and communicating with the first region; a passivation layer disposed on the barrier layer and having an opening; an ohmic electrode disposed on the passivation layer and connected to the first region through the opening and the recess; wherein a peak ion concentration of the first region is greater than a peak ion concentration of the second region.

2. The transistor of claim 1, wherein: A shortest distance of a lower boundary of the second region to a lower surface of the channel layer ranges from 50 nm to 150 nm.

3. The transistor of claim 1, wherein: A thickness of the first implantation region ranges from 100 nm to 200 nm, and a thickness of the second implantation region ranges from 85 nm to 300 nm.

4. The transistor of claim 1, wherein: Silicon ions are implanted in the first region, and the silicon concentration in the first region ranges from 1E18 to 5E20 atoms / cm 3 .

5. The transistor of claim 4, wherein: A silicon concentration in the first region increases first and then decreases along a direction from the barrier layer to the channel layer.

6. The transistor of claim 1, wherein: Silicon ions are implanted in the second region, and the silicon concentration in the second region ranges from 1E17 to 1E18 atoms / cm 3 .

7. The transistor of claim 6, wherein: A silicon concentration in the second region gradually decreases along a direction from the barrier layer to the channel layer.

8. The transistor of claim 1, wherein: The transistor further comprises a gate disposed on the passivation layer and connected to the barrier layer, a shortest distance of a contact point of the gate on an upper surface of the barrier layer to a side boundary of the first region on the upper surface of the barrier layer being L2, L2 ranging from 0.6 μm to 1.5 μm.

9. The transistor of claim 1, wherein: A shortest distance of a contact point of the ohmic electrode on the upper surface of the barrier layer to the side boundary of the first region on the upper surface of the barrier layer being L1, L1 ranging from 0.5 μm to 0.7 μm.

10. The transistor of claim 1, wherein: A vertical distance of a lower surface of the ohmic electrode to the upper surface of the barrier layer being d1, a thickness of the barrier layer being d2, 5 nm + d2 ≤ d1 ≤ 100 nm, and 10 nm ≤ d2 ≤ 35 nm.

11. The transistor of claim 1, wherein: A thickness of the channel layer ranges from 200 nm to 640 nm.

12. The transistor of claim 1, wherein: The ohmic electrode is a source electrode or a drain electrode.

13. A method of fabricating a transistor, comprising: The preparation method comprises the following steps: growing a channel layer and a barrier layer on a substrate in sequence; growing a passivation layer on the barrier layer and performing opening on the passivation layer to expose a source region and a drain region; performing ion implantation on the source region and the drain region to form an ion implantation region, the ion implantation region comprising a first region and a second region, the first region extending from an upper surface of the barrier layer to the channel layer, the second region being located in the channel layer and communicating with the first region, wherein a peak ion concentration of the first region is greater than a peak ion concentration of the second region; etching a recess at the first region and disposing an ohmic electrode at the source region and the drain region, the ohmic electrode being connected to the first region through the recess.

14. The method of claim 13, wherein: The step of performing ion implantation on the source region and the drain region comprises two times of ion implantation, an implantation energy of a first time of ion implantation being greater than an implantation energy of a second time of ion implantation, and an energy difference between the implantation energy of the first time of ion implantation and the implantation energy of the second time of ion implantation being greater than or equal to 10 kev.

15. The method of claim 14, wherein: The first ion implantation has an implant energy ranging from 65 to 110 keV and an implant dose ranging from 1E18 to 5E20 atoms / cm 3 The second ion implantation has an implant energy of 45 to 60 keV and an implant dose ranging from 1E17 to 1E18 atoms / cm 3 .

16. A radio frequency amplifier characterized by: The radio frequency amplifier comprises the transistor according to any one of claims 1 to 12.

17. A communications device, characterized by: The communication device includes the radio frequency amplifier as claimed in claim 16.

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