Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a semiconductor element having an element main surface facing a first side in a first direction, and a source electrode disposed on the element main surface; a cushioning member joined to the source electrode; and a first wire joined to the cushioning member. The cushioning member includes a substrate layer, a first plating layer disposed on the outermost side of the substrate layer on the first side in the first direction, and a second plating layer disposed on the outermost side of the substrate layer on a second side in the first direction. The second plating layer is joined to the source electrode, and the first wire is joined to the first plating layer.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a semiconductor element, a metal plate, and a connection member. The metal plate is joined to the first electrode of the semiconductor element, and the connection member is joined thereto. As a result, the load applied to the first electrode is suppressed compared to the case where the connection member is directly joined to the first electrode of the semiconductor element, so that damage to the semiconductor element is suppressed. The metal plate is formed by depositing a first metal layer made of, for example, Ag on a metal base material made of, for example, Cu by a sputtering method or vacuum evaporation.

[0003] International Publication No. WO2021 / 176996

[0004] [Summary] Since the manufacturing cost of the metal plate is relatively high, the manufacturing cost of the semiconductor device increases.

[0005] One problem of the present disclosure is to provide a semiconductor device improved from the prior art. In particular, in view of the above circumstances, one problem of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress damage to a semiconductor element while suppressing an increase in manufacturing cost.

[0006] The semiconductor device provided by the first aspect of the present disclosure includes a semiconductor element having an element main surface facing the first side in the first direction and a first electrode disposed on the element main surface, a buffer member joined to the first electrode, and a conductive connection member joined to the buffer member. The buffer member includes a base material layer, a first plating layer disposed on the outermost side of the first side of the base material layer in the first direction, and a second plating layer disposed on the outermost side of the second side of the base material layer in the first direction. The second plating layer is joined to the first electrode. The conductive connection member is joined to the first plating layer.

[0007] A method for manufacturing a semiconductor device provided by a second aspect of this disclosure comprises the steps of: placing a buffer member on the first electrode of a semiconductor device having an element main surface facing a first side in a first direction and a first electrode disposed on the element main surface; solid-phase diffusion bonding the first electrode and the buffer member; and bonding a conductive connecting member to the buffer member. The buffer member comprises a substrate layer, a first plating layer disposed on the outermost side of the substrate layer on the first side in the first direction, and a second plating layer disposed on the outermost side of the substrate layer on the second side in the first direction.

[0008] Other features and advantages of this disclosure will become more apparent from the detailed description below, with reference to the accompanying drawings.

[0009] Figure 1 is a plan view showing a semiconductor device according to the first embodiment of the present disclosure. Figure 2 is a partial plan view showing a semiconductor device according to the first embodiment of the present disclosure. Figure 3 is a cross-sectional view along the line III-III in Figure 2. Figure 4 is a partially enlarged view of Figure 3. Figure 5 is a partially enlarged plan view showing a semiconductor device according to the first embodiment of the present disclosure. Figure 6 is a cross-sectional view along the line VI-VI in Figure 5. Figure 7 is a partially enlarged view of Figure 6. Figure 8 is a system configuration diagram showing a vehicle equipped with a semiconductor device according to the first embodiment of the present disclosure. Figure 9 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. Figure 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. Figure 11 is a partially enlarged cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. Figure 12 is a partially enlarged plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. Figure 13 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. Figure 14 is a partially enlarged cross-sectional view showing a semiconductor device according to the second embodiment of the present disclosure. Figure 15 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present disclosure. Figure 16 is a cross-sectional view showing a semiconductor device according to the third embodiment of the present disclosure. Figure 17 is a partially enlarged cross-sectional view showing a semiconductor device according to the third embodiment of the present disclosure. Figure 18 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the third embodiment of the present disclosure. Figure 19 is a cross-sectional view showing a first modified example of a semiconductor device according to the third embodiment of the present disclosure. Figure 20 is a cross-sectional view showing a second modified example of a semiconductor device according to the third embodiment of the present disclosure. Figure 21 is a partially enlarged plan view showing a semiconductor device according to the fourth embodiment of the present disclosure. Figure 22 is a cross-sectional view along the line XXII-XXII in Figure 21. Figure 23 is a plan view showing a semiconductor device according to the fifth embodiment of the present disclosure.

[0010] [Detailed Description] Preferred embodiments of this disclosure will be described below with reference to the drawings.

[0011] The terms "first," "second," "third," etc., used in this disclosure are for identification purposes only and are not intended to assign any order to the objects.

[0012] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is located on object B in contact with object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, unless otherwise specified, "object A overlaps with object B when viewed in a certain direction" includes "object A overlapping with all of object B" and "object A overlapping with a part of object B." Also, in this disclosure, "a surface A facing direction B (one or the other side of it)" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is inclined with respect to direction B.

[0013] First Embodiment: Figures 1 to 7 show a semiconductor device according to the first embodiment of the present disclosure. The semiconductor device A1 of this embodiment comprises one or more first semiconductor elements 5A, one or more buffer members 5C, and a plurality of first wires 8A. In this embodiment, the semiconductor device A1 may further comprise a support 1, a first metal layer 3A, a fourth metal layer 3B, a first bonding layer 4A, a third bonding layer 4B, one or more second semiconductor elements 5B, one or more second bonding layers 6A, one or more fourth bonding layers 6B, a positive input terminal 7A, an output terminal 7B, a negative input terminal 7C, a plurality of control terminals 7D, a plurality of control terminals 7E, a plurality of second wires 8B, a plurality of third wires 8C, a plurality of fourth wires 8D, and a sealing resin 9.

[0014] In these diagrams, for example, one side of the first direction z is referred to as the first side z1, and the other side as the second side z2. Also, for example, one direction perpendicular to the first direction z is defined as the second direction x. Also, for example, one side of the second direction x is referred to as the first side x1, and the other side opposite to the first side x1 is referred to as the second side x2. Also, for example, a direction perpendicular to both the first direction z and the second direction x is defined as the third direction y. Also, for example, one side of the third direction y is referred to as the first side y1, and the other side as the second side y2.

[0015] The specific applications of semiconductor device A1 are not limited in any way. In semiconductor device A1, a half-bridge circuit is formed by a plurality of first semiconductor elements 5A forming an upper arm circuit and a plurality of second semiconductor elements 5B forming a lower arm circuit. For example, semiconductor device A1 constitutes an inverter for converting DC power to AC power and supplying power to a drive source such as a motor. In this embodiment, semiconductor device A1 will be described using the case where it has one half-bridge circuit as an example, but it may also be configured to supply power to a so-called three-phase AC motor by having, for example, three half-bridge circuits.

[0016] Each of the multiple first semiconductor elements 5A and the multiple second semiconductor elements 5B may be constructed using a semiconductor material mainly composed of SiC (silicon carbide). This semiconductor material is not limited to SiC, but may be Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride), etc. In this embodiment, the first semiconductor elements 5A and the second semiconductor elements 5B may be MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The first semiconductor elements 5A and the second semiconductor elements 5B may be field-effect transistors including MISFETs (Metal-Insulator-Semiconductor FETs), bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors), IC chips such as LSIs, diodes, capacitors, etc.

[0017] As shown in Figures 5 and 6, the first semiconductor element 5A of this embodiment may have an element body 50, a drain electrode 51, a source electrode 52, a gate electrode 53, and a source sense electrode 54. The element body 50 may be made of the semiconductor material described above. The element body 50 has an element main surface 50a and an element back surface 50b that face opposite each other in the first direction z. The element main surface 50a faces the first side z1 in the first direction z. The source electrode 52, gate electrode 53, and source sense electrode 54 are arranged on the element main surface 50a. The element back surface 50b faces the second side z2 in the first direction z. The drain electrode 51 is arranged on the element back surface 50b. The second semiconductor element 5B may have an element body 50, a drain electrode 51, a source electrode 52, a gate electrode 53, and a source sense electrode 54, similar to the first semiconductor element 5A.

[0018] As shown in Figure 7, the source electrode 52 may include a base layer 52a and a surface metal layer 52b. The base layer 52a may include, for example, Cu (copper) and Al (aluminum). The surface metal layer 52b is located on the first side z1 in the first direction z relative to the base layer 52a. The surface metal layer 52b is composed of, for example, stacked Ni (nickel) layers, Pd (palladium) layers, and Au (gold) layers. The materials of the base layer 52a and the surface metal layer 52b are not limited. The source electrode 52 does not have to include the surface metal layer 52b. The gate electrode 53, source sense electrode 54, and drain electrode 51 may also include a base layer and a surface metal layer, similar to the source electrode 52.

[0019] A buffer member 5C is placed on the source electrode 52 of the first semiconductor element 5A and the second semiconductor element 5B. The buffer member 5C is joined to the source electrode 52 by solid-phase diffusion bonding. The shape of the buffer member 5C as viewed in the first direction z is not limited in any way, and in the illustrated example it may be rectangular. The buffer member 5C is enclosed within the source electrode 52 as viewed in the first direction z. The buffer member 5C is a member for absorbing the shock when the first wire 8A is joined.

[0020] As shown in Figure 7, in the illustrated example, the buffer member 5C may include a base layer 500, a first plating layer 501, a second plating layer 502, a third plating layer 503, and a fourth plating layer 504.

[0021] The base layer 500 may contain a material that is softer than the material of the first wire 8A (Cu (copper) as described later), such as Al (aluminum), which has a lower Vickers hardness. The material of the base layer 500 is not limited and can be any relatively soft material with high conductivity. The thickness of the base layer 500 is not limited and may be, for example, 0.01 mm or more and 0.5 mm or less.

[0022] The third plating layer 503 is positioned in contact with the surface of the substrate layer 500 facing the first side z1 in the first direction z. The thickness of the third plating layer 503 in the first direction z is thinner than the thickness of the substrate layer 500 in the first direction z. The third plating layer 503 is formed by plating the substrate layer 500 and may contain, for example, Ni (nickel). The material of the third plating layer 503 is not limited. Furthermore, the third plating layer 503 may be composed of multiple metal layers made of different metallic materials. The thickness of the third plating layer 503 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less.

[0023] The first plating layer 501 is positioned in contact with the surface of the third plating layer 503 facing the first side z1 in the first direction z. The thickness of the first plating layer 501 in the first direction z is thinner than the thickness of the base layer 500 in the first direction z. The first plating layer 501 is formed by plating the third plating layer 503 and may contain, for example, Cu (copper). The material of the first plating layer 501 is not limited. The first plating layer 501 is located on the outermost first side z1 (outermost) of the buffer member 5C. The thickness of the first plating layer 501 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less. The buffer member 5C may not include the third plating layer 503, and the first plating layer 501 may be positioned in contact with the base layer 500. For example, in the buffer member 5C, the first plating layer 501 containing Ni (nickel) may be positioned in contact with the base layer 500.

[0024] The fourth plating layer 504 is positioned in contact with the surface of the substrate layer 500 facing the second side z2 in the first direction z. The thickness of the fourth plating layer 504 in the first direction z is thinner than the thickness of the substrate layer 500 in the first direction z. The fourth plating layer 504 is formed by plating the substrate layer 500 and may contain, for example, Ni (nickel). The material of the fourth plating layer 504 is not limited. Furthermore, the fourth plating layer 504 may be composed of multiple metal layers made of different metallic materials. The thickness of the fourth plating layer 504 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less. The composition and material of the fourth plating layer 504 may be the same as or different from that of the third plating layer 503. If the third plating layer 503 and the fourth plating layer 504 have the same composition and material, they can be formed in a common plating process, thus simplifying the manufacturing process. On the other hand, the third plating layer 503 and the fourth plating layer 504 may each have a more advantageous configuration and material.

[0025] The second plating layer 502 is positioned in contact with the surface of the fourth plating layer 504 facing the second side z2 in the first direction z. The thickness of the second plating layer 502 in the first direction z is thinner than the thickness of the base layer 500 in the first direction z. The second plating layer 502 is formed by plating the fourth plating layer 504 and may contain, for example, Cu (copper). The material of the second plating layer 502 is not limited. The second plating layer 502 is located on the second side z2 (outermost) of the buffer member 5C. The thickness of the second plating layer 502 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less. The buffer member 5C may not have the fourth plating layer 504, and the second plating layer 502 may be positioned in contact with the base layer 500. The composition and material of the second plating layer 502 may be the same as or different from that of the first plating layer 501. If the first plating layer 501 and the second plating layer 502 have the same composition and material, they can be formed using a common plating process, thus simplifying the manufacturing process. On the other hand, the first plating layer 501 and the second plating layer 502 may each be made of a more advantageous composition and material. For example, the material of the first plating layer 501 may be Cu (copper) and the material of the second plating layer 502 may be Ag (silver).

[0026] The buffer member 5C has a second plating layer 502 that is bonded to the source electrode 52 (surface metal layer 52b) of the first semiconductor element 5A or the second semiconductor element 5B by solid-phase diffusion bonding. In addition, the buffer member 5C has a first wire 8A or the second wire 8B bonded to the first plating layer 501.

[0027] As shown in Figures 2 and 3, the support 1 may have an insulating layer 10, a back metal layer 11, a second metal layer 2A, and a fifth metal layer 2B.

[0028] The insulating layer 10 may be an insulating plate-shaped member containing, for example, ceramic. The back metal layer 11 is laminated on the second side z2 in the first direction z of the insulating layer 10. The back metal layer 11 may contain a metal such as Cu (copper). The second metal layer 2A is laminated on the first side z1 in the first direction z of the insulating layer 10 on the first side x1 in the second direction x. The fifth metal layer 2B is laminated on the first side z1 in the first direction z of the insulating layer 10 on the second side x2 in the second direction x. The second metal layer 2A and the fifth metal layer 2B are separated from each other. The insulating layer 10, the back metal layer 11, the second metal layer 2A, and the fifth metal layer 2B may constitute, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate.

[0029] As shown in Figure 4, the second metal layer 2A may include a base layer 20 and a surface metal layer 21. The base layer 20 may include, for example, Cu (copper). The surface metal layer 21 is located on the first side z1 in the first direction z with respect to the base layer 20. The thickness of the surface metal layer 21 in the first direction z is thinner than the thickness of the base layer 20 in the first direction z. The surface metal layer 21 may include, for example, Ag (silver). The fifth metal layer 2B may include a base layer 20 and a surface metal layer 21, similar to the second metal layer 2A. The thickness of the base layer 20 is not limited in any way and may be, for example, 0.1 mm or more and 5 mm or less. The thickness of the surface metal layer 21 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less.

[0030] The first metal layer 3A is bonded to the second metal layer 2A via the first bonding layer 4A. The first metal layer 3A may include a base layer 30 and a surface metal layer 31. The base layer 30 may include a metal such as Cu (copper). The surface metal layer 31 is located on the second side z2 in the first direction z with respect to the base layer 30. The thickness of the surface metal layer 31 in the first direction z is thinner than the thickness of the base layer 30 in the first direction z. The surface metal layer 31 may include a metal such as Ag (silver). The thickness of the base layer 30 is not limited and may be, for example, 0.5 mm or more and 20 mm or less. The thickness of the surface metal layer 31 is not limited and may be, for example, 0.1 μm or more and 30 μm or less.

[0031] The first bonding layer 4A is for bonding the second metal layer 2A and the first metal layer 3A by solid-phase diffusion bonding. The specific configuration of the first bonding layer 4A is not limited in any way. As shown in Figure 4, in the illustrated example, the first bonding layer 4A may include a base layer 40, a surface metal layer 41, and a surface metal layer 42.

[0032] The base layer 40 may contain a material that is softer than the base layer 30 (for example, has a lower Vickers hardness), such as Al (aluminum). The surface metal layer 41 is located on the first side z1 of the first direction z of the base layer 40. The thickness of the surface metal layer 41 in the first direction z is thinner than the thickness of the base layer 40 in the first direction z. The surface metal layer 41 may contain, for example, Ag (silver). The surface metal layer 42 is located on the second side z2 of the first direction z of the base layer 40. The thickness of the surface metal layer 42 in the first direction z is thinner than the thickness of the base layer 40 in the first direction z. The surface metal layer 42 may contain, for example, Ag (silver). The thickness of the base layer 40 is not limited in any way and may be, for example, 0.01 mm or more and 0.5 mm or less. The thickness of the surface metal layer 41 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less. The thickness of the surface metal layer 42 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less.

[0033] Surface metal layer 31 and surface metal layer 41 are joined by solid-phase diffusion bonding. Surface metal layer 21 and surface metal layer 42 are joined by solid-phase diffusion bonding.

[0034] The fourth metal layer 3B is bonded to the fifth metal layer 2B via the third bonding layer 4B. The fourth metal layer 3B may include, for example, a base layer 30 and a surface metal layer 31 similar to the first metal layer 3A. In this example, the thicknesses of the first metal layer 3A and the fourth metal layer 3B are greater than the thicknesses of the second metal layer 2A and the fifth metal layer 2B.

[0035] The third bonding layer 4B is for bonding the fifth metal layer 2B and the fourth metal layer 3B by solid-phase diffusion bonding. The specific configuration of the third bonding layer 4B is not limited in any way, and the third bonding layer 4B may include, for example, a base layer 40, a surface metal layer 41, and a surface metal layer 42 similar to those of the first bonding layer 4A.

[0036] Multiple first semiconductor elements 5A may be electrically bonded to a first metal layer 3A via multiple second junction layers 6A. In this embodiment, the drain electrodes 51 of the first semiconductor elements 5A may be electrically bonded to the first metal layer 3A via the second junction layer 6A. The second junction layer 6A may be for electrically bonding the first semiconductor elements 5A and the first metal layer 3A, for example, by solid-phase diffusion bonding. The specific configuration of the second junction layer 6A is not limited in any way. When solid-phase diffusion bonding is used, the second junction layer 6A may have a configuration in which metal layers containing, for example, Ag (silver) are formed on both sides of a substrate layer containing Al (aluminum). In this case, metal layers containing, for example, Ag (silver) may be formed on the surfaces of the first semiconductor elements 5A and the first metal layer 3A. This allows, for example, the drain electrodes 51 of multiple first semiconductor elements 5A to be electrically connected to the first metal layer 3A. The specific shape of the second bonding layer 6A is not limited in any way, and in the illustrated example, it may be rectangular.

[0037] Multiple second semiconductor elements 5B may be electrically bonded to a fourth metal layer 3B via multiple fourth junction layers 6B. In this embodiment, the drain electrodes 51 of the second semiconductor elements 5B may be electrically bonded to the fourth metal layer 3B via the fourth junction layer 6B. The fourth junction layer 6B may be for electrically bonding the second semiconductor elements 5B and the fourth metal layer 3B, for example, by solid-phase diffusion bonding. The specific configuration of the fourth junction layer 6B is not limited in any way. When solid-phase diffusion bonding is used, the fourth junction layer 6B may have a configuration in which metal layers containing, for example, Ag (silver) are formed on both sides of a substrate layer containing Al (aluminum). In this case, metal layers containing, for example, Ag (silver) may be formed on the surfaces of the second semiconductor elements 5B and the fourth metal layer 3B. This allows, for example, the drain electrodes 51 of multiple second semiconductor elements 5B to be electrically connected to the fourth metal layer 3B. The specific shape of the fourth bonding layer 6B is not limited in any way, and in the illustrated example, it may be rectangular. The fourth bonding layer 6B may have the same configuration as the second bonding layer 6A, or it may have a different configuration.

[0038] The positive input terminal 7A may be a terminal connected to the positive side of a DC power supply. The positive input terminal 7A may be electrically connected to the first metal layer 3A.

[0039] The output terminal 7B may be a terminal connected to the load side, such as a motor. The output terminal 7B may be electrically connected to the fourth metal layer 3B.

[0040] The negative input terminal 7C may be a terminal connected to the negative side of a DC power supply. The negative input terminal 7C can be electrically connected to, for example, the source electrode 52 of a plurality of second semiconductor elements 5B via a plurality of second wires 8B. In this embodiment, the second wires 8B are, for example, Cu (copper). Note that the second wires 8B are not limited to Cu (copper) and may include metals such as Cu (copper), Al (aluminum), and Au (gold).

[0041] For example, the source electrodes 52 of multiple first semiconductor elements 5A can be electrically connected to the fourth metal layer 3B via multiple first wires 8A. In this embodiment, the first wires 8A are, for example, made of Cu (copper). However, the first wires 8A are not limited to Cu (copper) and may include metals such as Cu (copper), Al (aluminum), and Au (gold).

[0042] The first wire 8A is joined to the source electrode 52 of the first semiconductor element 5A via the buffer member 5C. The second wire 8B is joined to the source electrode 52 of the second semiconductor element 5B via the buffer member 5C. The first wire 8A and the second wire 8B are formed by wedge bonding as will be described later. Since the impact is mitigated by the buffer member 5C, breakage of the first semiconductor element 5A due to impact is suppressed.

[0043] The plurality of control terminals 7D may be terminals for controlling the plurality of first semiconductor elements 5A. The plurality of control terminals 7D can be electrically connected to, for example, the gate electrodes 53, source sense electrodes 54, etc. of the plurality of first semiconductor elements 5A via the plurality of third wires 8C. The third wire 8C can contain a metal such as Cu (copper), Al (aluminum), Au (gold), etc.

[0044] The plurality of control terminals 7E may be terminals for controlling the plurality of second semiconductor elements 5B. The plurality of control terminals 7E can be electrically connected to, for example, the gate electrodes 53, source sense electrodes 54, etc. of the plurality of second semiconductor elements 5B via the plurality of fourth wires 8D. The fourth wire 8D can contain a metal such as Cu (copper), Al (aluminum), Au (gold), etc.

[0045] The encapsulating resin 9 may cover a part of the support 1, the first metal layer 3A, the fourth metal layer 3B, the first bonding layer 4A, the third bonding layer 4B, the plurality of first semiconductor elements 5A, the plurality of second semiconductor elements 5B, etc. A part of the positive input terminal 7A, output terminal 7B, negative input terminal 7C, the plurality of control terminals 7D, and the plurality of control terminals 7E may protrude from the encapsulating resin 9.

[0046] Next, based on FIG. 8, the vehicle C1 on which the semiconductor device A1 is mounted will be described. The vehicle C1 is, for example, an electric vehicle (EV).

[0047] As shown in FIG. 8, the vehicle C1 includes an in-vehicle charger 910, a storage battery 920, and a drive system 930. The in-vehicle charger 910 is wirelessly supplied with power from a power supply facility (not shown) installed outdoors. In addition, the power supply means from the power supply facility to the in-vehicle charger 910 may be wired. The in-vehicle charger 910 is configured with a step-up DC-DC converter. The voltage of the power supplied to the in-vehicle charger 910 is stepped up by the converter and then supplied to the storage battery 920. The stepped-up voltage is, for example, 600V.

[0048] The drive system 930 drives the vehicle C1. The drive system 930 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes a part of the inverter 931. The power stored in the storage battery 920 is supplied to the inverter 931. The power supplied from the storage battery 920 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 8, a step-up DC-DC converter may be further provided between the storage battery 920 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is connected to the drive source 932.

[0049] The drive source 932 has an AC motor and a transmission. When the AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotational speed transmitted from the AC motor and then rotates the drive shaft of the vehicle C1. Thereby, the vehicle C1 is driven. When driving the vehicle C1, it is necessary to freely operate the rotational speed of the AC motor based on information such as the amount of change in the accelerator pedal. The semiconductor device A1 in the inverter 931 is necessary to output AC power with an appropriately changed frequency in order to correspond to the required rotational speed of the AC motor.

[0050] Next, a manufacturing method of the semiconductor device A1 will be described below with reference to FIGS. 9 to 11.

[0051] As shown in Figure 9, a support 1 is prepared. Next, a first bonding layer 4A and a third bonding layer 4B are placed on the support 1. The first bonding layer 4A is placed on the second metal layer 2A, and the third bonding layer 4B is placed on the fifth metal layer 2B. Next, the first metal layer 3A is placed on the first bonding layer 4A. The fourth metal layer 3B may be placed on the third bonding layer 4B. Next, the second bonding layer 6A is placed on the first metal layer 3A. The fourth bonding layer 6B may be placed on the fourth metal layer 3B. Next, the first semiconductor element 5A is placed on the second bonding layer 6A. The second semiconductor element 5B may be placed on the fourth bonding layer 6B. Next, the buffer member 5C is placed on the source electrode 52 of the first semiconductor element 5A. The buffer member 5C may be placed on the source electrode 52 of the second semiconductor element 5B.

[0052] Next, as shown in Figure 10, solid-phase diffusion bonding is performed by applying predetermined temperature and pressure to the support 1, the first bonding layer 4A, the first metal layer 3A, the second bonding layer 6A, the first semiconductor element 5A, and the buffer member 5C. The second metal layer 2A (surface metal layer 21) and the first bonding layer 4A (surface metal layer 42) of the support 1 are bonded by solid-phase diffusion bonding. The first bonding layer 4A (surface metal layer 41) and the first metal layer 3A (surface metal layer 31) are also bonded by solid-phase diffusion bonding. As a result, the second metal layer 2A and the first metal layer 3A are bonded via the first bonding layer 4A. The first metal layer 3A and the second bonding layer 6A are bonded by solid-phase diffusion bonding. The second bonding layer 6A and the first semiconductor element 5A (drain electrode 51) are also bonded by solid-phase diffusion bonding. As a result, the first metal layer 3A and the first semiconductor element 5A are joined via the second bonding layer 6A. The source electrode 52 (surface metal layer 52b) and the buffer member 5C (second plating layer 502) of the first semiconductor element 5A are joined by solid-phase diffusion bonding.

[0053] Alternatively, solid-phase diffusion bonding may be performed by applying predetermined temperatures and pressures to the support 1, the third bonding layer 4B, the fourth metal layer 3B, the fourth bonding layer 6B, the second semiconductor element 5B, and the buffer member 5C. The fifth metal layer 2B (surface metal layer 21) and the third bonding layer 4B (surface metal layer 42) of the support 1 are bonded by solid-phase diffusion bonding. The third bonding layer 4B (surface metal layer 41) and the fourth metal layer 3B (surface metal layer 31) are also bonded by solid-phase diffusion bonding. As a result, the fifth metal layer 2B and the fourth metal layer 3B are bonded via the third bonding layer 4B. The fourth metal layer 3B and the fourth bonding layer 6B are bonded by solid-phase diffusion bonding. The fourth bonding layer 6B and the second semiconductor element 5B (drain electrode 51) are also bonded by solid-phase diffusion bonding. As a result, the fourth metal layer 3B and the second semiconductor element 5B are bonded via the fourth bonding layer 6B. The source electrode 52 (surface metal layer 52b) and the buffer member 5C (second plating layer 502) of the second semiconductor element 5B are joined by solid-phase diffusion bonding.

[0054] Next, the positive input terminal 7A, output terminal 7B, negative input terminal 7C, multiple control terminals 7D, and multiple control terminals 7E are fixed. Then, multiple first wires 8A, multiple second wires 8B, multiple third wires 8C, and multiple fourth wires 8D are formed.

[0055] As shown in Figure 11, the first wire 8A is formed by wedge bonding using a wedge tool B1. The wedge tool B1 presses the wire material B9 against the object to be bonded and joins it using ultrasonic vibration. In forming the first wire 8A, the wedge tool B1 presses the tip of the wire material B9 against the buffer member 5C on the source electrode 52 of the first semiconductor element 5A and applies ultrasonic vibration in the direction of the white arrow shown in the figure to join by ultrasonic welding (first bonding). Subsequently, the wedge tool B1 moves while pulling out the wire material B9 and joins the wire material B9 to the fourth metal layer 3B by ultrasonic welding (second bonding), and the wire material B9 is cut by the cutter B2. This forms the first wire 8A that connects the source electrode 52 of the first semiconductor element 5A and the fourth metal layer 3B. The second wire 8B is also formed by wedge bonding using the wedge tool B1. The first wire 8A and the second wire 8B may be formed by other methods such as ball bonding.

[0056] Next, the semiconductor device A1 is manufactured through processes such as the formation of the sealing resin 9.

[0057] Next, the operation of semiconductor device A1 will be explained.

[0058] In this embodiment, a buffer member 5C is bonded to the source electrode 52 of the first semiconductor element 5A. The first wire 8A is bonded to the source electrode 52 of the first semiconductor element 5A via the buffer member 5C. The first wire 8A is formed by wedge bonding, but the shock is mitigated by the buffer member 5C, thus suppressing damage to the first semiconductor element 5A due to shock. Similarly, a buffer member 5C is bonded to the source electrode 52 of the second semiconductor element 5B. The second wire 8B is bonded to the source electrode 52 of the second semiconductor element 5B via the buffer member 5C. The second wire 8B is formed by wedge bonding, but the shock is mitigated by the buffer member 5C, thus suppressing damage to the second semiconductor element 5B due to shock. As a result, the semiconductor device A1 can suppress damage to the first semiconductor element 5A and the second semiconductor element 5B due to wire bonding. The buffer member 5C is formed by plating the base layer 500. Therefore, compared to the case where a metal plate with a metal layer deposited by sputtering or the like is used, the semiconductor device A1 can suppress an increase in manufacturing costs.

[0059] Furthermore, according to this embodiment, the first wire 8A and the second wire 8B contain Cu and are harder than aluminum wires, etc. If the first wire 8A (second wire 8B) is directly bonded to the source electrode 52, a large impact is applied to the first semiconductor element 5A (second semiconductor element 5B), making it prone to damage. In semiconductor device A1, as described above, the impact on the source electrode 52 during wire bonding is mitigated by the buffer member 5C.

[0060] Furthermore, according to this embodiment, the base layer 500 of the buffer member 5C contains a material (Al) that is softer than the material (Cu) of the first wire 8A and the second wire 8B. Therefore, the buffer member 5C can sufficiently mitigate the impact when joining the first wire 8A and the second wire 8B. Also, the first plating layer 501 contains Cu. Therefore, it is suitable for joining the first wire 8A and the second wire 8B, whose material is Cu. The composition and material of the second plating layer 502 are the same as those of the first plating layer 501. Therefore, since both can be formed in a common plating process, the manufacturing process can be simplified. The second plating layer 502 (Cu) can be solid-phase diffusion bonded to the Au layer of the surface metal layer 52b of the source electrode 52. In addition, a third plating layer 503 (Ni) is interposed between the base layer 500 and the first plating layer 501. The third plating layer 503 can suppress the peeling of the first plating layer 501 from the substrate layer 500. Furthermore, the third plating layer 503 can suppress the diffusion of the material of the first plating layer 501 into the substrate layer 500. Additionally, a fourth plating layer 504 (Ni) is interposed between the substrate layer 500 and the second plating layer 502. The fourth plating layer 504 can suppress the peeling of the second plating layer 502 from the substrate layer 500. Furthermore, the fourth plating layer 504 can suppress the diffusion of the material of the second plating layer 502 into the substrate layer 500.

[0061] Furthermore, according to this embodiment, the buffer member 5C is bonded to the source electrode 52 by solid-phase diffusion bonding. In a semiconductor device different from semiconductor device A1, it is conceivable to bond copper foil to the source electrode 52 using, for example, a silver-fired material. In this case, copper foil with a silver-fired material pre-formed on one side may be used. Such copper foil with a silver-fired material formed on it is expensive because it is necessary to keep the paste-like silver-fired material in a dry state. On the other hand, the buffer member 5C is formed by plating the base layer 500, so it is relatively inexpensive and easy to handle. Therefore, semiconductor device A1 can suppress damage to the first semiconductor element 5A and the second semiconductor element 5B while suppressing an increase in manufacturing costs.

[0062] Furthermore, according to this embodiment, in the manufacturing process of the semiconductor device A1, solid-phase diffusion bonding is performed by applying predetermined temperatures and pressures to the mounted support 1, the first bonding layer 4A, the first metal layer 3A, the second bonding layer 6A, the first semiconductor element 5A, and the buffer member 5C. In other words, the bonding of the second metal layer 2A and the first metal layer 3A via the first bonding layer 4A, the bonding of the first metal layer 3A and the first semiconductor element 5A via the second bonding layer 6A, and the bonding of the buffer member 5C and the source electrode 52 of the first semiconductor element 5A are performed simultaneously (or nearly simultaneously) in the same process. Therefore, the manufacturing process of the semiconductor device A1 is simplified compared to the case where the bonding of the buffer member 5C and the source electrode 52 is performed in a separate process from the other bonding processes.

[0063] In this embodiment, the case in which the first bonding layer 4A bonds the second metal layer 2A and the first metal layer 3A, and the second bonding layer 6A bonds the first metal layer 3A and the first semiconductor element 5A has been described, but the invention is not limited to this. The semiconductor device A1 may have the second metal layer 2A and the first metal layer 3A bonded together by, for example, solder, metal paste material, or sintered metal. Alternatively, the semiconductor device A1 may have the first metal layer 3A and the first semiconductor element 5A bonded together by, for example, solder, metal paste material, or sintered metal. The same applies to the bonding between the fifth metal layer 2B, the fourth metal layer 3B, and the second semiconductor element 5B.

[0064] Figures 12 to 23 show modified examples and other embodiments of the present disclosure. In these figures, elements identical or similar to those in the above embodiments are denoted by the same reference numerals. Furthermore, the configurations of each part in each modified example and each embodiment can be appropriately combined with each other to the extent that no technical inconsistencies arise.

[0065] First Embodiment, First Modification: Figure 12 shows a first modification of semiconductor device A1. In this modification, the semiconductor device A11 has a source electrode 52 of the first semiconductor element 5A that is divided into two parts. In this modification, a buffer member 5C is bonded to each part of the source electrode 52. Each buffer member 5C is contained within each part of the source electrode 52 when viewed in the first direction z.

[0066] Second Embodiment: Figures 13 and 14 show a semiconductor device according to a second embodiment of the present disclosure. In this embodiment, the semiconductor device A2 uses a buffer member 5C instead of the first bonding layer 4A, the second bonding layer 6A, the third bonding layer 4B, and the fourth bonding layer 6B. The configuration and operation of the other parts of this embodiment are the same as in the first embodiment.

[0067] The second metal layer 2A (surface metal layer 21) and the buffer member 5C (second plating layer 502) of the support 1 are joined by solid-phase diffusion bonding. The first metal layer 3A (surface metal layer 31) and the buffer member 5C (first plating layer 501) are also joined by solid-phase diffusion bonding. As a result, the second metal layer 2A and the first metal layer 3A are joined via the buffer member 5C. The first metal layer 3A and the buffer member 5C (second plating layer 502) are joined by solid-phase diffusion bonding. Furthermore, the first semiconductor element 5A (drain electrode 51) and the buffer member 5C (first plating layer 501) are joined by solid-phase diffusion bonding. As a result, the first metal layer 3A and the first semiconductor element 5A are joined via the buffer member 5C.

[0068] Furthermore, the fifth metal layer 2B (surface metal layer 21) and the buffer member 5C (second plating layer 502) of the support 1 are joined by solid-phase diffusion bonding. Also, the fourth metal layer 3B (surface metal layer 31) and the buffer member 5C (first plating layer 501) are joined by solid-phase diffusion bonding. As a result, the fifth metal layer 2B and the fourth metal layer 3B are joined via the buffer member 5C. The fourth metal layer 3B and the buffer member 5C (second plating layer 502) are joined by solid-phase diffusion bonding. Also, the second semiconductor element 5B (drain electrode 51) and the buffer member 5C (first plating layer 501) are joined by solid-phase diffusion bonding. As a result, the fourth metal layer 3B and the second semiconductor element 5B are joined via the buffer member 5C.

[0069] Next, the manufacturing method for semiconductor device A2 will be described below with reference to Figure 15.

[0070] As shown in Figure 15, buffer members 5C are placed on the second metal layer 2A and the fifth metal layer 2B of the support 1, respectively. Next, the first metal layer 3A is placed on the buffer member 5C on the second metal layer 2A. The fourth metal layer 3B may be placed on the buffer member 5C on the fifth metal layer 2B. Next, the buffer member 5C is placed on the first metal layer 3A. The buffer member 5C may be placed on the fourth metal layer 3B. Next, the first semiconductor element 5A is placed on the buffer member 5C on the first metal layer 3A. The second semiconductor element 5B may be placed on the buffer member 5C on the fourth metal layer 3B. Next, the buffer member 5C is placed on the source electrode 52 of the first semiconductor element 5A. The buffer member 5C may be placed on the source electrode 52 of the second semiconductor element 5B. The subsequent manufacturing process is the same as in the first embodiment.

[0071] In this embodiment, the buffer member 5C is also used at each of the junctions between the second metal layer 2A and the first metal layer 3A, the first metal layer 3A and the first semiconductor element 5A, the fifth metal layer 2B and the fourth metal layer 3B, and the fourth metal layer 3B and the second semiconductor element 5B. Therefore, by using a common material (buffer member 5C) at each junction of the semiconductor device A2, the manufacturing cost can be reduced compared to when other materials are used.

[0072] Third Embodiment: Figures 16 and 17 show a semiconductor device according to a third embodiment of the present disclosure. The semiconductor device A3 of this embodiment further comprises a heat sink Hs and a fifth bonding layer 4C. The configuration and operation of the other parts of this embodiment are the same as those of the first embodiment.

[0073] The heat sink Hs is intended to facilitate heat dissipation from the first semiconductor element 5A to the outside. The heat sink Hs may also facilitate heat dissipation from the second semiconductor element 5B to the outside. The specific configuration of the heat sink Hs is not limited in any way, and in the illustrated example, it may have a configuration having a plurality of fins, each extending in the second side z2 in the first direction z. Alternatively, the heat sink Hs may have a flow path through which a cooling fluid flows.

[0074] As shown in Figure 17, the heat sink Hs may include a base material H0 and a surface metal layer H1. The base material H0 may include, for example, Al (aluminum) or Cu (copper). The surface metal layer H1 is located on the first side z1 in the first direction z relative to the base material H0. The thickness of the surface metal layer H1 in the first direction z is thinner than the thickness of the base material H0 in the first direction z. The surface metal layer H1 may include, for example, Ag (silver). The thickness of the base material H0 is not limited in any way and may be, for example, 1 mm or more and 100 mm or less. The thickness of the surface metal layer H1 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less.

[0075] The fifth bonding layer 4C is for bonding the heat sink Hs and the back metal layer 11 by solid-phase diffusion bonding. The specific configuration of the fifth bonding layer 4C is not limited in any way. In the illustrated example, the fifth bonding layer 4C may include a base layer 40, a surface metal layer 41, and a surface metal layer 42, similar to the first bonding layer 4A.

[0076] The back metal layer 11 may include a base layer 110 and a surface metal layer 111. The base layer 110 may include, for example, Cu (copper). The surface metal layer 111 is located on the second side z2 in the first direction z relative to the base layer 110. The thickness of the surface metal layer 111 in the first direction z is thinner than the thickness of the base layer 110 in the first direction z. The surface metal layer 111 may include, for example, Ag (silver). The thickness of the base layer 110 is not limited in any way and may be, for example, 0.1 mm or more and 5 mm or less. The thickness of the surface metal layer 111 is not limited in any way and may be, for example, 0.1 μm or more and 30 μm or less.

[0077] The surface metal layer H1 of the heat sink Hs and the surface metal layer 42 of the fifth bonding layer 4C are joined by solid-phase diffusion bonding. The surface metal layer 111 of the back metal layer 11 and the surface metal layer 41 of the fifth bonding layer 4C are joined by solid-phase diffusion bonding.

[0078] Next, the manufacturing method of semiconductor device A3 will be described below with reference to Figure 18.

[0079] As shown in Figure 18, a heat sink Hs is prepared. Next, the fifth bonding layer 4C is placed on the heat sink Hs. Then, the support 1 is placed on the fifth bonding layer 4C. After that, similar to the first embodiment, the first bonding layer 4A and the third bonding layer 4B are placed on the support 1, the first metal layer 3A is placed on the first bonding layer 4A, the second bonding layer 6A is placed on the first metal layer 3A, the first semiconductor element 5A is placed on the second bonding layer 6A, and the buffer member 5C is placed on the source electrode 52 of the first semiconductor element 5A. Alternatively, the fourth metal layer 3B may be placed on the third bonding layer 4B, the fourth bonding layer 6B may be placed on the fourth metal layer 3B, the second semiconductor element 5B may be placed on the fourth bonding layer 6B, and the buffer member 5C may be placed on the source electrode 52 of the second semiconductor element 5B.

[0080] Subsequently, solid-phase diffusion bonding is performed by applying predetermined temperature and pressure to the heat sink Hs, the fifth bonding layer 4C, the support 1, the first bonding layer 4A, the first metal layer 3A, the second bonding layer 6A, the first semiconductor element 5A, and the buffer member 5C. The heat sink Hs (surface metal layer H1) and the fifth bonding layer 4C (surface metal layer 42) are bonded by solid-phase diffusion bonding. The back metal layer 11 (surface metal layer 111) and the fifth bonding layer 4C (surface metal layer 41) of the support 1 are bonded by solid-phase diffusion bonding. As a result, the heat sink Hs and the back metal layer 11 are bonded via the fifth bonding layer 4C. The subsequent manufacturing process is the same as in the first embodiment. Alternatively, solid-phase diffusion bonding between the heat sink Hs and the back metal layer 11 via the fifth bonding layer 4C may be performed first. Alternatively, after performing solid-phase diffusion bonding as shown in Figures 9 and 10, the heat sink Hs and the support 1 (backside metal layer 11) may be solid-phase diffusion bonded via the fifth bonding layer 4C.

[0081] According to this embodiment, in the manufacturing process of the semiconductor device A3, it is possible to perform solid-phase diffusion bonding, including the heat sink Hs, in a single step. Therefore, the manufacturing process for the semiconductor device A3 can be further simplified.

[0082] Third Embodiment, First Modification: Figure 19 shows a first modification of semiconductor device A3. In this modification, semiconductor device A31 uses a buffer member 5C instead of the first bonding layer 4A, second bonding layer 6A, third bonding layer 4B, fourth bonding layer 6B, and fifth bonding layer 4C.

[0083] The heat sink Hs (surface metal layer H1) and the buffer member 5C (second plating layer 502) are joined by solid-phase diffusion bonding. The back metal layer 11 (surface metal layer 111) of the support 1 and the buffer member 5C (first plating layer 501) are joined by solid-phase diffusion bonding. As a result, the heat sink Hs and the back metal layer 11 are joined via the buffer member 5C. In this modified example, the case in which all of the first bonding layer 4A, second bonding layer 6A, third bonding layer 4B, fourth bonding layer 6B, and fifth bonding layer 4C are replaced with the buffer member 5C has been described, but the invention is not limited to this. Only one of the first bonding layer 4A, second bonding layer 6A, third bonding layer 4B, fourth bonding layer 6B, and fifth bonding layer 4C may be replaced with the buffer member 5C.

[0084] Third Embodiment, Second Modification: Figure 20 shows a second modification of semiconductor device A3. The semiconductor device A32 of this modification does not need to have the first metal layer 3A, the fourth metal layer 3B, the first junction layer 4A, and the third junction layer 4B of semiconductor device A3. The first semiconductor element 5A may be bonded to the second metal layer 2A via the second junction layer 6A. The second semiconductor element 5B may be bonded to the fifth metal layer 2B via the fourth junction layer 6B.

[0085] As can be seen from this modification, the semiconductor device A3 according to the third embodiment of the present disclosure may be configured without the first metal layer 3A and the fourth metal layer 3B.

[0086] Fourth Embodiment: Figures 21 and 22 show a semiconductor device according to a fourth embodiment of the present disclosure. In the semiconductor device A4 of this embodiment, a lead member 8E is bonded to the source electrode 52 of the first semiconductor element 5A instead of the first wire 8A. A lead member may also be bonded to the source electrode 52 of the second semiconductor element 5B instead of the second wire 8B. The configuration and operation of other parts of this embodiment are the same as in the first embodiment.

[0087] In the first to third embodiments, the conductive connecting member joined to the source electrode 52 is shown to be a bonding wire, but is not limited to this. A plate-shaped lead member may be used instead of a bonding wire. In the semiconductor device A4, the source electrode 52 of the first semiconductor element 5A is joined to a lead member 8E instead of a first wire 8A. The lead member 8E is joined to the source electrode 52, for example, by ultrasonic bonding. A buffer member 5C is solid-phase diffusion bonded to the source electrode 52, and the lead member 8E is joined to the source electrode 52 via the buffer member 5C. The buffer member 5C mitigates vibrations and shocks caused by loads during ultrasonic bonding, thus suppressing damage to the first semiconductor element 5A due to shock. The lead member 8E may also be joined to the source electrode 52, for example, by laser bonding. The buffer member 5C can suppress the transmission of heat generated by laser irradiation to the main body of the first semiconductor element 5A, thus suppressing damage to the first semiconductor element 5A due to such heat.

[0088] As can be seen from this embodiment, the conductive connecting member joined to the source electrode 52 is not limited.

[0089] Fifth Embodiment: Figure 23 shows a semiconductor device according to the fifth embodiment of the present disclosure. The semiconductor device A5 of this embodiment has a different package configuration from the semiconductor device A1 of the first embodiment. The configuration and operation of other parts of this embodiment are the same as in the first embodiment.

[0090] The package type of semiconductor device A5 is DFN (Dual Flatpack No-leaded). Semiconductor device A5 comprises leads 71-73, a first semiconductor element 5A, a buffer member 5C, a first wire 8A, a third wire 8C, and a sealing resin 9. The first semiconductor element 5A, buffer member 5C, first wire 8A, third wire 8C, and sealing resin 9 are the same as in the first embodiment. In this embodiment, the shape of the source electrode 52 and gate electrode 53 on the main surface 50a of the first semiconductor element 5A differs from that of the first semiconductor element 5A in the first embodiment.

[0091] Leads 71-73 are electrically connected to the first semiconductor element 5A. Leads 71-73 are made of metal, preferably Cu and Ni, or alloys thereof or 42 alloy. The constituent material of leads 71-73 is not limited, but in this embodiment it is Cu. Leads 71-73 consist of a lead frame formed by, for example, stamping a metal plate.

[0092] The first semiconductor element 5A has its back surface 50b (not shown) joined to the lead 71 via a conductive bonding material (not shown). The drain electrode 51 (not shown) is electrically connected to the lead 71 via the conductive bonding material. The conductive bonding material may be the first bonding layer 4A or the buffer member 5C, or it may be solder, metal paste, or sintered metal. One end of the first wire 8A is joined to the buffer member 5C which is joined to the source electrode 52, and the other end is joined to the lead 72, thereby connecting the source electrode 52 and the lead 72. One end of the third wire 8C is joined to the gate electrode 53, and the other end is joined to the lead 73, thereby connecting the gate electrode 53 and the lead 73.

[0093] In this embodiment as well, a buffer member 5C is bonded to the source electrode 52 of the first semiconductor element 5A, and the first wire 8A is bonded to the source electrode 52 via the buffer member 5C. This reduces the impact when the first wire 8A is bonded, thereby suppressing damage to the first semiconductor element 5A due to impact. Since the buffer member 5C is formed by plating the base layer 500, the semiconductor device A5 can be manufactured without increasing manufacturing costs.

[0094] As can be understood from this embodiment, the package format of the semiconductor device to which this disclosure applies is not limited.

[0095] The semiconductor device and method for manufacturing the semiconductor device described herein are not limited to the embodiments described above. The specific configuration of the semiconductor device and method for manufacturing the semiconductor device described herein can be modified in various ways. This disclosure includes the embodiments described in the following appendix.

[0096] Note 1. A semiconductor device comprising: a semiconductor element (5A) having an element main surface (50a) facing a first side (z1) in a first direction (z), and a first electrode (52) disposed on the element main surface; a buffer member (5C) bonded to the first electrode; and a conductive connecting member (8A) bonded to the buffer member, wherein the buffer member comprises: a base layer (500); a first plating layer (501) disposed on the outermost side of the base layer on the first side in the first direction; and a second plating layer (502) disposed on the outermost side of the base layer on the second side in the first direction, wherein the second plating layer is bonded to the first electrode, and the conductive connecting member is bonded to the first plating layer. Note 2. The semiconductor device according to Note 1, wherein the base layer contains Al. Note 3. The semiconductor device according to Note 1 or 2, wherein the first plating layer and the second plating layer contain Cu. Note 4. The semiconductor device according to any one of Appendix 1 to 3, wherein the buffer member comprises a third plating layer (503) interposed between the substrate layer and the first plating layer. Appendix 5. The semiconductor device according to any one of Appendix 1 to 4, wherein the buffer member comprises a fourth plating layer (504) interposed between the substrate layer and the second plating layer. Appendix 6. The semiconductor device according to any one of Appendix 1 to 5, wherein the first electrode and the second plating layer are solid-phase diffusion bonded. Appendix 7. The semiconductor device according to any one of Appendix 1 to 6, wherein, viewed in the first direction, the buffer member is embedded in the first electrode. Appendix 8. The semiconductor device according to any one of Appendix 1 to 7, wherein the conductive connecting member is a wire. Appendix 9. The semiconductor device according to Appendix 8, wherein the wire contains Cu.Note 10, Second Embodiment, Figure 13. A semiconductor device according to any one of Notes 1 to 9, further comprising: a second buffer member (5C) having a second substrate layer, a fifth plating layer disposed on the outermost side of the second substrate layer in the first direction, and a sixth plating layer disposed on the outermost side of the second substrate layer in the first direction; and a metal layer (3A) on which the semiconductor element is mounted via the second buffer member, wherein the fifth plating layer and the semiconductor element are solid-phase diffusion bonded, and the sixth plating layer and the metal layer are solid-phase diffusion bonded. Note 11, Second Embodiment, Figure 13. A semiconductor device according to Appendix 10, further comprising: a third buffer member (5C) having a third substrate layer; a seventh plating layer disposed on the outermost side of the third substrate layer on the first side in the first direction; and an eighth plating layer disposed on the outermost side of the third substrate layer on the second side in the first direction; and a support (1) on which the metal layer is mounted via the third buffer member, wherein the seventh plating layer and the metal layer are solid-phase diffusion bonded, and the eighth plating layer and the support are solid-phase diffusion bonded. Appendix 12, Third Embodiment, First Modification, Figure 19. A semiconductor device according to Appendix 11, further comprising: a fourth substrate layer; a ninth plating layer disposed on the outermost side of the fourth substrate layer on the first side in the first direction; and a tenth plating layer disposed on the outermost side of the fourth substrate layer on the second side in the first direction; and a heat sink (Hs) bonded to the support via the fourth buffer member, wherein the ninth plating layer and the support are solid-phase diffusion bonded, and the tenth plating layer and the heat sink are solid-phase diffusion bonded. Appendix 13, Figures 9 to 11. A method for manufacturing a semiconductor device, comprising: a step of placing a buffer member (5C) on the first electrode of a semiconductor device (5A) having a main surface of the device facing a first side in a first direction and a first electrode disposed on the main surface of the device; a bonding step of solid-phase diffusion bonding the first electrode and the buffer member; and a step of bonding a conductive connecting member (8A) to the buffer member, wherein the buffer member comprises a base layer, a first plating layer disposed on the outermost side of the base layer on the first side in the first direction, and a second plating layer disposed on the outermost side of the base layer on the second side in the first direction.The method for manufacturing a semiconductor device according to Appendix 13, further comprising the step of placing the semiconductor element (5A) on a metal layer (3A) via a second buffer member (5C) having a second substrate layer, a fifth plating layer disposed on the outermost side of the second substrate layer in the first direction, and a sixth plating layer disposed on the outermost side of the second substrate layer in the first direction, wherein in the bonding step, the semiconductor element and the second buffer member, and the second buffer member and the metal layer are simultaneously solid-phase diffusion bonded.

[0097] A1, A11, A2, A3, A31, A32, A4, A5: semiconductor device, 1: support, 2A: second metal layer, 2B: fifth metal layer, 3A: first metal layer, 3B: fourth metal layer, 4A: first contact Composite layer, 4B: Third bonding layer, 4C: Fifth bonding layer, 5A: First semiconductor element, 5B: Second semiconductor element, 5C: Buffer member, 6A: Second bonding layer, 6B: Fourth bonding layer, 7A: Positive input terminal, 7B : Output terminal, 7C: Negative input terminal, 7D: Control terminal, 7E: Control terminal, 8A: First wire, 8B: Second wire, 8C: Third wire, 8D: Fourth wire, 8E: Lead member, 9: Sealing resin, 10: Insulating layer, 11: Backside metal layer, 20: Base layer, 21: Front metal layer, 30: Base layer, 31: Front metal layer, 40: Base layer, 41: Front metal layer, 42: Front metal layer, 50: Element body Body, 50a: Main surface of the element, 50b: Back surface of the element, 51: Drain electrode, 52: Source electrode, 52a: Substrate layer, 52b: Surface metal layer, 53: Gate electrode, 54: Source sense electrode, 71, 72, 73: Leads, 110: Substrate layer, 111: Surface metal layer, 500: Substrate layer, 501: First plating layer, 502: Second plating layer, 503: Third plating layer, 504: Fourth plating layer, 91 0: Onboard charger, 920: Battery, 930: Drive system, 931: Inverter, 932: Power source, B1: Wedge tool, B2: Cutter, B9: Wire material, C1: Vehicle, H0: Substrate, H1: Surface metal layer, Hs: Heat sink, x: Second direction, x1: First side, x2: Second side, y: Third direction, y1: First side, y2: Second side, z: First direction, z1: ​​First side, z2: Second side

Claims

1. A semiconductor device comprising: a semiconductor element having a main surface facing a first side in a first direction, and a first electrode disposed on the main surface of the element; a buffer member bonded to the first electrode; and a conductive connecting member bonded to the buffer member, wherein the buffer member comprises: a base layer; a first plating layer disposed on the outermost side of the base layer on the first side in the first direction; and a second plating layer disposed on the outermost side of the base layer on the second side in the first direction, the second plating layer being bonded to the first electrode, and the conductive connecting member being bonded to the first plating layer.

2. The semiconductor device according to claim 1, wherein the substrate layer contains Al.

3. The semiconductor device according to claim 1 or 2, wherein the first plating layer and the second plating layer contain Cu.

4. The semiconductor device according to any one of claims 1 to 3, wherein the buffer member comprises a third plating layer interposed between the substrate layer and the first plating layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the buffer member comprises a fourth plating layer interposed between the substrate layer and the second plating layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first electrode and the second plating layer are solid-phase diffusion bonded.

7. The semiconductor device according to any one of claims 1 to 6, wherein, when viewed in the first direction, the buffer member is enclosed within the first electrode.

8. The conductive connecting member is a wire, according to any one of claims 1 to 7.

9. The semiconductor device according to claim 8, wherein the wire contains Cu.

10. A semiconductor device according to any one of claims 1 to 9, further comprising: a second substrate layer; a fifth plating layer disposed on the outermost side of the second substrate layer on the first side in the first direction; and a sixth plating layer disposed on the outermost side of the second substrate layer on the second side in the first direction; and a metal layer on which the semiconductor element is mounted via the second buffer layer, wherein the fifth plating layer and the semiconductor element are solid-phase diffusion bonded, and the sixth plating layer and the metal layer are solid-phase diffusion bonded.

11. The semiconductor device according to claim 10, further comprising: a third substrate layer; a seventh plating layer disposed on the outermost side of the third substrate layer on the first side in the first direction; and an eighth plating layer disposed on the outermost side of the third substrate layer on the second side in the first direction; and a support on which the metal layer is mounted via the third buffer member, wherein the seventh plating layer and the metal layer are solid-phase diffusion bonded, and the eighth plating layer and the support are solid-phase diffusion bonded.

12. A semiconductor device according to claim 11, further comprising: a fourth buffer member having a fourth substrate layer; a ninth plating layer disposed on the outermost side of the fourth substrate layer on the first side in the first direction; and a tenth plating layer disposed on the outermost side of the fourth substrate layer on the second side in the first direction; and a heat sink bonded to the support via the fourth buffer member, wherein the ninth plating layer and the support are solid-phase diffusion bonded, and the tenth plating layer and the heat sink are solid-phase diffusion bonded.

13. A method for manufacturing a semiconductor device, comprising the steps of: placing a buffer member on the first electrode of a semiconductor device having a main surface facing a first side in a first direction and a first electrode disposed on the main surface of the device; solid-phase diffusion bonding the first electrode and the buffer member; and bonding a conductive connecting member to the buffer member, wherein the buffer member comprises a base layer, a first plating layer disposed on the outermost side of the base layer on the first side in the first direction, and a second plating layer disposed on the outermost side of the base layer on the second side in the first direction.

14. A method for manufacturing a semiconductor device according to claim 13, further comprising the step of arranging the semiconductor device on a metal layer via a second buffer member having a second substrate layer, a fifth plating layer disposed on the outermost side of the second substrate layer on the first side in the first direction, and a sixth plating layer disposed on the outermost side of the second substrate layer on the second side in the first direction, wherein in the bonding step, the semiconductor device and the second buffer member, and the second buffer member and the metal layer are simultaneously solid-phase diffusion bonded.

Images