Data input / output circuit and memory

Abstract

Embodiments of the present application relate to the field of memories, and provide a data input / output circuit and a memory. The data input / output circuit comprises: a parallel-to-serial circuit, configured to receive N pieces of data and output the N pieces of data in series within a first time period; a read enable signal generation circuit configured to generate a read enable signal, the read enable signal being at an active level within the first time period; a resistance control circuit electrically connected to the read enable signal generation circuit and configured to receive a termination resistance control code, an output driving resistance control code and the read enable signal, and select, on the basis of the read enable signal, to output the termination resistance control code or output the output driving resistance control code; and an output driving circuit electrically connected to the parallel-to-serial circuit and the resistance control circuit and configured to receive the N pieces of data and a signal outputted by the resistance control circuit, and configure, on the basis of the signal outputted by the resistance control circuit, an output driving resistance value and output the N pieces of data, or configure a termination resistance value, wherein N is a positive integer greater than 1.

Description

A data input / output circuit and a memory

[0001] This application claims priority to Chinese Patent Application No. 202411400832.2, filed on October 9, 2024, entitled “A Data Input / Output Circuit and Memory”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of memory, and in particular to a data input / output circuit and a memory including the input / output circuit. Background Technology

[0003] Currently, memory plays a crucial role in various electronic devices. Reading and writing data in memory (such as Dynamic Random Access Memory, DRAM) requires data input / output terminals (DQ). To ensure stable data transmission on the DQ, ODT (On-Die Termination) resistors and ODI (Output Drive Resistors) need to be configured. In high-speed data transmission, signal reflection and attenuation can degrade signal quality and increase the bit error rate. The value of the ODT resistor can be matched to the characteristic impedance of the data bus, reducing / absorbing signal reflection and ensuring stable data transmission on the DQ pins. During data output, adjusting the value of the output drive resistor controls the drive strength of the output signal, matching it to the characteristic impedance of the external bus, thereby reducing signal reflection and improving signal integrity and stability.

[0004] However, memory read and write operations have strict timing requirements. Therefore, the configuration of the ODT resistor and output drive resistor also has corresponding timing requirements, ensuring that the ODT resistor and output drive resistor are matched to the timing of read and write operations so that data can be correctly read from / written to the memory. Designing a data input / output circuit that allows impedance matching of the memory under different operating conditions is a pressing problem that needs to be solved. Summary of the Invention

[0005] This application provides a data input / output circuit and a memory containing the input / output circuit, which at least helps to solve the problem of impedance matching under different DQ operations.

[0006] According to some embodiments of this application, one aspect of this application provides a data input / output circuit, including a parallel-to-serial converter, a read enable signal generation circuit, a resistor control circuit, and an output drive circuit; wherein, the parallel-to-serial converter is configured to receive N data and serially output the N data within a first time period; the read enable signal generation circuit is configured to generate a read enable signal, which is at an active level within the first time period; the resistor control circuit, electrically connected to the read enable signal generation circuit, is configured to receive a termination resistor control code, an output drive resistor control code, and the read enable signal, and select to output the termination resistor control code or the output drive resistor control code based on the read enable signal; the output drive circuit, electrically connected to the parallel-to-serial converter and the resistor control circuit, is configured to receive the N data and the signal output by the resistor control circuit, and configure an output drive resistor value and output the N data based on the signal output by the resistor control circuit, or configure a termination resistor value; wherein, N is a positive integer greater than 1.

[0007] In some embodiments, the data input / output circuit further includes a pull-up drive circuit and a pull-down drive circuit, and the parallel-to-serial conversion circuit connects the pull-up drive circuit and the pull-down drive circuit to output the N data to the pull-up drive circuit and the pull-down drive circuit.

[0008] In some embodiments, the parallel-to-serial converter includes a first data input port, a second data input port, a third data input port, and a fourth data input port. The parallel-to-serial converter receives the N data through the first to fourth data input ports. The parallel-to-serial converter also receives a first clock, a second clock, a third clock, and a fourth clock, and samples the N data based on the first to fourth clocks, and serially outputs the N data within a first time period.

[0009] The first time period includes a second time period, a third time period, and a fourth time period, wherein the second time period is earlier than the third time period, and the third time period is earlier than the fourth time period; the parallel-to-serial converter is further configured to: output a first level at a fixed time during the second and fourth time periods, and serially output the N data during the third time period;

[0010] The first, second, third, and fourth clocks have the same clock frequency and their phase differences are successively a quarter of a cycle; N is a positive integer multiple of 4.

[0011] In some embodiments, the parallel-to-serial converter includes a first sampling circuit, a second sampling circuit, and a first NAND gate; the first input terminal of the first sampling circuit receives a first clock, and the second input terminal of the first sampling circuit is connected to the first data input port, and the data input to the first data input port is sampled by the first clock; the first input terminal of the second sampling circuit receives a second clock, and the second input terminal of the second sampling circuit receives a second level, and the second level is sampled by the second clock; the first input terminal of the first NAND gate is connected to the output terminal of the first sampling circuit, the second input terminal of the first NAND gate is connected to the output terminal of the second sampling circuit, and the first NAND gate outputs a first sampling result;

[0012] The parallel-to-serial converter further includes a third sampling circuit, a fourth sampling circuit, and a second NAND gate; the first input terminal of the third sampling circuit receives the third clock, and the second input terminal of the third sampling circuit is connected to the third data input port, sampling the data input to the third data input port through the third clock; the first input terminal of the fourth sampling circuit receives the fourth clock, and the second input terminal of the fourth sampling circuit receives the second level, sampling the second level through the fourth clock; the first input terminal of the second NAND gate is connected to the output terminal of the third sampling circuit, the second input terminal of the second NAND gate is connected to the output terminal of the fourth sampling circuit, and the second NAND gate outputs the third sampling result;

[0013] The parallel-to-serial converter further includes a fifth sampling circuit, a sixth sampling circuit, and a third NAND gate; the first input terminal of the fifth sampling circuit receives the second clock, and the second input terminal of the fifth sampling circuit is connected to the second data input port, sampling the data input to the second data input port through the second clock; the first input terminal of the sixth sampling circuit receives the third clock, and the second input terminal of the sixth sampling circuit receives a second level, sampling the second level through the third clock; the first input terminal of the third NAND gate is connected to the output terminal of the fifth sampling circuit, the second input terminal of the third NAND gate is connected to the output terminal of the sixth sampling circuit, and the third NAND gate outputs the second sampling result;

[0014] The parallel-to-serial converter further includes a seventh sampling circuit, an eighth sampling circuit, and a fourth NAND gate; the first input terminal of the seventh sampling circuit receives the fourth clock, and the second input terminal of the seventh sampling circuit is connected to the fourth data input port, sampling the data input to the fourth data input port through the fourth clock; the first input terminal of the eighth sampling circuit receives the first clock, and the second input terminal of the eighth sampling circuit receives a second level, sampling the second level through the first clock; the first input terminal of the fourth NAND gate is connected to the output terminal of the seventh sampling circuit, and the second input terminal of the fourth NAND gate is connected to the output terminal of the eighth sampling circuit, outputting the fourth sampling result;

[0015] The first AND logic circuit is connected to the first to fourth NAND gates, receives the first to fourth sampling results, and performs first AND logic processing on the first to fourth sampling results, thereby outputting the first level in the second time period and the fourth time period, and serially outputting the N data in the third time period.

[0016] In some embodiments, the resistor control circuit includes a first selection circuit, which is configured to: receive a termination resistor control code, an output drive resistor control code, and a read enable signal; when the read enable signal is at an active level, the output terminal of the first selection circuit outputs the output drive resistor control code or its inverted signal; when the read enable signal is at an inactive level, the output terminal of the first selection circuit outputs the termination resistor control code.

[0017] In some embodiments, the first selection circuit includes a fifth NAND gate, a sixth NAND gate, and a seventh NAND gate; the first input of the fifth NAND gate receives a read enable signal, and the second input of the fifth NAND gate receives an output drive resistor control code or its inverted signal; the first input of the sixth NAND gate receives the inverted signal of the read enable signal, and the second input of the sixth NAND gate receives a termination resistor control code; the two inputs of the seventh NAND gate are respectively connected to the outputs of the fifth NAND gate and the sixth NAND gate, and the output of the seventh NAND gate serves as the output of the first selection circuit.

[0018] In some embodiments, the resistor control circuit includes a first selection circuit, which is configured to: receive a termination resistor control code, an output drive resistor control code, and a read enable signal; when the read enable signal is active, the output terminal of the first selection circuit outputs the output drive resistor control code or its inverted signal to the pull-up drive circuit; when the read enable signal is inactive, the output terminal of the first selection circuit outputs the termination resistor control code or its inverted signal to the pull-up drive circuit.

[0019] The resistor control circuit further includes a second selection circuit, which is configured to receive an invalid level, output a drive resistor control code, and the read enable signal. When the read enable signal is valid, the output terminal of the second selection circuit outputs the output drive resistor control code or its inverted signal to the pull-down drive circuit. When the read enable signal is invalid, the output terminal of the second selection circuit outputs the invalid level to the pull-down drive circuit.

[0020] In some embodiments, the output driving circuit includes a pre-driving circuit and a main driving circuit. The pre-driving circuit includes a second AND logic circuit. The first input terminal of the second AND logic circuit receives the N data, and the second input terminal of the second AND logic circuit receives the signal output by the resistor control circuit.

[0021] The second AND logic circuit performs AND-NOT logic processing on the signals received at its first input terminal and the signals received at its second input terminal and then outputs the signal. The main driving circuit includes a PMOS transistor electrically connected between the power supply voltage and the output port. The control terminal of the PMOS transistor receives the signal output by the second AND logic circuit.

[0022] Alternatively, the second AND logic circuit performs AND logic processing on the signal received at its first input terminal and the signal received at its second input terminal, and then outputs the signal. The main driving circuit includes an NMOS transistor electrically connected between the power supply voltage and the output port. The control terminal of the NMOS transistor receives the signal output by the second AND logic circuit.

[0023] In some embodiments, the pull-up drive circuit is connected to the output terminal of the parallel-to-serial conversion circuit and receives the N data within a first time period; the pull-down drive circuit is connected to the output terminal of the parallel-to-serial conversion circuit and receives the N data within a first time period.

[0024] The pull-up drive circuit is configured to: output a high level among the N data during a first time period, and configure the output drive resistor value based on the output drive resistor control code; the pull-down drive circuit is configured to: output a low level among the N data during a first time period, and configure the output drive resistor value based on the output drive resistor control code.

[0025] The pull-up drive circuit is also configured to: configure a termination resistor value outside the first time period.

[0026] According to some embodiments of this application, another aspect of this application provides a memory, the memory including the input / output circuit described in any of the foregoing embodiments, the memory further including a storage array and a data transmission circuit, the storage array storing data; when a read operation is performed on the memory, the data is read out via the storage array, transmitted via the data transmission circuit, and then output via the data input / output circuit.

[0027] The technical solution provided in this application has at least the following advantages: the memory can perform impedance matching under both read and non-read operations. Since the timing of the RTT state switching of the termination resistor is the same as the timing of the data output during a read operation, by multiplexing the timing of the RTT state switching of the termination resistor and the timing of the control data output, and selecting the termination resistor control code or the output drive resistor control code through the read enable signal, the signal of the output control codeword matches the timing of the data output by the parallel-to-serial circuit. Therefore, power consumption and circuit area can be reduced, while avoiding the impact on the tADC. Furthermore, the control code of the termination resistor and the control code of the output drive resistor are combined into a single resistor control circuit, which can save circuit area while ensuring normal circuit operation. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0029] Figure 1 is a schematic diagram of a data input / output circuit provided in an embodiment of this disclosure.

[0030] Figure 2 is a schematic diagram of another data input / output circuit provided in an embodiment of this disclosure.

[0031] Figure 3 is a schematic diagram of a parallel-to-serial conversion circuit provided in an embodiment of this disclosure.

[0032] Figure 4 is a timing diagram of a parallel-to-serial conversion circuit provided in an embodiment of this disclosure.

[0033] Figure 5 is a schematic diagram of a read enable signal generation circuit provided in an embodiment of this disclosure.

[0034] Figure 6 is a timing diagram of the read enable signal generation circuit provided in an embodiment of this disclosure.

[0035] Figure 7 is a schematic diagram of a first selection circuit provided in an embodiment of this disclosure.

[0036] Figure 8 is a timing diagram of the first selection circuit provided in an embodiment of this disclosure.

[0037] Figure 9 is a schematic diagram of the circuit structure of a second selection circuit provided in an embodiment of this disclosure.

[0038] Figure 10 is a schematic diagram of a pull-up pre-drive circuit provided in an embodiment of this disclosure.

[0039] Figure 11 is a schematic diagram of the structure of a first sub-pull-up main drive circuit provided in an embodiment of this disclosure.

[0040] Figure 12 is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0041] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily practice the invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. For example, the exemplary embodiments provided herein are thought to be implementable by combining them, in whole or in part. Specifically, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, can be understood as a description relating to another exemplary embodiment, unless a contrary or contradictory description is provided therein.

[0042] Throughout this specification, when any part is referred to as being “connected” to another part, it includes cases where any part and another part are “indirectly connected” to each other due to the presence of another part between them, as well as cases where any part and another part are “directly connected” to each other. For example, it should be understood that when an element is referred to as being “connected” or “attached” or “on another element” to another element, it may be directly connected or attached to or on that other element, or there may be an intermediate element present. Conversely, when an element is referred to as being “directly connected” or “directly attached” to another element, or referred to as being “in contact” or “in contact” with another element, there is no intermediate element at the point of contact.

[0043] Furthermore, "electrical connection" conceptually includes both physical connection and physical disconnection. It is understood that when an element is referred to using terms such as "first" and "second," the element is not limited in this respect. These terms may be used only to distinguish the element from other elements and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

[0044] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0045] Figure 1 is a schematic diagram of a data input / output circuit provided in an embodiment of this disclosure. As shown in Figure 1, the data input / output circuit 100 includes a parallel-to-serial converter 110, a read enable signal generation circuit 120, a resistor control circuit 130, and an output drive circuit 140. Wherein:

[0046] The parallel-to-serial converter 110 is configured to receive N data points D0, D1, D2, ..., D... N-2 D N-1 The inverted signals D0B, D1B, D2B…, D N-2 B, D N-1 B, and serially output the N data D0-D within the first time period. N-1 Its output signal is DATA. N is a positive integer greater than 1, such as 4, 8, 16, 32, etc. In some embodiments, N may also be other values.

[0047] The read enable signal generation circuit 120 is configured to generate a read enable signal Read_enable, which is an effective level during a first time period. In this embodiment, a high level is used as an example of an effective level. It should be understood that a low level can also be used as an effective level. High and low levels can be achieved simply by inverting them. During signal transmission, signals are frequently driven by circuits such as inverters; therefore, for the same signal, its inverted signal can be obtained again by simple inversion. Thus, using either a high or low level as an effective level is common. Unless otherwise stated, in this embodiment, a signal itself and its inverted signal are considered as simple variations.

[0048] The resistor control circuit 130 is electrically connected to the read enable signal generation circuit 120 and is configured to receive the termination resistor control code ODT, the output drive resistor control code RON, and the read enable signal Read_enable, and select either the termination resistor control code ODT or the output drive resistor control code RON as its output signal RON_ODT_code based on the read enable signal Read_enable.

[0049] The output drive circuit 140, electrically connected to the parallel-to-serial converter circuit 110 and the resistor control circuit 130, is configured to receive the N data (DATA) and the output signal RON_ODT_code of the resistor control circuit 130, and configure the output drive resistor value and output the N data based on the output signal RON_ODT_code of the resistor control circuit 130, or configure the termination resistor value.

[0050] Specifically, when the memory performs a read operation and outputs data via the input / output circuit and the DQ terminal, the parallel-to-serial converter 110 outputs data DATA during the first time period. At this time, the read enable signal Read_enable is at an active level. Based on the active level of the read enable signal Read_enable, the resistor control circuit 130 selects the output drive resistor control code RON as its output signal RON_ODT_code. Based on the output drive resistor control code RON, the output drive circuit 140 serially outputs the data DATA received from the parallel-to-serial converter 110 and configures the corresponding output drive resistor value.

[0051] When the memory is in other stages of a read operation, or in a write operation or other operation, the input / output circuit and the DQ terminal do not output data. At this time, the parallel-to-serial circuit 110 does not output data DATA, the read enable signal Read_enable is invalid, the resistor control circuit 130 selects the termination resistor control code ODT as its output signal RON_ODT_code based on the invalid level of the read enable signal Read_enable; the output drive circuit 140 configures the corresponding termination resistor value based on the termination resistor control code ODT.

[0052] In other words, this disclosure provides a data input / output circuit, including a parallel-to-serial converter, a read enable signal generation circuit, a resistor control circuit, and an output drive circuit. The read enable signal generated by the read enable signal generation circuit is time-matched with the output data of the parallel-to-serial converter (i.e., the read enable signal is valid during the first time period of the serial output data from the parallel-to-serial converter). The resistor control circuit receives the termination resistor control code and the output drive resistor control code, and selects either the output termination resistor control code or the output drive resistor control code based on the timing of the output data from the parallel-to-serial converter using the read enable signal. This controls the output drive circuit, configuring the output drive resistor value and outputting data corresponding to a read operation, or configuring the termination resistor value corresponding to a non-read operation. Therefore, the memory can perform impedance matching under both read and non-read operations. Since the timing of the termination resistor RTT state switching is the same as the timing of the read operation output data, the timing of the termination resistor RTT state switching and the timing of controlling the data output are reused. Therefore, power consumption and circuit area can be reduced, while avoiding the impact on the tADC. On the other hand, the control codes for the termination resistor and the output drive resistor are combined into a single resistor control circuit, which can save circuit area while ensuring normal circuit operation.

[0053] Figure 2 is a schematic diagram of another data input / output circuit provided in an embodiment of this disclosure. In some cases, it can be an extended implementation of the embodiment shown in Figure 1, encompassing all the contents of the embodiment in Figure 1. As shown in Figures 1 and 2, the data input / output circuit 100 includes a parallel-to-serial converter 110, a read enable signal generation circuit 120, a resistor control circuit 130, and an output drive circuit 140. Specifically, the output drive circuit 140 includes pull-up drive circuits 141 and 143 and pull-down drive circuits 142 and 144. The parallel-to-serial converter 110 is connected to the pull-up drive circuit 141 and the pull-down drive circuit 142, and outputs N data DATA to the pull-up drive circuit 141 and the pull-down drive circuit 142.

[0054] The resistor control circuit 130 includes a pull-up resistor control circuit 131 and a pull-down resistor control circuit 132. The pull-up resistor control circuit 131 receives the termination resistor control code ODT, the output drive resistor control code RON, and the read enable signal Read_enable, and configures the output drive resistor value or termination resistor value of the pull-up drive circuit 141 based on the read enable signal Read_enable. The pull-down resistor control circuit 132 receives the output drive resistor control code RON and the read enable signal Read_enable, and configures the output drive resistor value of the pull-down drive circuit 142 based on the read enable signal Read_enable, or sets it to float (or to a high impedance state). When the read enable signal Read_enable is at a valid level, the pull-down resistor control circuit 132 selects the output drive resistor control code RON as its output signal RON_PD_CTL; when the read enable signal Read_enable is at an invalid level, the pull-down resistor control circuit 132 outputs an invalid level, turning off the corresponding pull-down drive circuit 142, causing it to output an invalid level (or to be in a high impedance state). In other embodiments, the pull-down resistor control circuit 132 may also receive a low level Vss to facilitate circuit design corresponding to the termination resistor control code ODT received by the pull-up resistor control circuit 131.

[0055] In some embodiments, the output drive resistor control code RON includes the pull-up output drive resistor control code Pu_Ron and the pull-down output drive resistor control code Pd_Ron. The pull-up resistor control circuit 131 outputs the pull-up output drive resistor control code Pu_Ron or the termination resistor control code ODT to the pull-up drive circuit 141, and the pull-down resistor control circuit 132 outputs the pull-down output drive resistor control code Pd_Ron or outputs an invalid level to the pull-down drive circuit 142.

[0056] In this embodiment, since the pull-up drive circuit 141 and the pull-down drive circuit 142 receive control signals that are timed and selected, the pull-up drive circuit 141 and the pull-down drive circuit 142 can be connected to the same parallel-to-serial converter circuit and receive the same data DATA.

[0057] Before and after data is read from the memory, the DQ terminal needs to be in a floating state. Due to the different circuit structures of pull-up and pull-down drive circuits, in existing technology, two sets of parallel-to-serial conversion circuits are required to output to the pull-up and pull-down drive circuits respectively. This ensures that before and after reading N data points, the pull-up drive circuit receives the default signal output by the parallel-to-serial conversion circuit, causing the DQ terminal to float (i.e., in a high-impedance state), and the pull-down drive circuit receives the default signal output by the parallel-to-serial conversion circuit, causing the DQ terminal to float (i.e., in a high-impedance state). For example, when the pull-up drive circuit is composed of PMOS transistors and the pull-down drive circuit is composed of NMOS transistors, the pull-up drive circuit outputs a high-impedance state when receiving a high-level signal, and the pull-down drive circuit outputs a high-impedance state when receiving a low-level signal. In this case, the control signal requirements of the pull-up and pull-down drive circuits are different. That is, two sets of parallel-to-serial conversion circuits are needed. When the memory is not reading data, the pull-up drive circuit receives the invalid level, and the pull-down drive circuit receives the invalid level, so that the DQ terminal maintains a high impedance output.

[0058] By means of the scheme in this embodiment, since the timing of the RTT state switching of the termination resistor is the same as the timing of the data output during the read operation, the timing of the RTT state switching of the termination resistor (termination resistor control timing) is used to control the pull-up drive circuit 141. This allows the pull-up resistor control circuit to directly configure the termination resistor value of the pull-up drive circuit during non-read operations (and keep the DQ terminal in a high-impedance output state). Therefore, the pull-up drive circuit and the pull-down drive circuit can be connected to the same parallel-to-serial circuit (that is, the parallel-to-serial circuit only needs to keep the output of the pull-down drive circuit in a high-impedance state), realizing the multiplexing of the parallel-to-serial circuit. Under the premise of ensuring the normal operation of the circuit, the circuit area can be further saved.

[0059] In some embodiments, referring to FIG2, the parallel-to-serial converter 110 may include a first data input port D0, a second data input port D1, a third data input port D2, and a fourth data input port D3. The parallel-to-serial converter 110 receives N data D0-D through the first to fourth data input ports D0-D3. N-1 The inverted signal D0B-D N-1 B; the parallel-to-serial converter also receives the first clock CLK0D, the second clock CLK1D, the third clock CLK2D, and the fourth clock CLK3D, and based on the first to fourth clocks CLK0D-CLK3D, processes N data D0-D N-1 The inverted signal D0B-D N-1B sampling is performed, and N data points are serially output within the first time period T1. Referring to Figure 4, the clock frequencies of the first clock CLK0D, the second clock CLK1D, the third clock CLK2D, and the fourth clock CLK3D are the same, and their phase differences are successively one-quarter of a cycle. In some embodiments, N can be a positive integer multiple of 4, such as 4, 8, 16, or 32, and the first to fourth data input ports D0-D3 sequentially receive N data points D0-D1. N-1 The signal is an inverted signal, and is sampled alternately by the first to fourth clock cycles CLK0D-CLK3D. In other embodiments, N may not be a positive integer multiple of 4; only normal sampling is required, and then the extra data is masked out. For example, N can be 15, and the last sampled data is considered invalid.

[0060] Referring only to Figure 4, the first time period T1 includes a second time period T2, a third time period T3, and a fourth time period T4, with the second time period T2 preceding the third time period T3 and the third time period T3 preceding the fourth time period T4. The serial-to-parallel converter circuit is further configured to output a first level at a fixed rate during the second and fourth time periods, and to serially output N data points during the third time period. In some embodiments, the first level can be a high level; correspondingly, this high level is inverted and enters the pull-up output circuit composed of PMOS transistors and the pull-down output circuit composed of NMOS transistors at the DQ terminal, causing the pull-up output circuit to output a high level at the DQ terminal during the second time period T2 and the fourth time period T4, and the pull-down output circuit to output a high impedance state during the second and fourth time periods T2 and the fourth time period T4. In some embodiments, the first level can also be a low level; correspondingly, this low level is not inverted and enters the pull-up output circuit composed of PMOS transistors and the pull-down output circuit composed of NMOS transistors at the DQ terminal, so that the pull-up output circuit outputs a high level at the DQ terminal in the second time period T2 and the fourth time period T4, and the pull-down output circuit outputs a high impedance state at the DQ terminal in the second time period T2 and the fourth time period T4. In some embodiments, the pull-up output circuit can also be composed of NMOS transistors, and / or the pull-down output circuit can also be composed of PMOS transistors. In this case, the high level can enter the pull-up output circuit and / or the pull-down output circuit without inversion to output a high impedance state at the DQ terminal, and the low level can enter the pull-up output circuit and / or the pull-down output circuit through inversion to output a high impedance state at the DQ terminal.

[0061] In some other embodiments, the first time period T1 also includes other time periods besides the second time period T2, the third time period T3, and the fourth time period T4. That is, the second time period T2 and the third time period T3 may be discontinuous, and the third time period T3 and the fourth time period T4 may be discontinuous.

[0062] In some embodiments, the duration of the second time period is a unit time interval (1 UI), the duration of the fourth time period is a unit time interval (1 UI), and N data points D0-D N-1 Each data point is also 1 UI wide to facilitate tADC measurements.

[0063] Therefore, by setting a fixed output level in the second and fourth time periods, the preset information for tADC measurement can be manually set before and after N data outputs, thereby measuring whether the tADC meets the requirements.

[0064] Figure 3 is a schematic diagram of a parallel-to-serial converter circuit provided in an embodiment of this disclosure. Figure 4 shows the timing diagram of the parallel-to-serial converter circuit. Referring to Figure 3, the parallel-to-serial converter circuit 110 includes a first sampling circuit 111, a second sampling circuit 112, and a first NAND gate NAND1. The first input terminal of the first sampling circuit 111 receives a first clock CLK0D, and the second input terminal of the first sampling circuit is connected to a first data input port D0 to receive data input into the first data input port D0. The data input into the first data input port D0 is sampled by the first clock CLK0D.

[0065] Figure 4 shows an example where N=16, with data D0, D4, D8, and D1 sequentially transmitted within the first data input port D0. 12 The inverted signals D0B, D4B, D8B, D 12 B, and defaults to a low level L when no data is being transmitted. The first clock CLK0D samples these signals sequentially to obtain the sampling result CLKD0. Figure 3 shows the first sampling circuit 111 as an AND gate (NAND gate + NOT gate). In other embodiments, all sampling circuits, including the first sampling circuit, can also use OR gates (NOR gates and NOT gates), and flip-flops (such as D flip-flops) and other sampling circuits.

[0066] The first input of the second sampling circuit 112 receives the second clock CLK1D, and the second input receives the second level Vdd. The second level Vdd is sampled by the second clock CLK1D, and the sampled data is inverted. The first input of the first NAND gate NAND1 is connected to the output of the first sampling circuit 111, receiving the sampling result CLKD0 output by the first sampling circuit. The second input of the first NAND gate NAND1 is connected to the output of the second sampling circuit 112, receiving the sampling result CLKB0 output by the second sampling circuit. After performing a NAND operation on CLKD0 and CLKB0, the first NAND gate outputs the first sampling result Sample_0.

[0067] When the second sampling circuit is an AND gate, the second level Vdd is correspondingly set to a high level H. In other embodiments, the second level can be a low level; correspondingly, the second sampling circuit uses an OR gate, and the second sampling circuit does not invert the sampling result.

[0068] The parallel-to-serial conversion circuit 110 also includes a third sampling circuit 113, a fourth sampling circuit 114, and a second NAND gate NAND2. The first input terminal of the third sampling circuit 113 receives the third clock CLK2D, and the second input terminal of the third sampling circuit 113 is connected to the third data input port D2 to receive the data input from the third data input port D2. The data input from the third data input port D2 (referred to as D2, D6, and D7 in Figure 4) is processed by the third clock CLK2D. 10 D 14 For example, sampling is performed to obtain the sampling result CLKD2; the first input terminal of the fourth sampling circuit 114 receives the fourth clock CLK3D, and the second input terminal of the fourth sampling circuit 114 receives the second level Vdd. The second level Vdd is sampled by the fourth clock CLK3D and then inverted to obtain the sampling result CLKB2; the first input terminal of the second NAND gate NAND2 is connected to the output terminal of the third sampling circuit 113 to receive its output sampling result CLKD2, and the second input terminal of the second NAND gate is connected to the output terminal of the fourth sampling circuit to receive its output sampling result CLKB2. The second NAND gate NAND2 performs NAND logic processing on CLKD2 and CLKB2 and outputs the third sampling result Sample_2.

[0069] The parallel-to-serial conversion circuit also includes a fifth sampling circuit 115, a sixth sampling circuit 116, and a third NAND gate 3; the first input of the fifth sampling circuit 115 receives the second clock CLK1D, and the second input of the fifth sampling circuit 115 is connected to the second data input port D1 to receive the data input from the second data input port D1 (referred to as D1, D5, D9, D in Figure 4). 13 For example, the data input to the second data input port D1 is sampled by the second clock CLK1D to obtain the sampling result CLKD1; the first input of the sixth sampling circuit 116 receives the third clock CLK2D, the second input of the sixth sampling circuit 116 receives the second level Vdd, the second level Vdd is sampled by the third clock CLK2D, and then inverted to obtain the sampling result CLKB1; the first input of the third NAND gate NAND3 is connected to the output of the fifth sampling circuit 115 to receive the sampling result CLKD1, the second input of the third NAND gate NAND3 is connected to the output of the sixth sampling circuit 116 to receive the sampling result CLKB1, the third NAND gate NAND3 performs NAND logic processing on CLKD1 and CLKB1 to output the second sampling result Sample_1.

[0070] The parallel-to-serial conversion circuit 110 also includes a seventh sampling circuit 117, an eighth sampling circuit 118, and a fourth NAND gate 4; the first input of the seventh sampling circuit 117 receives the fourth clock CLK3D, and the second input of the seventh sampling circuit 117 is connected to the fourth data input port D3 to receive the data input from the fourth data input port D3 (referred to as D3, D7, and D8 in Figure 4). 11 D 15 For example, the data input to the fourth data input port D3 is sampled by the fourth clock CLK3D to obtain the sampling result CLKD3; the first input of the eighth sampling circuit 118 receives the first clock CLK0D, and the second input of the eighth sampling circuit 118 receives the second level Vdd. The second level Vdd is sampled by the first clock CLK0D to obtain the sampling result CLKB3; the first input of the fourth NAND gate NAND4 is connected to the output of the seventh sampling circuit 117 to receive the sampling result CLKD3, and the second input of the fourth NAND gate NAND4 is connected to the output of the eighth sampling circuit 118 to receive the sampling result CLKB3. The fourth NAND gate NAND4 performs NAND logic processing on CLKD3 and CLKB3 to output the fourth sampling result Sample_3.

[0071] The above example uses an AND logic circuit as a sampling circuit, but it should be understood that OR logic circuits and sequential circuits (such as flip-flop circuits, specifically, D flip-flop circuits) can also implement the above sampling logic, thus serving as other embodiments of the sampling logic circuit.

[0072] The parallel-to-serial converter 110 also includes a first AND logic circuit 119. The first AND logic circuit 119 is connected to the outputs of the first to fourth NAND gates NAND1-NAND4, receives the first to fourth sampling results Sample_0-Sample_3 output by the first to fourth NAND gates NAND1-NAND4, and performs first AND logic processing on the first to fourth sampling results, thereby outputting a first level during the second and fourth time periods, and serially outputting N data points during the third time period. In the embodiments shown in Figures 3 and 4, the first level is a high level H. Figure 3 uses a combination of multiple two-input NAND gates to implement the AND logic as an example. In other embodiments, the AND logic can also be implemented directly using, for example, four-input NAND gates.

[0073] Referring to Figure 4, CLK represents the external clock cycle, and CL is the time point at which the memory begins outputting data. Starting from the CL time point, the first to fourth data input ports D0-D3 successively receive N data points. In Figure 4, taking N=16 as an example, starting from the CL time point, the first data input port D0 begins receiving data D0, D4, D8, and D9. 12The inverted signals D0B, D4B, D8B, D 12 B. In addition, except for the timing of data transmission, the data signal defaults to a low level L. The data width of each data point is 2T, where T is the external clock cycle, and each half-clock cycle is a unit time interval of 1UI. In the N data points, the interval between any two adjacent data points is 1UI. Therefore, the second data input port D1 receives data D1, D5, D9, D... sequentially starting from CL+1UI. 13 The inverted signals D1B, D5B, D9B, D 13 B, the third data input port D2 receives data sequentially from CL+2UI, D2, D6, and D7. 10 D 14 The inverted signals D2B, D6B, D 10 B, D 14 B, the fourth data input port D3 receives data sequentially from CL+3UI, D3, D7, and D... 11 D 15 The inverted signals D3B, D7B, and D 11 B, D 15 B, the data width of each data point is 2T.

[0074] Correspondingly, the clock periods of the first to fourth clocks, CLK0D-CLK3D, are also 2T, and their timings differ by 1UI. After sampling, the data width of each sample result, CLKD0-CLKB3, is 1T. Subsequently, the width of the sample result is aligned using a clock interval of 1UI from the sampling clock, resulting in sample results Sample_0-Sample_3 with a data width of 1UI.

[0075] In other words, N data points are first sampled sequentially using a four-phase clock (CLK0D-CLK3D, the first to fourth clocks). Then, the width of the sampled results is aligned with a clock interval of 1UI from the sampling clock, resulting in the first to fourth sampled results, Sample_0-Sample_3, where each data point has a width of 1UI. Furthermore, the first to fourth sampled results, Sample_0-Sample_3, carry the phase information of the clock. After merging the data through the first AND logic processing, the parallel-to-serial conversion is completed, resulting in N data points serially output with a width of 1UI. Moreover, this circuit defaults to a high-level output when neither clock nor data is being transmitted, allowing subsequent output driver circuits to default to a high-impedance output when no data is being transmitted.

[0076] Figure 5 shows a schematic diagram of a read enable signal generation circuit. Figure 6 shows a timing diagram of the read enable signal generation circuit. The read enable signal generation circuit 120 includes an even reset signal sampling circuit FF1, an odd reset signal sampling circuit FF2, and a read enable signal NAND gate NANDR;

[0077] Taking a D flip-flop (DFF) as an example, the data input terminal of the even reset signal sampling circuit FF1 receives the even reset signal TRST_EVEN with ODT timing information, and the clock input terminal receives the corresponding even sampling clock signal CK1. The even reset signal TRST_EVEN is sampled by the even sampling clock signal CK1 to match the data output timing of the parallel-to-serial converter circuit and obtain the even sampling result.

[0078] The odd reset signal sampling circuit also takes a D flip-flop (DFF) as an example. The data input terminal of the odd reset signal sampling circuit FF2 receives the odd reset signal TRST_ODD with ODT timing information, and the clock input terminal receives the odd sampling clock signal CK3. CK1 and CK3 are differential clock signals. The odd reset signal TRST_ODD is sampled by the odd sampling clock signal CK3 to match the data output timing of the parallel-to-serial converter circuit and obtain the odd sampling result.

[0079] The NAND gate NANDR receives both even and odd sampled results. It performs AND logic processing on the even and odd sampled results, merging the odd and even paths to obtain the read enable signal that matches the timing of the serial-to-parallel converter. The read enable signal remains active for the first 1UI of data output (high level in Figure 6), and ends its active state 1UI after the data output ends, transitioning to an inactive level.

[0080] The odd reset signal and even reset signal are the processing signals for the odd and even paths during internal processing. During data output, the odd and even paths need to be merged. Figure 6 uses the even reset signal TRST_EVEN as an example for reading data first. First, four data streams enter the parallel-to-serial converter sequentially from the first to the fourth data ports D0-D3, with a phase difference of 1UI between the four streams. If the first data stream entering D0 is the first bit read, and the burst length (BL) is 16, then the even reset signal TRST_EVEN is active from time CL, and the odd reset signal TRST_ODD is active from time CL-1(T). The pulse width of both the odd reset signal TRST_ODD and the even reset signal TRST_EVEN is 8T (8 external clock cycles). The sampling clock CK1 is from the same source and frequency as the first clock, and is 1UI earlier than the first clock CK0D. CK1 or CK3 starts sampling data at CL-0.5(T). In the embodiment where the even reset signal TRST_EVEN reads data first, CK1 starts sampling data at CL-0.5(T); if the odd reset signal TRST_ODD reads data first, then CK3 starts sampling data at CL-0.5(T). After data merging via NAND gates, a pulse signal with a width of 9T is generated, with an effective level from CL-0.5 to CL+8.5(T).

[0081] In other embodiments, the read enable signal generation circuit can also be generated by other circuits, as long as it is ensured that a pulse signal with an effective level from CL-0.5 to CL+8.5(T) is generated to ensure that the timing of the data signal and the control signal entering the drive circuit is matched.

[0082] In some embodiments, as shown in FIG2, the resistor control circuit 130 includes a first selection circuit 1311. FIG7 is a schematic diagram of the structure of a first selection circuit provided in an embodiment of the present disclosure. FIG8 illustrates a timing diagram of a first selection circuit. As shown in FIG7, the first selection circuit 1311 is configured to: receive a termination resistor control code ODT, an output drive resistor control code RON, and a read enable signal Read_enable. When the read enable signal Read_enable is at an active level, the output terminal of the first selection circuit 1311 outputs the output drive resistor control code RON as the output signal RON_ODT_CTL of the first selection circuit 1311; when the read enable signal Read_enable is at an inactive level, the output terminal of the first selection circuit 1311 outputs the termination resistor control code ODT as the output signal RON_ODT_CTL of the first selection circuit 1311.

[0083] It should be understood that, in order to improve signal quality, inverters and other driving devices are placed throughout digital circuits to enhance driving capability. Since a signal and its inverted signal can be easily converted with only one inverter, and given the inverse relationship between the driving signals of PMOS and NMOS transistors, in the embodiments of this disclosure, unless otherwise stated, multiple input signals or output signals can be replaced with their inverted signals. For example, in Figure 7, the signal RON_ODT_CTL passes through two stages of inverters at output. However, based on the need for driving capability, one stage of inverter can also be set in a subsequent path. Therefore, the signal RON_ODT_CTL can also be output with only one stage of inverter, thus the output signal is its inverted signal.

[0084] Referring to Figure 8, which uses a high-level signal as an example, when the read enable signal Read_enable is invalid (i.e., before data is read), the output signal RON_ODT_CTL of the first selection circuit 1311 (which also serves as the output signal of the resistor control circuit) is the termination resistor control code ODT. When the read enable signal Read_enable is valid (i.e., during data reading), the output signal RON_ODT_CTL of the first selection circuit 1311 (which also serves as the output signal of the resistor control circuit) is the inverted signal of the output drive resistor control code RON. When the read enable signal Read_enable is invalid (i.e., after data reading ends), the output signal RON_ODT_CTL of the first selection circuit 1311 (which also serves as the output signal of the resistor control circuit) is the termination resistor control code ODT. Therefore, the resistor control circuit automatically outputs different control codes during the read and non-read stages, thus matching the different impedances required for different memory operation stages (e.g., read and non-read stages).

[0085] The timing diagram in Figure 8 can be implemented using the circuit in Figure 7. As shown in Figure 7, the first selection circuit 1311 includes a fifth NAND gate NAND5, a sixth NAND gate NAND6, and a seventh NAND gate NAND7. The first input of the fifth NAND gate NAND5 receives the read enable signal Read_enable, and the second input of the fifth NAND gate NAND5 receives the output drive resistor control code RON or its inverted signal RONB. The first input of the sixth NAND gate NAND6 receives the inverted signal of the read enable signal Read_enable, and the second input of the sixth NAND gate NAND6 receives the termination resistor control code ODT. The two inputs of the seventh NAND gate NAND7 are respectively connected to the outputs of the fifth NAND gate NAND5 and the sixth NAND gate NAND6, and the output of the seventh NAND gate NAND7 serves as the output of the first selection circuit 1311.

[0086] In some embodiments, in order to match the gate-level delay caused by the inverter before the first input of the sixth NAND gate NAND6, the read enable signal Read_enable is connected to the input of the fifth NAND gate NAND5 after passing through a transmission gate or other timing-matched gate-level delay.

[0087] In some embodiments, the first selection circuit can also be implemented using a 2-to-1 multiplexer. The read enable signal Read_enable serves as the input signal to the selection terminal. The two input terminals receive the termination resistor control code ODT and the output drive resistor control code RON, respectively. Therefore, when the read enable signal Read_enable is active, the output drive resistor control code RON is output; when the read enable signal Read_enable is inactive, the termination resistor control code ODT is output. In other embodiments, the first selection circuit can also be implemented using NOR gates. The fifth to seventh NAND gates are replaced with NOR gates, and the corresponding input or output signals are inverted, thereby fulfilling the requirement of the read enable signal Read_enable selecting the output signal. Selection circuits implemented using NAND gates or NOR gates can match timing and avoid the MOSFET superposition effect in high-speed circuits.

[0088] The termination resistor control code ODT and the output drive resistor control code RON can be codewords sent by the memory controller to the memory, and then sent by the memory to the data input / output circuit via registers. The termination resistor control code ODT can be a multi-bit control codeword, such as 3 bits; the output drive resistor control code RON can also be a multi-bit control codeword, such as 2 bits. Correspondingly, the resistor control circuit can have multiple first selection circuits, each receiving multiple bits of control codewords. For example, the resistor control circuit can include four first selection circuits, thereby outputting multiple termination resistor control codewords ODT and output drive resistor control codewords RON, thus setting different termination resistor values ​​and output drive resistor values.

[0089] In some embodiments, as shown in FIG2, the output driving circuit includes pull-up driving circuits 141 and 143 and pull-down driving circuits 142 and 144, and the resistor control circuit 130 includes pull-up resistor control circuit 131 and pull-down resistor control circuit 132. The pull-up resistor control circuit 131 may include multiple first selection circuits, and correspondingly, the output driving resistor control code RON received by the first selection circuit 1311 is the pull-up output driving resistor control code Pu_Ron. The pull-down resistor control circuit 132 may also include multiple second selection circuits, and correspondingly, the output driving resistor control code RON received by the second selection circuit is the pull-down output driving resistor control code Pd_Ron. For memory with pull-up termination, when it acts as a termination resistor, only the pull-up driving circuit outputs the termination resistor value, and the pull-down driving circuit is in a high-impedance state.

[0090] At this time, the resistor control circuit 130 includes a pull-up resistor control circuit, which includes a first selection circuit 1311. The first selection circuit 1311 is configured to receive the termination resistor control code ODT, the output drive resistor control code RON, and the read enable signal Read_enable. When the read enable signal Read_enable is at an active level, the output terminal of the first selection circuit 1311 outputs the output drive resistor control code RON or its inverted signal to the pull-up drive circuit. When the read enable signal Read_enable is at an inactive level, the output terminal of the first selection circuit 1311 outputs the termination resistor control code ODT or its inverted signal to the pull-up drive circuit.

[0091] The pull-down resistor control circuit 130 includes a second selection circuit 1321. The second selection circuit 1321 is configured to receive the termination resistor control code ODT, the output drive resistor control code RON, and the read enable signal Read_enable. When the read enable signal Read_enable is active, the output of the second selection circuit 1321 outputs the output drive resistor control code RON or its inverted signal RONB to the pull-down drive circuit. When the read enable signal is inactive, the output of the second selection circuit outputs an inactive level to the pull-down drive circuit. In an embodiment using an NMOS transistor-based pull-down drive circuit, the inactive level can be low, thus the pull-down drive circuit using the NMOS transistor is not activated, the output is in a floating state, and the output is in a high-impedance state.

[0092] Figure 9 shows a schematic diagram of the circuit structure of a second selection circuit 1321. The second selection circuit 1321 may include an eighth NAND gate NAND8, a ninth NAND gate NAND9, and a tenth NAND gate NAND10; the first input terminal of the eighth NAND gate NAND8 receives a read enable signal Read_enable through a transmission gate, and the second input terminal of the eighth NAND gate NAND8 receives the output drive resistor control code RON or its inverted signal RONB; the first input terminal of the ninth NAND gate NAND9 receives the inverted signal of the read enable signal Read_enable, and the second input terminal of the ninth NAND gate NAND9 receives an invalid level (in some embodiments, the invalid level can be a low level Vss); the two input terminals of the tenth NAND gate NAND10 are respectively connected to the output terminals of the eighth NAND gate NAND8 and the ninth NAND gate NAND9, and the output terminal of the tenth NAND gate NAND10 serves as the output terminal of the second selection circuit 1321, outputting the signal RON_PD_CTL.

[0093] In other embodiments, for pull-down terminated memories, the settings can be reversed. The signal input to the corresponding termination resistor code ODT of the pull-up drive resistor selection circuit is invalid, while the signal input to the corresponding termination resistor code ODT of the pull-down drive circuit selection circuit is the code value of ODT.

[0094] As shown in Figure 2, the output drive circuit includes pre-drive circuits 141 and 142 and main drive circuits 143 and 144. The pre-drive circuit includes a pull-up pre-drive circuit 141 and a pull-down pre-drive circuit 142, and the main drive circuit includes a pull-up main drive circuit 143 and a pull-down main drive circuit 144. The pull-up pre-drive circuit 141 is connected to the parallel-to-serial converter circuit 110 and the pull-up resistor control circuit 131, and receives the data signal DATA and the control code output by the pull-up resistor control circuit 131. The pull-down pre-drive circuit 142 is connected to the parallel-to-serial converter circuit 110 and the pull-down resistor control circuit 132, and receives the data signal DATA and the signal output by the pull-down resistor control circuit 132. The pull-up main drive circuit 143 is connected to the pull-up pre-drive circuit 141 and receives its output pre-drive signal PU. The pull-down main drive circuit 144 is connected to the pull-down pre-drive circuit 142 and receives its output pre-drive signal PD.

[0095] The pre-drive circuits 141 and 142 include a second AND logic circuit. The first input terminal of the second AND logic circuit serially receives N data DATA, and the second input terminal of the second AND logic circuit receives a signal (RON_ODT_CTL or RON_PD_CTL) output by the resistor control circuit. The second AND logic circuit performs AND-NOT logic processing on the signals received at its first and second input terminals and then outputs the signal. The main drive circuit 143 includes a PMOS transistor electrically connected between the power supply voltage Vdd and the output port DQ. The control terminal of the PMOS transistor receives the signal output by the second AND logic circuit. Alternatively, the second AND logic circuit performs AND-NOT logic processing on the signals received at its first and second input terminals and then outputs the signal. The main drive circuit 144 includes an NMOS transistor electrically connected between the power supply voltage Vss and the output port DQ. The control terminal of the NMOS transistor receives the signal output by the second AND logic circuit.

[0096] Specifically, referring to Figure 10, which is a schematic diagram of a pull-up pre-drive circuit provided in an embodiment of this disclosure. The pull-up pre-drive circuit includes multiple second AND logic circuits 1411. The first input terminal of the second AND logic circuit 1411 serially receives N data (DATA). The second input terminal of the second AND logic circuit 1411 receives one bit of the control code RON_ODT_CTL output by the pull-up resistor control circuit 131 (e.g., RON_ODT_CTL0 in 1411 represents the least significant bit of the control code RON_ODT_CTL output by the pull-up resistor control circuit 131). After performing AND-NOT logic processing on the signals received at its first and second input terminals, the second AND logic circuit 1411 is driven by an even number of inverters similar to those shown in Figure 10, and then outputs a pull-up data signal to the pull-up main drive circuit 143 (the least significant bit PU_0 used to drive the pull-up data signal in Figure 10). In some embodiments, the second AND logic circuit 1411 can directly output the pull-up data signal PU_0 after performing AND-NOT logic processing on the signal received at its first input terminal and the signal received at its second input terminal, without passing through an even number of inverters.

[0097] The pull-up main drive circuit 143 includes multiple sub-pull-up main drive circuits. Figure 11 is a schematic diagram of the structure of a first sub-pull-up main drive circuit provided in an embodiment of this disclosure. As shown in Figure 11, the first sub-pull-up main drive circuit 1431 includes a PMOS transistor electrically connected between the power supply voltage Vdd (high-level power supply voltage) and the output port DQ. The control terminal of the PMOS transistor receives the data signal PU_0 output by the second AND logic circuit.

[0098] Referring to Figure 10, the second AND logic circuit 1411 performs AND logic processing on the serial data signal DATA and the signal RON_ODT_CTL1 output by the pull-up resistor control circuit 131. The result of this AND logic processing is then ANDed with the ZQ calibration code ZQ_CODE<5:0> for calibrating the ZQ resistor of the main drive circuit to obtain the processed ZQ calibration code ZQ_0<5:0>. The calibrated ZQ calibration code ZQ_0<5:0> is sent to the main drive circuit for calibrating the ZQ resistor. By performing AND and NOT processing on the ZQ calibration code and the signal RON_ODT_CTL1 output by the pull-up resistor control circuit 131, the ZQ calibration code carries timing information for both read and non-read operations. This allows the ZQ resistor path of the main drive circuit to be closed during read operations, saving power.

[0099] Referring to Figure 11, the first sub-pull-up main drive circuit 1431 includes a data output path (the path containing the PMOS1 transistor) and a ZQ resistor path (the path containing the P0-P5 transistors). The data output path receives the pull-up data signal PU_0 from the pre-drive circuit and outputs the data. The ZQ resistor path receives the processed ZQ calibration code ZQ_0<5:0>, which is used to adjust the resistance of the first sub-pull-up main drive circuit 1431 so that the resistance value of the first sub-pull-up main drive circuit 1431 is 240 ohms. Both the data output path and the ZQ circuit path have resistors for adjusting the linearity of the path.

[0100] A second AND logic circuit 1411 is used to drive a corresponding first sub-pull-up main drive circuit 1431. In some embodiments, the pull-up pre-drive circuit 141 includes 7 second AND logic circuits, and the pull-up main drive circuit 143 includes 7 sub-pull-up main drive circuits, with each of the 7 second AND logic circuits corresponding to one of the 7 sub-pull-up main drive circuits.

[0101] Through the design of the pull-up drive circuits 141 and 143 described above, when the memory enters the data read state, the output signal RON_ODT_CTL of the resistor control circuit is the pull-up output drive resistor control code Pu_Ron, which controls the path of the pull-up drive circuit. When Pu_Ron = 0, the output of the pull-up pre-drive circuit is high, and the output of the pull-up drive circuit is in a high-impedance state. When Pu_Ron = 1, the output of the pull-up drive circuit is the data signal DATA. When the memory enters a non-read state (such as the termination resistor ODT state), the output signal RON_ODT_CTL of the resistor control circuit is the termination resistor control code ODT. Since the parallel-to-serial circuit output is the default value "1" at this time, when the termination resistor control code ODT equals 1, the output of the pull-up pre-drive circuit is 0, and the corresponding pull-up main drive circuit is turned on as the pull-up resistor. When the termination resistor control code ODT equals 0, the output of the pull-up pre-drive circuit is 1, and the pull-up main drive circuit outputs in a high-impedance state.

[0102] Therefore, the pull-up pre-drive circuit can send data to the pull-up main drive circuit without deviation, and then the pull-up main drive circuit outputs the data. When the data is "0", the pull-up main drive circuit is turned on; when it is "1", the pull-up main drive circuit is turned off. Since the pull-up pre-drive circuit is combined with the output signal of the resistor control circuit, the data transmission process of the pull-up pre-drive circuit includes the timing of read and non-read operations. It can automatically set the output drive resistor value or configure the termination resistor value while transmitting data. When the output signal (control code) of the resistor control circuit is "1", the data output from the parallel-to-serial converter can be transmitted to the pull-up main drive circuit through the pull-up pre-drive circuit. Conversely, if the output signal (control code) of the resistor control circuit is "0", the data output from the parallel-to-serial converter will be ignored, and the pull-up main drive circuit will be turned off directly. Furthermore, by combining the output signals (control codes) of the parallel-to-serial circuit, the pull-up pre-drive circuit, and the resistor control circuit, the output function can be achieved by connecting a single parallel-to-serial circuit to the pull-up output drive and pull-down output drive circuits during the reading process. Moreover, since only one read enable signal, Read_enable, is used, the deviation of the tADC can be reduced.

[0103] The pull-down pre-drive circuit and pull-down main drive circuit can also adopt the circuit structures corresponding to Figures 10 and 11. For example, the pull-down pre-drive circuit may include a second AND logic circuit. The first input terminal of the second AND logic circuit serially receives N data (DATA), and the second input terminal receives one bit of the control code RON_PD_CTL output by the pull-down resistor control circuit 132. The second AND logic circuit performs AND logic processing on the signals received at its first and second input terminals and outputs the result to the pull-down main drive circuit 144. The pull-down main drive circuit 144 includes multiple sub-pull-down main drive circuits, each including a data output path composed of NMOS transistors and a ZQ resistor path. Specifically, each sub-pull-down main drive circuit includes an NMOS transistor electrically connected between the power supply voltage Vss (low-level power supply voltage D) and the output port DQ, and a resistor for improving linearity. The control terminal of the NMOS transistor in the data output path receives the signal output by the second AND logic circuit, and the control terminal of the NMOS transistor in the ZQ resistor path receives the processed ZQ calibration code.

[0104] In some other embodiments, the NAND gate in the pull-up pre-drive circuit of FIG10 can be replaced with NOR gate processing logic. In this case, the input control code RON_PD_CTL can be the inverted signal of the output signal in FIG7.

[0105] As shown in Figure 2, pull-up drive circuits 141 and 143 are connected to the output of parallel-to-serial converter 110 and receive N data DATA within the first time period T1; pull-down drive circuits 142 and 144 are connected to the output of parallel-to-serial converter 110 and receive N data DATA within the first time period T1; pull-up drive circuits 141 and 143 are configured to output a high level among the N data within the first time period T1 and configure the output drive resistance value based on the output drive resistance control code RON; pull-down drive circuits 142 and 144 are configured to output a low level among the N data DATA within the first time period and configure the output drive resistance value based on the output drive resistance control code ODT; the pull-up drive circuits are also configured to configure a termination resistance value outside the first time period T1.

[0106] Therefore, the pull-up drive circuit and the pull-down drive circuit are connected to the same parallel-to-serial circuit to output data, and the output drive resistor value can be configured in read operation and the termination resistor value can be configured in non-read operation device.

[0107] This disclosure also provides a memory. Figure 12 is a schematic diagram of the structure of a memory provided in this disclosure. As shown in Figure 12, the memory 10 includes the input / output circuit 100 described in any of the preceding embodiments. The memory 10 also includes a storage array 20 and a data transmission circuit 30. The storage array 20 is composed of multiple storage cells and is used to store data. The data transmission circuit 30 is used to perform various processing and transmission on the data when writing or reading it. When a read operation is performed on the memory 10, the data DATA is read out via the storage array 20, transmitted via the data transmission circuit 30, and then output via the data input / output circuit 100.

[0108] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A data input / output circuit, characterized in that, It includes a parallel-to-serial converter, a read enable signal generation circuit, a resistor control circuit, and an output drive circuit; among which, The parallel-to-serial conversion circuit is configured to receive N data and serially output the N data within a first time period. The read enable signal generation circuit is configured to generate a read enable signal, which is at an effective level during a first time period. The resistor control circuit is electrically connected to the read enable signal generation circuit and is configured to receive the termination resistor control code, the output drive resistor control code and the read enable signal, and based on the read enable signal, select to output the termination resistor control code or the output drive resistor control code. The output driving circuit, which is electrically connected to the parallel-to-serial circuit and the resistor control circuit, is configured to receive the N data and the signal output by the resistor control circuit, and configure the output driving resistor value and output the N data based on the signal output by the resistor control circuit, or configure the termination resistor value. Where N is a positive integer greater than 1.

2. The data input / output circuit according to claim 1, characterized in that, The output driving circuit includes a pull-up driving circuit and a pull-down driving circuit. The parallel-to-serial conversion circuit connects the pull-up driving circuit and the pull-down driving circuit, and outputs the N data to the pull-up driving circuit and the pull-down driving circuit.

3. The data input / output circuit according to claim 1 or 2, characterized in that, The parallel-to-serial converter includes a first data input port, a second data input port, a third data input port, and a fourth data input port. The parallel-to-serial converter receives the N data through the first to fourth data input ports. The parallel-to-serial converter also receives a first clock, a second clock, a third clock, and a fourth clock, and samples the N data based on the first to fourth clocks, and serially outputs the N data within a first time period. The first time period includes a second time period, a third time period, and a fourth time period, wherein the second time period is earlier than the third time period, and the third time period is earlier than the fourth time period; the parallel-to-serial converter is further configured to: output a first level fixedly during the second and fourth time periods, and serially output the N data during the third time period; The first, second, third, and fourth clocks have the same clock frequency and their phase differences are successively a quarter of a cycle; N is a positive integer multiple of 4.

4. The data input / output circuit according to claim 3, characterized in that, The parallel-to-serial conversion circuit includes a first sampling circuit, a second sampling circuit, and a first NAND gate; the first input terminal of the first sampling circuit receives the first clock, and the second input terminal of the first sampling circuit is connected to the first data input port, and the data input to the first data input port is sampled by the first clock; The first input terminal of the second sampling circuit receives the second clock, and the second input terminal of the second sampling circuit receives the second level. The second level is sampled by the second clock. The first input terminal of the first NAND gate is connected to the output terminal of the first sampling circuit, the second input terminal of the first NAND gate is connected to the output terminal of the second sampling circuit, and the first NAND gate outputs the first sampling result. The parallel-to-serial conversion circuit further includes a third sampling circuit, a fourth sampling circuit, and a second NAND gate; the first input terminal of the third sampling circuit receives the third clock, and the second input terminal of the third sampling circuit is connected to the third data input port, and the data input to the third data input port is sampled by the third clock. The first input terminal of the fourth sampling circuit receives the fourth clock, and the second input terminal of the fourth sampling circuit receives the second level, and the second level is sampled by the fourth clock; The first input terminal of the second NAND gate is connected to the output terminal of the third sampling circuit, the second input terminal of the second NAND gate is connected to the output terminal of the fourth sampling circuit, and the second NAND gate outputs the third sampling result; The parallel-to-serial conversion circuit further includes a fifth sampling circuit, a sixth sampling circuit, and a third NAND gate; the first input terminal of the fifth sampling circuit receives the second clock, and the second input terminal of the fifth sampling circuit is connected to the second data input port, and the data input to the second data input port is sampled by the second clock. The first input terminal of the sixth sampling circuit receives the third clock, and the second input terminal of the sixth sampling circuit receives the second level, and samples the second level through the third clock; The first input terminal of the third NAND gate is connected to the output terminal of the fifth sampling circuit, the second input terminal of the third NAND gate is connected to the output terminal of the sixth sampling circuit, and the third NAND gate outputs the second sampling result; The parallel-to-serial conversion circuit further includes a seventh sampling circuit, an eighth sampling circuit, and a fourth NAND gate; the first input terminal of the seventh sampling circuit receives the fourth clock, and the second input terminal of the seventh sampling circuit is connected to the fourth data input port, and the data input to the fourth data input port is sampled by the fourth clock; The first input terminal of the eighth sampling circuit receives the first clock, and the second input terminal of the eighth sampling circuit receives the second level. The second level is sampled by the first clock. The first input terminal of the fourth NAND gate is connected to the output terminal of the seventh sampling circuit, the second input terminal of the fourth NAND gate is connected to the output terminal of the eighth sampling circuit, and the fourth NAND gate outputs the fourth sampling result; The first AND logic circuit is connected to the first to fourth NAND gates, receives the first to fourth sampling results, and performs first AND logic processing on the first to fourth sampling results, thereby outputting the first level in the second time period and the fourth time period, and serially outputting the N data in the third time period.

5. The data input / output circuit according to claim 1 or 2, characterized in that, The resistor control circuit includes a first selection circuit, which is configured to receive a termination resistor control code, an output drive resistor control code, and a read enable signal. When the read enable signal is at a valid level, the output terminal of the first selection circuit outputs the output drive resistor control code or its inverted signal. When the read enable signal is at an invalid level, the output terminal of the first selection circuit outputs the termination resistor control code.

6. The data input / output circuit according to claim 5, characterized in that, The first selection circuit includes a fifth NAND gate, a sixth NAND gate, and a seventh NAND gate; the first input terminal of the fifth NAND gate receives a read enable signal, and the second input terminal of the fifth NAND gate receives an output drive resistor control code or its inverted signal. The first input terminal of the sixth NAND gate receives the inverted signal of the read enable signal, and the second input terminal of the sixth NAND gate receives the termination resistor control code; the two input terminals of the seventh NAND gate are respectively connected to the output terminals of the fifth NAND gate and the sixth NAND gate, and the output terminal of the seventh NAND gate serves as the output terminal of the first selection circuit.

7. The data input / output circuit according to claim 2, characterized in that, The resistor control circuit includes a first selection circuit, which is configured to receive a termination resistor control code, an output drive resistor control code, and a read enable signal. When the read enable signal is at a valid level, the output terminal of the first selection circuit outputs the output drive resistor control code or its inverted signal to the pull-up drive circuit. When the read enable signal is invalid, the output of the first selection circuit outputs the termination resistor control code or its inverted signal to the pull-up drive circuit. The resistor control circuit further includes a second selection circuit, which is configured to receive an invalid level, output a drive resistor control code and the read enable signal. When the read enable signal is an valid level, the output terminal of the second selection circuit outputs the output drive resistor control code or its inverted signal to the pull-down drive circuit. When the read enable signal is invalid, the output of the second selection circuit outputs the invalid level to the pull-down drive circuit.

8. The data input / output circuit according to claim 1 or 2, characterized in that, The output driving circuit includes a pre-driving circuit and a main driving circuit. The pre-driving circuit includes a second AND logic circuit. The first input terminal of the second AND logic circuit receives the N data, and the second input terminal of the second AND logic circuit receives the signal output by the resistor control circuit. The second AND logic circuit performs AND-NOT logic processing on the signals received at its first input terminal and the signals received at its second input terminal and then outputs the signal. The main driving circuit includes a PMOS transistor electrically connected between the power supply voltage and the output port. The control terminal of the PMOS transistor receives the signal output by the second AND logic circuit. Alternatively, the second AND logic circuit performs AND logic processing on the signal received at its first input terminal and the signal received at its second input terminal, and then outputs the signal. The main driving circuit includes an NMOS transistor electrically connected between the power supply voltage and the output port. The control terminal of the NMOS transistor receives the signal output by the second AND logic circuit.

9. The data input / output circuit according to claim 2, characterized in that, The pull-up drive circuit is connected to the output terminal of the parallel-to-serial circuit and receives the N data within a first time period. The pull-down drive circuit is connected to the output of the parallel-to-serial converter circuit and receives the N data within a first time period. The pull-up drive circuit is configured to: output a high level among the N data during a first time period, and configure the output drive resistor value based on the output drive resistor control code; The pull-down drive circuit is configured to: output a low level among the N data during a first time period, and configure the output drive resistor value based on the output drive resistor control code; The pull-up drive circuit is also configured to: configure a termination resistor value outside the first time period.

10. A memory, characterized in that, The memory includes the input / output circuitry as described in any one of claims 1-9, and the memory further includes a storage array and a data transmission circuitry, wherein the storage array stores data; When the memory is read, the data is read out via the memory array, transmitted via the data transmission circuit, and then output via the data input / output circuit.

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