Timestamp synchronization circuit, method, chip, and electronic device
By using a global timer and synchronization circuit to provide a unified time reference for the chip modules, the problem of timestamp synchronization between different sub-modules within the chip is solved, achieving consistency and accuracy of timestamps.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BEIJING YOUZHUJU NETWORK TECH CO LTD
- Filing Date
- 2024-11-11
- Publication Date
- 2026-05-15
AI Technical Summary
As chip size increases, there are uncertainties and delays in the synchronization of timestamps between different sub-modules within the chip, leading to inconsistencies in the timestamp readings by the CPU or MCU.
By employing a global timer, synchronization circuit, and snapshot module, a unified global clock signal and counter value are provided to different chip modules through cross-clock domain synchronization, and the timestamp is latched during interrupt signal to prevent multiple processors from reading the counter value at the same location.
It achieves timestamp synchronization within and between different sub-modules within the chip, avoiding read delay errors and ensuring timestamp consistency.
Smart Images
Figure CN2024131338_15052026_PF_FP_ABST
Abstract
Description
Timestamp synchronization circuits, methods, chips, and electronic devices Technical Field
[0001] This disclosure relates to the field of chip technology, and more particularly to a timestamp synchronization circuit, method, chip, and electronic device. Background Technology
[0002] As chip technology advances, chips are becoming increasingly larger, with a growing number of sub-modules. Different clocks can be used within or between different sub-modules within a chip. When processing data, software programs need a unified time base to record the order of data within or between sub-modules; this unified time base is called a timestamp.
[0003] Timestamps are typically represented using the count value of a timer counter. However, as chip size increases, the number of processors, such as the Central Processing Unit (CPU) or Microcontroller Unit (MCU), also increases. If each processor reads the value of the timer counter at the same location, it can lead to unpredictable delays in software reads. For example, if CPU 1 and CPU 2 read the timer counter value at the same location, they will compete for the time. When CPU 1 reads the timer counter value at that location, CPU 2 needs to wait, resulting in CPU 2 reading a time that is not the actual time, causing timestamp desynchronization.
[0004] Summary of the Invention
[0005] In view of this, embodiments of the present disclosure provide a timestamp synchronization circuit, method, chip, and electronic device, which realizes timestamp synchronization within different sub-modules within a chip and timestamp synchronization between different sub-modules within a chip.
[0006] According to a first aspect of the present disclosure, a timestamp synchronization circuit is provided, comprising: a global timer, a first synchronization circuit, and a second synchronization circuit; the first synchronization circuit and the second synchronization circuit are disposed in different chip modules within a chip, and the global timer and the first synchronization circuit are disposed in the same chip module within the chip; both the first synchronization circuit and the second synchronization circuit include: a global count value synchronization module, a global timer register, and a snapshot module; wherein, the global count value synchronization module is respectively connected to the corresponding global timer register and the snapshot module, and the global count value synchronization modules in both the first synchronization circuit and the second synchronization circuit are connected to the global timer; the global timer... The system is configured to output the global clock signal and the global counter value to the global counter value synchronization modules in the first synchronization circuit and the second synchronization circuit, respectively, based on the input global clock signal. The global counter value synchronization module is configured to perform cross-clock domain synchronization based on the input global clock signal and the global counter value, and output the global counter synchronization value corresponding to the global counter value to the corresponding global timer register and the snapshot module. The global timer register is configured to store the real-time value of the input global counter synchronization value. The snapshot module is configured to latch the global counter synchronization value corresponding to the internal interrupt signal when an internal interrupt signal is input, wherein the internal interrupt signal is an interrupt signal generated within the chip.
[0007] According to a second aspect of the present disclosure, a timestamp synchronization method is provided, comprising: acquiring a global clock signal and a global counter value of a first chip module within a chip; broadcasting the global clock signal and the global counter value to at least one second chip module within the chip; performing cross-clock domain synchronization for the first chip module or the second chip module based on the global clock signal and the global counter value to obtain a global counter synchronization value corresponding to the global counter value; reading the real-time value of the global counter synchronization value stored in a global timer register; and, upon detecting an internal interrupt signal, reading the global counter synchronization value corresponding to the internal interrupt signal latched by a snapshot module; wherein the internal interrupt signal is an interrupt signal generated within the chip; and performing timestamp synchronization within the first chip module, or timestamp synchronization within the second chip module, or timestamp synchronization between the first chip module and the second chip module based on the real-time value of the global counter synchronization value and the global counter synchronization value corresponding to the internal interrupt signal.
[0008] According to a third aspect of the present disclosure, a chip is provided, including at least two chip modules and a timestamp synchronization circuit provided in the first aspect.
[0009] According to a fourth aspect of the present disclosure, a chip is provided, including a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform the method provided in the second aspect.
[0010] According to a fifth aspect of the present disclosure, an electronic device is provided, including the chip provided in the third aspect.
[0011] According to a sixth aspect of the present disclosure, an electronic device is provided, including a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform the method provided in the second aspect.
[0012] According to a seventh aspect of the present disclosure, a computer storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method provided in the second aspect.
[0013] The timestamp synchronization circuit provided in this disclosure includes a global timer, a first synchronization circuit, and a second synchronization circuit. The first and second synchronization circuits are located in different chip modules, while the global timer and the first synchronization circuit are located in the same chip module; that is, different chip modules all include synchronization circuits. The first and second synchronization circuits have the same structure, including a global timer synchronization module, a global timer register, and a snapshot module. The global timer provides a unified global clock signal and a global timer counter value for different chip modules. Since different chip modules all include a global timer register, multiple processors can avoid reading the value of the timer counter at the same location. Since different chip modules all include a snapshot module, multiple processors can avoid reading the latched timestamp at the same location. Through the global timer register, snapshot module, and bias register in the chip module, different processors can read the values of the timer counter and the latched timestamp at different locations, achieving timestamp synchronization within the chip module and timestamp synchronization between different chip modules. Attached Figure Description
[0014] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.
[0015] Figure 1 is a schematic diagram of a timestamp synchronization circuit provided in an embodiment of this disclosure;
[0016] Figure 2 is a schematic diagram of a global timer provided in an embodiment of this disclosure;
[0017] Figure 3 is a schematic diagram of a global count value synchronization module provided in an embodiment of this disclosure;
[0018] Figure 4 is a flowchart of a timestamp synchronization method provided in an embodiment of this disclosure;
[0019] Figure 5 is a schematic diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solutions in the embodiments of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art should fall within the protection scope of this disclosure.
[0021] To facilitate understanding of the embodiments of this disclosure, the concepts involved in this disclosure will first be explained.
[0022] 1. Chip Module
[0023] The chip comprises multiple chip modules, and this disclosure does not limit the names of the chip modules or the number of chip modules in the chip. For example, a chip module may also be called a subblock, a subsystem, etc.
[0024] For ease of explanation, this disclosure uses an example of a chip comprising two chip modules.
[0025] 2. Global Timer, Global Timer Clock Signal (global_timer_clk), Global Timer Counter (global_timer_counter)
[0026] The global timer is a crucial component in a chip used to provide a precise time reference. The global timer provides a global timer clock signal (global_timer_clk) and a timer count value. The global timer clock signal is also simply referred to as the global clock signal. The timer count value is the value of the global counter (global_timer_counter), also known as the global counter count value or global counter value.
[0027] In a chip, time is indicated by the count value of a global timer, i.e., a timestamp. Specifically, the global timer records the count value of the global timer based on the clock cycle of the global clock signal (global_timer_clk). For example, if the frequency of the global clock signal is 50MHz, the count value of the global timer is incremented by 1 after each global clock cycle, i.e., after 20ns. The value of the global timer can be, for example, 1, 2, 3, 4, ...
[0028] For example, the count value of a global counter can be represented as global_timer_counter[N:0], where N represents the number of bits in the output. N can be any non-negative integer, and 0 represents the least significant bit of the output. For instance, assuming N = 4, then global_timer_counter[3:0] represents a 4-bit wide counter output, which can represent any value from 0 to 15.
[0029] To ensure the normal operation of the chip, a global timer is usually set on a chip module that is in an always-on power domain.
[0030] 3. Global timer synchronization value (global_timer_counter_sync)
[0031] Within a chip module and between different chip modules, different frequency clock signals can be used. For example, the frequency of the clock signal used by the CPU can be different from the frequency of the clock signal used by the registers. Synchronization across clock domains can be achieved based on the values of the global clock signal (global_timer_clk) and the global counter (global_timer_counter) provided by the global timer, resulting in the global counter synchronization value (global_timer_counter_sync).
[0032] For example, suppose the global clock signal has a frequency of 50MHz, and the global counter increments by 1 every 20ns. Suppose the chip module uses a 100MHz operating clock signal, which is twice as fast as the global clock signal's 50MHz frequency. Through cross-clock domain synchronization, it can be ensured that the global timer value is correctly sampled by the 100MHz clock domain. For instance, if the global counter takes values of 1, 2, 3, 4, ..., then the count values sampled by the 100MHz clock domain will be 2, 4, ...
[0033] The technical solution of this disclosure will now be described in detail with reference to the accompanying drawings.
[0034] Figure 1 is a schematic diagram of a timestamp synchronization circuit provided in an embodiment of this disclosure. As shown in Figure 1, the timestamp synchronization circuit provided in this embodiment includes:
[0035] The chip includes a global timer 11, a first synchronization circuit 12, and a second synchronization circuit 13. The first synchronization circuit 12 and the second synchronization circuit 13 are located in different chip modules within the chip, while the global timer 11 and the first synchronization circuit 12 are located in the same chip module within the chip.
[0036] Both the first synchronization circuit 12 and the second synchronization circuit 13 include: a global count value synchronization module 121, a global timer register 122, and a snapshot module 124. The global count value synchronization module 121 is connected to the corresponding global timer register 122 and snapshot module 124, respectively. The global count value synchronization module 121 in both the first synchronization circuit 12 and the second synchronization circuit 13 is connected to the global timer 11.
[0037] The global timer 11 is used to output a global clock signal and a global counter value to the global counter value synchronization module 121 in the first synchronization circuit 12 and the second synchronization circuit 13 respectively, based on the input global clock signal.
[0038] The global counter value synchronization module 121 is used to perform cross-clock domain synchronization based on the input global clock signal and global counter value, and output the global counter synchronization value corresponding to the global counter value to the corresponding global timer register 122 and snapshot module 123.
[0039] Global timer register 122 is used to store the real-time value of the input global counter synchronization value.
[0040] The snapshot module 124 is used to latch the global counter synchronization value corresponding to the internal interrupt signal when an internal interrupt signal is input. The internal interrupt signal is an interrupt signal generated within the chip.
[0041] For ease of explanation, we will use an example of a chip comprising two chip modules. As shown in Figure 1, the two chip modules include chip module 150 and chip module 151. Chip module 150 is in an always-on power domain. When the chip is powered on, chip module 150 powers on first. A global timer 11 and a first synchronization circuit 12 are located in chip module 150, and a second synchronization circuit 13 is located in chip module 151.
[0042] The timestamp synchronization circuit provided in this embodiment includes a synchronization circuit in each chip module. Specifically, each chip module includes a global timer counter sync module 121, a global timer counter register 122, and a snapshot module 124.
[0043] The timestamp synchronization circuit provided in this embodiment works as follows:
[0044] Global timer 11, located in chip module 150, provides a global clock signal (global_timer_clk) and global counter values (global_timer_counters) to chip module 150. The global counter values (global_timer_counters) refer to the count values of global timer 11. Global timer 11 also sends the global clock signal (global_timer_clk) and global counter values (global_timer_counters) to other chip modules within the chip (e.g., chip module 151), thus providing a unified global clock signal (global_timer_clk) and global counter values (global_timer_counters) to different chip modules within the chip.
[0045] The operating principle of the synchronization circuit is similar for each chip module. The following explanation uses the first synchronization circuit 12 on chip module 150 as an example.
[0046] The global counter synchronization module 121 can achieve cross-clock domain synchronization. Based on the input global clock signal (global_timer_clk) and global counter values (global_timer_counters), it outputs a global counter synchronization value (global_timer_counters_sync) to the global timer register 122 and the snapshot module 124. The global counter synchronization value can be found in the conceptual explanation above, and will not be repeated here.
[0047] Global timer register 122 can record the real-time value of the global counter synchronization value. The CPU / MCU and other processors in the chip can read this real-time value to obtain a timestamp. For example, when the CPU processes data, if data 1 arrives, the CPU reads the real-time value of the global counter synchronization value from global timer register 122, for example, it is 4. Subsequently, if data 2 arrives, the CPU reads the real-time value of the global counter synchronization value from global timer register 122, for example, it is 10.
[0048] The snapshot module 124 is used to latch the global counter synchronization value corresponding to the internal interrupt signal when an internal interrupt signal (internal_interrupt) is input. The internal interrupt signal is used for timestamp synchronization within a chip module or for timestamp synchronization between different chip modules within the chip. For example, for chip module 150, if the internal interrupt signal is generated by chip module 150, timestamp synchronization within chip module 150 can be achieved; if the internal interrupt signal is generated by chip module 151, timestamp synchronization between chip module 150 and chip module 151 can be achieved.
[0049] In computer processing, an interrupt refers to the process of pausing the execution of the current program during CPU operation and switching to other programs. It can also be extended to events that require storing temporary states. An interrupt signal is generated when an interrupt event occurs. Internally, after receiving an internal interrupt, the CPU / MCU typically reads the global timer counter register 122 to obtain the real-time timestamp. However, if there are multiple internal interrupts, the CPU / MCU will process them one by one. Therefore, only the timestamp corresponding to the first internal interrupt is retrieved promptly; the others will introduce different delay errors. To avoid this error, a snapshot module 124 is used to latch the timestamps corresponding to the internal interrupts.
[0050] In this embodiment, a scenario that generates an internal interrupt signal is as follows: During CPU data processing, data 1 arrives, and the CPU reads the timestamp of data 1's arrival from the global timer register 122, assuming the timestamp is 2. Before the CPU finishes processing data 1, data 2 arrives. Since the CPU cannot process data 2 temporarily due to its serial data processing, the arrival of data 2 is considered an interrupt event, and an internal interrupt signal is generated. Correspondingly, when the snapshot module 124 acquires the input internal interrupt signal, it can latch the global counter synchronization value corresponding to the internal interrupt signal, that is, latch the timestamp of data 2's arrival, assuming the timestamp is 4. Subsequently, when the CPU finishes processing data 1 and can process data 2, the CPU reads the current real-time timestamp from the global timer register 122, assuming the timestamp is 6, and simultaneously reads the latched timestamp of data 2 from the snapshot module 124, i.e., timestamp 4.
[0051] For example, the CPU / MCU obtaining the timestamp latch value corresponding to the interrupt from the snapshot module 124 based on the interrupt can be represented as follows:
[0052] Configure interrupt_mask[N] = 1 via the apb interface;
[0053] Obtain the timestamp timer_counter_out[N:0] via the app interface;
[0054] Configure interrupt_mask[N] = 0 via the apb interface.
[0055] Here, apb interface represents the APB interface, and interrupt_mask[N] represents the interrupt masking signal. Before the CPU / MCU reads the timestamp latched by the snapshot module 124, it is necessary to configure the interrupt_mask[N] of the snapshot module 124 to be 1. After the CPU / MCU finishes reading the latched timestamp timer_counter_out[N:0], the interrupt masking signal interrupt_mask[N] is configured to be 0 through the APB interface.
[0056] As can be seen, the timestamp synchronization circuit provided in this embodiment includes a global timer, a first synchronization circuit, and a second synchronization circuit. The first and second synchronization circuits are located in different chip modules within the chip, while the global timer and the first synchronization circuit are located in the same chip module. That is, different chip modules all include synchronization circuits. The first and second synchronization circuits have the same structure, including a global counter value synchronization module, a global timer register, and a snapshot module. The global timer provides a unified global clock signal and a global counter value for different chip modules within the chip. For each chip module, cross-clock domain synchronization can be achieved through the global counter value synchronization module. Since different chip modules all include a global timer register, which stores the real-time value of the global counter synchronization value (i.e., the real-time value of the timestamp), this avoids multiple processors reading the value of the timestamp at the same location, allowing different processors to read the values of timestamps at different locations. Since different chip modules all include a snapshot module, the snapshot module can latch the timestamp based on an internal interrupt signal, avoiding multiple processors reading the latched timestamp at the same location, allowing different processors to read the latched timestamp at different locations. The timestamp synchronization circuit provided in this embodiment enables different processors to read the values of time counters and latch timestamps at different locations through the global timer register and snapshot module in each chip module. This achieves timestamp synchronization within the chip module and timestamp synchronization between different chip modules within the chip.
[0057] Optionally, as shown in Figure 1, the first synchronization circuit 12 and the second synchronization circuit 13 may further include a bias register 123 (offset).
[0058] Bias register 123 is used to store the timestamp difference between different chips.
[0059] The snapshot module 124 is also used to latch the global counter synchronization value corresponding to the external interrupt signal when an external interrupt signal is input. The external interrupt signal is an interrupt signal generated by a chip other than the chip itself.
[0060] The following example illustrates this.
[0061] Assume Figure 1 shows chip 0, which includes chip module 150 and chip module 151. There is also a chip 1. Chip 1 generates an external interrupt signal to latch the timestamp of chip 0 (e.g., chip module 150). After obtaining the timestamp latched by chip 0, chip 1 calculates the offset between the timestamps of chip 1 and chip 0 using software. Chip 1 sends this offset to chip 0. Chip modules 150 and 151 store the offset in bias register 123. Subsequently, after obtaining its own timestamp, chip module 150 simultaneously obtains the offset stored in bias register 123, and calculates the synchronized timestamps of chip 0 (or chip module 150) and chip 1.
[0062] For example, at the same moment, chip 0's timestamp is 1, and chip 1's timestamp is 3. Therefore, the timestamp difference between chip 0 and chip 1 is 2. Chip 0 stores this timestamp difference of 2 in bias register 123. When reading the timestamp, assuming that chip 0's CPU reads timestamp N from global timer register 122, then based on the timestamp difference stored in bias register 123, it can be determined that chip 1's timestamp is N+2, thus maintaining timestamp synchronization between chip 0 and chip 1.
[0063] For example, during data processing by the CPU of chip 0, chip 1 generates an external interrupt signal and outputs it to chip module 150 of chip 0. When the snapshot module 124 in chip module 150 receives the input external interrupt signal, it latches the global counter synchronization value corresponding to the external interrupt signal, assuming the timestamp is 4. Assuming the timestamp difference between chip 0 and chip 1 stored in bias register 123 is 2, then the timestamp of chip 1 corresponding to timestamp 4 is 2 + 4 = 6, thus maintaining the timestamp synchronization between chip 0 and chip 1.
[0064] It should be noted that this embodiment does not limit the number of bias registers 123, and there can be one or more.
[0065] As can be seen, in this implementation, each chip module within the chip includes a bias register that stores the timestamp difference between the different chips. Furthermore, the snapshot module latches the global counter synchronization value corresponding to the external interrupt signal. Through the bias registers and the snapshot module, timestamp synchronization between different chips is achieved.
[0066] Optionally, the snapshot module 124 includes a first input port and a second input port.
[0067] The first input port of the snapshot module 124 is used to input the internal interrupt signal (internal_interrupt) generated within the chip.
[0068] The second input port of the snapshot module 124 is used to input external interrupt signals (external_interrupt) generated by other chip modules outside the chip.
[0069] Optionally, as shown in Figure 1, the first input port of the snapshot module 124 is used to input an internal interrupt signal through the configuration interface of the Advanced Peripheral Bus (APB), or in other words, through the APB interface.
[0070] The second input port of the snapshot module is used to input an external interrupt signal via the PAD pin. For example, in Figure 1, an external interrupt signal is input via PAD pin 180.
[0071] PAD pins, also known as pins, are the wiring leads from the internal circuitry of an integrated circuit (chip) to the external circuitry.
[0072] Optionally, as shown in Figure 1, the timestamp synchronization circuit also includes a frequency multiplier 14 (PLL) and a selector 15. The output of the frequency multiplier 14 is connected to the input of the selector 15, and the output of the selector 15 is connected to the global timer 11.
[0073] Frequency multiplier 14 is used to multiply the input first clock signal (ref_clk) of the first frequency to generate a second clock signal (pll_clk) of the second frequency, and output the second clock signal to the selector.
[0074] Selector 15 is used to select either the first clock signal or the second clock signal from the input first clock signal (ref_clk) and the second clock signal (pll_clk) to be output as the global clock signal (global_timer_clk).
[0075] Optionally, as shown in Figure 1, the first clock signal (ref_clk) is generated by crystal oscillator 16, which is located outside the chip module (e.g., chip module 150) where the global timer 11 is located.
[0076] Optionally, as shown in Figure 1, the first clock signal (ref_clk) is input to the chip module 150 through the PAD pin 181.
[0077] This implementation provides two selection methods for the global clock signal (global_timer_clk). The first method uses the first clock signal (ref_clk) generated by the external crystal oscillator 16, directly selecting it as the global clock signal (global_timer_clk) to reduce switching frequency errors caused by low power consumption within the chip. The second method uses a faster second clock signal (pll_clk) obtained by multiplying the first clock signal (ref_clk) by the frequency multiplier 14. For example, the second clock signal (pll_clk) can have a frequency close to or the same as the clock signals of other chip modules to reduce errors between different chip modules, reduce the number of synchronization calibrations, and facilitate time synchronization between chip modules.
[0078] This embodiment does not limit the values or ranges of the first frequency, the second frequency, and the preset frequency. The first frequency can be greater than or less than the second frequency. For example, the first clock signal (ref_clk) can be a low-frequency clock signal, used in scenarios where the chip module 150 is in a low-power scenario.
[0079] For example, chip modules cannot use the same crystal oscillator clock. In low-power scenarios, when the PLL is off or enters low-power mode, the PLL has no output, and the first clock signal (ref_clk) serves as the global clock signal (global_timer_clk). If the global timer 11 uses the second clock signal (pll_clk) output by the PLL, it needs to switch from the first clock signal (ref_clk) to the second clock signal (pll_clk), which may introduce clock switching errors in this scenario.
[0080] Optionally, selector 15 is also used for:
[0081] From the input chip clock signal (pad_clk), the first clock signal (ref_clk), and the second clock signal (pll_clk), the output chip clock signal, the first clock signal, or the second clock signal is selected as the global clock signal. The chip clock signal is a clock signal provided by other chips outside the chip itself.
[0082] Optionally, as shown in Figure 1, the chip clock signal (pad_clk) is input to the chip module 150 through the PAD pin 182.
[0083] This implementation provides three options for the global clock signal (global_timer_clk). The first clock signal (ref_clk) and the second clock signal (pll_clk) are explained above and will not be repeated here. The chip clock signal (pad_clk) is the clock of other chips outside the chip. For example, Figure 1 shows chip 0, which includes chip module 150 and chip module 151. The chip clock signal is provided by chip 1. In scenarios where time synchronization is required between different chips, the chip clock signal (pad_clk) can be selected as the global clock signal (global_timer_clk). This reduces the cumulative error caused by different crystal oscillators between different chips, reduces the number of synchronization calibrations, and facilitates time synchronization between different chips.
[0084] Optionally, global timer 11 is also used for:
[0085] The global timer 11's shutdown debugging function is turned on or off based on the input global timer shutdown debugging signal (timerhltdbgen);
[0086] When the shutdown debugging function is enabled, the global counter value is stopped or continued to count according to the input control signal (hltdbg).
[0087] This implementation is suitable for scenarios where the halting and debugging function (hltdbg) is activated when global timer 11 encounters an exception. Here, hlt stands for Halt, and dbg stands for debug. When the halting and debugging function is activated and effective, the global counter value (global_timer_counters) will stop counting.
[0088] For example, this will be illustrated with reference to Figure 2.
[0089] As shown in Figure 2, the global timer 11 includes register 21 (also called reg), register 22, combinational logic unit 23, register 24, register 25, selector 26, register 27, and register 28. After power-on, the global counter value of the global timer 11 increments from 0. Register 21 is used to configure the shutdown debugging function of the global timer 11. The signal por_rstn is used for power-on reset, ensuring register 21 functions normally. When the global timer 11 malfunctions, the CPU / MCU, etc., can access register 21 through the APB interface to configure the shutdown debugging function of the global timer 11 and output a global timer shutdown debugging signal (timerhltdbgen). This signal is used to control whether the shutdown debugging function of the global timer 11 is enabled or disabled. The global timer 11 also receives a control signal (hltdbg), which is used to stop or resume the global counter value. Specifically, the inputs to selector 26 include timer_counter_out[N:0] and timer_counter_out[N:0]+1. timer_counter_out[N:0] indicates that the timer has stopped counting, and timer_counter_out[N:0]+1 indicates that the timer is counting normally and incrementing by 1. Registers 24, 25, 27, and 28 are used for timing to achieve time synchronization.
[0090] For example, Figure 3 is a schematic diagram of a global counter value synchronization module provided in an embodiment of this disclosure, illustrating the principle of the global counter value synchronization module realizing cross-clock domain synchronization. As shown in Figure 3, the global counter value synchronization module includes registers 31 to 35. Among them, registers 31 and 32 belong to the global_timer_clk clock domain, and registers 33, 34, and 35 belong to the dst_clk clock domain. Time synchronization across clock domains can be achieved by register timing. Wherein, global_timer_counter[N:0] represents the global counter value, and global_timer_counter_sync[N:0] represents the global counter synchronization value.
[0091] Figure 4 is a flowchart of a timestamp synchronization method provided in an embodiment of this disclosure. As shown in Figure 4, the timestamp synchronization method provided in this embodiment includes:
[0092] S401. Obtain the global clock signal and global counter value of the first chip module within the chip, and broadcast the global clock signal and global counter value to at least one second chip module within the chip.
[0093] S402. For the first chip module or the second chip module, cross-clock domain synchronization is performed based on the global clock signal and the global counter value to obtain the global counter synchronization value corresponding to the global counter value.
[0094] S403: Read the real-time value of the global counter synchronization value stored in the global timer register.
[0095] S404. When an internal interrupt signal is detected, read the global counter synchronization value corresponding to the internal interrupt signal latched by the snapshot module. The internal interrupt signal is an interrupt signal generated within the chip.
[0096] S405. Based on the real-time value of the global counter synchronization value and the global counter synchronization value corresponding to the internal interrupt signal, perform timestamp synchronization within the first chip module, or timestamp synchronization within the second chip module, or timestamp synchronization between the first chip module and the second chip module.
[0097] Optionally, timestamp synchronization also includes:
[0098] When an external interrupt signal is detected, the global counter synchronization value corresponding to the external interrupt signal, which is latched by the snapshot module, is read; where the external interrupt signal is an interrupt signal generated by a chip other than the chip itself.
[0099] The chip synchronizes its timestamps with other chips based on the real-time value of the global counter synchronization value, the global counter synchronization value corresponding to the external interrupt signal, and the timestamp difference between different chips stored in the bias register.
[0100] Optionally, the global clock signal of the first chip module is obtained, including:
[0101] Obtain a first clock signal of a first frequency input from outside the first chip module; or,
[0102] Obtain a second clock signal with a second frequency generated by multiplying the first clock signal using a frequency multiplier; or...
[0103] Obtain the chip clock signal provided by other chips besides the chip itself.
[0104] Optionally, the first chip module includes a global timer, and the timestamp synchronization method also includes:
[0105] Obtain the global timer stop debugging signal, and enable or disable the global timer stop debugging function based on the global timer stop debugging signal;
[0106] When the shutdown and debugging function is enabled, a control signal is acquired, and the global counter value is stopped or continued to be counted according to the control signal.
[0107] The timestamp synchronization method provided in this embodiment is applied to the timestamp synchronization circuit provided in this disclosure embodiment. The technical principle and technical effect are similar, and can be found in the relevant description. Further details are omitted here.
[0108] Referring to FIG5, a schematic diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown. The specific embodiments of the present disclosure do not limit the specific implementation of the electronic device.
[0109] As shown in Figure 5, the electronic device may include: a processor 401, a memory 403, a communication bus 404, and a communication interface 405.
[0110] The processor 401, memory 403, and communication interface 405 communicate with each other via communication bus 404.
[0111] Communication interface 405 is used for communication with other electronic devices or servers.
[0112] The processor 401 is used to execute the program 402, which can specifically execute the steps of any of the timestamp synchronization methods in the above embodiments.
[0113] Specifically, program 402 may include program code that includes computer operation instructions.
[0114] Processor 401 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.
[0115] Memory 403 is used to store program 402. Memory 403 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.
[0116] Specifically, program 402 can be used to cause processor 401 to execute steps to implement any of the timestamp synchronization methods described in the embodiments. The specific implementation of each step in program 402 can be found in the corresponding descriptions of the steps and units executed by any of the timestamp synchronization methods described above, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments.
[0117] This disclosure also provides a chip having a computer program stored thereon, which, when executed by a processor, implements the timestamp synchronization method as described in any of the above-described method embodiments.
[0118] This disclosure also provides a computer storage medium storing a computer program that, when executed by a processor, implements the timestamp synchronization method as described in any of the above method embodiments.
[0119] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to the timestamp synchronization method described in any of the above-described method embodiments.
[0120] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this disclosure can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this disclosure.
[0121] The methods described above according to embodiments of this disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.
[0122] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments disclosed herein.
[0123] The above embodiments are only used to illustrate the embodiments of this disclosure, and are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this disclosure, and the patent protection scope of the embodiments of this disclosure should be defined by the claims.
Claims
1. A timestamp synchronization circuit, characterized in that, include: A global timer, a first synchronization circuit, and a second synchronization circuit; the first synchronization circuit and the second synchronization circuit are disposed in different chip modules within the chip, while the global timer and the first synchronization circuit are disposed in the same chip module within the chip; Both the first synchronization circuit and the second synchronization circuit include: a global count value synchronization module, a global timer register, and a snapshot module; wherein, the global count value synchronization module is connected to the corresponding global timer register and the snapshot module respectively, and the global count value synchronization module in both the first synchronization circuit and the second synchronization circuit is connected to the global timer; The global timer is used to output the global clock signal and the global counter value to the global counter value synchronization module in the first synchronization circuit and the second synchronization circuit respectively, based on the input global clock signal. The global counter value synchronization module is used to perform cross-clock domain synchronization based on the input global clock signal and the global counter value, and output the global counter synchronization value corresponding to the global counter value to the corresponding global timer register and the snapshot module. The global timer register is used to store the real-time value of the input global counter synchronization value; The snapshot module is used to latch the global counter synchronization value corresponding to the internal interrupt signal when an internal interrupt signal is input, wherein the internal interrupt signal is an interrupt signal generated within the chip.
2. The timestamp synchronization circuit according to claim 1, characterized in that, The first synchronization circuit and the second synchronization circuit also include a bias register; The bias register is used to store the timestamp difference between different chips; The snapshot module is also used to latch the global counter synchronization value corresponding to the external interrupt signal when an external interrupt signal is input, wherein the external interrupt signal is an interrupt signal generated by a chip other than the chip itself.
3. The timestamp synchronization circuit according to claim 2, characterized in that, The snapshot module includes a first input port and a second input port; The first input port of the snapshot module is used to input the internal interrupt signal through the configuration interface of the peripheral bus APB; The second input port of the snapshot module is used to input the external interrupt signal via the PAD pin.
4. The timestamp synchronization circuit according to any one of claims 1-3, characterized in that, The timestamp synchronization circuit further includes a frequency multiplier and a selector, the output of the frequency multiplier is connected to the input of the selector, and the output of the selector is connected to the global timer; The frequency multiplier is used to multiply the input first clock signal of the first frequency to generate a second clock signal of the second frequency, and output the second clock signal to the selector. The selector is used to select, from the input first clock signal and the second clock signal, to output either the first clock signal or the second clock signal as the global clock signal.
5. The timestamp synchronization circuit according to claim 4, characterized in that, The selector is also used for: Among the input chip clock signal, the first clock signal, and the second clock signal, the chip clock signal, the first clock signal, or the second clock signal is selected to be output as the global clock signal; wherein, the chip clock signal is a clock signal provided by other chips besides the chip itself.
6. The timestamp synchronization circuit according to claim 4, characterized in that, The first clock signal is generated by a crystal oscillator located outside the chip.
7. The timestamp synchronization circuit according to any one of claims 1-3, characterized in that, The global timer is also used for: The global timer's shutdown and debugging function can be turned on or off based on the input global timer shutdown and debugging signal; When the shutdown and debugging function is enabled, the global counter value is stopped or continued to count according to the input control signal.
8. A timestamp synchronization method, characterized in that, include: Obtain the global clock signal and global counter value of the first chip module within the chip, and broadcast the global clock signal and the global counter value to at least one second chip module within the chip; For the first chip module or the second chip module, cross-clock domain synchronization is performed based on the global clock signal and the global counter value to obtain the global counter synchronization value corresponding to the global counter value; Read the real-time value of the global counter synchronization value stored in the global timer register; When an internal interrupt signal is detected, the global counter synchronization value corresponding to the internal interrupt signal, which is latched by the snapshot module, is read; wherein, the internal interrupt signal is an interrupt signal generated within the chip; Based on the real-time value of the global counter synchronization value and the global counter synchronization value corresponding to the internal interrupt signal, timestamp synchronization is performed within the first chip module, or timestamp synchronization is performed within the second chip module, or timestamp synchronization is performed between the first chip module and the second chip module.
9. The method according to claim 8, characterized in that, The method further includes: When an external interrupt signal is detected, the global counter synchronization value corresponding to the external interrupt signal, which is latched by the snapshot module, is read; wherein, the external interrupt signal is an interrupt signal generated by a chip other than the chip itself. The chip is synchronized with the other chips based on the real-time value of the global counter synchronization value, the global counter synchronization value corresponding to the external interrupt signal, and the timestamp difference between different chips stored in the bias register.
10. The method according to claim 8, characterized in that, The step of obtaining the global clock signal of the first chip module includes: Obtain a first clock signal of a first frequency input from outside the first chip module; or, Obtain a second clock signal with a second frequency generated by multiplying the first clock signal using a frequency multiplier; or... Obtain the chip clock signal provided by other chips input from outside the first chip module.
11. The method according to any one of claims 8-10, characterized in that, The first chip module includes a global timer, and the method further includes: Obtain the global timer stop debugging signal, and enable or disable the global timer stop debugging function according to the global timer stop debugging signal; When the shutdown and debugging function is enabled, a control signal is acquired, and the global counter value is stopped or continued to be counted according to the control signal.
12. A chip, characterized in that, The chip comprises: at least two chip modules and a timestamp synchronization circuit as described in any one of claims 1-7; or, The chip includes a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the method as described in any one of claims 8-11.
13. An electronic device, characterized in that, The electronic device includes: the chip as described in claim 12; or, The electronic device includes: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the method as described in any one of claims 8-11.
14. A computer storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 8-11.