Display substrate and display apparatus

Abstract

Provided in the embodiments of the present disclosure are a display substrate and a display apparatus. The display substrate comprises a plurality of repeat units, wherein at least one repeat unit comprises a display unit and a light-transmitting unit, the display unit is configured to perform double-sided image display, and the light-transmitting unit is configured to transmit light. The display unit comprises 2n circuit units and 2n light-emitting units, wherein the 2n light-emitting units comprise n first-type light-emitting units and n second-type light-emitting units, emergent light of the first-type light-emitting units is in a bottom emission mode, emergent light of the second-type light-emitting units is in a top emission mode, the 2n circuit units comprise n first-type circuit units and n second-type circuit units, pixel driving circuits of the first-type circuit units are connected to the first-type light-emitting units, and pixel driving circuits of the second-type circuit units are connected to the second-type light-emitting units. In the present disclosure, double-sided transparent display is realized by means of an organic combination of a top emission structure and a bottom emission structure in a repeat unit.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411591898.4, filed on November 7, 2024, entitled "Display Substrate and Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as active emission, ultra-thinness, wide viewing angle, high brightness, high contrast, low power consumption, extremely high response speed, lightweight design, customizability, and flexible display capabilities. They have gradually become a promising next-generation display technology. Among them, active matrix (AM) OLEDs are current-driven devices that use independent transistors (Thin Film Transistors, TFTs) to control each circuit unit, allowing each unit to emit light continuously and independently.

[0004] With the continuous development of display technology, OLED technology is increasingly being applied to transparent displays. Transparent display is an important area of ​​personalized display technology, referring to the display of images in a transparent state. Viewers can see not only the images in the display device, but also the scene behind the display device, enabling virtual reality (VR), augmented reality (AR), and 3D display functions. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] On one hand, this disclosure provides a display substrate including a plurality of repeating units, at least one repeating unit including a display unit and a light-transmitting unit located on at least one side of the display unit. The display unit is configured to perform bi-lateral image display, and the light-transmitting unit is configured to transmit light. In a direction perpendicular to the display substrate, the display substrate includes at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer of the display unit includes 2n circuit units, and the light-emitting structure layer of the display unit includes 2n light-emitting units. Each circuit unit includes at least a pixel driving circuit, and each light-emitting unit includes at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and n is 3 or 4. The 2n light-emitting units include n first-type light-emitting units and n second-type light-emitting units. The emitted light from the first-type light-emitting units is bottom-emitting, and the emitted light from the second-type light-emitting units is top-emitting. Alternatively, the emitted light from the first-type light-emitting units is bottom-emitting, and the emitted light from the second-type light-emitting units is top-emitting. The emitted light is emitted from the top, while the emitted light from the second type of light-emitting unit is emitted from the bottom. The 2n circuit units include n first-type circuit units and n second-type circuit units. The pixel driving circuit in the first-type circuit unit is connected to the light-emitting device in the first-type light-emitting unit, and the pixel driving circuit in the second-type circuit unit is connected to the light-emitting device in the second-type light-emitting unit. The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a first node electrode with a first node potential, and a second node electrode with a second node potential. The second electrode of the first transistor and the gate electrode of the second transistor are connected to the first node electrode, and the second electrode of the second transistor and the second electrode of the third transistor are connected to the second node electrode. In at least one circuit unit, the first transistor, the second transistor, and the third transistor are arranged sequentially along a first direction. In at least one repeating unit, the 2n circuit units are arranged sequentially along a second direction, and the first direction and the second direction intersect.

[0007] In an exemplary embodiment, the n first-type light-emitting units include at least a first-type first-light-emitting unit emitting a first-color light, a first-type second-light-emitting unit emitting a second-color light, and a first-type third-light-emitting unit emitting a third-color light; the n second-type light-emitting units include at least a second-type first-light-emitting unit emitting a first-color light, a second-type second-light-emitting unit emitting a second-color light, and a second-type third-light-emitting unit emitting a third-color light; the n first-type circuit units include at least a first-type first-circuit unit connected to the first-type first-light-emitting unit, a first-type second-circuit unit connected to the first-type second-light-emitting unit, and a first-type third-circuit unit connected to the first-type third-light-emitting unit; the n second-type circuit units include at least a second-type first-circuit unit connected to the second-type first-light-emitting unit, a second-type second-circuit unit connected to the second-type second-light-emitting unit, and a second-type third-circuit unit connected to the second-type third-light-emitting unit; in at least one repeating unit, the first-type first-circuit unit, the second-type first-circuit unit, the first-type second-circuit unit, the second-type second-circuit unit, the first-type third-circuit unit, and the second-type third-circuit unit are arranged sequentially along the second direction.

[0008] In an exemplary embodiment, the first type of first light-emitting unit, the first type of second light-emitting unit, and the first type of third light-emitting unit are arranged sequentially along the second direction to form a first light-emitting unit group; the second type of first light-emitting unit, the second type of second light-emitting unit, and the second type of third light-emitting unit are arranged sequentially along the second direction to form a second light-emitting unit group; the first light-emitting unit group is disposed on one side of the second light-emitting unit group in the first direction.

[0009] In an exemplary embodiment, the n first-type light-emitting units include at least a first-type first-light-emitting unit emitting a first-color light, a first-type second-light-emitting unit emitting a second-color light, and a first-type third-light-emitting unit emitting a third-color light; the n second-type light-emitting units include at least a second-type first-light-emitting unit emitting a first-color light, a second-type second-light-emitting unit emitting a second-color light, and a second-type third-light-emitting unit emitting a third-color light; the n first-type circuit units include at least a first-type first-circuit unit connected to the first-type first-light-emitting unit, a first-type second-circuit unit connected to the first-type second-light-emitting unit, and a first-type third-circuit unit connected to the first-type third-light-emitting unit; the n second-type circuit units include at least a second-type first-circuit unit connected to the second-type first-light-emitting unit, a second-type second-circuit unit connected to the second-type second-light-emitting unit, and a second-type third-circuit unit connected to the second-type third-light-emitting unit; in at least one repeating unit, the first-type first-circuit unit, the first-type second-circuit unit, the first-type third-circuit unit, the second-type first-circuit unit, the second-type second-circuit unit, and the second-type third-circuit unit are arranged sequentially along the second direction.

[0010] In an exemplary embodiment, the first type of first light-emitting unit, the first type of second light-emitting unit, and the first type of third light-emitting unit are arranged sequentially along the second direction to form a third light-emitting unit group; the second type of first light-emitting unit and the second type of second light-emitting unit are arranged sequentially along the second direction to form a fourth light-emitting unit group; the third light-emitting unit group is disposed on one side of the fourth light-emitting unit group in the first direction, and the second type of third light-emitting unit is disposed on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction.

[0011] In an exemplary embodiment, at least one repeating unit further includes a scan signal line, the scan signal line being a straight line or a broken line extending along the first direction, and the first transistor and the third transistor in the 2n circuit units of the repeating unit being connected to the same scan signal line.

[0012] In an exemplary embodiment, at least one repeating unit further includes a first gate line and a third gate line connected to the scan signal line. The first gate line and the third gate line are in the shape of a straight line or a broken line extending along a second direction. The third gate line is disposed on one side of the first gate line in the first direction. The first gate line is connected to the gate electrode of the first transistor of each of the 2n circuit units in the repeating unit, and the third gate line is connected to the gate electrode of the third transistor of each of the 2n circuit units in the repeating unit.

[0013] In an exemplary embodiment, at least one repeating unit further includes a first power line, a second power line, a compensation signal line, and 2n data signal lines. The first terminals of the second transistors of the 2n circuit units in the repeating unit are connected to the same first power line, the first terminals of the third transistors of the 2n circuit units in the repeating unit are connected to the same compensation signal line, and the first terminals of the first transistors of the 2n circuit units in the repeating unit are respectively connected to the 2n data signal lines.

[0014] In an exemplary embodiment, the first power line, the second power line, the compensation signal line, and the data signal line are in the shape of a straight line or a broken line extending along the second direction; in at least one repeating unit, in the first direction, the second power line is disposed on the side of the first gate line away from the third gate line, the 2n data signal lines are disposed between the first gate line and the second power line, the compensation signal line is disposed on the side of the third gate line away from the first gate line, and the first power line is disposed between the first gate line and the third gate line.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, the structure of which differs from the structure of the storage capacitor in the first type of circuit unit.

[0016] In an exemplary embodiment, the emitted light from the first type of light-emitting unit is bottom-emitting, and the emitted light from the second type of light-emitting unit is top-emitting. The first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit. In the bottom-emitting circuit unit, the storage capacitor includes at least a transparent first electrode plate and a transparent second electrode plate. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode plate is connected to the second node electrode, and the second electrode plate is connected to the first node electrode. The first electrode plate and the second electrode plate form the transparent storage capacitor in the bottom-emitting circuit unit.

[0017] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, and a semiconductor layer disposed on a side of the first conductive layer away from the substrate, wherein the first electrode plate is disposed in the first transparent conductive layer and the second electrode plate is disposed in the semiconductor layer.

[0018] In an exemplary embodiment, the emitted light from the first type of light-emitting unit is bottom-emitting, and the emitted light from the second type of light-emitting unit is top-emitting. The first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit. In at least one of the top-emitting circuit units, the storage capacitor includes at least a third plate, a fourth plate, and a fifth plate. The orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate, and the orthographic projection of the fifth plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate. The third plate and the fifth plate are connected to the second node electrode, and the fourth plate is connected to the first node electrode. The third plate and the fourth plate form a first sub-capacitor, and the fourth plate and the fifth plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the storage capacitor in the top-emitting circuit unit.

[0019] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on the substrate, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on the side of the first conductive layer away from the substrate, a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate. The third electrode plate is disposed in the first conductive layer, the fourth electrode plate is disposed in the semiconductor layer, and the fifth electrode plate is disposed in the third conductive layer.

[0020] In an exemplary embodiment, the emitted light from the first type of light-emitting unit is bottom-emitting, and the emitted light from the second type of light-emitting unit is top-emitting. The first type of light-emitting unit includes at least a first anode, and the second type of light-emitting unit includes at least a second anode. The structure of the first anode is different from the structure of the second anode.

[0021] In an exemplary embodiment, the first anode includes at least a main body and a connecting part. The main body is disposed in the display unit, a first end of the connecting part is connected to the main body, and a second end of the connecting part extends behind the light-transmitting unit and is connected to the pixel driving circuit of the first type of circuit unit.

[0022] In an exemplary embodiment, the second anode includes at least a first sub-anode, a second sub-anode, and a sub-connecting electrode. The first sub-anode and the second sub-anode are disposed in the display unit and isolated from each other. One end of the sub-connecting electrode is connected to the first sub-anode and the second sub-anode, respectively. The other end of the sub-connecting electrode extends to the back of the light-transmitting unit and is connected to the pixel driving circuit of the second type of circuit unit.

[0023] In an exemplary embodiment, the second type of light-emitting unit further includes a third anode, the third anode including at least a first reflective electrode and a second reflective electrode, the first reflective electrode and the second reflective electrode being disposed in the display unit and isolated from each other, the orthographic projection of the first reflective electrode on the substrate at least partially overlapping the orthographic projection of the first sub-anode on the substrate and overlapping with the first sub-anode, the orthographic projection of the second reflective electrode on the substrate at least partially overlapping the orthographic projection of the second sub-anode on the substrate and overlapping with the second sub-anode.

[0024] In an exemplary embodiment, the first type of light-emitting unit further includes a first cathode, and the second type of light-emitting unit further includes a second cathode. The first cathode and the second cathode are isolated from each other. The first cathode is made of a reflective material, and the second cathode is made of a transparent material.

[0025] In an exemplary embodiment, the first type of light-emitting unit further includes a third cathode, which overlaps with the first cathode. The second cathode and the third cathode are disposed in the same layer and are an integral structure that is interconnected.

[0026] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0029] Figure 1 is a schematic diagram of a display device;

[0030] Figure 2 is a schematic diagram of the arrangement of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 3A is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure;

[0032] Figure 3B is a schematic diagram of the arrangement of a circuit unit according to an exemplary embodiment of the present disclosure;

[0033] Figure 4 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit of an exemplary embodiment of the present disclosure;

[0034] Figure 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 6 is a schematic diagram of the first transparent conductive layer pattern after it is formed according to an embodiment of the present disclosure;

[0036] Figures 7A and 7B are schematic diagrams of the first conductive layer pattern formed according to an embodiment of the present disclosure;

[0037] Figures 8A and 8B are schematic diagrams of the semiconductor layer pattern formed according to the embodiments of this disclosure;

[0038] Figures 9A and 9B are schematic diagrams of the second conductive layer pattern after it has been formed according to an embodiment of the present disclosure;

[0039] Figure 10 is a schematic diagram of the third insulating layer pattern after it is formed according to an embodiment of the present disclosure;

[0040] Figures 11A and 11B are schematic diagrams of the formation of the third conductive layer pattern according to an embodiment of the present disclosure;

[0041] Figure 12 is a schematic diagram of the formation of the planarization layer and the fourth insulating layer pattern according to an embodiment of the present disclosure;

[0042] Figures 13A and 13B are schematic diagrams after the formation of the second transparent conductive layer pattern according to an embodiment of the present disclosure;

[0043] Figures 14A and 14B are schematic diagrams of the formation of the reflective conductive layer pattern according to an embodiment of the present disclosure;

[0044] Figure 15 is a schematic diagram of the cathode pattern formed according to an embodiment of the present disclosure;

[0045] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 17 is a schematic diagram of the cathode pattern formed in the embodiment shown in Figure 16;

[0047] Figure 18A is a schematic diagram of another arrangement of light-emitting units in an exemplary embodiment of the present disclosure;

[0048] Figure 18B is a schematic diagram of another circuit unit arrangement in an exemplary embodiment of the present disclosure;

[0049] Figure 19 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0050] Explanation of reference numerals in the attached figures: 11—First electrode plate; 12—Second electrode plate; 13—Third electrode plate; 14—Fourth electrode plate; 15—Fifth electrode plate; 16—Shielding electrode; 21—First active layer; 22—Second active layer; 23—Third active layer; 30—Scan signal line; 31—First gate line; 32—Second gate electrode; 33—Third gate line; 34—Data connection line; 35—Power supply auxiliary line; 41—First connecting electrode; 42—Second connecting electrode; 43—Third connecting electrode; 50—Data connecting electrode; 51—Eleventh connecting electrode; 52—Twelfth connecting electrode; 53—Thirteenth connecting electrode; 54—First anode connecting electrode; 61—Twenty-first connecting electrode; 62—Twenty-second connecting electrode; 63—Twenty-third connecting electrode; 64—Second anode connecting electrode; 71—First power supply line; 72—Second power line; 73—Data signal line; 74—Compensation signal line; 75—First auxiliary electrode; 76—Second auxiliary electrode; 77—Third auxiliary electrode; 81—First anode; 81-1—Main body; 81-2—Connecting part; 82—Second anode; 82-1—First sub-anode; 82-2—Second sub-anode; 82-3—Sub-connecting electrode; 83—Third anode; 83-1—First reflective electrode; 83-2—Second reflective electrode; 91—First cathode; 92—Second cathode; 93—Third cathode; 94—Pixel definition layer; 95—Organic light-emitting layer; 96—Color filter layer; 97—Black matrix; 98—Cover plate; 100—Repetition unit; 110—Display unit; 120—Light-transmitting unit. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0052] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0053] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0054] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0055] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0056] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0057] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0058] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0059] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0060] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0061] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0062] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0063] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to both the data driver and the scan driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the scan driver is connected to multiple scan signal lines (S1 to Sm). The pixel array may include multiple sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. At least one circuit unit Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit, which is connected to both the scan signal line and the data signal line. The display unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and connected to the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn, where n can be a natural number. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm, where m can be a natural number, by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0064] An exemplary embodiment of this disclosure provides a display substrate including a plurality of repeating units. At least one repeating unit includes a display unit and a light-transmitting unit located on at least one side of the display unit. The display unit is configured to perform bi-lateral image display, and the light-transmitting unit is configured to transmit light. In a direction perpendicular to the display substrate, the display substrate includes at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer of the display unit includes 2n circuit units, and the light-emitting structure layer of the display unit includes 2n light-emitting units. Each circuit unit includes at least a pixel driving circuit, and each light-emitting unit includes at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and n is 3 or 4. The 2n light-emitting units include n first-type light-emitting units and n second-type light-emitting units. The emitted light from the first-type light-emitting units is bottom-emitted, and the emitted light from the second-type light-emitting units is top-emitted. Alternatively, the emitted light from the first-type light-emitting units... The light emitted is from the top, while the light emitted by the second type of light-emitting unit is emitted from the bottom. The 2n circuit units include n first-type circuit units and n second-type circuit units. The pixel driving circuit of the first-type circuit unit is connected to the light-emitting device in the first-type light-emitting unit, and the pixel driving circuit of the second-type circuit unit is connected to the light-emitting device in the second-type light-emitting unit. The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a first node electrode with a first node potential, and a second node electrode with a second node potential. The second electrode of the first transistor and the gate electrode of the second transistor are connected to the first node electrode, and the second electrode of the second transistor and the second electrode of the third transistor are connected to the second node electrode. In at least one circuit unit, the first transistor, the second transistor, and the third transistor are arranged sequentially along a first direction. In at least one repeating unit, the 2n circuit units are arranged sequentially along a second direction, and the first direction and the second direction intersect.

[0065] In an exemplary embodiment, at least one repeating unit further includes a scan signal line, the scan signal line being a straight line or a broken line extending along the first direction, and the first transistor and the third transistor in the 2n circuit units of the repeating unit being connected to the same scan signal line.

[0066] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, the structure of which differs from the structure of the storage capacitor in the first type of circuit unit.

[0067] In an exemplary embodiment, the emitted light from the first type of light-emitting unit is bottom-emitting, and the emitted light from the second type of light-emitting unit is top-emitting. The first type of light-emitting unit includes at least a first anode, and the second type of light-emitting unit includes at least a second anode. The structure of the first anode is different from the structure of the second anode.

[0068] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0069] Figure 2 is a schematic diagram of the arrangement of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 2, on a plane parallel to the display substrate, the display substrate may include a plurality of repeating units 100 arranged in a regular pattern. The repeating units 100 are the basic units constituting the display substrate. The display substrate is formed by repeating and continuously arranging them along at least one direction, that is, the display substrate is spliced ​​together by a plurality of repeating units. In an exemplary embodiment, at least one repeating unit 100 may include a display unit 110 and a light-transmitting unit 120. The display unit 110 is configured to perform image display on both sides, and the light-transmitting unit 120 may be located on at least one side of the display unit 110. The light-transmitting unit 120 is configured to transmit light, so that the display substrate composed of a plurality of repeating units 100 can realize image display on both the front and back sides in a transparent state, that is, double-sided transparent display.

[0070] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. In at least one repeating unit, the driving circuit layer of the display unit may include 2n circuit units, and the light-emitting structure layer of the display unit may include 2n light-emitting units. The circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit.

[0071] In an exemplary implementation, n can be 3 or n can be 4.

[0072] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0073] Figure 3A is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure, and Figure 3B is a schematic diagram of the arrangement of circuit units according to an exemplary embodiment of the present disclosure, illustrating the case where n is 3. On a plane parallel to the display substrate, at least one repeating unit may include a display unit 110 and a light-transmitting unit 120. The display unit 110 may be located on one side of the light-transmitting unit 120 in the first direction X. The display unit 110 may include 6 circuit units and 6 light-emitting units.

[0074] As shown in Figure 3A, the six light-emitting units in at least one display unit 110 may include three first-type light-emitting units and three second-type light-emitting units. The emitted light from the first-type light-emitting units may be bottom-emitting, and the emitted light from the second-type light-emitting units may be top-emitting. The three first-type light-emitting units may be a first bottom-emitting light-emitting unit P1_B, a second bottom-emitting light-emitting unit P2_B, and a third bottom-emitting light-emitting unit P3_B, respectively. The three second-type light-emitting units may be a first top-emitting light-emitting unit P1_T, a second top-emitting light-emitting unit P2_T, and a third top-emitting light-emitting unit P3_T, respectively.

[0075] In an exemplary embodiment, in at least one display unit 110, a first bottom-emitting light-emitting unit P1_B, a second bottom-emitting light-emitting unit P2_B, and a third bottom-emitting light-emitting unit P3_B can be sequentially arranged along the second direction Y to form a first light-emitting unit group. A first top-emitting light-emitting unit P1_T, a second top-emitting light-emitting unit P2_T, and a third top-emitting light-emitting unit P3_T can be sequentially arranged along the second direction Y to form a second light-emitting unit group. The first light-emitting unit group can be located on one side of the second light-emitting unit group in the first direction X.

[0076] In an exemplary embodiment, the first bottom-emitting light-emitting unit P1_B and the first top-emitting light-emitting unit P1_T can be red light-emitting units (R) that emit red light, the second bottom-emitting light-emitting unit P2_B and the second top-emitting light-emitting unit P2_T can be green light-emitting units (G) that emit green light, and the third bottom-emitting light-emitting unit P3_B and the third top-emitting light-emitting unit P3_T can be blue light-emitting units (B) that emit blue light. In some possible embodiments, the arrangement of RGB can be adjusted according to actual needs, and this disclosure does not limit it.

[0077] In one possible implementation, the first type of light-emitting unit can be configured to emit light in a top-emitting manner, and the second type of light-emitting unit can be configured to emit light in a bottom-emitting manner, without limitation herein.

[0078] As shown in Figure 3B, the six circuit units in at least one display unit 110 may include three first-type circuit units and three second-type circuit units. The first-type circuit units are connected to the first-type light-emitting units, and the second-type circuit units are connected to the second-type light-emitting units. In an exemplary embodiment, the connection between the circuit units and the light-emitting units, as stated in this disclosure, refers to the connection between the pixel driving circuit in the circuit unit and the light-emitting device in the light-emitting unit. The three first-type circuit units may be a first bottom-emitting circuit unit Q1_B, a second bottom-emitting circuit unit Q2_B, and a third bottom-emitting circuit unit Q3_B, respectively. The three second-type circuit units may be a first top-emitting circuit unit Q1_T, a second top-emitting circuit unit Q2_T, and a third top-emitting circuit unit Q3_T, respectively.

[0079] In an exemplary embodiment, in at least one display unit 110, the first bottom emitting circuit unit Q1_B, the first top emitting circuit unit Q1_T, the second bottom emitting circuit unit Q2_B, the second top emitting circuit unit Q2_T, the third bottom emitting circuit unit Q3_B, and the third top emitting circuit unit Q3_T can be arranged sequentially along the second direction Y. The six circuit units are arranged vertically, and the bottom emitting circuit unit and the top emitting circuit unit are arranged in an interleaved manner.

[0080] In an exemplary embodiment, the light-transmitting unit 120 may be located on the side opposite to the first direction X of the display unit 110, where the first direction X intersects with the second direction Y.

[0081] Figure 4 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit including 6 pixel driving circuits. As shown in Figure 4, at least one repeating unit may include 6 pixel driving circuits, which may be arranged vertically, and each pixel driving circuit may be a 3T1C structure.

[0082] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (first transistor T1, second transistor T2 and third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to the scan signal line 30, the first power supply line 71, the data signal line 73 and the compensation signal line 74, respectively.

[0083] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively.

[0084] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0085] In an exemplary embodiment, the first transistor T1 can be used as a data writing transistor. The gate electrode of the first transistor T1 is connected to the scan signal line 30, the first electrode of the first transistor T1 is connected to the data signal line 73, and the second electrode of the first transistor T1 is connected to the first node N1.

[0086] In an exemplary embodiment, the second transistor T2 can be used as a driving transistor. The gate electrode of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first power line 71, and the second electrode of the second transistor T2 is connected to the second node N2.

[0087] In an exemplary embodiment, the third transistor T3 can be used as a compensation transistor. The gate electrode of the third transistor T3 is connected to the scan signal line 30, the first electrode of the third transistor T3 is connected to the compensation signal line 74, and the second electrode of the third transistor T3 is connected to the second node N2.

[0088] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30.

[0089] In an exemplary embodiment, in the six pixel driving circuits of at least one repeating unit, the gate electrodes of six first transistors T1 and the gate electrodes of six third transistors T3 are connected to the same scan signal line 30.

[0090] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line 72. The light-emitting device EL emits light of corresponding brightness in response to the current of the second transistor T2. In an exemplary embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0091] In an exemplary embodiment, the signal of the first power line 71 is a continuously supplied high-level signal, and the signal of the second power line 72 is a continuously supplied low-level signal.

[0092] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the third transistor T3 may include both P-type and N-type transistors.

[0093] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), or oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs have advantages such as high mobility and fast charging, while OPTs have advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0094] Figure 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit including six circuit units. As shown in Figure 5, the display substrate may include a plurality of repeating units arranged in a regular manner. At least one repeating unit may include a display unit 110 and a light-transmitting unit 120 located on at least one side of the display unit 110. The display unit 110 is configured to perform bi-lateral image display, and the light-transmitting unit 120 is configured to transmit light. The display unit 110 may include a first bottom transmitting circuit unit Q1_B, a first top transmitting circuit unit Q1_T, a second bottom transmitting circuit unit Q2_B, a second top transmitting circuit unit Q2_T, a third bottom transmitting circuit unit Q3_B, and a third top transmitting circuit unit Q3_T arranged vertically. The first top transmitting circuit unit Q1_T may be located on one side of the first bottom transmitting circuit unit Q1_B in the second direction Y. The second bottom transmitting circuit unit Q2_B may be located on one side of the first top transmitting circuit unit Q1_T in the second direction Y. The second top transmitting circuit unit Q2_T may be located on one side of the second bottom transmitting circuit unit Q2_B in the second direction Y. The third bottom transmitting circuit unit Q3_B may be located on one side of the second top transmitting circuit unit Q2_T in the second direction Y. The third top transmitting circuit unit Q3_T may be located on one side of the third bottom transmitting circuit unit Q3_B in the second direction Y. At least one circuit unit may include a pixel driving circuit, the pixel driving circuit of the bottom emission circuit unit is connected to a light-emitting device that emits light in a bottom emission mode, the pixel driving circuit of the top emission circuit unit is connected to a light-emitting device that emits light in a top emission mode, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0095] In an exemplary embodiment, in at least one circuit unit, a pixel driving circuit can be connected to a scan signal line 30, a first power supply line 71, a data signal line 73, and a compensation signal line 74, respectively. The light-emitting device connected to the pixel driving circuit is connected to a second power supply line 72. The scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power supply line 71 is configured to provide a first power signal to the pixel driving circuit, the second power supply line 72 is configured to provide a second power signal to the light-emitting device, the data signal line 73 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 74 is configured to provide a compensation signal to the pixel driving circuit.

[0096] In an exemplary embodiment, the shape of the scan signal line 30 can be a straight line or a broken line extending along the first direction X, and it can be located on the side of the first bottom transmitting circuit unit Q1_B away from the first top transmitting circuit unit Q1_T. The first transistor T1 and the third transistor T3 of the six circuit units in the repeating unit are connected to the same scan signal line 30.

[0097] In an exemplary embodiment, at least one repeating unit may further include a first gate line 31 and a third gate line 33. In the first direction X, the third gate line 33 may be disposed on one side of the first gate line 31 in the first direction X; in the second direction Y, the first gate line 31 and the third gate line 33 may be disposed on one side of the scan signal line 30 in the second direction Y. The first gate line 31 and the third gate line 33 may be straight or zigzag-shaped extending along the second direction Y. The first ends of the first gate line 31 and the third gate line 33 are connected to the scan signal line 30. The first ends of the first gate line 31 and the third gate line 33 extend along the second direction Y from the first bottom emitting circuit unit Q1_B to the third top emitting circuit unit Q3_T. The first gate line 31 is connected to the gate electrode of the first transistor T1 of each of the six circuit units, and the third gate line 33 is connected to the gate electrode of the third transistor T3 of each of the six circuit units.

[0098] In an exemplary embodiment, at least one repeating unit may include a first power line 71, a second power line 72, a compensation signal line 74, and six data signal lines 73. The shapes of the first power line 71, the second power line 72, the data signal line 73, and the compensation signal line 74 may be straight lines or broken lines extending along the second direction Y. The cathodes of the six light-emitting devices in the repeating unit are connected to the same second power line 72. The first terminals of the second transistors T2 of the six circuit units in the repeating unit are connected to the same first power line 71. The first terminals of the third transistors T3 of the six circuit units in the repeating unit are connected to the same compensation signal line 74. The first terminals of the first transistors T1 of the six circuit units in the repeating unit are respectively connected to the six data signal lines 73.

[0099] In an exemplary embodiment, in at least one repeating unit, in the first direction X, the second power line 72 may be disposed on the side of the first gate line 31 away from the third gate line 33, the compensation signal line 74 may be disposed on the side of the third gate line 33 away from the first gate line 31, six data signal lines 73 may be disposed between the first gate line 31 and the second power line 72, and the first power line 71 may be disposed between the first gate line 31 and the third gate line 33.

[0100] In an exemplary embodiment, at least one circuit unit may include a pixel driving circuit comprising at least a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a compensation transistor, a first node electrode having a first node potential, and a second node electrode having a second node potential. The first electrode of the first transistor T1 is connected to the data signal line 73; the second electrode of the first transistor T1 and the gate electrode of the second transistor T2 are connected to the first node electrode; the first electrode of the second transistor T2 is connected to the first power supply line 71; the second electrodes of the second transistor T2 and the second electrodes of the third transistor T3 are connected to the second node electrode; and the first electrode of the third transistor T3 is connected to the compensation signal line 74.

[0101] In an exemplary embodiment, in at least one circuit unit, the pixel driving circuit may further include a storage capacitor, and the structure of the storage capacitor in the bottom emitter circuit unit is different from the structure of the storage capacitor in the top emitter circuit unit.

[0102] In an exemplary embodiment, in at least one of the bottom-emitting circuit units Q1_B, Q2_B, and Q3_B, the storage capacitor may include at least a transparent first electrode 11 and a transparent second electrode 12, wherein the orthographic projection of the second electrode 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode 11 on the substrate.

[0103] In an exemplary embodiment, the first electrode plate 11 is connected to the second electrode of the second transistor T2 at least through the twelfth connecting electrode 52, and to the second electrode of the third transistor T3 at least through the thirteenth connecting electrode 53. This achieves interconnection between the first electrode plate 11, the second electrode of the second transistor T2, and the second electrode of the third transistor T3, forming the second node N2 of the pixel driving circuit. In an exemplary embodiment, the twelfth connecting electrode 52 and the thirteenth connecting electrode 53 can serve as the second node electrodes in the emitter circuit unit of the present disclosure.

[0104] In an exemplary embodiment, the second electrode plate 12 is connected to the second electrode of the first transistor T1 on one hand, and to the gate electrode of the second transistor T2 at least through the eleventh connection electrode 51 on the other hand. This achieves interconnection between the second electrode plate 12, the second electrode of the first transistor T1, and the gate electrode of the second transistor T2, forming the first node N1 of the pixel driving circuit. In an exemplary embodiment, the eleventh connection electrode 51 can serve as the first node electrode in the emitter circuit unit of the present disclosure.

[0105] In an exemplary embodiment, a first electrode 11 having a second node potential and a second electrode 12 having a first node potential constitute the storage capacitor in the bottom emitter circuit unit.

[0106] In an exemplary embodiment, in at least one of the top-emitting circuit units Q1_T, Q2_T, and Q3_T, the storage capacitor may include at least a third electrode 13, a fourth electrode 14, and a fifth electrode 15, wherein the orthographic projection of the fourth electrode 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode 13 on the substrate, and the orthographic projection of the fifth electrode 15 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode 14 on the substrate.

[0107] In an exemplary embodiment, the third electrode plate 13 is connected to the second electrode of the third transistor T3 at least via the twenty-third connecting electrode 63, and is also connected to the fifth electrode plate 15 via a via. The fifth electrode plate 15 is connected to the twenty-second connecting electrode 62, which is in turn connected to the second electrode of the second transistor T2. This interconnection between the third electrode plate 13, the fifth electrode plate 15, the second electrode of the second transistor T2, and the second electrode of the third transistor T3 forms the second node N2 of the pixel driving circuit. In an exemplary embodiment, the twenty-second connecting electrode 62 and the twenty-third connecting electrode 63 can serve as the second node electrodes in the top-emitting circuit unit of this disclosure.

[0108] In an exemplary embodiment, the fourth electrode plate 14 is connected to the second electrode of the first transistor T1 on one hand, and to the gate electrode of the second transistor T2 at least through the twenty-first connecting electrode 61 on the other hand. This achieves interconnection between the fourth electrode plate 14, the second electrode of the first transistor T1, and the gate electrode of the second transistor T2, forming the first node N1 of the pixel driving circuit. In an exemplary embodiment, the twenty-first connecting electrode 61 can serve as the first node electrode in the top-emitting circuit unit of this disclosure.

[0109] In an exemplary embodiment, a third electrode 13 having a second node potential and a fourth electrode 14 having a first node potential form a first sub-capacitor, and a fourth electrode 14 having a first node potential and a fifth electrode 15 having a second node potential form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the storage capacitor in the top-emitting circuit unit.

[0110] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on a side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on a side of the first conductive layer away from the substrate, a second conductive layer disposed on a side of the semiconductor layer away from the substrate, and a third conductive layer disposed on a side of the second conductive layer away from the substrate. A first electrode 11 may be disposed in the first transparent conductive layer, a third electrode 13 may be disposed in the first conductive layer, a second electrode 12 and a fourth electrode 14 may be disposed in the semiconductor layer, and a fifth electrode 15 may be disposed in the third conductive layer.

[0111] In an exemplary embodiment, since the first electrode 11 is disposed in a transparent first transparent conductive layer and the second electrode 12 is disposed in a transparent semiconductor layer, the storage capacitor in the bottom emitter circuit unit is a transparent storage capacitor.

[0112] In an exemplary embodiment, the scan signal line 30, the first gate line 31, and the third gate line 33 may be disposed in the second conductive layer, and the first power line 71, the second power line 72, the data signal line 73, and the compensation signal line 74 may be disposed in the third conductive layer.

[0113] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film, coating with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating with organic materials, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0114] In an exemplary embodiment, taking a repeating unit comprising six circuit units (a first bottom-emitting circuit unit Q1_B, a first top-emitting circuit unit Q1_T, a second bottom-emitting circuit unit Q2_B, a second top-emitting circuit unit Q2_T, a third bottom-emitting circuit unit Q3_B, and a third top-emitting circuit unit Q3_T) as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0115] (1) Forming a first transparent conductive layer pattern. In an exemplary embodiment, forming the first transparent conductive layer pattern includes: depositing a first transparent conductive film on a substrate, patterning the first transparent conductive film using a patterning process, and forming a first transparent conductive layer pattern on the substrate, as shown in FIG6. In an exemplary embodiment, the first transparent conductive layer may be referred to as a 1st ITO (1ITO) layer.

[0116] In an exemplary embodiment, the first transparent conductive layer pattern of each bottom emitter circuit unit in the repeating unit may include at least the first electrode 11 of the storage capacitor, and each top emitter circuit unit has no pattern.

[0117] In an exemplary embodiment, the first electrode plate 11 can be block-shaped (such as rectangular), and the corners of the block shape can be chamfered, raised or grooved, and the edges of the block shape can be broken lines. The first electrode plate 11 can serve as a transparent lower electrode plate for the storage capacitor in the bottom emitter circuit unit. The first electrode plate 11 is configured to form a storage capacitor in the bottom emitter circuit unit together with the subsequently formed second electrode plate.

[0118] In an exemplary embodiment, the material of the first transparent conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0119] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the first conductive thin film using a patterning process, and forming the first conductive layer pattern on the substrate, as shown in Figures 7A and 7B, where Figure 7B is a schematic diagram of the first conductive layer in Figure 7A. In an exemplary embodiment, the first conductive layer may be referred to as a light-shielding layer (SHL).

[0120] In an exemplary embodiment, the first conductive layer of each bottom emitter circuit unit in the repeating unit may include at least a shielding electrode 16 and a first connection electrode 41.

[0121] In an exemplary embodiment, the shielding electrode 16 may be block-shaped (e.g., rectangular), with chamfered, raised, or recessed corners. The orthographic projection of the shielding electrode 16 onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 onto the substrate, and is in contact with the first electrode plate 11. The shielding electrode 16 is configured to shield the second transistor T2 in the bottom-emitting circuit unit, reducing the light intensity illuminating the second transistor T2, reducing the leakage current of the second transistor T2, and thereby reducing the impact of illumination on the characteristics of the second transistor T2.

[0122] In an exemplary embodiment, the first connecting electrode 41 may be a strip extending along the first direction X, and may span between the display unit 110 and the light-transmitting unit 120. The first connecting electrode 41 may be disposed on one side of the shielding electrode 16 along the first direction X, with a first end of the first connecting electrode 41 connected to the shielding electrode 16, and a second end of the first connecting electrode 41 extending along the first direction X to the light-transmitting unit 120.

[0123] In an exemplary embodiment, in at least one bottom-emitting circuit unit, the shielding electrode 16 and the first connecting electrode 41 can be an integral structure that is interconnected.

[0124] In an exemplary embodiment, a first connecting block 41-1 and a first compensation connecting block 41-2 may be provided on the first connecting electrode 41.

[0125] In an exemplary embodiment, the first connecting block 41-1 may be block-shaped (such as rectangular), and may be disposed at the end of the first connecting electrode 41 away from the shielding electrode 16, located within the light-transmitting unit 120, and connected to the first connecting electrode 41. The first connecting block 41-1 is configured to be connected to the subsequently formed first anode connecting electrode.

[0126] In an exemplary embodiment, the first compensation connection block 41-2 may be block-shaped (such as rectangular), may be disposed between the shielding electrode 16 and the first connection block 41-1, and may be connected to the first connection electrode 41. The first compensation connection block 41-2 is configured to be connected to the subsequently formed thirteenth connection electrode.

[0127] In an exemplary embodiment, the first conductive layer of each top-emitting circuit unit in the repeating unit may include at least a third electrode 13, a second connecting electrode 42, and a third connecting electrode 43.

[0128] In an exemplary embodiment, the third electrode plate 13 can be block-shaped (such as rectangular), and the corners of the block shape can be chamfered, raised or grooved, and the edges of the block shape can be broken lines. The third electrode plate 13 can serve as the lower electrode plate of the storage capacitor in the top emitter circuit unit. The third electrode plate 13 is configured to form the first sub-capacitor of the storage capacitor in the top emitter circuit unit together with the subsequently formed fourth electrode plate.

[0129] In an exemplary embodiment, the third electrode plate 13 is also configured to block light from the second transistor T2 in the top-emitting circuit unit, thereby reducing the light intensity illuminating the second transistor T2, reducing the leakage current of the second transistor T2, and thus reducing the impact of light on the characteristics of the second transistor T2.

[0130] In an exemplary embodiment, the second connecting electrode 42 may be a strip extending along the first direction X, and may span between the display unit 110 and the light-transmitting unit 120. The second connecting electrode 42 may be disposed on the side of the third electrode plate 13 opposite to the first direction X, with the first end of the second connecting electrode 42 connected to the third electrode plate 13, and the second end of the second connecting electrode 42 extending to the light-transmitting unit 120 along the opposite direction of the first direction X.

[0131] In an exemplary embodiment, in at least one top-emitting circuit unit, the third electrode plate 13 and the second connecting electrode 42 can be an integral structure that is interconnected.

[0132] In an exemplary embodiment, a second connecting block 42-1 may be provided on the second connecting electrode 42. The second connecting block 42-1 may be block-shaped (such as rectangular), and may be provided at the end of the second connecting electrode 42 away from the third electrode plate 13, located within the light-transmitting unit 120, and connected to the second connecting electrode 42. The second connecting block 42-1 is configured to be connected to the second anode connecting electrode that is subsequently formed.

[0133] In an exemplary embodiment, the third connecting electrode 43 may be a strip extending along the first direction X, and may be disposed on one side of the third electrode plate 13 along the first direction X. The first end of the third connecting electrode 43 is connected to the third electrode plate 13, and the second end of the third connecting electrode 43 extends along the first direction X.

[0134] In an exemplary embodiment, in at least one top-emitting circuit unit, the third electrode 13 and the third connecting electrode 43 can be an integral structure that is interconnected.

[0135] In an exemplary embodiment, a second compensation connection block 43-1 may be provided on the third connection electrode 43. The second compensation connection block 43-1 may be block-shaped (such as rectangular), may be provided at the end of the third connection electrode 43 away from the third electrode plate 13, and may be connected to the third connection electrode 43. The second compensation connection block 43-1 is configured to be connected to the subsequently formed twenty-third connection electrode.

[0136] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in Figures 8A and 8B, where Figure 8B is a schematic diagram of the semiconductor layer in Figure 8A.

[0137] In an exemplary embodiment, the semiconductor layer of each bottom emitter circuit unit in the repeating unit may include at least a second electrode 12, a first active layer 21, a second active layer 22, and a third active layer 23.

[0138] In an exemplary embodiment, the second electrode plate 12 can be block-shaped (such as rectangular), and the corners of the block shape can be chamfered, protruded, or grooved. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as a transparent upper electrode plate for the storage capacitor in the bottom emitter circuit unit, and the first electrode plate 11 and the second electrode plate 12 form a transparent storage capacitor in the bottom emitter circuit unit.

[0139] In an exemplary embodiment, the first active layer 21, the second active layer 22, and the third active layer 23 can be strip-shaped extending along the first direction X. The first active layer 21 can serve as the active layer of the first transistor T1, the second active layer 22 can serve as the active layer of the second transistor T2, and the third active layer 23 can serve as the active layer of the third transistor T3. The active layer of each transistor can include a first region, a second region, and a channel region located between the first region and the second region.

[0140] In an exemplary embodiment, the first active layer 21 may be disposed on the side opposite to the first direction X of the second electrode plate 12. The first region of the first active layer 21 may be disposed on the side of the channel region of the first active layer 21 away from the second electrode plate 12, and the second region of the first active layer 21 may be disposed on the side of the channel region of the first active layer 21 close to the second electrode plate 12 and connected to the second electrode plate 12.

[0141] In an exemplary embodiment, the second active layer 22 may be disposed on one side of the second electrode plate 12 in the first direction X. The first region of the second active layer 22 may be disposed on the side of the channel region of the second active layer 22 away from the second electrode plate 12, and the second region of the second active layer 22 may be disposed on the side of the channel region of the second active layer 22 close to the second electrode plate 12.

[0142] In an exemplary embodiment, the orthogonal projection of the channel region and the second region of the second active layer 22 onto the substrate is within the range of the orthogonal projection of the shielding electrode 16 onto the substrate, so that the shielding electrode 16 can shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0143] In an exemplary embodiment, in at least one bottom-emitting circuit unit, the second electrode 12 and the first active layer 21 can be an integral structure that is interconnected, which not only saves space but also reduces via connection structures and simplifies the fabrication process.

[0144] In an exemplary embodiment, the third active layer 23 may be disposed on one side of the second active layer 22 in the first direction X. The first region of the third active layer 23 may be disposed on the side of the channel region of the third active layer 23 away from the second active layer 22, and the second region of the third active layer 23 may be disposed on the side of the channel region of the third active layer 23 close to the second active layer 22.

[0145] In an exemplary embodiment, the semiconductor layer of each top emitter circuit unit in the repeating unit may include at least a fourth electrode 14, a first active layer 21, a second active layer 22, and a third active layer 23.

[0146] In an exemplary embodiment, the fourth electrode plate 14 can be block-shaped (such as rectangular), and the corners of the block shape can be chamfered, protruded, or grooved. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The fourth electrode plate 14 can serve as the intermediate electrode plate of the storage capacitor in the top-emitting circuit unit. The fourth electrode plate 14 and the third electrode plate 13 form the first sub-capacitor of the storage capacitor in the top-emitting circuit unit. The fourth electrode plate 14 and the subsequently formed fifth electrode plate form the second sub-capacitor of the storage capacitor in the top-emitting circuit unit.

[0147] In an exemplary embodiment, the first active layer 21 may be disposed on the side opposite to the first direction X of the fourth electrode plate 14. The first region of the first active layer 21 may be disposed on the side of the channel region of the first active layer 21 away from the fourth electrode plate 14, and the second region of the first active layer 21 may be disposed on the side of the channel region of the first active layer 21 close to the fourth electrode plate 14 and connected to the fourth electrode plate 14.

[0148] In an exemplary embodiment, in at least one top-emitting circuit unit, the fourth electrode plate 14 and the first active layer 21 can be an integral structure that is interconnected, which not only saves space but also reduces via connection structures and simplifies the fabrication process.

[0149] In an exemplary embodiment, the second active layer 22 may be disposed on one side of the fourth electrode plate 14 in the first direction X. The first region of the second active layer 22 may be disposed on the side of the channel region of the second active layer 22 away from the fourth electrode plate 14, and the second region of the second active layer 22 may be disposed on the side of the channel region of the second active layer 22 close to the fourth electrode plate 14.

[0150] In an exemplary embodiment, the orthogonal projection of the channel region and the second region of the second active layer 22 onto the substrate is within the range of the orthogonal projection of the third electrode plate 13 onto the substrate, so that the third electrode plate 13, as a shielding electrode, can shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2.

[0151] In an exemplary embodiment, the third active layer 23 may be disposed on one side of the second active layer 22 in the first direction X. The first region of the third active layer 23 may be disposed on the side of the channel region of the third active layer 23 away from the second active layer 22, and the second region of the third active layer 23 may be disposed on the side of the channel region of the third active layer 23 close to the second active layer 22.

[0152] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0153] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process, and forming a second conductive layer pattern on a second insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. In an exemplary embodiment, the second conductive layer may be referred to as a gate metal layer (GATE).

[0154] In an exemplary embodiment, the second conductive layer in the repeating unit may include at least a scan signal line 30.

[0155] In an exemplary embodiment, the shape of the scanning signal line 30 can be a straight line or a broken line extending along the first direction X. In the first direction X, the scanning signal line 30 can be continuously arranged in multiple repeating units, that is, extending from the light-transmitting unit 120 of the repeating unit to the display unit 110 of the repeating unit, and extending from the display unit 110 of the repeating unit to the light-transmitting unit 120 of the adjacent repeating unit. In the second direction Y, the scanning signal line 30 can be arranged on the side opposite to the second direction Y of the repeating unit, that is, it can be arranged on the side of the first bottom emitting circuit unit Q1_B away from the first top emitting circuit unit Q1_T.

[0156] In an exemplary embodiment, at least one repeating unit may have a first concave structure 30A and a second concave structure 30B disposed on the scan signal line 30. The first concave structure 30A and the second concave structure 30B may be in the shape of a reclining "C", and the two ends of the "C" shape are respectively connected to the scan signal line 30. The scan signal line 30 and the first concave structure 30A form a first annular structure, and the scan signal line 30 and the second concave structure 30B form a second annular structure.

[0157] In an exemplary embodiment, in at least one repeating unit, the orthographic projections of the first and second ring structures onto the substrate at least partially overlap with the orthographic projections of the subsequently formed second power line, data signal line, and compensation signal line onto the substrate. The scan signal line structure with the first and second ring structures has repair capabilities. When a short circuit occurs in the overlapping area between the scan signal line and the second power line, data signal line, or compensation signal line, the scan signal lines 30 on both sides of the short circuit point can be cut off by laser cutting, thereby repairing the short circuit.

[0158] In an exemplary embodiment, in at least one repeating unit, the scan signal line 30, the first concave structure 30A, and the second concave structure 30B can be an integral structure that is interconnected.

[0159] In an exemplary embodiment, the second conductive layer of each circuit unit in the repeating unit (i.e., each bottom emitter circuit unit and each top emitter circuit unit, hereinafter the same) may include at least a first gate line 31, a second gate electrode 32, a third gate line 33, and a data connection line 34.

[0160] In an exemplary embodiment, the shape of the first gate line 31 can be a straight line or a broken line extending along the second direction Y. The first end of the first gate line 31 is connected to the scan signal line 30, and the second end of the first gate line 31 can extend along the second direction Y from the first bottom emitter circuit unit Q1_B to the third top emitter circuit unit Q3_T. The region of the first gate line 31 that overlaps with the first active layer in each circuit unit can serve as the gate electrode of the first transistor T1, that is, the first gate line 31 is connected to the gate electrode of the first transistor T1 in the six circuit units of the repeating unit. Therefore, the scan signal line 30 can control the conduction or disconnection of the first transistor T1 in the six circuit units of the repeating unit.

[0161] In an exemplary embodiment, the shape of the second gate electrode 32 in each bottom emitter circuit unit can be a strip shape extending along the second direction Y, and the region where the second gate electrode 32 overlaps with the second active layer in each bottom emitter circuit unit can serve as the gate electrode of the second transistor T2 in the bottom emitter circuit unit.

[0162] In an exemplary embodiment, in at least one bottom-emitting circuit unit, the orthogonal projection of the second gate electrode 32 onto the substrate may be located within the range of the orthogonal projection of the shielding electrode 16 onto the substrate.

[0163] In an exemplary embodiment, the shape of the second gate electrode 32 in each top emitter circuit unit can be an inverted "L" shape, and the area where the second gate electrode 32 overlaps with the second active layer in each top emitter circuit unit can serve as the gate electrode of the second transistor T2 in the top emitter circuit unit.

[0164] In an exemplary embodiment, in at least one top-emitting circuit unit, the orthogonal projection of the second gate electrode 32 onto the substrate may be located within the range of the orthogonal projection of the third electrode plate 13 onto the substrate.

[0165] In an exemplary embodiment, the shape of the third gate line 33 can be a straight line or a broken line extending along the second direction Y. The first end of the third gate line 33 is connected to the scan signal line 30, and the second end of the third gate line 33 can extend along the second direction Y from the first bottom emitter circuit unit Q1_B to the third top emitter circuit unit Q3_T. The region where the third gate line 33 overlaps with the third active layer in each circuit unit can serve as the gate electrode of the third transistor T3. That is, the third gate line 33 is connected to the gate electrode of the third transistor T3 in the six circuit units of the repeating unit. Therefore, the scan signal line 30 can control the conduction or disconnection of the third transistor T3 in the six circuit units of the repeating unit.

[0166] In an exemplary embodiment, in at least one circuit unit, the second gate electrode 32 may be disposed between the first gate line 31 and the third gate line 33.

[0167] In an exemplary embodiment, in at least one repeating unit, the scan signal line 30, the first gate line 31, and the third gate line 33 can be an integral structure that is interconnected.

[0168] In an exemplary embodiment, in at least one circuit unit, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30.

[0169] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of six first transistors T1 and the gate electrodes of six third transistors T3 are connected to the same scan signal line 30.

[0170] In an exemplary embodiment, the data connection line 34 may be a strip shape extending along the first direction X, and may be disposed on the side of the first gate line 31 away from the third gate line 33. The first end of the data connection line 34 is configured to be connected to a subsequently formed data signal line, and the second end of the data connection line 34 is configured to be connected to the first region of the first active layer through a subsequently formed data connection electrode.

[0171] In an exemplary embodiment, in at least one repeating unit, the shape and extension length of the data connection line 34 in the bottom transmitting circuit unit and the data connection line 34 in the top transmitting circuit unit may be different. The shape and extension length of the data connection line 34 in the three bottom transmitting circuit units may be different, and the shape and extension length of the data connection line 34 in the three top transmitting circuit units may be different, in order to accommodate the data connection line 34 connecting different data signal lines. This disclosure does not limit this.

[0172] In an exemplary embodiment, the second conductive layer in the repeating unit may further include a power auxiliary line 35.

[0173] In an exemplary embodiment, the power auxiliary line 35 may be a strip shape extending along the second direction Y, and may be disposed on the side of the data connection line 34 away from the first gate line 31. The power auxiliary line 35 is configured to connect to the subsequently formed second power line. In an exemplary embodiment, there may be multiple power auxiliary lines 35 in the repeating unit, and the multiple power auxiliary lines 35 may be spaced apart along the second direction Y.

[0174] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film by a patterning process to form a third insulating layer pattern covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG10.

[0175] In an exemplary embodiment, the plurality of vias in each circuit unit of the repeating unit may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, and a sixth via V6.

[0176] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The third and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow subsequently formed data connection electrodes to be connected to the first region of the first active layer through the via.

[0177] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the first region of the second active layer onto the substrate. The third and second insulating layers within the second via V2 are etched away, exposing the surface of the first region of the second active layer. The second via V2 is configured to allow a subsequently formed first power line to be connected to the first region of the second active layer through the via.

[0178] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the third active layer onto the substrate. The third insulating layer and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the third active layer. The third via V3 is configured to allow subsequently formed compensation signal lines to be connected to the first region of the third active layer through the via.

[0179] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the third active layer onto the substrate. The third and second insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the third active layer. The fourth via V4 is configured to allow the subsequently formed thirteenth or twenty-third connection electrode to be connected to the second region of the third active layer through the via.

[0180] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is within the range of the orthographic projection of the first end of the data connection line 34 on the substrate. The third insulating layer within the fifth via V5 is etched away, exposing the surface of the first end of the data connection line 34. The fifth via V5 is configured to allow subsequently formed data signal lines to be connected to the first end of the data connection line 34 through the via.

[0181] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the second end of the data connection line 34 onto the substrate. The third insulating layer within the sixth via V6 is etched away, exposing the surface of the second end of the data connection line 34. The sixth via V6 is configured to allow subsequently formed data connection electrodes to be connected to the second end of the data connection line 34 through the via.

[0182] In an exemplary embodiment, the plurality of vias in each bottom emitter circuit unit in the repeating unit may further include: an eleventh via V11, a twelfth via V12, a thirteenth via V13, and a fourteenth via V14.

[0183] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projections of the second electrode 12 and the second gate electrode 32 onto the substrate. The eleventh via V11 is a transition via, comprising a shallow half-hole and a deep half-hole. The third insulating layer in the shallow half-hole is etched away, exposing the surface of the second gate electrode 32. The third and second insulating layers in the deep half-hole are etched away, exposing the surface of the second electrode 12. The eleventh via V11 is configured to allow the subsequently formed eleventh connection electrode to be simultaneously connected to the second electrode 12 and the second gate electrode 32 through this via.

[0184] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the range of the orthographic projection of the shielding electrode 16 and the second region of the second active layer onto the substrate. The twelfth via V12 is a transition via, including a shallow half-hole and a deep half-hole. The third and second insulating layers in the shallow half-hole are etched away, exposing the surface of the second region of the second active layer. The third, second, and first insulating layers in the deep half-hole are etched away, exposing the surface of the shielding electrode 16. The twelfth via V12 is configured to allow a subsequently formed twelfth connection electrode to simultaneously connect to the shielding electrode 16 and the second region of the second active layer through this via.

[0185] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate is within the range of the orthographic projection of the first connecting block 41-1 on the first connecting electrode 41 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the thirteenth via V13 are etched away, exposing the surface of the first connecting block 41-1. The thirteenth via V13 is configured to allow the subsequently formed first anode connecting electrode to be connected to the first connecting block 41-1 through the via.

[0186] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate is within the range of the orthographic projection of the first compensation connection block 41-2 on the first connection electrode 41 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the fourteenth via V14 are etched away, exposing the surface of the first compensation connection block 41-2. The fourteenth via V14 is configured to allow the subsequently formed thirteenth connection electrode to be connected to the first compensation connection block 41-2 through the via.

[0187] In an exemplary embodiment, the plurality of vias in each top-emitting circuit unit in the repeating unit may further include: a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26.

[0188] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the second region of the second active layer onto the substrate. The third and second insulating layers within the 21st via V21 are etched away, exposing the surface of the second region of the second active layer. The 21st via V21 is configured to allow the subsequently formed 22nd connection electrode to be connected to the second region of the second active layer through the via.

[0189] In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the substrate is within the range of the orthographic projection of the third electrode plate 13 on the substrate. The third insulating layer, the second insulating layer and the first insulating layer in the 22nd via V22 are etched away to expose the surface of the third electrode plate 13. The 22nd via V22 is configured to allow the subsequently formed fifth electrode plate to be connected to the third electrode plate 13 through the via.

[0190] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the fourth electrode plate 14 on the substrate. The third and second insulating layers within the 23rd via V23 are etched away, exposing the surface of the fourth electrode plate 14. The 23rd via V23 is configured to allow the subsequently formed 21st connection electrode to be connected to the fourth electrode plate 14 through the via.

[0191] In an exemplary embodiment, the orthographic projection of the 24th via V24 on the substrate is within the range of the orthographic projection of the second gate electrode 32 on the substrate. The third insulating layer within the 24th via V24 is etched away, exposing the surface of the second gate electrode 32. The 24th via V24 is configured to allow the subsequently formed 21st connection electrode to be connected to the second gate electrode 32 through the via.

[0192] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate is within the range of the orthographic projection of the second compensation connection block 43-1 on the substrate onto the third connection electrode 43. The third insulating layer, the second insulating layer, and the first insulating layer within the 25th via V25 are etched away, exposing the surface of the second compensation connection block 43-1. The 25th via V25 is configured to allow the subsequently formed 23rd connection electrode to be connected to the second compensation connection block 43-1 through the via.

[0193] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate is within the range of the orthographic projection of the second connecting block 42-1 on the substrate onto the second connecting electrode 42. The third insulating layer, the second insulating layer, and the first insulating layer within the 26th via V26 are etched away, exposing the surface of the second connecting block 42-1. The 26th via V26 is configured to allow the subsequently formed second anode connecting electrode to be connected to the second connecting block 42-1 through the via.

[0194] In an exemplary embodiment, the repeating unit may further include a plurality of thirtieth vias V30. The orthographic projection of the thirtieth via V30 onto the substrate lies within the range of the orthographic projection of the power auxiliary line 35 onto the substrate. The third insulating layer within the thirtieth via V30 is etched away, exposing the surface of the power auxiliary line 35. The thirtieth via V30 is configured to allow a subsequently formed second power line to connect to the power auxiliary line 35 through the via. In an exemplary embodiment, there may be a plurality of thirtieth vias V30, which may be sequentially arranged along the second direction Y to increase connection reliability.

[0195] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the third conductive thin film using a patterning process, and forming a third conductive layer pattern on a third insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. In an exemplary embodiment, the third conductive layer may be referred to as a source / drain metal layer (SD).

[0196] In an exemplary embodiment, the third conductive layer in the repeating unit may include at least one first power line 71, one second power line 72, six data signal lines 73, and one compensation signal line 74.

[0197] In an exemplary embodiment, the shapes of the first power line 71, the second power line 72, the data signal line 73, and the compensation signal line 74 can be straight lines or broken lines extending along the second direction Y of the main body. The second power line 72 can be located on the side of the first gate line 31 away from the third gate line 33, and the compensation signal line 74 can be located on the side of the third gate line 33 away from the first gate line 31. The first power line 71 and the six data signal lines 73 can be located between the second power line 72 and the compensation signal line 74, and the six data signal lines 73 can be located between the first gate line 31 and the second power line 72. The first power line 71 can be located between the first gate line 31 and the third gate line 33.

[0198] In an exemplary embodiment, the first power line 71 can be connected to the first region of the second active layer of each circuit unit through the second via V2 of each circuit unit, thereby enabling a first power line 71 to write the first power signal into the first pole of the second transistor T2 of the six circuit units in the repeating unit.

[0199] In an exemplary embodiment, the first power line 71 disposed between the first gate line 31 and the third gate line 33 can effectively shield the mutual influence between the first gate line 31 and the third gate line 33, ensuring the stability of the pixel driving circuit.

[0200] In an exemplary embodiment, the one-to-six structure of the first power line in a repeating unit can effectively save the number of signal lines, reduce the space occupied, and has a simple structure and reasonable layout. It makes full use of the layout space, improves the space utilization rate, and is conducive to improving resolution and transparency.

[0201] In an exemplary embodiment, the second power line 72 can be disposed on the side of the data connection line 34 away from the first gate line 31. The orthographic projection of the second power line 72 on the substrate at least partially overlaps with the orthographic projection of the plurality of power auxiliary lines 35 on the substrate. The second power line 72 can be connected to the plurality of power auxiliary lines 35 through the plurality of thirtieth vias V30. The power auxiliary lines 35 and the second power line 72 form a double-layer trace structure, which can not only ensure the reliability of power signal transmission, but also effectively reduce the resistance of the second power line, effectively reduce the voltage drop of the second power signal, and improve the display effect.

[0202] In an exemplary embodiment, the compensation signal line 74 can be disposed on the side of the third gate line 33 away from the first gate line 31. The compensation signal line 74 can be connected to the first region of the third active layer of each circuit unit through the third via V3 of each circuit unit, thus realizing that one compensation signal line 74 can write the compensation signal into the first pole of the third transistor T3 of the six circuit units in the repeating unit.

[0203] In an exemplary embodiment, the one-to-six structure of compensation signal lines in a repeating unit can effectively save the number of signal lines, reduce the space occupied, and has a simple structure and reasonable layout. It makes full use of the layout space, improves the space utilization rate, and is conducive to improving resolution and transparency.

[0204] In an exemplary embodiment, the compensation signal line 74 is directly connected to the first region of the third active layer of each circuit unit through a via, which can ensure that the RC delay of the compensation signal written to the third transistor T3 is substantially the same, thus guaranteeing display uniformity.

[0205] In an exemplary embodiment, six data signal lines 73 may be disposed between the first gate line 31 and the second power supply line 72. The six data signal lines 73 may include a first data signal line 73-1, a second data signal line 73-2, a third data signal line 73-3, a fourth data signal line 73-4, a fifth data signal line 73-5, and a sixth data signal line 73-6 arranged sequentially along a first direction X. The first data signal line 73-1 may be located on one side of the second power supply line 72 along the first direction X and can be connected to the first end of the data connection line 34 in the first bottom-emitting circuit unit Q1_B through a fifth via V5. The second data signal line 73-2 may be located on one side of the first data signal line 73-1 along the first direction X and can be connected to the first end of the data connection line 34 in the second bottom-emitting circuit unit Q2_B through a fifth via V5. The third data signal line 73-3 can be located on one side of the second data signal line 73-2 in the first direction X, and can be connected to the first end of the data connection line 34 in the second top transmitting circuit unit Q2_T through the fifth via V5. The fourth data signal line 73-4 can be located on one side of the third data signal line 73-3 in the first direction X, and can be connected to the first end of the data connection line 34 in the first top transmitting circuit unit Q1_T through the fifth via V5. The fifth data signal line 73-5 can be located on one side of the fourth data signal line 73-4 in the first direction X, and can be connected to the first end of the data connection line 34 in the third bottom transmitting circuit unit Q3_B through the fifth via V5. The sixth data signal line 73-6 can be located on one side of the fifth data signal line 73-5 in the first direction X, and can be connected to the first end of the data connection line 34 in the third top transmitting circuit unit Q3_T through the fifth via V5.

[0206] In an exemplary embodiment, the first power line 71, the second power line 72, the data signal line 73, and the compensation signal line 74 can be straight lines or polygonal lines of varying widths. Using straight lines or polygonal lines of varying widths not only facilitates the layout of pixel structures but also reduces parasitic capacitance.

[0207] In an exemplary embodiment, the third conductive layer of each circuit unit in the repeating unit may include at least a data connection electrode 50.

[0208] In an exemplary embodiment, the data connection electrode 50 can be a strip extending along the second direction Y, and can be disposed between the first gate line 31 and the sixth data signal line 73-6. The first end of the data connection electrode 50 is connected through the first region of the first active layer of the first via V1, and the second end of the data connection electrode 50 is connected to the second end of the data connection line 34 through the sixth via V6. Since the first end of the data connection line 34 is connected to a data signal line 73, a data signal line 73 is used to write a data signal into the first terminal of the first transistor T1 in a circuit unit.

[0209] In an exemplary embodiment, the third conductive layer of each bottom-emitting circuit unit in the repeating unit may include at least an eleventh connecting electrode 51, a twelfth connecting electrode 52, a thirteenth connecting electrode 53, and a first anode connecting electrode 54.

[0210] In an exemplary embodiment, the eleventh connecting electrode 51 can be block-shaped (e.g., rectangular). The eleventh connecting electrode 51 can be connected to the second electrode plate 12 and the second gate electrode 32 simultaneously through the eleventh via V11. Since the second electrode plate 12 is connected to the second region of the first active layer, the eleventh connecting electrode 51 realizes the interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 12, forming the first node N1 of the pixel driving circuit in the bottom emitter circuit unit. The eleventh connecting electrode 51 and the second electrode plate 12 in the bottom emitter circuit unit have a first node potential. The eleventh connecting electrode 51 can serve as the first node electrode in the bottom emitter circuit unit of this disclosure.

[0211] In an exemplary embodiment, the twelfth connecting electrode 52 may be block-shaped (e.g., rectangular), and the twelfth connecting electrode 52 may be connected to the shielding electrode 16 and the second region of the second active layer simultaneously through the twelfth via V12.

[0212] In an exemplary embodiment, the thirteenth connecting electrode 53 can be a strip shape extending along the second direction Y. The first end of the thirteenth connecting electrode 53 can be connected to the second region of the third active layer through the fourth via V4, and the second end of the thirteenth connecting electrode 53 can be connected to the first compensation connecting block 41-2 through the fourteenth via V14.

[0213] In an exemplary embodiment, since the first compensation connection block 41-2 is connected to the first connection electrode 41, and the first connection electrode 41 is connected to the shielding electrode 16, the shielding electrode 16 is connected to the second region of the second active layer through the twelfth connection electrode 52 on the one hand, and overlaps with the first electrode plate 11 on the other hand. Therefore, the twelfth connection electrode 52 and the thirteenth connection electrode 53 realize the interconnection between the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode plate 11, forming the second node N2 of the pixel driving circuit in the bottom emission circuit unit. The twelfth connection electrode 52, the thirteenth connection electrode 53 and the first electrode plate 11 in the bottom emission circuit unit have the second node potential. The twelfth connection electrode 52 and the thirteenth connection electrode 53 can be used as the second node electrode in the bottom emission circuit unit of this disclosure.

[0214] In an exemplary embodiment, in the bottom-emitting circuit unit, a first electrode 11 located in the first transparent conductive layer and having a second node potential, and a second electrode 12 located in the semiconductor layer and having a first node potential, constitute a transparent storage capacitor in the bottom-emitting circuit unit.

[0215] In an exemplary embodiment, the first anode connection electrode 54 can be block-shaped (e.g., rectangular), and can be connected to the first connection block 41-1 via the thirteenth via V13. Since the first connection block 41-1 is connected to the first connection electrode 41, and the first connection electrode 41 is connected to the first electrode plate 11 via the shielding electrode 16, and the first electrode plate 11 has a second node potential, the first anode connection electrode 54 in the bottom emitter circuit unit also has a second node potential.

[0216] In an exemplary embodiment, the third conductive layer of each top-emitting circuit unit in the repeating unit may include at least a fifth electrode plate 15, a twenty-first connecting electrode 61, a twenty-second connecting electrode 62, a twenty-third connecting electrode 63, and a second anode connecting electrode 64.

[0217] In an exemplary embodiment, the fifth electrode plate 15 can be block-shaped (such as rectangular), and the corners of the block shape can be chamfered, protruded, or grooved. The edge of the block shape can be a broken line. The orthographic projection of the fifth electrode plate 15 on the substrate and the orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlap. The fifth electrode plate 15 can serve as the upper electrode plate of the storage capacitor in the top emitter circuit unit. The fifth electrode plate 15 and the fourth electrode plate 14 form the second sub-capacitor of the storage capacitor in the top emitter circuit unit.

[0218] In an exemplary embodiment, the fifth electrode plate 15 can be connected to the third electrode plate 13 through the twenty-second via V22, thereby enabling the third electrode plate 13 and the fifth electrode plate 15 to have the same potential.

[0219] In an exemplary embodiment, the twenty-first connecting electrode 61 can be a strip shape extending along the second direction Y. The first end of the twenty-first connecting electrode 61 can be connected to the fourth electrode plate 14 through the twenty-third via V23, and the second end of the twenty-first connecting electrode 61 can be connected to the second gate electrode 32 through the twenty-fourth via V24. Since the fourth electrode plate 14 is connected to the second region of the first active layer, the twenty-first connecting electrode 61 realizes the interconnection between the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the fourth electrode plate 14, forming the first node N1 of the pixel driving circuit in the top emission circuit unit. The twenty-first connecting electrode 61 and the fourth electrode plate 14 in the top emission circuit unit have a first node potential, and the twenty-first connecting electrode 61 can serve as the first node electrode in the top emission circuit unit of this disclosure.

[0220] In an exemplary embodiment, the shape of the second-second connecting electrode 62 can be a strip shape extending along the second direction Y, and the second-second connecting electrode 62 can be connected to the second region of the second active layer through the second-first via V21.

[0221] In an exemplary embodiment, in at least one top-emitting circuit unit, the fifth electrode plate 15 and the twenty-second connecting electrode 62 can be an integral structure that is interconnected.

[0222] In an exemplary embodiment, the shape of the twenty-third connecting electrode 63 can be a strip shape extending along the second direction Y. The first end of the twenty-third connecting electrode 63 can be connected to the second region of the third active layer through the fourth via V4, and the second end of the twenty-third connecting electrode 63 can be connected to the second compensation connecting block 43-1 through the twenty-fifth via V25.

[0223] In an exemplary embodiment, since the second compensation connection block 43-1 is connected to the third connection electrode 43, the third connection electrode 43 is connected to the third electrode plate 13, the third electrode plate 13 is connected to the fifth electrode plate 15 through a via, the fifth electrode plate 15 is connected to the twenty-second connection electrode 62, and the twenty-second connection electrode 62 is connected to the second region of the second active layer through a via, the twenty-second connection electrode 62 and the twenty-third connection electrode 63 realize the interconnection between the second electrode of the second transistor T2, the second electrode of the third transistor T3, the third electrode plate 13 and the fifth electrode plate 15, forming the second node N2 of the pixel driving circuit in the top emission circuit unit. The twenty-second connection electrode 62, the twenty-third connection electrode 63, the third electrode plate 13 and the fifth electrode plate 15 in the top emission circuit unit have a second node potential. The twenty-second connection electrode 62 and the twenty-third connection electrode 63 can be used as the second node electrode in the top emission circuit unit of this disclosure.

[0224] In an exemplary embodiment, in the top-emitting circuit unit, the third electrode 13 located in the first conductive layer and having a second node potential and the fourth electrode 14 located in the semiconductor layer and having a first node potential constitute the first sub-capacitor of the storage capacitor in the top-emitting circuit unit, and the fourth electrode 14 located in the semiconductor layer and having a first node potential and the fifth electrode 15 located in the third conductive layer and having a second node potential constitute the second sub-capacitor of the storage capacitor in the top-emitting circuit unit. The first sub-capacitor and the second sub-capacitor connected in parallel constitute the storage capacitor of the pixel driving circuit in the top-emitting circuit unit.

[0225] In an exemplary embodiment, the second anode connection electrode 64 can be block-shaped (e.g., rectangular), and can be connected to the second connection block 42-1 via the second sixteenth via V26. Since the second connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the third electrode plate 13, which has a second node potential, the second anode connection electrode 64 in the top-emitting circuit unit also has a second node potential.

[0226] In an exemplary embodiment, the first anode connecting electrode 54 and the second anode connecting electrode 64 can be disposed in the light-transmitting unit 120 to change the light-transmitting area into an irregular shape. When light passes through the irregularly shaped light-transmitting area, the diffraction fringes are generated at different positions and in different directions. Therefore, the light will not diffuse in one direction but in multiple directions, thus greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0227] In an exemplary embodiment, the third conductive layer in the repeating unit may further include at least one first auxiliary electrode 75 and at least one auxiliary connecting strip 75-1.

[0228] In an exemplary embodiment, the first auxiliary electrode 75 may be block-shaped (e.g., rectangular) and may be disposed in the light-transmitting unit 120 near the second power line 72. The first auxiliary electrode 75 is configured to connect with the subsequently formed second auxiliary electrode. The auxiliary connecting strip 75-1 may be strip-shaped extending along the first direction X and may be disposed between the second power line 72 and the first auxiliary electrode 75. The first end of the auxiliary connecting strip 75-1 is connected to the second power line 72, and the second end of the auxiliary connecting strip 75-1 is connected to the first auxiliary electrode 75.

[0229] In an exemplary embodiment, in at least one repeating unit, the second power line 72, at least one first auxiliary electrode 75, and at least one auxiliary connecting strip 75-1 can be an integral structure that is interconnected.

[0230] In an exemplary embodiment, the first auxiliary electrode 75 is disposed in the light-transmitting unit 120, which can change the light-transmitting area into an irregular shape. When light passes through the irregularly shaped light-transmitting area, the direction of the diffraction fringes is different due to the different positions of the diffraction fringes. Therefore, the light will not spread in one direction, but in multiple directions, thus greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0231] (7) Forming a planarization layer and a fourth insulating layer pattern. In an exemplary embodiment, forming a planarization layer and a fourth insulating layer pattern may include: first coating a planarization film on a substrate on which the aforementioned pattern is formed, then patterning the planarization film using a patterning process, then depositing a fourth insulating film, and then patterning the fourth insulating film using a patterning process to form a planarization layer covering a third conductive layer and a fourth insulating layer pattern disposed on the planarization layer. The planarization layer has planar openings, and the fourth insulating layer has a plurality of vias, as shown in FIG12.

[0232] In an exemplary embodiment, the planarization layer covers both the display unit 110 and the area where the scan signal line 30 is located in the light-transmitting unit 120. The planar opening TV1 provided on the planarization layer can be located outside the area of ​​the scan signal line 30 in the light-transmitting unit 120. The planar film inside the planar opening TV1 is removed, exposing the third conductive layer.

[0233] In an exemplary embodiment, the flat opening TV can be rectangular in shape, and the corners of the rectangle can be provided with grooves or chamfers. The first anode connecting electrode 54, the second anode connecting electrode 64 and the first auxiliary electrode 75 in the light-transmitting unit 120 can all be located within the flat opening TV, that is, the flat film above the first anode connecting electrode 54, the second anode connecting electrode 64 and the first auxiliary electrode 75 is removed.

[0234] In an exemplary embodiment, the plurality of vias of at least one repeating unit may include at least three thirty-first vias V31, three thirty-second vias V32, and at least one thirty-third via V33.

[0235] In an exemplary embodiment, the 31st via V31 may be disposed in the light-transmitting unit 120. The orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the first anode connection electrode 54 on the substrate. The fourth insulating layer in the 31st via V31 is etched away, exposing the surface of the first anode connection electrode 54. The 31st via V31 is configured to allow the first anode in the subsequently formed bottom-emitting circuit unit to be connected to the first anode connection electrode 54 through the via.

[0236] In an exemplary embodiment, the 32nd via V32 may be disposed in the light-transmitting unit 120. The orthogonal projection of the 32nd via V32 on the substrate is within the range of the orthogonal projection of the second anode connection electrode 64 on the substrate. The fourth insulating layer in the 32nd via V32 is etched away, exposing the surface of the second anode connection electrode 64. The 32nd via V32 is configured to allow the second anode in the subsequently formed top-emitting circuit unit to be connected to the second anode connection electrode 64 through the via.

[0237] In an exemplary embodiment, the 33rd via V33 can be disposed in the light-transmitting unit 120. The orthogonal projection of the 33rd via V33 on the substrate is within the range of the orthogonal projection of the first auxiliary electrode 75 on the substrate. The fourth insulating layer in the 33rd via V33 is etched away, exposing the surface of the first auxiliary electrode 75. The 33rd via V33 is configured to allow the subsequently formed second auxiliary electrode to be connected to the first auxiliary electrode 75 through the via.

[0238] In an exemplary embodiment, the orthographic projections of the thirty-first via V31, the thirty-second via V32, and the thirty-third via V33 on the substrate can all be located within the range of the orthographic projection of the flat opening TV on the substrate.

[0239] (8) Forming a second transparent conductive layer pattern. In an exemplary embodiment, forming a second transparent conductive layer pattern may include: depositing a second transparent conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second transparent conductive film by a patterning process to form a second transparent conductive layer pattern, as shown in Figures 13A and 13B, where Figure 13B is a schematic diagram of the second transparent conductive layer in Figure 13A.

[0240] In an exemplary embodiment, the second transparent conductive layer of the repeating unit may include at least three first anodes 81, which may serve as anodes in the bottom-emitting light-emitting unit.

[0241] In an exemplary embodiment, at least one first anode 81 may include at least a main body portion 81-1 and a connecting portion 81-2. The main body portion 81-1 may be block-shaped (e.g., rectangular) and may be disposed on a planar layer of the display unit 110. The connecting portion 81-2 may be strip-shaped extending along a first direction X and may be disposed on one side of the main body portion 81-1 in the first direction X. The first end of the connecting portion 81-2 is connected to the main body portion 81-1, and the second end of the connecting portion 81-2 extends to the light-transmitting unit 120 and is connected to the first anode connecting electrode 54 through a thirty-first via V31. Since the first anode connecting electrode 54 has a second node potential, the connection between the first anode 81 and the second node N2 of the pixel driving circuit in the bottom emission circuit unit is realized.

[0242] In an exemplary embodiment, in at least one bottom-emitting light-emitting unit, the main body 81-1 and the connecting part 81-2 can be an integral structure that is interconnected.

[0243] In an exemplary embodiment, the second transparent conductive layer of the repeating unit may further include three second anodes 82, which may serve as one anode in the top-emitting light-emitting unit.

[0244] In an exemplary embodiment, at least one second anode 82 may include at least a first sub-anode 82-1, a second sub-anode 82-2, and a sub-connection electrode 82-3. The first sub-anode 82-1 and the second sub-anode 82-2 may be block-shaped (e.g., rectangular) and may be disposed on a flat layer of the display unit 110. The first sub-anode 82-1 and the second sub-anode 82-2 may be arranged sequentially along the second direction Y, and the first sub-anode 82-1 and the second sub-anode 82-2 are isolated from each other.

[0245] In an exemplary embodiment, the main body of the sub-connecting electrode 82-3 can be disposed on the fourth insulating layer of the light-transmitting unit 120. The sub-connecting electrode 71-3 can be in the shape of an "F", with the end of the first horizontal strip connected to the first sub-anode 82-1, the end of the second horizontal strip connected to the second sub-anode 82-2, and the end of the vertical strip furthest from the horizontal strip connected to the second anode connecting electrode 64 through the thirty-second via V32. Since the second anode connecting electrode 64 has a second node potential, the connection between the second anode 82 and the second node N2 of the pixel driving circuit in the top emission circuit unit is realized.

[0246] In an exemplary embodiment, in at least one top-emitting light-emitting unit, the first sub-anode 82-1, the second sub-anode 82-2, and the sub-connecting electrode 82-3 can be an integral structure that is interconnected.

[0247] In an exemplary embodiment, when a bright spot defect occurs on the display substrate, the first or second horizontal strip can be cut off by laser cutting, so that one of the first sub-anode 82-1 and the second sub-anode 82-2 is connected to the second node N2, while the other is floating, thereby repairing the bright spot defect.

[0248] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate does not overlap with the orthographic projection of the main body 81-1 of the first anode 81 on the substrate, and the orthographic projection of the thirty-second via V32 on the substrate does not overlap with the orthographic projections of the first sub-anode 82-1 and the second sub-anode 82-2 of the second anode 82 on the substrate. This not only improves the success rate of repairing defective bright spots and avoids the impact of repair on the pixel driving circuit, but also ensures the flatness of the first anode and the second anode, improves the light output quality of the light-emitting device, and enhances the display effect.

[0249] In an exemplary embodiment, three first anodes 81 in a repeating unit can be arranged vertically. The first first anode 81 is connected to the pixel driving circuit in the first bottom emitting circuit unit Q1_B, the second first anode 81 is connected to the pixel driving circuit in the second bottom emitting circuit unit Q2_B, and the third first anode 81 is connected to the pixel driving circuit in the third bottom emitting circuit unit Q3_B. The three first anodes 81 can be arranged sequentially along the second direction Y to form a first light-emitting unit group.

[0250] In an exemplary embodiment, three second anodes 82 in a repeating unit can be arranged vertically. The first second anode 82 is connected to the pixel driving circuit in the first top emitting circuit unit Q1_T, the second second anode 82 is connected to the pixel driving circuit in the second top emitting circuit unit Q2_T, and the third second anode 82 is connected to the pixel driving circuit in the third top emitting circuit unit Q3_T. The three second anodes 82 can be arranged sequentially along the second direction Y to form a second light-emitting unit group.

[0251] In an exemplary embodiment, the three first anodes 81 in a repeating unit can be disposed on one side of the three second anodes 82 in the first direction X, that is, the first light-emitting unit group is disposed on one side of the second light-emitting unit group in the first direction X. In some possible implementations, the arrangement of the first anodes and the second anodes can be adjusted according to actual needs, and this disclosure does not limit it.

[0252] In the exemplary embodiment, since the bottom-emitting process essentially eliminates dark spot issues, and to maximize the aperture ratio of the bottom-emitting circuit unit, the first anode is a monolithic structure without any maintenance structure. Because the top-emitting process is prone to dark spot defects, the second anode is equipped with a maintenance structure, dividing it into two sub-anodes of a separate structure, allowing for dark spot repair to improve product yield. The scheme proposed in this disclosure, which eliminates the maintenance structure for the bottom-emitting light-emitting unit and includes a maintenance structure for the top-emitting light-emitting unit, fully considers process capability and aperture ratio, achieving optimized product yield and maximized aperture ratio.

[0253] In an exemplary embodiment, the second transparent conductive layer of at least one repeating unit may further include at least one second auxiliary electrode 76. The shape of the second auxiliary electrode 76 may be block-shaped (e.g., rectangular), and the orthographic projection of the second auxiliary electrode 76 on the substrate at least partially overlaps with the orthographic projection of the first auxiliary electrode 75 on the substrate. The second auxiliary electrode 76 may be connected to the first auxiliary electrode 75 through a thirty-third via V33, and the second auxiliary electrode 76 is configured to be connected to a subsequently formed third auxiliary electrode.

[0254] In an exemplary embodiment, the material of the second transparent conductive layer can be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0255] (9) Forming a reflective conductive layer pattern. In an exemplary embodiment, forming a reflective conductive layer pattern may include: depositing a reflective conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the reflective conductive thin film by a patterning process to form a reflective conductive layer pattern, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the reflective conductive layer in Figure 14A.

[0256] In an exemplary embodiment, the reflective conductive layer in the repeating unit may include three third anodes 83.

[0257] In an exemplary embodiment, at least one third anode 83 may include a first reflective electrode 83-1 and a second reflective electrode 83-2 arranged sequentially along the second direction Y. The first reflective electrode 83-1 and the second reflective electrode 83-2 may be block-shaped (such as rectangular). The first reflective electrode 83-1 and the second reflective electrode 83-2 may be arranged sequentially along the second direction Y, and the first reflective electrode 83-1 and the second reflective electrode 83-2 are isolated from each other.

[0258] In an exemplary embodiment, the orthographic projection of the first reflective electrode 83-1 onto the substrate at least partially overlaps with the orthographic projection of the first sub-anode 82-1 onto the substrate, and the first reflective electrode 83-1 and the first sub-anode 82-1 are directly connected. The orthographic projection of the second reflective electrode 83-2 onto the substrate at least partially overlaps with the orthographic projection of the second sub-anode 82-2 onto the substrate, and the second reflective electrode 83-2 and the second sub-anode 82-2 are directly connected.

[0259] In an exemplary embodiment, the reflective conductive layer of at least one repeating unit may further include a third auxiliary electrode 77. The third auxiliary electrode 77 may be block-shaped (e.g., rectangular), and the orthographic projection of the third auxiliary electrode 77 on the substrate at least partially overlaps with the orthographic projection of the second auxiliary electrode 76 on the substrate, and the third auxiliary electrode 77 and the second auxiliary electrode 76 are directly connected.

[0260] In an exemplary embodiment, the stacked first auxiliary electrode 75, second auxiliary electrode 76 and third auxiliary electrode 77 can constitute an auxiliary cathode.

[0261] In an exemplary embodiment, the third auxiliary electrode 77 is configured to connect to the subsequently formed cathode, thereby connecting the second power line 72 to the cathode. Considering the voltage drop (IR Drop) problem present in large-size transparent displays, this disclosure effectively reduces the cathode voltage drop by providing a second power line for transmitting a second voltage signal in each repeating unit. This second power line connects to the cathode in the subsequently formed light-emitting structure layer via the auxiliary cathode, effectively solving the voltage drop problem in large-size transparent displays and ensuring display uniformity.

[0262] In an exemplary embodiment, the auxiliary cathode can adopt an isolation pillar (RIB) structure. The cross-sectional shape of the auxiliary cathode can be an inverted trapezoid or an "I" shape, so that the organic light-emitting layer formed subsequently can be broken at the side edge of the auxiliary cathode to form an isolated and isolated organic light-emitting block. This can effectively avoid the interference of the organic light-emitting block on the emitted light, improve the quality of the emitted light, and help improve the display quality.

[0263] (10) Sequentially forming a pixel definition layer, an organic light-emitting layer, and a cathode pattern. In an exemplary embodiment, sequentially forming a pixel definition layer, an organic light-emitting layer, and a cathode pattern may include:

[0264] First, a pixel definition layer 94 is formed. At least a first pixel opening K1 and a second pixel opening K2 are provided on the pixel definition layer 94. The first pixel opening K1 exposes the surface of the first anode 81, and the second pixel opening K2 exposes the surface of the third anode 83. Then, an organic light-emitting layer 95 is formed in the display unit 110. The organic light-emitting layer 95 is connected to the first anode 81 and the third anode 83 through the first pixel opening K1 and the second pixel opening K2, respectively. Subsequently, a first cathode 91 and a second cathode 92, which are isolated from each other, are formed sequentially through two patterning processes. The first cathode 91 and the second cathode 92 are connected to the organic light-emitting layer, as shown in Figure 15.

[0265] In an exemplary embodiment, the emitted light from the first type of light-emitting unit is emitted from the bottom, and the emitted light from the second type of light-emitting unit is emitted from the top. The first cathode 91 disposed in the first type of light-emitting unit can be made of a reflective material to achieve bottom-side light emission, and the second cathode 92 disposed in the second type of light-emitting unit can be made of a transparent material to achieve top-side light emission.

[0266] In an exemplary embodiment, the pixel definition layer 91 may also be provided with a light-transmitting opening, which may be provided in the light-transmitting unit 120, and the cathode formed by the light-transmitting unit 120 may be connected to the third auxiliary electrode.

[0267] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0268] As shown in Figure 15, when the emitted light from the organic light-emitting layer is white light, the fabrication process of the display substrate may further include forming a color filter layer 96 and a black matrix 97. In an exemplary embodiment, the color filter layer 96 of the bottom-emitting light-emitting unit can be disposed between the third conductive layer and the planarization layer, forming a CF On Array structure. The emitted light from the bottom-emitting light-emitting unit achieves full-color display through the color filter structure of the CF On Array structure. The color filter layer 96 of the top-emitting light-emitting unit can be disposed on the cover plate 98, forming a CF On Cover Glass structure. The emitted light from the top-emitting light-emitting unit achieves full-color display through the color filter structure of the CF On Cover Glass structure.

[0269] In some possible implementations, the position of the color filter layer can be adjusted according to actual needs. For example, the color filter layers of both the bottom-emitting and top-emitting units can adopt a CF On Array structure. Alternatively, the color filter layer of the bottom-emitting unit can be disposed on the substrate, and the color filter layer of the top-emitting unit can be disposed on the cover plate; this disclosure does not impose any limitations on these aspects.

[0270] In an exemplary embodiment, the fabrication process of the display substrate may further include forming an encapsulation structure layer pattern. Forming the encapsulation structure layer pattern may include: firstly, depositing a first inorganic thin film using an open mask to form a first encapsulation layer; subsequently, using an inkjet printing process to inkjet print an organic material onto the first encapsulation layer, and after curing, forming a second encapsulation layer; subsequently, depositing a second inorganic thin film using an open mask to form a third encapsulation layer, wherein the first, second, and third encapsulation layers constitute the encapsulation structure layer. The first and third encapsulation layers may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The second encapsulation layer may be made of a resin material, forming an inorganic / organic / inorganic material stacked structure. The organic material layer is disposed between the two inorganic material layers to ensure that external moisture cannot enter the light-emitting structure layer. This completes the fabrication of the display substrate according to the exemplary embodiment of this disclosure.

[0271] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0272] In an exemplary embodiment, the first, second, and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The planarization layer can be made of organic materials, such as resin.

[0273] An exemplary embodiment of this disclosure provides an OLED transparent display device. By organically combining the top-emitting structure and the bottom-emitting structure in a repeating unit, not only can double-sided transparent display be achieved, but also the interaction between the two light-emitting surfaces can be ensured without obstruction, providing technical support for double-sided transparent OLED display.

[0274] The embodiments disclosed herein provide a simple and reasonable structure by arranging a first transistor, a second transistor, and a third transistor sequentially along a first direction in a circuit unit, and arranging multiple pixel driving circuits sequentially along a second direction in a repeating unit. This makes full use of the layout space, ensuring unobstructed interaction between the two light-emitting surfaces and improving space utilization, which is beneficial for improving resolution and product yield.

[0275] This embodiment of the present disclosure improves the aperture ratio of the bottom emitter circuit unit by setting a first electrode plate in a first transparent conductive layer and a second electrode plate in a semiconductor layer, with the first and second electrode plates forming a transparent storage capacitor. This embodiment also improves the storage capacitance of the top emitter circuit unit by setting a third electrode plate in the first conductive layer, a fourth electrode plate in the semiconductor layer, and a fifth electrode plate in the third conductive layer, with the third and fourth electrode plates forming a first sub-capacitor and the fourth and fifth electrode plates forming a second sub-capacitor. The parallel connection of the first and second sub-capacitors forms the storage capacitor of the top emitter circuit unit. This effectively increases the capacitance value of the storage capacitor while reducing the electrode area to maintain the capacitance value, thus reducing the area occupied by the pixel driving circuit and facilitating high-resolution display.

[0276] This disclosure embodiment, by employing a scheme where the bottom-emitting light-emitting unit lacks a maintenance structure while the top-emitting light-emitting unit does, fully considers process capabilities and aperture ratio, achieving optimal product yield and maximizing aperture ratio. The top-emitting light-emitting unit's maintenance structure not only improves the success rate of repairing bright spots and avoids impacting the pixel driving circuitry during repair, preventing other defects and ensuring a high repair success rate, but also guarantees the flatness of the anode, improving the light emission quality of the light-emitting device and enhancing the display effect.

[0277] The exemplary embodiments disclosed herein provide a ring structure on the scanning signal line, enabling the scanning signal line to have repair capabilities, thereby achieving the repair of short-circuit defects and improving product yield.

[0278] This disclosure exemplarily saves the number of signal lines, reduces the space occupied, and improves space utilization by setting a one-to-six structure for the first power line and a one-to-six structure for the compensation signal line, which is beneficial to improving resolution.

[0279] The exemplary embodiments of this disclosure, by providing a second power line and an auxiliary cathode, with the second power line connected to the cathode via the auxiliary cathode, can effectively reduce the voltage drop of the power signal, ensure display uniformity, and improve display effect.

[0280] This embodiment of the invention effectively reduces the diffraction effect of the light-transmitting unit and improves the transparent display effect by placing the anode connecting electrode and the auxiliary electrode in the light-transmitting unit and changing the light-transmitting unit into an irregular shape using the anode connecting electrode and the auxiliary electrode.

[0281] The preparation process of the exemplary embodiments disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0282] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 16, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 5, except that the arrangement of the second anode is different.

[0283] In an exemplary embodiment, the structure of the bottom emitting circuit unit and the top emitting circuit unit in the substrate is substantially the same as that in the embodiment shown in FIG. 5, and the structure of the first anode 81 is substantially the same as that in the embodiment shown in FIG. 5.

[0284] In an exemplary embodiment, at least one second anode 82 may include a first sub-anode 82-1, a second sub-anode 82-2, and a sub-connecting electrode 82-3. The first sub-anode 82-1 may be block-shaped (e.g., rectangular), and the second sub-anode 82-2 may be strip-shaped extending along a first direction X. In the first direction X, the first sub-anode 82-1 may be located on the side opposite to the first anode 81 in the first direction X, and in the second direction Y, the second sub-anode 82-2 may be located on the side of the first anode 81 and the first sub-anode 82-1 in the second direction Y.

[0285] In the exemplary embodiment, the preparation process of the display substrate in this embodiment is basically the same as that in the embodiment shown in FIG5. The difference is that in the preparation of the cathode pattern, the first cathode 91 of the reflective material is first formed by the patterning process, and then the transparent conductive material is deposited to form a transparent conductive layer covering the entire surface. The second cathode 92 disposed in the second type of light-emitting unit and the third cathode 93 disposed in the first type of light-emitting unit are formed. The third cathode 93 overlaps with the first cathode 91. The second cathode 92 and the third cathode 93 are disposed in the same layer and are an integral structure connected to each other, as shown in FIG17.

[0286] This embodiment maximizes the aperture ratio by arranging the second anode. By forming a transparent conductive layer covering the entire surface, it not only ensures that the top-emitting and bottom-emitting cathodes are shared, but also reduces one patterning process, improves production efficiency, and lowers production costs.

[0287] Figure 18A is a schematic diagram of the arrangement of another light-emitting unit in an exemplary embodiment of the present disclosure, and Figure 18B is a schematic diagram of the arrangement of another circuit unit in an exemplary embodiment of the present disclosure, illustrating the case where n is 3.

[0288] As shown in Figure 18A, in at least one display unit 110, a first bottom-emitting light-emitting unit P1_B, a second bottom-emitting light-emitting unit P2_B, and a third bottom-emitting light-emitting unit P3_B can be arranged sequentially along the second direction Y to form a third light-emitting unit group. A first top-emitting light-emitting unit P1_T and a second top-emitting light-emitting unit P2_T can be arranged sequentially along the second direction Y to form a fourth light-emitting unit group. The third light-emitting unit group can be located on one side of the fourth light-emitting unit group in the first direction X, and the third top-emitting light-emitting unit P3_T can be located on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction Y.

[0289] As shown in Figure 18B, in at least one display unit 110, the first bottom emitting circuit unit Q1_B, the second bottom emitting circuit unit Q2_B, the third bottom emitting circuit unit Q3_B, the first top emitting circuit unit Q1_T, the second top emitting circuit unit Q2_T, and the third top emitting circuit unit Q3_T can be arranged sequentially along the second direction Y. The six circuit units are arranged vertically, and the bottom emitting circuit unit and the top emitting circuit unit are set separately.

[0290] Figure 19 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 19, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 5. The difference is that the three bottom emitting circuit units are arranged in one area and the three top emitting circuit units are arranged in another area, that is, the bottom emitting circuit units and the top emitting circuit units are arranged separately.

[0291] In the exemplary embodiment, the structure of the pixel driving circuit in the circuit unit of the display substrate is basically the same as that of the embodiment shown in FIG5, and will not be described again here.

[0292] In an exemplary embodiment, three first anodes 81 in a repeating unit can be arranged vertically. The first first anode 81 is connected to the pixel driving circuit in the first bottom emitting circuit unit Q1_B, the second first anode 81 is connected to the pixel driving circuit in the second bottom emitting circuit unit Q2_B, and the third first anode 81 is connected to the pixel driving circuit in the third bottom emitting circuit unit Q3_B. The three first anodes 81 can be arranged sequentially along the second direction Y to form a third light-emitting unit group.

[0293] In an exemplary embodiment, two second anodes 82 in a repeating unit can be arranged vertically. The first second anode 82 is connected to the pixel driving circuit in the first top emitting circuit unit Q1_T, and the second second anode 82 is connected to the pixel driving circuit in the second top emitting circuit unit Q2_T. The two second anodes 82 can be arranged sequentially along the second direction Y to form a fourth light-emitting unit group.

[0294] In an exemplary embodiment, three first anodes 81 in a repeating unit can be disposed on one side of the two second anodes 82 in the first direction X, that is, the third light-emitting unit group is disposed on one side of the fourth light-emitting unit group in the first direction X. The third second anode 82 can be disposed on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction Y, and the third second anode 82 is connected to the pixel driving circuit in the third top emission circuit unit Q3_T.

[0295] This embodiment uses separate bottom and top emission circuit units, which facilitates the layout of the pixel driving circuit and improves process quality. Although considering bottom emission maintenance and aperture ratio arrangement, a longer sub-connecting electrode needs to be set in the transparent unit, the longer sub-connecting electrode in the transparent unit can effectively weaken the diffraction effect and improve the transparent display effect.

[0296] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0297] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0298] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0299] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of repeating units, at least one repeating unit comprising a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit being configured to perform bi-lateral image display, and the light-transmitting unit being configured to transmit light; in a direction perpendicular to the display substrate, the display substrate at least comprises a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer of the display unit comprising 2n circuit units, the light-emitting structure layer of the display unit comprising 2n light-emitting units, each circuit unit comprising at least a pixel driving circuit, each light-emitting unit comprising at least a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, n being 3 or 4; the 2n light-emitting units comprising n first-type light-emitting units and n second-type light-emitting units, the first-type light-emitting units emitting light in a bottom-emission mode, the second-type light-emitting units emitting light in a top-emission mode, or the first-type light-emitting units emitting light in a top-emission mode. The emission method is as follows: the emitted light from the second type of light-emitting unit is bottom emission; the 2n circuit units include n first type circuit units and n second type circuit units, the pixel driving circuit in the first type circuit unit is connected to the light-emitting device in the first type of light-emitting unit, and the pixel driving circuit in the second type circuit unit is connected to the light-emitting device in the second type of light-emitting unit; the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a first node electrode with a first node potential and a second node electrode with a second node potential, the second electrode of the first transistor and the gate electrode of the second transistor are connected to the first node electrode, and the second electrode of the second transistor and the second electrode of the third transistor are connected to the second node electrode; in at least one circuit unit, the first transistor, the second transistor and the third transistor are arranged sequentially along a first direction, and in at least one repeating unit, the 2n circuit units are arranged sequentially along a second direction, the first direction and the second direction intersect.

2. The display substrate according to claim 1, wherein, The n first-type light-emitting units include at least a first-type first-light-emitting unit emitting a first-color light, a first-type second-light-emitting unit emitting a second-color light, and a first-type third-light-emitting unit emitting a third-color light; the n second-type light-emitting units include at least a second-type first-light-emitting unit emitting a first-color light, a second-type second-light-emitting unit emitting a second-color light, and a second-type third-light-emitting unit emitting a third-color light; the n first-type circuit units include at least a first-type first-circuit unit connected to the first-type first-light-emitting unit, a first-type second-circuit unit connected to the first-type second-light-emitting unit, and a first-type third-circuit unit connected to the first-type third-light-emitting unit; the n second-type circuit units include at least a second-type first-circuit unit connected to the second-type first-light-emitting unit, a second-type second-circuit unit connected to the second-type second-light-emitting unit, and a second-type third-circuit unit connected to the second-type third-light-emitting unit; in at least one repeating unit, the first-type first-circuit unit, the second-type first-circuit unit, the first-type second-circuit unit, the second-type second-circuit unit, the first-type third-circuit unit, and the second-type third-circuit unit are arranged sequentially along the second direction.

3. The display substrate according to claim 2, wherein, The first type of first light-emitting unit, the first type of second light-emitting unit, and the first type of third light-emitting unit are arranged sequentially along the second direction to form a first light-emitting unit group; the second type of first light-emitting unit, the second type of second light-emitting unit, and the second type of third light-emitting unit are arranged sequentially along the second direction to form a second light-emitting unit group; the first light-emitting unit group is arranged on one side of the second light-emitting unit group in the first direction.

4. The display substrate according to claim 1, wherein, The n first-type light-emitting units include at least a first-type first-light-emitting unit emitting a first-color light, a first-type second-light-emitting unit emitting a second-color light, and a first-type third-light-emitting unit emitting a third-color light; the n second-type light-emitting units include at least a second-type first-light-emitting unit emitting a first-color light, a second-type second-light-emitting unit emitting a second-color light, and a second-type third-light-emitting unit emitting a third-color light; the n first-type circuit units include at least a first-type first-circuit unit connected to the first-type first-light-emitting unit, a first-type second-circuit unit connected to the first-type second-light-emitting unit, and a first-type third-circuit unit connected to the first-type third-light-emitting unit; the n second-type circuit units include at least a second-type first-circuit unit connected to the second-type first-light-emitting unit, a second-type second-circuit unit connected to the second-type second-light-emitting unit, and a second-type third-circuit unit connected to the second-type third-light-emitting unit; in at least one repeating unit, the first-type first-circuit unit, the first-type second-circuit unit, the first-type third-circuit unit, the second-type first-circuit unit, the second-type second-circuit unit, and the second-type third-circuit unit are arranged sequentially along the second direction.

5. The display substrate according to claim 4, wherein, The first type of first light-emitting unit, the first type of second light-emitting unit, and the first type of third light-emitting unit are arranged sequentially along the second direction to form a third light-emitting unit group; the second type of first light-emitting unit and the second type of second light-emitting unit are arranged sequentially along the second direction to form a fourth light-emitting unit group; the third light-emitting unit group is located on one side of the fourth light-emitting unit group in the first direction, and the second type of third light-emitting unit is located on one side of the third light-emitting unit group and the fourth light-emitting unit group in the second direction.

6. The display substrate according to any one of claims 1 to 5, wherein, At least one repeating unit further includes a scan signal line, the scan signal line being a straight line or a broken line extending along the first direction, wherein the first transistor and the third transistor in the 2n circuit units of the repeating unit are connected to the same scan signal line.

7. The display substrate according to claim 6, wherein, At least one repeating unit further includes a first gate line and a third gate line connected to the scan signal line. The first gate line and the third gate line are in the shape of a straight line or a broken line extending along a second direction. The third gate line is disposed on one side of the first gate line in the first direction. The first gate line is connected to the gate electrode of the first transistor of each of the 2n circuit units in the repeating unit, and the third gate line is connected to the gate electrode of the third transistor of each of the 2n circuit units in the repeating unit.

8. The display substrate according to claim 7, wherein, At least one repeating unit further includes a first power line, a second power line, a compensation signal line, and 2n data signal lines. The first terminals of the second transistors of the 2n circuit units in the repeating unit are connected to the same first power line. The first terminals of the third transistors of the 2n circuit units in the repeating unit are connected to the same compensation signal line. The first terminals of the first transistors of the 2n circuit units in the repeating unit are respectively connected to the 2n data signal lines.

9. The display substrate according to claim 8, wherein, The first power line, the second power line, the compensation signal line, and the data signal line are in the shape of a straight line or a broken line extending along the second direction; in at least one repeating unit, in the first direction, the second power line is disposed on the side of the first gate line away from the third gate line, the 2n data signal lines are disposed between the first gate line and the second power line, the compensation signal line is disposed on the side of the third gate line away from the first gate line, and the first power line is disposed between the first gate line and the third gate line.

10. The display substrate according to any one of claims 1 to 5, wherein, The pixel driving circuit also includes a storage capacitor, and the structure of the storage capacitor in the first type of circuit unit is different from the structure of the storage capacitor in the second type of circuit unit.

11. The display substrate according to claim 10, wherein, The first type of light-emitting unit emits light in a bottom-emitting manner, and the second type of light-emitting unit emits light in a top-emitting manner. The first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit. In the bottom-emitting circuit unit, the storage capacitor includes at least a transparent first electrode plate and a transparent second electrode plate. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate. The first electrode plate is connected to the second node electrode, and the second electrode plate is connected to the first node electrode. The first electrode plate and the second electrode plate form the transparent storage capacitor in the bottom-emitting circuit unit.

12. The display substrate according to claim 11, wherein, In a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on a substrate, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate, and a semiconductor layer disposed on the side of the first conductive layer away from the substrate, wherein the first electrode plate is disposed in the first transparent conductive layer and the second electrode plate is disposed in the semiconductor layer.

13. The display substrate according to claim 10, wherein, The first type of light-emitting unit emits light in a bottom-emitting manner, and the second type of light-emitting unit emits light in a top-emitting manner. The first type of circuit unit is a bottom-emitting circuit unit, and the second type of circuit unit is a top-emitting circuit unit. In at least one of the top-emitting circuit units, the storage capacitor includes at least a third plate, a fourth plate, and a fifth plate. The orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the third plate on the substrate, and the orthographic projection of the fifth plate on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate. The third plate and the fifth plate are connected to the second node electrode, and the fourth plate is connected to the first node electrode. The third plate and the fourth plate form a first sub-capacitor, and the fourth plate and the fifth plate form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel form the storage capacitor in the top-emitting circuit unit.

14. The display substrate according to claim 13, wherein, In a direction perpendicular to the display substrate, the display substrate includes at least a first transparent conductive layer disposed on the substrate, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate, a semiconductor layer disposed on the side of the first conductive layer away from the substrate, a second conductive layer disposed on the side of the semiconductor layer away from the substrate, and a third conductive layer disposed on the side of the second conductive layer away from the substrate, wherein a third electrode plate is disposed in the first conductive layer, a fourth electrode plate is disposed in the semiconductor layer, and a fifth electrode plate is disposed in the third conductive layer.

15. The display substrate according to any one of claims 1 to 5, wherein, The first type of light-emitting unit emits light from the bottom, while the second type of light-emitting unit emits light from the top. The first type of light-emitting unit includes at least a first anode, and the second type of light-emitting unit includes at least a second anode. The structure of the first anode is different from that of the second anode.

16. The display substrate according to claim 15, wherein, The first anode includes at least a main body and a connecting part. The main body is disposed in the display unit. A first end of the connecting part is connected to the main body, and a second end of the connecting part extends to the back of the light-transmitting unit and is connected to the pixel driving circuit of the first type of circuit unit.

17. The display substrate according to claim 15, wherein, The second anode includes at least a first sub-anode, a second sub-anode, and a sub-connecting electrode. The first sub-anode and the second sub-anode are disposed in the display unit and isolated from each other. One end of the sub-connecting electrode is connected to the first sub-anode and the second sub-anode, respectively. The other end of the sub-connecting electrode extends to the back of the light-transmitting unit and is connected to the pixel driving circuit of the second type of circuit unit.

18. The display substrate according to claim 17, wherein, The second type of light-emitting unit further includes a third anode, which includes at least a first reflective electrode and a second reflective electrode. The first reflective electrode and the second reflective electrode are disposed in the display unit and are isolated from each other. The orthographic projection of the first reflective electrode on the substrate at least partially overlaps with the orthographic projection of the first sub-anode on the substrate and is in contact with the first sub-anode. The orthographic projection of the second reflective electrode on the substrate at least partially overlaps with the orthographic projection of the second sub-anode on the substrate and is in contact with the second sub-anode.

19. The display substrate according to claim 15, wherein, The first type of light-emitting unit further includes a first cathode, and the second type of light-emitting unit further includes a second cathode. The first cathode and the second cathode are isolated from each other. The first cathode is made of a reflective material, and the second cathode is made of a transparent material.

20. The display substrate according to claim 19, wherein, The first type of light-emitting unit also includes a third cathode, which overlaps with the first cathode. The second cathode and the third cathode are disposed in the same layer and are an integral structure that is interconnected.

21. A display device comprising a display substrate as described in any one of claims 1 to 20.

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