Electronic component

Abstract

This electronic component includes: a base electrode having an upper surface and a side walls; a first via electrode disposed on the base electrode and having a first connection portion for the upper surface of the base electrode and second connection portions for the side walls of the base electrode; and a first electrode disposed on the first via electrode and electrically connected to the base electrode via the first via electrode.

Description

Electronic components

[0001] This application claims priority under Patent Application No. 2024-194740 and Patent Application No. 2024-194741, both filed with the Japan Patent Office on November 6, 2024, and the entire contents of these applications are incorporated herein by reference. This disclosure relates to electronic components such as semiconductor devices.

[0002] Patent document 1 (US2016 / 379992A1) discloses a semiconductor device comprising a SiC epitaxial layer, a gate insulating film, an embedded resistor, an interlayer film, a gate pad, and contact vias. The gate insulating film covers the SiC epitaxial layer. The embedded resistor is located on top of the gate insulating film. The interlayer film covers the embedded resistor. The gate pad overlaps the embedded resistor on the interlayer film. Contact vias electrically connect the embedded resistor and the gate pad within the interlayer film.

[0003] U.S. Patent Application Publication No. 2016 / 379992

[0004] [Summary] This disclosure provides an electronic component that contributes to improving electrical characteristics.

[0005] This disclosure provides an electronic component comprising: a base electrode having a top surface and side walls; a first via electrode disposed on the base electrode and having a first connection portion to the top surface of the base electrode and a second connection portion to the side walls of the base electrode; and a first electrode disposed on the first via electrode and electrically connected to the base electrode via the first via electrode.

[0006] This disclosure provides an electronic component comprising: a resistive electrode having a top surface and side walls; a first via electrode disposed on the resistive electrode and having a first connection portion to the top surface of the resistive electrode and a second connection portion to the side walls of the resistive electrode; and a second via electrode disposed on the resistive electrode at a distance from the first via electrode and having a third connection portion to the top surface of the resistive electrode and a fourth connection portion to the side walls of the resistive electrode.

[0007] This disclosure provides an electronic component comprising: a chip; a base insulating film covering the chip; a base electrode disposed on the base insulating film and having an upper surface and side walls; an insulating interlayer film covering the base electrode; a via electrode embedded in the interlayer film and having a first connection portion to the upper surface of the base electrode and a second connection portion to the side walls of the base electrode; and an electrode electrically connected to the base electrode via the via electrode on the interlayer film.

[0008] This disclosure provides an electronic component comprising a base electrode, a via electrode disposed on the base electrode, and a wiring electrode disposed on the via electrode, wherein the wiring electrode includes a via connection portion extending in a first direction on the via electrode, a wiring portion spaced apart on one side in a second direction intersecting the first direction from the via electrode and having a portion extending in the first direction along the via connection portion, and a connecting portion connected between the via connection portion and the wiring portion and having a length less than the length of the via connection portion with respect to the first direction.

[0009] This disclosure provides an electronic component comprising: a base electrode extending in a strip shape in a first direction; a via electrode disposed on the base electrode; and a pad electrode disposed on the via electrode, wherein the pad electrode includes a via connection portion extending in a first direction along the base electrode on the via electrode; a pad portion disposed on the second direction side intersecting the via connection portion in the first direction, having a first side extending for a first length along the base electrode in the first direction and a second side extending for a second length less than the first length in the second direction; and a connecting portion connected between the via connection portion and the pad portion.

[0010] The aforementioned or any other purposes, features, and effects will be revealed in the detailed description with reference to the attached drawings.

[0011] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface. Figure 4 is an enlarged plan view of the active region shown in Figure 3. Figure 5 is a cross-sectional view along the line VV shown in Figure 4. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. Figure 7 is an enlarged cross-sectional view showing the main part of the configuration shown in Figure 5. Figure 8 is a cross-sectional view of the outer region (inactive region) shown in Figure 3. Figure 9 is a plan view showing an example of the layout of the wiring electrodes. Figure 10 is an enlarged plan view showing the pad region (inactive region) shown in Figure 9 together with an example of the electrode layout. Figure 11 is an enlarged plan view of the base electrode shown in Figure 10. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 11. Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 11. Figure 14 is an enlarged cross-sectional view of the first base via electrode shown in Figure 12. Figure 15 is an enlarged cross-sectional view of the first base via electrode shown in Figure 13. Figure 16 is a further enlarged cross-sectional view of the inactive region shown in Figure 8. Figure 17 is an enlarged cross-sectional view of the gate via electrode shown in Figure 16. Figure 18 is an enlarged cross-sectional view of the outer via electrode shown in Figure 16. Figure 19 is an enlarged plan view showing the pad region shown in Figure 10 together with the gate pad electrode and gate wiring electrode. Figure 20 is an electrical circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 1. Figure 21 is an enlarged plan view showing the pad region of the semiconductor device according to the second embodiment together with an example of electrode layout. Figure 22 is an enlarged plan view showing the pad region of the semiconductor device according to the third embodiment together with an example of electrode layout. Figure 23 is an enlarged plan view showing the pad region of the semiconductor device according to the fourth embodiment together with an example of electrode layout. Figure 24 is an enlarged plan view showing the pad region of the semiconductor device according to the fifth embodiment together with an example of electrode layout. Figure 25 is an enlarged plan view showing the pad region of the semiconductor device according to the sixth embodiment together with an example of electrode layout. Figure 26 is an enlarged plan view showing the pad region of the semiconductor device according to the seventh embodiment together with an example of electrode layout. Figure 27 is an electrical circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 26. Figure 28 is an enlarged plan view showing the pad area of ​​the semiconductor device according to the eighth embodiment, along with an example of electrode layout. Figure 29 is an electrical circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 28.Figure 30 is an enlarged plan view showing the pad area of ​​the semiconductor device according to the ninth embodiment, along with an example of electrode layout. Figure 31 is an enlarged plan view showing the semiconductor device according to the tenth embodiment, along with an example of electrode layout. Figure 32 is a cross-sectional view along the line XXXII-XXXII shown in Figure 31. Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 31. Figure 34 is an electrical circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 31. Figure 35 is an enlarged plan view showing the semiconductor device according to the eleventh embodiment, along with an example of electrode layout. Figure 36 is an electrical circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 35. Figure 37 is an enlarged plan view showing the semiconductor device according to the twelfth embodiment, along with an example of electrode layout. Figure 38 is an enlarged plan view of the active area of ​​the semiconductor device according to the thirteenth embodiment. Figure 39 is a cross-sectional view along the line XXXIX-XXXIX shown in Figure 38. Figure 40 is an enlarged plan view showing the pad area of ​​the semiconductor device according to the fourteenth embodiment, along with an example of electrode layout. Figure 41 is an enlarged plan view showing the pad area of ​​a semiconductor device according to the 15th embodiment, along with an example of electrode layout. Figure 42 is an enlarged cross-sectional view showing the electrode structure according to the first modified example. Figure 43 is an enlarged cross-sectional view showing the electrode structure according to the second modified example. Figure 44 is an enlarged cross-sectional view showing the electrode structure according to the third modified example. Figure 45 is an enlarged cross-sectional view showing the electrode structure according to the fourth modified example.

[0012] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0013] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0014] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0015] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0016] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0017] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example layout of the first main surface 3. Figure 4 is an enlarged plan view of the active region 8 shown in Figure 3.

[0018] Figure 5 is a cross-sectional view along the VV line shown in Figure 4. Figure 6 is a cross-sectional view along the VI-VI line shown in Figure 4. Figure 7 is an enlarged cross-sectional view showing the main part of the configuration shown in Figure 5. Figure 8 is a cross-sectional view of the outer region 9B (inactive region 9) shown in Figure 3.

[0019] Figure 9 is a plan view showing an example layout of the line electrode 40. Figure 10 is an enlarged plan view showing the pad region 9A (inactive region 9) shown in Figure 9 along with the electrode layout example. Figure 11 is an enlarged plan view of the base electrode 35 shown in Figure 10. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 11. Figure 13 is a cross-sectional view along the line XIII-XIII shown in Figure 11.

[0020] Figure 14 is an enlarged cross-sectional view of the first base via electrode 50 shown in Figure 12. Figure 15 is an enlarged cross-sectional view of the first base via electrode 50 shown in Figure 13. Figure 16 is a further enlarged cross-sectional view of the inactive region 9 shown in Figure 8.

[0021] Figure 17 is an enlarged cross-sectional view of the gate via electrode 67 shown in Figure 16. Figure 18 is an enlarged cross-sectional view of the outer via electrode 71 shown in Figure 16. Figure 19 is an enlarged plan view showing the pad region 9A shown in Figure 10 together with the gate pad electrode 74 and the gate wiring electrode 79.

[0022] Referring to Figures 1 to 19, semiconductor device 1A is a semiconductor switching device as an example of an electronic component having an insulated gate type transistor structure T as an example of a device structure (functional device). The transistor structure T has a trench gate type vertical structure.

[0023] The semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 includes either a single crystal of Si (silicon) or a single crystal of a wide-bandgap semiconductor, or both. A wide-bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si. Examples of wide-bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0024] In this embodiment, chip 2 includes a single crystal of a wide-bandgap semiconductor. Chip 2 may also be referred to as a "semiconductor chip," a "wide-bandgap semiconductor chip," etc. Semiconductor device 1A may also be referred to as a "wide-bandgap semiconductor device." In this embodiment, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal. In other words, semiconductor device 1A is a "SiC semiconductor device."

[0025] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0026] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed in plan from the thickness direction Z of the chip 2 (hereinafter simply referred to as "plan view"). The thickness direction Z is also the normal direction (vertical direction) to the first main surface 3 and the second main surface 4.

[0027] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0028] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0029] In this form, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction, and the second direction Y may be the m-axis direction. The first direction X may be a direction intersecting both the a-axis direction and the m-axis direction, and the second direction Y may be a direction intersecting both the a-axis direction and the m-axis direction.

[0030] The chip 2 (the first main surface 3 and the second main surface 4) has an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle in the off-direction from the thickness direction Z (vertical line). The off-direction is preferably the a-axis direction (that is, the second direction Y) of the SiC single crystal. The off-direction may be the m-axis direction of the SiC single crystal.

[0031] The off-angle may be greater than 0° and 10° or less. The off-angle may have a value belonging to at least one range of greater than 0° and 1° or less, 1° or more and 2.5° or less, 2.5° or more and 5° or less, 5° or more and 7.5° or less, and 7.5° or more and 10° or less.

[0032] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude the form in which the off-angle is 0° (that is, the form in which the first main surface 3 is just the c-plane).

[0033] The first main surface 3 (chip 2) is more than 0 mm ２ and 400 mm or less ２ and may have the following planar area. The planar area of the first main surface 3 (chip 2) is more than 0 mm ２ and 1 mm or less, from 1 mm ２ and 25 mm or less, from 25 mm ２ and 50 mm or less, from 50 mm ２ and 75 mm or less, from 75 mm ２ and 100 mm or less, from 100 mm ２ and 75 mm or less, from 75 mm ２ and 100 mm or less, from 100 mm ２ and 75 mm or less, from 75 mm ２ and 100 mm or less, from 100 mm ２Hereinafter, 100 mm ２ or more and 200 mm ２ or less and 200 mm ２ or more and 300 mm ２ or less, and, 300 mm ２ or more and 400 mm ２ It may have a value belonging to at least one of the following ranges.

[0034] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in a region on the side of the second main surface 4 within the chip 2. The first semiconductor layer 6 may be referred to as the "first layer (region)", "drain layer (region)", etc. The first semiconductor layer 6 extends in a layer shape along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The n-type impurity concentration of the first semiconductor layer 6 may be substantially constant in the thickness direction Z.

[0035] The first semiconductor layer 6 includes a single crystal of a wide bandgap semiconductor. In this form, the first semiconductor layer 6 is a semiconductor substrate (SiC substrate) including a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of 3C-SiC polycrystal.

[0036] The first semiconductor layer 6 may have a thickness greater than 0 μm and less than or equal to 500 μm. The thickness of the first semiconductor layer 6 may be greater than 0 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 50 μm, greater than or equal to 50 μm and less than or equal to 100 μm, greater than or equal to 100 μm and less than or equal to 150 μm, greater than or equal to 150 μm and less than or equal to 200 μm, greater than or equal to 200 μm and less than or equal to 250 μm, greater than or equal to 250 μm and less than or equal to 300 μm, greater than or equal to 300 μm and less than or equal to 350 μm, greater than or equal to 350 μm and less than or equal to 400 μm, greater than or equal to 400 μm and less than or equal to 450 μm, and greater than or equal to 450 μm and less than or equal to 500 μm. It may have a value belonging to at least one of the ranges.

[0037] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in a region on the side of the first main surface 3 with respect to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may be referred to as the "second layer (region)", "drain layer (region)", "drift layer (region)", etc.

[0038] The second semiconductor layer 7 has an n-type impurity concentration lower than that of the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be substantially constant in the thickness direction Z. The n-type impurity concentration of the second semiconductor layer 7 may be increased from the first semiconductor layer 6 side toward the first main surface 3 side.

[0039] The second semiconductor layer 7 is stacked on the first semiconductor layer 6. The second semiconductor layer 7 extends in a layer shape along the first main surface 3 (the first semiconductor layer 6), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0040] The second semiconductor layer 7 includes a single crystal of a wide bandgap semiconductor. In this form, the second semiconductor layer 7 is a semiconductor layer (SiC layer) including a hexagonal SiC single crystal. In this form, the second semiconductor layer 7 is composed of an epitaxial layer including a 4H-SiC single crystal (hexagonal crystal) and has the above-described off direction and off angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0041] The second semiconductor layer 7 has a thickness less than that of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may have a value belonging to at least one of the ranges of greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less.

[0042] The semiconductor device 1A includes an active region 8 (active region) provided on the first main surface 3. The active region 8 includes a device structure (transistor structure T) and is a region where an output current (drain current) is generated. The active region 8 is provided in the inner part of the first main surface 3 at an interval from the periphery (the first to fourth side surfaces 5A to 5D) of the first main surface 3.

[0043] In this form, the active region 8 includes a first active region 8A and a second active region 8B. The first active region 8A extends in a strip shape in the second direction Y in the region on the second side surface 5B side in plan view. The first active region 8A is set in a polygonal shape having four sides parallel to the periphery of the first main surface 3.

[0044] The second active region 8B is located on the fourth side surface 5D side, spaced apart from the first active region 8A in the first direction X when viewed from above, and faces the first active region 8A in the first direction X. The second active region 8B extends in a band shape in the second direction Y on the fourth side surface 5D side when viewed from above.

[0045] The second active region 8B is set to a polygonal shape having four sides parallel to the periphery of the first main surface 3. The second active region 8B has a layout that is symmetrical to the first active region 8A with respect to a virtual line extending in the second direction Y from the central part of the first main surface 3.

[0046] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0047] The semiconductor device 1A includes a non-active region 9 located outside the active region 8 on the first main surface 3. The non-active region 9 is a region that does not include the device structure (transistor structure T) and is located around the active region 8.

[0048] In this embodiment, the inactive region 9 includes a pad region 9A, an outer region 9B, and a boundary region 9C. The pad region 9A may be referred to as the "first inactive region," the outer region 9B as the "second inactive region," and the boundary region 9C as the "third inactive region."

[0049] The pad area 9A is located in the area on the first side surface 5A side in a plan view. Specifically, the pad area 9A is located along the central part of the first side surface 5A and is divided into the area between the end of the first active area 8A and the end of the second active area 8B, and is sandwiched between the ends of the first active area 8A and the end of the second active area 8B from both sides in the first direction X.

[0050] The pad region 9A is divided into a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the pad region 9A is divided into an L-shaped recessed boundary at the end of the first active region 8A and an L-shaped recessed boundary at the end of the second active region 8B.

[0051] The outer region 9B extends in a band shape along the first to fourth sides 5A to 5D in a plan view and is provided in a polygonal ring (a quadrilateral ring in this configuration) surrounding the active region 8 (first active region 8A and second active region 8B). The outer region 9B is connected to the pad region 9A on the side of the first side 5A.

[0052] The boundary region 9C is located in the region between the first active region 8A and the second active region 8B, and extends in a band shape in the second direction Y. The boundary region 9C is connected to the pad region 9A on the first side surface 5A side and to the outer region 9B on the third side surface 5C side. The boundary region 9C has a width less than the width of the pad region 9A with respect to the first direction X.

[0053] The configuration of the active region 8 is shown below. Since the configuration of the second active region 8B is the same as that of the first active region 8A, the configuration of the first active region 8A is shown below, and the explanation of the configuration of the second active region 8B is omitted. The explanation of the configuration of the second active region 8B can be obtained by replacing "first active region 8A" with "second active region 8B" in the following explanation.

[0054] The semiconductor device 1A includes a p-type body region 10 formed in the second semiconductor layer 7 in the inner portion (first active region 8A) of the first main surface 3. The body region 10 may also be referred to as an "impurity region," etc. The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0055] The body region 10 is formed in the first active region 8A, spaced apart from the periphery of the first main surface 3, and is not formed in the inactive region 9. In this configuration, the body region 10 is formed on the surface layer of the first main surface 3 across the entire area of ​​the first active region 8A.

[0056] The body region 10 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The body region 10 is formed with a gap from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0057] The semiconductor device 1A includes a plurality of trench-type (trench electrode type) gate structures 15 formed in the inner portion (first active region 8A) of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," etc.

[0058] Multiple gate structures 15 are formed in the first active region 8A at intervals from the periphery of the first main surface 3, but not in the inactive region 9. The multiple gate structures 15 penetrate the body region 10 and are formed at intervals from the bottom of the second semiconductor layer 7 (first semiconductor layer 6) toward the first main surface 3.

[0059] The multiple gate structures 15 each extend in a strip-like manner in the first direction X when viewed from above, and are arranged with gaps in the second direction Y. The multiple gate structures 15 extend in a stripe-like manner in the first direction X when viewed from above.

[0060] Each of the multiple gate structures 15 has a long side (side surface) formed by the m-plane ((1-100) plane) of the SiC single crystal, and a short side (side surface) formed by the a-plane ((11-20) plane) of the SiC single crystal. Depending on the extension direction of the multiple gate structures 15, the long side may be formed by the m-plane and the short side may be formed by the a-plane.

[0061] The sides of the multiple gate structures 15 are formed substantially perpendicular to the first main surface 3. The sides of the multiple gate structures 15 may be inclined at an angle with respect to the first main surface 3. In other words, the multiple gate structures 15 may be formed in a tapered shape toward the second main surface 4. The multiple gate structures 15 may have inclined open ends. The open ends of the multiple gate structures 15 may be curved in an arc shape (circular arc shape).

[0062] The bottom surfaces of the multiple gate structures 15 are formed by the c-planes (Si planes) of the SiC single crystal. The bottom surfaces of the multiple gate structures 15 may extend in a substantially flat manner. The bottom surfaces of the multiple gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0063] The gate structure 15 may have a width greater than 0 μm and less than or equal to 3 μm. The width of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0064] The spacing between the multiple gate structures 15 may be greater than the width of the gate structure 15. The spacing between the gate structures 15 may be less than the width of the gate structure 15. The spacing between the gate structures 15 may be greater than 0 μm and 3 μm or less.

[0065] The spacing of the gate structure 15 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0066] The gate structure 15 may have a depth greater than 0 μm and less than or equal to 3 μm. The depth of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0067] The multiple gate structures 15 each include a trench 16, an insulating film 17, and an embedded electrode 18. The trench 16 may be referred to as a "gate trench," the insulating film 17 as a "gate insulating film," and the embedded electrode 18 as a "gate embedded electrode." The trench 16 is formed on the first main surface 3 and demarcates the wall surfaces (sides and bottom surfaces) of the gate structure 15.

[0068] The insulating film 17 may have a single-layer structure or a multilayer structure comprising at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 17 may also comprise at least one of the oxide film of the chip 2 (second semiconductor layer 7) and an oxide film other than the oxide film of the chip 2.

[0069] The insulating film 17 may include at least one of the following: NSG film (nondoped silicate glass film), PSG film (phosphorus silicon glass film), BPSG film (boron phosphorus silicon glass film), and TEOS film (tetraethyl orthosilicate film). In this embodiment, the insulating film 17 has a single-layer structure consisting of the oxide film of the chip 2.

[0070] The insulating film 17 coats the walls (sides and bottom) of the trench 16 in a film-like manner. The insulating film 17 may cover the walls of the trench 16 with a uniform thickness. The thickness of the insulating film 17 covering the bottom of the trench 16 may be greater than the thickness of the insulating film 17 covering the sides of the trench 16.

[0071] The thickness of the insulating film 17 may be greater than 0 nm and 250 nm or less. The thickness of the insulating film 17 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0072] The embedded electrode 18 includes either a metal or a non-metallic conductor (a conductor other than metal), or both. In this embodiment, the embedded electrode 18 includes conductive polysilicon. The embedded electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both.

[0073] The embedded electrode 18 is embedded in the trench 16 via an insulating film 17. The embedded electrode 18 has an electrode surface located on the bottom side of the trench 16 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 16. The electrode surface may have a recess toward the bottom side.

[0074] The semiconductor device 1A includes a plurality of n-type source regions 20 formed in the second semiconductor layer 7 in the inner portion (first active region 8A) of the first main surface 3. The source regions 20 may also be referred to as "impurity regions," etc. The source regions 20 have an n-type impurity concentration higher than the p-type impurity concentration of the body region 10. The n-type impurity concentration of the source regions 20 is higher than the n-type impurity concentration of the second semiconductor layer 7.

[0075] In this configuration, the multiple source regions 20 are formed in the region between the multiple gate structures 15 on the surface of the body region 10, and are formed at intervals in the first direction X following the extending direction of the multiple gate structures 15. Each of the multiple source regions 20 extends in a strip-like shape in the first direction X following the extending direction of the multiple gate structures 15.

[0076] Multiple source regions 20 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the body region 10. Multiple source regions 20 are connected to multiple gate structures 15 in the second direction Y, and face the embedded electrode 18 via an insulating film 17.

[0077] The semiconductor device 1A includes a plurality of p-type contact regions 21 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The contact regions 21 may also be referred to as "impurity regions," etc. The contact regions 21 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10.

[0078] Multiple contact regions 21 are formed in the surface layer of the body region 10 in the region between the multiple gate structures 15, and are formed with spacing in the first direction X following the extending direction of the multiple gate structures 15. Specifically, the multiple contact regions 21 are arranged alternately with the multiple source regions 20 in the first direction X.

[0079] With respect to the multiple contact regions 21 formed on both sides of one gate structure 15, the other set of multiple contact regions 21 faces the first set of multiple contact regions 21 in the second direction Y in a plan view. The other set of multiple contact regions 21 may also face the region between the first set of multiple contact regions 21 (multiple source regions 20) in the second direction Y in a plan view.

[0080] The multiple contact regions 21 are formed in a rectangular shape in plan view. Each of the multiple contact regions 21 has a length smaller than the length of the multiple source regions 20 with respect to the first direction X. The length of the contact regions 21 may be greater than the length of the source regions 20. The multiple contact regions 21 are connected to the multiple gate structures 15 in the second direction Y and face the embedded electrodes 18 via an insulating film 17.

[0081] Multiple contact regions 21 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the body region 10. In this configuration, the multiple contact regions 21 are formed deeper than the multiple source regions 20. The multiple contact regions 21 may also be formed shallower than the multiple source regions 20.

[0082] The configuration of the inactive region 9 is shown below. The semiconductor device 1A includes a p-type well region 22 formed in the second semiconductor layer 7 in the inactive region 9. The well region 22 may also be referred to as the "impurity region," etc.

[0083] The well region 22 has a p-type impurity concentration lower than that of the contact region 21. The p-type impurity concentration of the well region 22 may be approximately equal to that of the body region 10. The p-type impurity concentration of the well region 22 may be higher or lower than that of the body region 10.

[0084] The well region 22 is formed on the surface of the first main surface 3 and forms a pn junction with the second semiconductor layer 7. The well region 22 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The well region 22 is formed with a gap from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0085] In this embodiment, the well region 22 has a depth greater than the depth of the body region 10. In this embodiment, the depth of the well region 22 is greater than the depth of the gate structure 15. The depth of the well region 22 may be less than the depth of the gate structure 15. The depth of the well region 22 may be approximately equal to the depth of the body region 10.

[0086] In this embodiment, the well region 22 includes a pad well region 22A (pad pn joint), an outer well region 22B (outer pn joint), and a boundary well region 22C (boundary pn joint). The pad well region 22A is formed in the surface layer of the first main surface 3 in the pad region 9A. The pad well region 22A extends in layers along the first main surface 3.

[0087] The pad well region 22A is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the pad well region 22A has a planar shape similar to the planar shape of the pad region 9A.

[0088] The padwell region 22A demarcates the end (L-shaped recessed end) of the first active region 8A on one side in the first direction X (the second side surface 5B side), and demarcates the end (L-shaped recessed end) of the second active region 8B on the other side in the first direction X (the fourth side surface 5D side).

[0089] The pad well region 22A is drawn out from the pad region 9A to both the first active region 8A and the second active region 8B, and is connected (electrically connected) to the body region 10 on the first active region 8A side and the body region 10 on the second active region 8B side at the surface layer of the first main surface 3. The pad well region 22A may have a portion that is along the bottom surface of the ends of the multiple gate structures 15.

[0090] The outer well region 22B is formed in the outer region 9B on the surface of the first main surface 3. The outer well region 22B is connected to the pad well region 22A on the first side surface 5A side. The outer well region 22B is formed at a distance from the periphery of the first main surface 3 toward the inside of the first main surface 3 and extends in a band shape along the active region 8 (first active region 8A and second active region 8B).

[0091] The outer well region 22B demarcates the active region 8 from the peripheral edge of the first main surface 3. The outer well region 22B has a portion extending in the first direction X and a portion extending in the second direction Y in a plan view, and demarcates the active region 8 from multiple directions.

[0092] In this embodiment, the outer well region 22B is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. The outer well region 22B may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0093] The outer well region 22B is drawn out from the outer region 9B to both the first active region 8A and the second active region 8B, and is connected (electrically connected) to the body region 10 on the first active region 8A side and the body region 10 on the second active region 8B side at the surface of the first main surface 3. The outer well region 22B may have a portion that is along the bottom surface of the ends of the multiple gate structures 15.

[0094] The boundary well region 22C is formed in the surface layer of the first main surface 3 in the boundary region 9C. The boundary well region 22C extends in a band shape in the second direction Y, following the direction of extension of the boundary region 9C, and demarcates the first active region 8A on one side of the first direction X (the second side surface 5B side) and the second active region 8B on the other side of the first direction X (the fourth side surface 5D side).

[0095] The boundary well region 22C is connected to the pad well region 22A on the first side surface 5A side and to the outer well region 22B on the third side surface 5C side. The boundary well region 22C is drawn out from the boundary region 9C to both the first active region 8A and the second active region 8B, and is connected (electrically connected) to the body region 10 on the first active region 8A side and the body region 10 on the second active region 8B side at the surface layer of the first main surface 3. The boundary well region 22C may have portions that are along the bottom surfaces of the ends of the multiple gate structures 15.

[0096] The semiconductor device 1A includes one or more (one in this embodiment) p-type outer contact regions 23 formed in the second semiconductor layer 7 at the peripheral edge (inactive region 9) of the first main surface 3. The outer contact region 23 may also be referred to as an "impurity region," etc. The outer contact region 23 has a higher p-type impurity concentration than the p-type impurity concentration of the well region 22.

[0097] The p-type impurity concentration in the outer contact region 23 is higher than that in the body region 10. The p-type impurity concentration in the outer contact region 23 may be approximately equal to that in the contact region 21. The p-type impurity concentration in the outer contact region 23 may be higher or lower than that in the contact region 21.

[0098] The outer contact region 23 is formed on the surface of the outer well region 22B, and is not formed in the pad well region 22A or the boundary well region 22C. Of course, the well region 22 may have either or both a portion formed in the pad well region 22A and a portion formed in the boundary well region 22C.

[0099] The outer contact region 23 has a width less than the width of the outer well region 22B and is formed in the inner part of the outer well region 22B. The outer contact region 23 extends in a band shape following the direction of extension of the outer well region 22B. In a plan view, the outer contact region 23 has a portion extending in a first direction X and a portion extending in a second direction Y.

[0100] In this embodiment, the outer contact region 23 is formed as an ended or endless polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. The outer contact region 23 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0101] The outer contact region 23 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. In this embodiment, the inner edge of the outer contact region 23 is connected to a plurality of gate structures 15.

[0102] The inner edge of the outer contact region 23 may be connected (electrically connected) to the body region 10 on the first active region 8A side and the body region 10 on the second active region 8B side. The inner edge of the outer contact region 23 may be formed with a gap outward from the plurality of gate structures 15. The outer edge of the outer contact region 23 is formed with a gap inward from the outer edge of the well region 22.

[0103] The outer contact region 23 is formed with a gap from the bottom of the outer well region 22B toward the first main surface 3, and faces the second semiconductor layer 7 via a portion of the outer well region 22B. In this configuration, the outer contact region 23 has a depth approximately equal to the depth of the contact region 21. The depth of the outer contact region 23 may be greater or less than the depth of the contact region 21.

[0104] If the semiconductor device 1A includes a plurality of outer contact regions 23, the plurality of outer contact regions 23 may be formed at intervals following the extending direction of the outer well region 22B. In this case, the plurality of outer contact regions 23 may extend in a strip shape along the extending direction of the outer well region 22B. The plurality of outer contact regions 23 may be formed in a polygonal shape (such as a quadrilateral shape) or a circular shape.

[0105] The semiconductor device 1A includes one or more (in this embodiment, more than one) p-type field regions 24 formed in the second semiconductor layer 7 at the periphery (inactive region 9) of the first main surface 3. The field regions 24 may also be referred to as "impurity regions," etc. The multiple field regions 24 may be formed in an electrically floating state. Source potentials may be applied to the multiple field regions 24.

[0106] The number of field regions 24 may be between 1 and 20. The number of field regions 24 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 24 is between 1 and 8. In this embodiment, the semiconductor device 1A includes 4 field regions 24.

[0107] Multiple field regions 24 have a lower p-type impurity concentration than the contact region 21. The p-type impurity concentration in the field regions 24 is lower than the p-type impurity concentration in the outer contact region 23.

[0108] The p-type impurity concentration in the field region 24 may be approximately equal to the p-type impurity concentration in the well region 22. The p-type impurity concentration in the field region 24 may be higher or lower than the p-type impurity concentration in the well region 22.

[0109] The p-type impurity concentration in the field region 24 may be approximately equal to the p-type impurity concentration in the body region 10. The p-type impurity concentration in the field region 24 may be higher or lower than the p-type impurity concentration in the body region 10.

[0110] Multiple field regions 24 are formed on the surface of the first main surface 3, spaced apart from each other in the region between the periphery of the first main surface 3 and the active region 8. Specifically, the multiple field regions 24 are formed spaced apart from the well region 22 toward the periphery of the first main surface 3 and extend in a band shape along the well region 22.

[0111] In this embodiment, the multiple field regions 24 are formed as ended or endless polygonal rings (in this embodiment, quadrangular rings) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (first active region 8A and second active region 8B). The multiple field regions 24 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape).

[0112] Multiple field regions 24 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 through a portion of the second semiconductor layer 7. Multiple field regions 24 are formed at intervals from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0113] Each of the multiple field regions 24 has a width less than the width of the well region 22. The width of the field region 24 may be greater than or less than the width of the gate structure 15. The width of the field region 24 may be greater than 0 μm and 5 μm or less.

[0114] The width of the field region 24 may have a value greater than 0 μm and belonging to at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0115] The spacing between multiple field regions 24 may be less than the width of a field region 24. The spacing between field regions 24 may be greater than the width of a field region 24. The spacing between field regions 24 may be greater than 0 μm and 5 μm or less.

[0116] The spacing of the field regions 24 may have a value greater than 0 μm and belonging to at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0117] In this configuration, the multiple field regions 24 have a depth approximately equal to the depth of the well region 22. The depth of the field region 24 may be greater or less than the depth of the well region 22. The depth of the field region 24 may be approximately equal to the depth of the body region 10. The depth of the field region 24 may be greater or less than the depth of the body region 10.

[0118] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 24 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 24 may be approximately constant or non-uniform. The width of the multiple field regions 24 may gradually increase or decrease toward the periphery of the first main surface 3.

[0119] The depths of the multiple field regions 24 may be approximately constant or non-uniform. The depths of the multiple field regions 24 may gradually increase or decrease toward the peripheral edge of the first main surface 3. The multiple field regions 24 may each have a relatively shallow portion and a deeper portion that is deeper than the shallow portion. The shallow portion may be formed on the inner side and the deep portion may be formed on the peripheral side.

[0120] The spacing between the multiple field regions 24 may be approximately constant or non-uniform. The spacing between the multiple field regions 24 may gradually increase or decrease toward the periphery of the first main surface 3. The p-type impurity concentration in the multiple field regions 24 may be approximately constant or non-uniform. The p-type impurity concentration in the multiple field regions 24 may gradually increase or decrease toward the periphery of the first main surface 3.

[0121] The semiconductor device 1A includes a main surface insulating film 25 that selectively covers the first main surface 3. The main surface insulating film 25 may also be referred to as a "surface insulating film," "external insulating film," etc. The main surface insulating film 25 may have a single-layer structure or a multilayer structure containing at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 25 may contain at least one of the oxide film of the chip 2 (second semiconductor layer 7) and an oxide film other than the oxide film of the chip 2.

[0122] The main surface insulating film 25 may include at least one of the following: an NSG film, a PSG film, a BPSG film, and a TEOS film. The main surface insulating film 25 may include the same type of insulator as the insulating film 17, or it may include a different type of insulator. In this embodiment, the main surface insulating film 25 includes the same type of insulator as the insulating film 17 and has a single-layer structure consisting of the oxide film of the chip 2.

[0123] The main surface insulating film 25 selectively coats the first main surface 3 in an active region 8 and an inactive region 9. The main surface insulating film 25 coats the first main surface 3 in the active region 8, exposing multiple gate structures 15. Specifically, the main surface insulating film 25 is connected to multiple insulating films 17, exposing multiple embedded electrodes 18. In this embodiment, the main surface insulating film 25 forms a single insulating film integral with the multiple insulating films 17.

[0124] The main surface insulating film 25 covers the first main surface 3 with an inactive region 9. The main surface insulating film 25 covers the well region 22, the outer contact region 23, and a plurality of field regions 24 with the inactive region 9. The main surface insulating film 25 covers the pad well region 22A with the pad region 9A, the outer well region 22B with the outer region 9B, and the boundary well region 22C with the boundary region 9C.

[0125] The main surface insulating film 25 is connected to the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The main surface insulating film 25 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0126] The main surface insulating film 25 may have a thickness approximately equal to the thickness of the insulating film 17. The thickness of the main surface insulating film 25 may be greater than or less than the thickness of the insulating film 17. The thickness of the main surface insulating film 25 may be greater than 0 nm and less than or equal to 250 nm.

[0127] The thickness of the main surface insulating film 25 may be greater than 0 nm and fall within at least one of the following ranges: 10 nm or less, 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 250 nm or less.

[0128] The semiconductor device 1A includes a base insulating film 30 that covers the first main surface 3 with an inactive region 9. The base insulating film 30 may have a single-layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The base insulating film 30 may include at least one of the oxide film of the chip 2 (second semiconductor layer 7) and an oxide film other than the oxide film of the chip 2.

[0129] The base insulating film 30 may include at least one of the following: an NSG film, a PSG film, a BPSG film, and a TEOS film. The base insulating film 30 may include the same type of insulator as the insulating film 17, or it may include a different type of insulator than the insulating film 17. The base insulating film 30 may include the same type of insulator as the main surface insulating film 25, or it may include a different type of insulator than the main surface insulating film 25.

[0130] The base insulating film 30 coats the first main surface 3 in a film-like manner in the inactive region 9 and has a thickness greater than the thickness of the main surface insulating film 25. In this embodiment, the base insulating film 30 is formed in the pad region 9A and covers the pad well region 22A (well region 22 / pn junction) on the first main surface 3. In this embodiment, the base insulating film 30 is formed at intervals from the plurality of gate structures 15 and is connected to the main surface insulating film 25 at the periphery of the pad region 9A.

[0131] In this embodiment, the base insulating film 30 is not formed in the outer region 9B and the boundary region 9C. Of course, the base insulating film 30 may cover the first main surface 3 in a film-like manner in the outer region 9B and cover the outer well region 22B (well region 22 / pn junction) on the first main surface 3. In this case, the base insulating film 30 may extend in a strip-like (annular) shape along the outer well region 22B.

[0132] The base insulating film 30 may cover the first main surface 3 in a film-like manner in the boundary region 9C, and may also cover the boundary well region 22C (well region 22 / pn junction) on the first main surface 3. In this case, the base insulating film 30 may extend in a strip-like manner along the boundary region 9C.

[0133] The thickness of the base insulating film 30 may be greater than 0 μm and 2 μm or less. The thickness of the base insulating film 30 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0134] In this embodiment, the base insulating film 30 has a laminated structure comprising multiple insulating films. Specifically, the base insulating film 30 includes a first base insulating film 31 and a second base insulating film 32, which are laminated in this order from the chip 2 (first main surface 3) side.

[0135] The first base insulating film 31 is made of an insulating film selected from the aforementioned group of insulating films and covers the first main surface 3 in a film-like manner. The first base insulating film 31 covers the well region 22 (pad well region 22A) on the first main surface 3.

[0136] The first base insulating film 31 is connected to the main surface insulating film 25. In this embodiment, the first base insulating film 31 is formed using a portion of the main surface insulating film 25. That is, the first base insulating film 31 contains the same type of insulator (oxide film of chip 2) as the main surface insulating film 25 (insulating film 17) and has a thickness approximately equal to the thickness of the main surface insulating film 25. Of course, the first base insulating film 31 may contain a different insulator than the main surface insulating film 25 and have a thickness different from the thickness of the main surface insulating film 25.

[0137] The second base insulating film 32 is made of an insulating film selected from the aforementioned group of insulating films and is laminated in a film-like manner on the first base insulating film 31. The second base insulating film 32 has a thickness equal to or greater than the thickness of the first base insulating film 31. In this embodiment, the thickness of the second base insulating film 32 is greater than the thickness of the first base insulating film 31.

[0138] The second base insulating film 32 may contain the same type of insulator as the first base insulating film 31, or it may contain a different insulator than the first base insulating film 31. In this embodiment, the second base insulating film 32 consists of an NSG film.

[0139] The second base insulating film 32 covers the well region 22 (pad well region 22A) via the first base insulating film 31. The second base insulating film 32 is formed at intervals from the multiple gate structures 15, and exposes the main surface insulating film 25 (first base insulating film 31) at the periphery of the pad region 9A.

[0140] The base insulating film 30 may have a laminated structure in which three or more (preferably five or fewer) insulating films are stacked. In other words, the base insulating film 30 may include a third base insulating film stacked on top of the second base insulating film 32. The third base insulating film may consist of an insulating film selected from the aforementioned group of insulating films.

[0141] Of course, the base insulating film 30 may also include a fourth base insulating film, a fifth base insulating film, ... an nth base insulating film (where n is a natural number), each consisting of an insulating film selected from the aforementioned group of insulating films, which are laminated on the third base insulating film. From the viewpoint of manufacturing efficiency, it is preferable that the number of layers of the base insulating film 30 be three or less.

[0142] Of course, the base insulating film 30 may have a single-layer structure consisting of a single insulating film selected from the aforementioned group of insulating films. In this case, the base insulating film 30 may be a field insulating film such as a LOCOS film (local oxidation of silicon film). The base insulating film 30 may consist of a main surface insulating film 25.

[0143] The semiconductor device 1A includes a base electrode 35 disposed on the first main surface 3 in a pad region 9A (inactive region 9). The base electrode 35 is provided as a resistor to a plurality of gate structures 15. The base electrode 35 may also be referred to as a "resistive electrode," "resistive film," "gate resistor," "built-in resistor," etc.

[0144] The base electrode 35 may contain a metallic or nonmetallic conductor. The base electrode 35 may contain the same conductor as the embedded electrode 18, or a different conductor than the embedded electrode 18. In this embodiment, the base electrode 35 contains conductive polysilicon. The base electrode 35 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon.

[0145] The base electrode 35 is arranged in a film-like manner on the base insulating film 30 in the pad region 9A. With respect to the second direction Y, the base electrode 35 is biased toward the side opposite to the active region 8 (towards the first side surface 5A) relative to the center of the pad region 9A, and faces both the first active region 8A and the second active region 8B in the first direction X.

[0146] In this embodiment, the base electrode 35 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the base electrode 35 extends in a strip-like (rectangular) shape in the first direction X. The extension direction of the base electrode 35 coincides with the extension direction of the multiple gate structures 15.

[0147] The base electrode 35 has a portion facing the first active region 8A (multiple gate structures 15) with respect to the second direction Y, a portion facing the boundary region 9C, and a portion facing the second active region 8B (multiple gate structures 15).

[0148] The base electrode 35 faces the chip 2 (first main surface 3) via the base insulating film 30. In this embodiment, the base electrode 35 faces the pad well region 22A (pn junction) via the base insulating film 30. The base electrode 35 is spaced apart from the multiple gate structures 15 and does not face the multiple gate structures 15 in the thickness direction Z.

[0149] The base electrode 35 is positioned only on the base insulating film 30, spaced inward from its periphery. In other words, the base electrode 35 is formed in an island shape in plan view and surrounded by the exposed portion of the base insulating film 30. Of course, the base electrode 35 may also have a portion that extends from the base insulating film 30 to the main surface insulating film 25 and is positioned on the main surface insulating film 25.

[0150] The base electrode 35 has an upper surface 35a and side walls 35b. The upper surface 35a of the base electrode 35 extends flat along the base insulating film 30 (first main surface 3). The side walls 35b include a pair of sides (side walls 35b) extending in a first direction X and a pair of sides (side walls 35b) extending in a second direction Y.

[0151] In this configuration, the side wall 35b extends almost perpendicularly to the upper surface 35a. The side wall 35b may also be obliquely inclined from the upper surface 35a toward the base insulating film 30. In other words, the base electrode 35 may be formed in a tapered shape in cross-section.

[0152] The inclination angle of the side wall 35b with respect to the upper surface 35a may be 90° or more and 140° or less. The inclination angle may have a value that falls within at least one of the following ranges: 90° or more and 100° or less, 100° or more and 110° or less, 110° or more and 120° or less, 120° or more and 130° or less, and 130° or more and 140° or less.

[0153] The base electrode 35 has a width greater than the width of the gate structure 15 with respect to the second direction Y. For example, the width of the base electrode 35 may be greater than 0 μm and less than or equal to 500 μm.

[0154] The width of the base electrode 35 may be greater than 0 μm and fall within at least one of the following ranges: 10 μm or less, 10 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, 75 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0155] The ratio of the flat area of ​​the base electrode 35 to the flat area of ​​the pad region 9A (area ratio) may be greater than 0 and between 0.3 and 0.01. The area ratio may have a value that falls within at least one of the following ranges: greater than 0 and between 0.01 and 0.03, between 0.03 and 0.06, between 0.06 and 0.09, between 0.09 and 0.12, between 0.12 and 0.15, between 0.15 and 0.18, between 0.18 and 0.21, between 0.21 and 0.24, between 0.24 and 0.27, and between 0.27 and 0.3.

[0156] The base electrode 35 has a thickness greater than the thickness of the main surface insulating film 25. In this embodiment, the thickness of the base electrode 35 is greater than the thickness of the base insulating film 30. The thickness of the base electrode 35 may be less than the thickness of the base insulating film 30. The thickness of the base electrode 35 may be greater than 0 μm and 2.5 μm or less.

[0157] The thickness of the base electrode 35 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or more and 2 μm or more and 2.25 μm or less.

[0158] The semiconductor device 1A includes a base pad electrode 36 disposed on the first main surface 3 in the pad region 9A (inactive region 9). The base pad electrode 36 may also be referred to as the "second base electrode," etc. The base pad electrode 36 may contain a metallic or non-metallic conductor. The base pad electrode 36 may contain the same conductor as the embedded electrode 18, or a different conductor than the embedded electrode 18.

[0159] The base pad electrode 36 may contain the same conductor as the base electrode 35, or a different conductor from the base electrode 35. In this embodiment, the base pad electrode 36 contains conductive polysilicon. The base pad electrode 36 may contain either or both p-type conductive polysilicon and n-type conductive polysilicon.

[0160] The base pad electrode 36 is arranged in a film-like manner on the base insulating film 30, spaced apart from the base electrode 35, and is adjacent to the base electrode 35. Specifically, the base pad electrode 36 is spaced apart from the base electrode 35 toward the active region 8 side (third side surface 5C side) with respect to the second direction Y. The base pad electrode 36 faces the first active region 8A and the second active region 8B in the first direction X, and faces the base electrode 35 in the second direction Y.

[0161] In this embodiment, the base pad electrode 36 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and has a larger planar area than the base electrode 35. The base pad electrode 36 has a portion facing the first active region 8A (multiple gate structures 15) with respect to the second direction Y, a portion facing the boundary region 9C, and a portion facing the second active region 8B (multiple gate structures 15).

[0162] The ratio of the flat area of ​​the base pad electrode 36 to the flat area of ​​the pad region 9A (area ratio) may be 0.3 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.

[0163] The base pad electrode 36 has a width (length) that is approximately equal to the width (length) of the base electrode 35 with respect to the first direction X. The width (length) of the base pad electrode 36 with respect to the first direction X may be greater than or less than the width (length) of the base electrode 35.

[0164] The base pad electrode 36 has a width (length) that is greater than the width (length) of the base electrode 35 with respect to the second direction Y. The width (length) of the base pad electrode 36 with respect to the second direction Y may be greater than or less than the width (length) of the base electrode 35.

[0165] With respect to the second direction Y, the width ratio (length ratio) of the base pad electrode 36 to the width (length) of the base electrode 35 may be greater than 1 and 100 or less. The width ratio may have a value that falls within at least one of the following ranges: greater than 1 and 10 or less, 10 to 25, 25 to 50, 50 to 75, and 75 to 100.

[0166] The base pad electrode 36 faces the chip 2 (first main surface 3) via the base insulating film 30. In this embodiment, the base pad electrode 36 faces the pad well region 22A (pn junction) via the base insulating film 30. The base pad electrode 36 is spaced apart from the multiple gate structures 15 and does not face the multiple gate structures 15 in the thickness direction Z.

[0167] The base pad electrode 36 is positioned only on the base insulating film 30, spaced inward from its periphery. The base pad electrode 36 may have a portion that extends from the base insulating film 30 to the main surface insulating film 25 and is positioned on the main surface insulating film 25. The base pad electrode 36 may also be positioned outside the base insulating film 30, only on the main surface insulating film 25.

[0168] The base pad electrode 36 has a thickness greater than the thickness of the main surface insulating film 25. In this embodiment, the thickness of the base pad electrode 36 is greater than the thickness of the base insulating film 30. The thickness of the base pad electrode 36 may be less than the thickness of the base insulating film 30.

[0169] The thickness of the base pad electrode 36 is approximately equal to the thickness of the base electrode 35. The thickness of the base pad electrode 36 may be greater than or less than the thickness of the base electrode 35. The thickness of the base pad electrode 36 may be greater than 0 μm and 2.5 μm or less.

[0170] The thickness of the base pad electrode 36 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or more and 2 μm or more and 2.25 μm or less.

[0171] The semiconductor device 1A includes line electrodes 40 selectively routed on the first main surface 3 in an inactive region 9. The line electrodes 40 may also be referred to as "underlayment wiring electrodes," "planar wiring," etc. The line electrodes 40 may contain a metallic or non-metallic conductor. The line electrodes 40 may contain the same conductor as the embedded electrode 18, or a different conductor than the embedded electrode 18.

[0172] The line electrode 40 may contain the same conductor as the base electrode 35, or a different conductor than the base electrode 35. The line electrode 40 may contain the same conductor as the base pad electrode 36, or a different conductor than the base pad electrode 36.

[0173] In this embodiment, the line electrode 40 includes conductive polysilicon. The line electrode 40 may include either or both p-type conductive polysilicon and n-type conductive polysilicon.

[0174] The line electrode 40 is selectively routed on the main surface insulating film 25 at a distance from the base electrode 35 and the base pad electrode 36, and is electrically connected to a plurality of gate structures 15 on the first active region 8A side and a plurality of gate structures 15 on the second active region 8B side. Depending on the layout of the base insulating film 30, the line electrode 40 may be positioned on the base insulating film 30, or it may have a portion positioned on the base insulating film 30.

[0175] The line electrode 40 has a thickness greater than the thickness of the main surface insulating film 25. In this embodiment, the thickness of the line electrode 40 is greater than the thickness of the base insulating film 30. The thickness of the line electrode 40 may be less than the thickness of the base insulating film 30.

[0176] The thickness of the line electrode 40 is approximately equal to the thickness of the base electrode 35. The thickness of the line electrode 40 may be greater than or less than the thickness of the base electrode 35. The thickness of the line electrode 40 is approximately equal to the thickness of the base pad electrode 36. The thickness of the line electrode 40 may be greater than 0 μm and 2.5 μm or less.

[0177] The thickness of the line electrode 40 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or more and 2 μm or more and 2.25 μm or less.

[0178] In this embodiment, the line electrode 40 includes a first line portion 41, a second line portion 42, a third line portion 43, a fourth line portion 44, and a fifth line portion 45.

[0179] The first line portion 41 is positioned in the outer region 9B with a gap in the second direction Y, on the opposite side from the base electrode 35 to the active region 8 (towards the first side surface 5A), and is adjacent to the base electrode 35 in the second direction Y.

[0180] The first line portion 41 is positioned on the main surface insulating film 25 and faces the chip 2 (first main surface 3) via the main surface insulating film 25. Depending on the layout of the base insulating film 30, the first line portion 41 may be positioned on the base insulating film 30, or it may have a portion positioned on the base insulating film 30.

[0181] The first line portion 41 extends in a strip shape in a first direction X following the extending direction of the base electrode 35, and faces the entire area of ​​the base electrode 35 in a second direction Y. In this embodiment, the first line portion 41 faces the base pad electrode 36 via the base electrode 35 in the second direction Y. In this embodiment, the first line portion 41 has a width less than the width of the base electrode 35 with respect to the second direction Y. The width of the first line portion 41 may be greater than the width of the base electrode 35.

[0182] The first line portion 41 is positioned at an inward spacing from the multiple field regions 24. The first line portion 41 is positioned at an inward spacing from the outer edge of the outer well region 22B and faces the outer well region 22B in the thickness direction Z.

[0183] In this configuration, the first line portion 41 is positioned at a distance inward from the outer edge of the outer contact region 23 and faces the outer contact region 23 in the thickness direction Z. The first line portion 41 does not necessarily have to face the outer contact region 23 in the thickness direction Z.

[0184] The second line portion 42 is drawn out from the first line portion 41 toward the first active region 8A on the main surface insulating film 25 and extends in a strip shape along the outer region 9B. The second line portion 42 faces the chip 2 (first main surface 3) via the main surface insulating film 25. Depending on the layout of the base insulating film 30, the second line portion 42 may be positioned on the base insulating film 30 or may have a portion positioned on the base insulating film 30.

[0185] The second line portion 42 is positioned at an inward spacing from the multiple field regions 24. The second line portion 42 is positioned at an inward spacing from the outer edge of the outer well region 22B and faces the outer well region 22B in the thickness direction Z.

[0186] In this configuration, the second line portion 42 is positioned at a distance from the outer edge of the outer contact region 23 and faces the outer contact region 23 in the thickness direction Z. The second line portion 42 does not necessarily have to face the outer contact region 23 in the thickness direction Z.

[0187] The second line portion 42 has a portion that extends in a first direction X along the first active region 8A and a portion that extends in a second direction Y along the first active region 8A. The portion of the second line portion 42 that extends in the second direction Y is drawn out from the outer region 9B to the first active region 8A and is connected to the ends of the plurality of gate structures 15.

[0188] Specifically, the second line portion 42 extends from above the main surface insulating film 25 into a plurality of trenches 16 and is mechanically and electrically connected to a plurality of embedded electrodes 18 within the plurality of trenches 16. In this configuration, the second line portion 42 (line electrode 40) is formed integrally with the plurality of embedded electrodes 18 as a lead electrode (lead wire).

[0189] The third line portion 43 is drawn out from the first line portion 41 toward the second active region 8B on the main surface insulating film 25 and extends in a strip shape along the outer region 9B. The third line portion 43 faces the chip 2 (first main surface 3) via the main surface insulating film 25. Depending on the layout of the base insulating film 30, the third line portion 43 may be positioned on the base insulating film 30 or may have a portion positioned on the base insulating film 30.

[0190] The third line portion 43 is positioned at an inward spacing from the multiple field regions 24. The third line portion 43 is positioned at an inward spacing from the outer edge of the outer well region 22B and faces the outer well region 22B in the thickness direction Z.

[0191] In this configuration, the third line portion 43 is positioned at a distance from the outer edge of the outer contact region 23 and faces the outer contact region 23 in the thickness direction Z. The third line portion 43 does not necessarily have to face the outer contact region 23 in the thickness direction Z.

[0192] The third line portion 43 has a portion that extends in a first direction X along the second active region 8B and a portion that extends in a second direction Y along the second active region 8B. The portion of the third line portion 43 that extends in the second direction Y is drawn out from the outer region 9B to the second active region 8B and connected to the ends of the plurality of gate structures 15.

[0193] Specifically, the third line portion 43 extends from above the main surface insulating film 25 into a plurality of trenches 16 and is mechanically and electrically connected to a plurality of embedded electrodes 18 within the plurality of trenches 16. In this configuration, the third line portion 43 (line electrode 40) is formed integrally with the plurality of embedded electrodes 18 as a lead electrode (lead wire).

[0194] The fourth line portion 44 is drawn out in a strip shape from the first line portion 41 toward the boundary region 9C on the main surface insulating film 25 and extends in a strip shape along the periphery of the pad region 9A. The fourth line portion 44 faces the chip 2 (first main surface 3) via the main surface insulating film 25. Depending on the layout of the base insulating film 30, the fourth line portion 44 may be positioned on the base insulating film 30 or may have a portion positioned on the base insulating film 30.

[0195] The fourth line portion 44 is routed at a distance from the base electrode 35 and the base pad electrode 36 and faces the pad well region 22A in the thickness direction Z. In this configuration, the fourth line portion 44 extends in a strip shape from one end of the first line portion 41 along the periphery of the pad region 9A and is connected to the other end of the first line portion 41.

[0196] In other words, the fourth line portion 44, together with the first line portion 41, is formed in an annular shape (a rectangular annular shape in this configuration) that surrounds the base electrode 35 and the base pad electrode 36, and defines the pad region 9A. Specifically, the fourth line portion 44 has a first portion 44A, a second portion 44B, and a third portion 44C.

[0197] The first portion 44A is drawn out in a strip shape in the second direction Y from one end of the first line portion 41 on the first active region 8A side. The first portion 44A is positioned at a distance from the base electrode 35 and the base pad electrode 36 in the first direction X, and faces the base electrode 35 and the base pad electrode 36 in the first direction X.

[0198] The second portion 44B is drawn out in a strip shape in the second direction Y from the other end of the first line portion 41 on the second active region 8B side. The second portion 44B is positioned at a distance from the base electrode 35 and the base pad electrode 36 in the first direction X, and faces the first portion 44A in the first direction X via the base electrode 35 and the base pad electrode 36.

[0199] The third portion 44C extends in a strip shape in the first direction X in the region on the boundary region 9C side, connecting the end of the first portion 44A and the end of the second portion 44B. The third portion 44C is positioned at a distance from the base pad electrode 36 in the second direction Y, and faces the first line portion 41 in the second direction Y via the base electrode 35 and the base pad electrode 36.

[0200] The fourth line portion 44 (first portion 44A) is drawn out from the pad region 9A to the first active region 8A and connected to the ends of the multiple gate structures 15 on the first active region 8A side. Specifically, the fourth line portion 44 enters into the multiple trenches 16 from above the main surface insulating film 25 in the first active region 8A and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16. In this embodiment, the fourth line portion 44 (line electrode 40) is formed integrally with the multiple embedded electrodes 18 as a lead electrode (lead wire).

[0201] The fourth line portion 44 (second portion 44B) is drawn out from the pad region 9A to the second active region 8B and connected to the ends of the multiple gate structures 15 on the second active region 8B side. Specifically, the fourth line portion 44 enters into the multiple trenches 16 from above the main surface insulating film 25 in the second active region 8B and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16. In this embodiment, the fourth line portion 44 (line electrode 40) is formed integrally with the multiple embedded electrodes 18 as a lead electrode (lead wire).

[0202] The fifth line portion 45 is drawn out in a strip shape from the fourth line portion 44 (third portion 44C) to the boundary region 9C on the main surface insulating film 25 and is electrically connected to the first line portion 41 via the fourth line portion 44.

[0203] The fifth line portion 45 faces the chip 2 (first main surface 3) via the main surface insulating film 25. Depending on the layout of the base insulating film 30, the fifth line portion 45 may be positioned on the base insulating film 30, or it may have a portion positioned on the base insulating film 30. The fifth line portion 45 extends in a strip shape in the second direction Y following the extending direction of the boundary region 9C, and faces the boundary well region 22C in the thickness direction Z.

[0204] The fifth line section 45 is drawn out from the boundary region 9C to the first active region 8A and connected to the ends of the multiple gate structures 15 on the first active region 8A side. Specifically, the fifth line section 45 enters into the multiple trenches 16 from above the main surface insulating film 25 in the first active region 8A and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16. In this configuration, the fifth line section 45 (line electrode 40) is formed integrally with the multiple embedded electrodes 18 as a lead-out electrode (lead-out wiring).

[0205] The fifth line section 45 is drawn out from the boundary region 9C to the second active region 8B and connected to the ends of the multiple gate structures 15 on the second active region 8B side. Specifically, the fifth line section 45 enters into the multiple trenches 16 from above the main surface insulating film 25 in the second active region 8B and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16. In this embodiment, the fifth line section 45 (line electrode 40) is formed integrally with the multiple embedded electrodes 18 as a lead-out electrode (lead-out wiring).

[0206] The semiconductor device 1A includes an insulating interlayer film 46 that selectively covers the first main surface 3. The interlayer film 46 may also be called an "interlayer insulating film," "intermediate insulating film," etc. The interlayer film 46 may have a single-layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0207] The interlayer film 46 may include at least one of the following: an NSG film, a PSG film, a BPSG film, and a TEOS film. The interlayer film 46 may include the same type of insulator as the base insulating film 30, or it may include a different insulator than the base insulating film 30.

[0208] The interlayer film 46 covers the main surface insulating film 25 in active regions 8 and inactive regions 9. In the active region 8, the interlayer film 46 penetrates multiple trenches 16 from above the main surface insulating film 25 and covers multiple embedded electrodes 18 within the multiple trenches 16.

[0209] The interlayer film 46 covers the well region 22, the outer contact region 23, and multiple field regions 24 via the main surface insulating film 25 in the inactive region 9. In the inactive region 9, the interlayer film 46 covers the base pad electrode 36, the base electrode 35, and the line electrode 40 on top of the main surface insulating film 25.

[0210] The interlayer film 46 has a portion that covers the main surface insulating film 25 in the pad region 9A and a portion that covers the base insulating film 30. The interlayer film 46 covers the pad well region 22A via the main surface insulating film 25 and covers the pad well region 22A via the base insulating film 30.

[0211] The interlayer film 46 covers the base pad electrode 36, the base electrode 35, and a portion of the line electrode 40 (the fourth line portion 44) in the pad region 9A. In this configuration, the interlayer film 46 covers the base electrode 35 and the base pad electrode 36 on the base insulating film 30, and covers a portion of the line electrode 40 (the fourth line portion 44) on the main surface insulating film 25.

[0212] The interlayer film 46 covers the outer well region 22B, the outer contact region 23, and multiple field regions 24 via the main surface insulating film 25 in the outer region 9B. In the outer region 9B, the interlayer film 46 covers a portion of the line electrode 40 (first line portion 41, second line portion 42, and third line portion 43) on the main surface insulating film 25.

[0213] The interlayer film 46 covers the boundary well region 22C via the main surface insulating film 25 in the boundary region 9C. The interlayer film 46 covers a part of the line electrode 40 (the fifth line portion 45) in the boundary region 9C. The interlayer film 46 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. The interlayer film 46 may be formed with a gap inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0214] The interlayer film 46 has a thickness greater than the thickness of the main surface insulating film 25. In this embodiment, the thickness of the interlayer film 46 is greater than the thickness of the base insulating film 30. The thickness of the interlayer film 46 may be less than the thickness of the base insulating film 30. In this embodiment, the thickness of the interlayer film 46 is greater than the thickness of the base electrode 35. The thickness of the interlayer film 46 may be less than the thickness of the base electrode 35.

[0215] The thickness of the interlaminar film 46 may be greater than 0 μm and 3 μm or less. The thickness of the interlaminar film 46 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0216] The semiconductor device 1A includes one or more (in this embodiment, more) first base via electrodes 50 embedded in the interlayer film 46 in a pad region 9A. The first base via electrodes 50 may also be referred to as "pad via electrodes" or "first via electrodes". The plurality of first base via electrodes 50 are metallic embeddings relative to the base electrode 35. The plurality of first base via electrodes 50 have a resistivity lower than that of the base electrode 35.

[0217] The number of first base via electrodes 50 may be between 1 and 20. The number of first base via electrodes 50 is the number of first base via electrodes 50 that appear when the base electrode 35 is cut in the second direction Y.

[0218] The number of first base via electrodes 50 may be a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, and 15 to 20. In this embodiment, semiconductor device 1A includes 3 first base via electrodes 50.

[0219] Multiple first base via electrodes 50 penetrate the interlayer film 46 and are mechanically and electrically connected to one end of the base electrode 35 (the inner end of the first main surface 3). In this configuration, the multiple first base via electrodes 50 are unevenly distributed towards one end of the base electrode 35 relative to the central part of the base electrode 35.

[0220] Multiple first base via electrodes 50 each extend in a strip shape in a first direction X, following the extending direction of the base electrode 35, and are arranged with gaps in the second direction Y. The extending direction of the multiple first base via electrodes 50 coincides with the extending direction of the multiple gate structures 15.

[0221] The first base via electrode 50 has a width less than the thickness of the interlayer film 46 and an aspect ratio that extends vertically in the thickness direction Z of the interlayer film 46. Alternatively, the first base via electrode 50 may have a width greater than the thickness of the interlayer film 46 and an aspect ratio that extends horizontally in the width direction of the interlayer film 46.

[0222] The width of the first base via electrode 50 may be greater than or less than the width of the gate structure 15. The width of the first base via electrode 50 may be greater than or less than the spacing of the gate structure 15. The width of the first base via electrode 50 may be greater than 0 μm and 2 μm or less.

[0223] The width of the first base via electrode 50 may be greater than 0 μm and fall within at least one of the following ranges: 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0224] In this embodiment, the spacing between the multiple first base via electrodes 50 is greater than the width of the first base via electrode 50. The spacing between the first base via electrodes 50 may be smaller than the width of the first base via electrode 50. The spacing between the first base via electrodes 50 may be greater than or smaller than the width of the gate structure 15. The spacing between the first base via electrodes 50 may be greater than or smaller than the spacing of the gate structure 15.

[0225] The spacing of the first base via electrodes 50 may be greater than 0 μm and 5 μm or less. The spacing of the first base via electrodes 50 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0226] Multiple first base via electrodes 50 intersect (specifically orthogonally) with at least one of the two side walls 35b of the base electrode 35 on both sides in the first direction X (two side walls 35b extending in the second direction Y). In this embodiment, the multiple first base via electrodes 50 have a length greater than the length of the base electrode 35 and intersect (specifically orthogonally) with the two side walls 35b of the base electrode 35.

[0227] Each of the multiple first base via electrodes 50 has a first connection portion 51 connected to the upper surface 35a of the base electrode 35, and one or more (in this embodiment, a pair) second connection portions 52 connected to the side wall 35b of the base electrode 35. Since the configuration of one and the other second connection portion 52 are the same, the configuration of one second connection portion 52 will be described below.

[0228] The first connecting portion 51 extends in a strip shape in a first direction X on the upper surface 35a of the base electrode 35, dividing the base electrode 35 into a region on one side of the second direction Y (the inner side of the first main surface 3) and a region on the other side of the second direction Y (the peripheral side of the first main surface 3). The first connecting portion 51 has a lower end connected to the base electrode 35.

[0229] The lower end of the first connecting portion 51 is located on the base insulating film 30 side of the height position of the upper surface 35a of the base electrode 35. The lower end of the first connecting portion 51 is formed with a gap from the middle thickness position of the base electrode 35 toward the upper surface 35a of the base electrode 35. The lower end of the first connecting portion 51 may be formed at a height position approximately equal to the upper surface 35a of the base electrode 35.

[0230] The second connecting portion 52 extends from the first connecting portion 51 across the side wall 35b of the base electrode 35 to the outside of the base electrode 35. The second connecting portion 52 extends in a strip shape in the first direction X, following the extending direction of the first connecting portion 51. The second connecting portion 52 extends in the thickness direction Z along the side wall 35b of the base electrode 35. In cross-sectional view, the second connecting portion 52 covers almost the entire area of ​​the side wall 35b of the base electrode 35.

[0231] The second connection portion 52 has a lower end that is connected to the base insulating film 30 at the lower end of the side wall 35b of the base electrode 35. The lower end of the second connection portion 52 faces the chip 2 (pad well region 22A) via a portion of the base insulating film 30. Specifically, the lower end of the second connection portion 52 is located on the first main surface 3 side of the height of the insulating surface of the base insulating film 30 and faces the chip 2 (first main surface 3) via a portion of the base insulating film 30.

[0232] In other words, the lower end of the second connection portion 52 is located below the lower end of the side wall 35b. To put it another way, the lower end of the second connection portion 52 is located on the first main surface 3 side of the height position of the connection interface between the base insulating film 30 and the base electrode 35. The lower end of the second connection portion 52 is formed with a gap from the middle thickness position of the base insulating film 30 towards the insulating surface side of the base insulating film 30.

[0233] In this configuration, the lower end of the second connecting portion 52 is formed within the thickness range of the second base insulating film 32, spaced apart from the thickness position of the first base insulating film 31 (main surface insulating film 25). In other words, the lower end of the second connecting portion 52 does not penetrate the second base insulating film 32.

[0234] Of course, the lower end of the second connection portion 52 may penetrate the second base insulating film 32 and be connected to the first base insulating film 31. The lower end of the second connection portion 52 may be formed at a height approximately equal to the insulating surface of the base insulating film 30.

[0235] The second connecting portion 52 has a width that is approximately equal to the width of the first connecting portion 51 with respect to the second direction Y. The width of the second connecting portion 52 may be greater than or less than the width of the first connecting portion 51. Preferably, the second connecting portion 52 has a protrusion amount that is greater than or equal to the width of the first connecting portion 51 (first base via electrode 50).

[0236] The amount of protrusion of the second connection portion 52 is the length of the second connection portion 52 in the first direction X, with the side wall 35b of the base electrode 35 as the reference (zero point). In this configuration, the amount of protrusion of the second connection portion 52 is greater than the width of the first connection portion 51. Of course, the amount of protrusion of the second connection portion 52 may be less than the width of the first connection portion 51.

[0237] The protrusion amount of the second connection portion 52 may be greater than 0 μm and 5 μm or less. The protrusion amount of the second connection portion 52 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0238] The first base via electrode 50 has an electrode surface exposed from the insulating surface of the interlayer film 46. The electrode surface is formed with a gap between it and the base electrode 35 at the height of the insulating surface of the interlayer film 46, exposing the insulating surface of the interlayer film 46.

[0239] The electrode surface may have a recess on the first connection portion 51 side toward the base electrode 35 side, and a recess on the second connection portion 52 side toward the base insulating film 30. The recess on the second connection portion 52 side may be deeper than the recess on the first connection portion 51 side.

[0240] Multiple first base via electrodes 50 are embedded in multiple first via openings 53 formed in the interlayer film 46. The first via openings 53 form the walls of the first base via electrodes 50 and are partitioned by the base insulating film 30, the base electrode 35, and the interlayer film 46. The width of the first base via electrodes 50 corresponds to the opening width of the first via openings 53.

[0241] The first via opening 53 has an opening wall partitioned by the interlayer film 46, and a bottom wall partitioned by the base insulating film 30 and the base electrode 35. In this embodiment, the opening wall is formed substantially perpendicular to the insulating surface of the interlayer film 46. The opening wall may also be inclined downwards from the insulating surface of the interlayer film 46 toward the base electrode 35. In other words, the first base via electrode 50 may be formed in a tapered shape (narrowing shape) in cross-section.

[0242] The bottom wall is partitioned by the insulating surface of the base insulating film 30, the upper surface 35a of the base electrode 35, and the side wall 35b of the base electrode 35, and has a stepped portion partitioned between the base insulating film 30 and the base electrode 35 by the side wall 35b of the base electrode 35.

[0243] The bottom wall has a bottom wall portion for a first connection portion 51, which is partitioned on the upper surface 35a of the base electrode 35, and a bottom wall portion for a second connection portion 52, which is partitioned on the insulating surface of the base insulating film 30. In this configuration, the bottom wall portion for the first connection portion 51 is partitioned on the upper surface 35a of the base electrode 35 by a first recess that is recessed in the thickness direction Z. The presence or absence of the first recess is optional.

[0244] The bottom wall portion for the second connection portion 52 is partitioned between the side wall 35b of the base electrode 35 and the wall surface of the interlayer film 46. In this configuration, the bottom wall portion for the second connection portion 52 is partitioned by a second recess that is recessed in the thickness direction Z on the insulating surface of the base insulating film 30. The presence or absence of the second recess is optional.

[0245] The first base via electrode 50 is mechanically and electrically connected to the base electrode 35 within the first via opening 53. Specifically, the first base via electrode 50 covers the base insulating film 30, the upper surface 35a and the side wall 35b of the base electrode 35 within the first via opening 53, and is mechanically and electrically connected to the upper surface 35a and the side wall 35b of the base electrode 35.

[0246] The first base via electrode 50 may have a single-layer structure consisting of a single metal film, or a multilayer structure including multiple metal films. The first base via electrode 50 may include a metal film containing at least one of aluminum (Al)-based metals, titanium (Ti)-based metals, nickel (Ni)-based metals, copper (Cu)-based metals, molybdenum (Mo)-based metals, and tungsten (W)-based metals.

[0247] The first base via electrode 50 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, and tungsten. The first base via electrode 50 may also include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, and tungsten alloy.

[0248] In this embodiment, the first base via electrode 50 has a laminated structure including a via base electrode 54 and a via body electrode 55, which are stacked in this order from the wall side of the first via opening 53. The via base electrode 54 is formed as a barrier electrode to the base electrode 35 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0249] In this embodiment, the via substrate electrode 54 has a laminated structure including a first substrate electrode 56 and a second substrate electrode 57. The first substrate electrode 56 consists of a metal film containing any one of the aforementioned metals, or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first substrate electrode 56 consists of a titanium-based metal film (titanium film).

[0250] The first base electrode 56 covers the wall surface of the first via opening 53 in a film-like manner. The first base electrode 56 has a portion that covers the base insulating film 30 in a film-like manner, a portion that covers the upper surface 35a of the base electrode 35 in a film-like manner, a portion that covers the side wall 35b of the base electrode 35 in a film-like manner, and a portion that covers the interlayer film 46 in a film-like manner.

[0251] The first base electrode 56 is mechanically and electrically connected to the upper surface 35a and side wall 35b of the base electrode 35. The first base electrode 56 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the first via opening 53, and forms the edge of the electrode surface of the first base via electrode 50.

[0252] The first base electrode 56 has a thickness less than the thickness of the interlayer film 46. The thickness of the first base electrode 56 is less than the thickness of the base electrode 35. The thickness of the first base electrode 56 is less than half the opening width of the first via opening 53. The thickness of the first base electrode 56 may be greater than 0 nm and 200 nm or less.

[0253] The thickness of the first substrate electrode 56 may be greater than 0 nm and fall within at least one of the following ranges: 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, and 150 nm or more and 200 nm or less.

[0254] The second base electrode 57 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second base electrode 57 consists of a different metal film or alloy film than the first base electrode 56. In this embodiment, the second base electrode 57 consists of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film).

[0255] The second base electrode 57 covers the wall surface of the first via opening 53 in a film-like manner via the first base electrode 56. The second base electrode 57 has a portion that covers the base insulating film 30 in a film-like manner via the first base electrode 56, a portion that covers the upper surface 35a of the base electrode 35 in a film-like manner via the first base electrode 56, a portion that covers the side wall 35b of the base electrode 35 in a film-like manner via the first base electrode 56, and a portion that covers the interlayer film 46 in a film-like manner via the first base electrode 56.

[0256] The second base electrode 57 is electrically connected to the upper surface 35a and side wall 35b of the base electrode 35 via the first base electrode 56. The second base electrode 57 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the first via opening 53, and forms the edge of the electrode surface of the first base via electrode 50.

[0257] The second base electrode 57 has a thickness less than the thickness of the interlayer film 46. The thickness of the second base electrode 57 is less than the thickness of the base electrode 35. The thickness of the second base electrode 57 is less than half the opening width of the first via opening 53.

[0258] In this embodiment, the thickness of the second base electrode 57 is greater than the thickness of the first base electrode 56. The thickness of the second base electrode 57 may be less than the thickness of the first base electrode 56. The thickness of the second base electrode 57 may be greater than 0 nm and 300 nm or less.

[0259] The thickness of the second substrate electrode 57 may be greater than 0 nm and fall within at least one of the following ranges: 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or more and 300 nm or less.

[0260] The via body electrode 55 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The via body electrode 55 is made of a different conductor than the first base electrode 56 and the second base electrode 57. In this embodiment, the via body electrode 55 is made of a tungsten-based metal (tungsten or tungsten alloy). Due to its physical properties, the tungsten-based metal can be embedded in the first via opening 53 at a relatively high density.

[0261] The via body electrode 55 is embedded in the first via opening 53 via a via base electrode 54 as the main body of the first base via electrode 50. The via body electrode 55 faces the bottom wall and the opening wall of the first via opening 53 via the via base electrode 54.

[0262] The via body electrode 55 has a portion that covers the base insulating film 30 via the via under electrode 54, a portion that covers the upper surface 35a of the base electrode 35 via the via under electrode 54, a portion that covers the side wall 35b of the base electrode 35 via the via under electrode 54, and a portion that covers the interlayer film 46 via the via under electrode 54.

[0263] The via body electrode 55 has a portion sandwiched between the side wall 35b of the base electrode 35 and the wall surface of the interlayer film 46 on the base insulating film 30. The via body electrode 55 is electrically connected to the upper surface 35a and side wall 35b of the base electrode 35 via the via under electrode 54. The via body electrode 55 is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, and forms the electrode surface of the first base via electrode 50.

[0264] The semiconductor device 1A includes one or more (in this embodiment, more) second base via electrodes 60 embedded in the interlayer film 46 in the pad region 9A. The second base via electrodes 60 may also be referred to as "wiring via electrodes" or "second via electrodes".

[0265] The cross-sectional views of the first base via electrode 50 shown in Figures 13 to 15 also apply to the configuration of the second base via electrode 60. In this case, the specific configuration of the second base via electrode 60 can be obtained by replacing the reference numerals for the first base via electrode 50 with the reference numerals for the second base via electrode 60 in Figures 13 to 15.

[0266] The multiple second base via electrodes 60 are metal embedded in the base electrode 35. The multiple second base via electrodes 60 have a resistivity lower than that of the base electrode 35. The resistivity of the second base via electrodes 60 may be approximately equal to that of the first base via electrode 50. The resistivity of the second base via electrodes 60 may be higher or lower than that of the first base via electrode 50.

[0267] The number of second base via electrodes 60 may be between 1 and 20. The number of second base via electrodes 60 is the number of second base via electrodes 60 that appear when the base electrode 35 is cut in the second direction Y.

[0268] The number of second base via electrodes 60 may be a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, and 15 to 20. In this embodiment, semiconductor device 1A includes 3 second base via electrodes 60.

[0269] The number of second base via electrodes 60 is preferably the same as the number of first base via electrodes 50. Of course, the number of second base via electrodes 60 may be more or less than the number of first base via electrodes 50.

[0270] Multiple second base via electrodes 60 penetrate the interlayer film 46 at intervals from multiple first base via electrodes 50 toward the other end of the base electrode 35 (the peripheral end of the first main surface 3), and are mechanically and electrically connected to the other end of the base electrode 35. In this configuration, the multiple second base via electrodes 60 are unevenly distributed toward the other end of the base electrode 35 relative to the central part of the base electrode 35.

[0271] Multiple second base via electrodes 60 are electrically connected to multiple first base via electrodes 50 via a portion of the base electrode 35, and together with the multiple first base via electrodes 50, they form a gate resistance Rg (wiring resistance) consisting of a portion of the base electrode 35.

[0272] The multiple second base via electrodes 60 each extend in a strip shape in the first direction X, following the extending direction of the base electrode 35, and are arranged with gaps in the second direction Y. The multiple second base via electrodes 60 coincide with the extending direction of the multiple gate structures 15 and the extending direction of the multiple first base via electrodes 50.

[0273] The second base via electrode 60 has a width less than the thickness of the interlaminar film 46 and an aspect ratio that extends vertically in the thickness direction Z of the interlaminar film 46. The second base via electrode 60 may have a width greater than the thickness of the interlaminar film 46 and an aspect ratio that extends horizontally in the width direction of the interlaminar film 46.

[0274] The width of the second base via electrode 60 may be greater than or less than the width of the gate structure 15. The width of the second base via electrode 60 may be greater than or less than the spacing of the gate structure 15. The width of the second base via electrode 60 is approximately equal to the width of the first base via electrode 50. The width of the second base via electrode 60 may be greater than or less than the width of the first base via electrode 50.

[0275] The width of the second base via electrode 60 may be greater than 0 μm and less than or equal to 2 μm. The width of the second base via electrode 60 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, and 1.75 μm or more and less than or equal to 2 μm.

[0276] In this embodiment, the spacing between the multiple second base via electrodes 60 is greater than the width of the second base via electrode 60. The spacing between the multiple second base via electrodes 60 may also be smaller than the width of the second base via electrode 60. In this embodiment, the spacing between the multiple second base via electrodes 60 is greater than the width of the first base via electrode 50. The spacing between the multiple second base via electrodes 60 may also be smaller than the width of the first base via electrode 50.

[0277] The spacing of the second base via electrodes 60 is approximately equal to the spacing of the first base via electrodes 50. The spacing of the second base via electrodes 60 may be larger or smaller than the spacing of the first base via electrodes 50. The spacing of the second base via electrodes 60 may be larger or smaller than the width of the gate structure 15. The spacing of the second base via electrodes 60 may be larger or smaller than the spacing of the gate structure 15.

[0278] The spacing of the second base via electrodes 60 may be greater than 0 μm and 5 μm or less. The spacing of the second base via electrodes 60 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0279] Multiple second base via electrodes 60 intersect (specifically orthogonally) with at least one of the two side walls 35b of the base electrode 35 on both sides in the first direction X (two side walls 35b extending in the second direction Y). In this embodiment, the multiple second base via electrodes 60 have a length greater than the length of the base electrode 35 and intersect (specifically orthogonally) with the two side walls 35b of the base electrode 35.

[0280] Each of the multiple second base via electrodes 60 has a third connection portion 61 to the upper surface 35a of the base electrode 35, and one or more (in this embodiment, a pair) fourth connection portions 62 to the side wall 35b of the base electrode 35. Since the configuration of one and the other fourth connection portion 62 is the same, the configuration of one fourth connection portion 62 will be described below.

[0281] The third connecting portion 61 extends in a strip shape in the first direction X on the upper surface 35a of the base electrode 35, dividing the base electrode 35 into a region on one side of the second direction Y (the inner side of the first main surface 3) and a region on the other side of the second direction Y (the peripheral side of the first main surface 3).

[0282] The third connection portion 61 faces the first connection portion 51 of the first base via electrode 50 in the second direction Y along the upper surface 35a of the base electrode 35. The third connection portion 61 is electrically connected to the first connection portion 51 and the second connection portion 52 of the first base via electrode 50 via the base electrode 35.

[0283] The third connecting portion 61 has a lower end connected to the base electrode 35. The lower end of the third connecting portion 61 is located on the base insulating film 30 side of the height position of the upper surface 35a of the base electrode 35. The lower end of the third connecting portion 61 is formed with a gap from the middle thickness position of the base electrode 35 toward the upper surface 35a of the base electrode 35.

[0284] The lower end of the third connecting portion 61 may be located at a depth approximately equal to that of the lower end of the first connecting portion 51. The depth of the lower end of the third connecting portion 61 may be greater or less than that of the lower end of the first connecting portion 51. The lower end of the third connecting portion 61 may be formed at a height approximately equal to that of the upper surface 35a of the base electrode 35.

[0285] The fourth connecting portion 62 extends from the third connecting portion 61 across the side wall 35b of the base electrode 35 to the outside of the base electrode 35. The fourth connecting portion 62 extends in a strip shape in the first direction X, following the extending direction of the third connecting portion 61. The fourth connecting portion 62 extends in the thickness direction Z along the side wall 35b of the base electrode 35. In cross-sectional view, the fourth connecting portion 62 covers almost the entire side wall 35b of the base electrode 35.

[0286] The fourth connection portion 62 faces the second connection portion 52 of the first base via electrode 50 in the second direction Y along the side wall 35b of the base electrode 35. The fourth connection portion 62 is electrically connected to the first connection portion 51 and the second connection portion 52 of the first base via electrode 50 via the base electrode 35.

[0287] The fourth connection portion 62 has a lower end that is connected to the base insulating film 30 at the lower end of the side wall 35b of the base electrode 35. The lower end of the fourth connection portion 62 faces the chip 2 (pad well region 22A) via a part of the base insulating film 30. Specifically, the lower end of the fourth connection portion 62 is located on the first main surface 3 side of the height of the insulating surface of the base insulating film 30 and faces the chip 2 (first main surface 3) via a part of the base insulating film 30.

[0288] In other words, the lower end of the fourth connection portion 62 is located below the lower end of the side wall 35b. To put it another way, the lower end of the fourth connection portion 62 is located on the first main surface 3 side of the height position of the connection interface between the base insulating film 30 and the base electrode 35. The lower end of the fourth connection portion 62 is formed with a gap from the intermediate thickness position of the base insulating film 30 towards the insulating surface side of the base insulating film 30.

[0289] In this configuration, the lower end of the fourth connecting portion 62 is formed within the thickness range of the second base insulating film 32, spaced apart from the thickness position of the first base insulating film 31 (main surface insulating film 25). In other words, the lower end of the fourth connecting portion 62 does not penetrate the second base insulating film 32. Of course, the lower end of the fourth connecting portion 62 may penetrate the second base insulating film 32 and be connected to the first base insulating film 31.

[0290] The lower end of the fourth connection portion 62 may be located at a depth approximately equal to that of the lower end of the second connection portion 52. The depth of the lower end of the fourth connection portion 62 may be greater or less than that of the lower end of the second connection portion 52. The lower end of the fourth connection portion 62 may be formed at a height approximately equal to that of the insulating surface of the base insulating film 30.

[0291] Preferably, the fourth connection portion 62 has a protrusion amount greater than or equal to the width of the third connection portion 61 (second base via electrode 60). The protrusion amount of the fourth connection portion 62 is the length of the fourth connection portion 62 in the first direction X, with the side wall 35b of the base electrode 35 as the reference (zero point). In this configuration, the protrusion amount of the fourth connection portion 62 is greater than the width of the third connection portion 61. Of course, the protrusion amount of the fourth connection portion 62 may be less than the width of the third connection portion 61.

[0292] The protrusion amount of the fourth connection portion 62 is preferably greater than or equal to the width of the first connection portion 51 (first base via electrode 50). In this configuration, the protrusion amount of the fourth connection portion 62 is greater than the width of the first connection portion 51. Of course, the protrusion amount of the fourth connection portion 62 may be less than the width of the first connection portion 51. The protrusion amount of the fourth connection portion 62 is approximately equal to the protrusion amount of the second connection portion 52. The protrusion amount of the fourth connection portion 62 may be greater than or less than the protrusion amount of the second connection portion 52.

[0293] The protrusion amount of the fourth connecting portion 62 may be greater than 0 μm and 5 μm or less. The protrusion amount of the fourth connecting portion 62 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0294] The second base via electrode 60 has an electrode surface exposed from the insulating surface of the interlayer film 46. The electrode surface is formed with a gap between it and the base electrode 35 at the height of the insulating surface of the interlayer film 46, exposing the insulating surface of the interlayer film 46.

[0295] The electrode surface may have a recess on the third connection portion 61 side toward the base electrode 35 side, and a recess on the fourth connection portion 62 side toward the base insulating film 30. The recess on the fourth connection portion 62 side may be deeper than the recess on the third connection portion 61 side.

[0296] Multiple second base via electrodes 60 are embedded in multiple second via openings 63 formed in the interlayer film 46. The second via openings 63 form the walls of the second base via electrodes 60 and are partitioned by the base insulating film 30, the base electrode 35, and the interlayer film 46. The width of the second base via electrode 60 corresponds to the opening width of the second via opening 63.

[0297] The second via opening 63 has an opening wall partitioned by the interlayer film 46, and a bottom wall partitioned by the base insulating film 30 and the base electrode 35. In this embodiment, the opening wall is formed substantially perpendicular to the insulating surface of the interlayer film 46. The opening wall may also be inclined downwards from the insulating surface of the interlayer film 46 toward the base electrode 35. In other words, the second base via electrode 60 may be formed in a tapered shape (narrowing shape) in cross-section.

[0298] The bottom wall is partitioned by the insulating surface of the base insulating film 30, the upper surface 35a of the base electrode 35, and the side wall 35b of the base electrode 35, and has a stepped portion partitioned between the base insulating film 30 and the base electrode 35 by the side wall 35b of the base electrode 35.

[0299] The bottom wall has a bottom wall portion for the third connection portion 61, which is partitioned on the upper surface 35a of the base electrode 35, and a bottom wall portion for the fourth connection portion 62, which is partitioned on the insulating surface of the base insulating film 30. In this embodiment, the bottom wall portion for the third connection portion 61 is partitioned on the upper surface 35a of the base electrode 35 by a third recess that is recessed in the thickness direction Z. The presence or absence of the third recess is optional.

[0300] The bottom wall portion for the fourth connection portion 62 is partitioned between the side wall 35b of the base electrode 35 and the wall surface of the interlayer film 46. In this embodiment, the bottom wall portion for the fourth connection portion 62 is partitioned by a fourth recess recessed in the thickness direction Z on the insulating surface of the base insulating film 30. The presence or absence of the fourth recess is optional.

[0301] The second base via electrode 60 is mechanically and electrically connected to the base electrode 35 within the second via opening 63. The second base via electrode 60 covers the base insulating film 30, the upper surface 35a and the side wall 35b of the base electrode 35 within the second via opening 63, and is mechanically and electrically connected to the upper surface 35a and the side wall 35b of the base electrode 35.

[0302] The second base via electrode 60 may have a single-layer structure consisting of a single metal film, or a multilayer structure including multiple metal films. The second base via electrode 60 may include a metal film containing at least one of aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, and tungsten-based metals.

[0303] The second base via electrode 60 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, and tungsten. The second base via electrode 60 may also include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, and tungsten alloy.

[0304] In this embodiment, the second base via electrode 60, like the first base via electrode 50, has a laminated structure including a via base electrode 54 and a via body electrode 55 stacked in this order from the wall side of the second via opening 63. The via base electrode 54 has a laminated structure including a first base electrode 56 and a second base electrode 57.

[0305] The first base electrode 56 covers the wall surface of the second via opening 63 in a film-like manner. The first base electrode 56 has a portion that covers the base insulating film 30 in a film-like manner, a portion that covers the upper surface 35a of the base electrode 35 in a film-like manner, a portion that covers the side wall 35b of the base electrode 35 in a film-like manner, and a portion that covers the interlayer film 46 in a film-like manner.

[0306] The first base electrode 56 is mechanically and electrically connected to the upper surface 35a and side wall 35b of the base electrode 35. The first base electrode 56 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the second via opening 63, and forms the edge of the electrode surface of the second base via electrode 60.

[0307] The second base electrode 57 covers the wall surface of the second via opening 63 in a film-like manner via the first base electrode 56. The second base electrode 57 has a portion that covers the base insulating film 30 in a film-like manner via the first base electrode 56, a portion that covers the upper surface 35a of the base electrode 35 in a film-like manner via the first base electrode 56, a portion that covers the side wall 35b of the base electrode 35 in a film-like manner via the first base electrode 56, and a portion that covers the interlayer film 46 in a film-like manner via the first base electrode 56.

[0308] The second base electrode 57 is electrically connected to the upper surface 35a and side wall 35b of the base electrode 35 via the first base electrode 56. The second base electrode 57 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the second via opening 63, and forms the edge of the electrode surface of the second base via electrode 60.

[0309] The via body electrode 55 is embedded in the second via opening 63 via a via base electrode 54 as the main body of the second base via electrode 60. The via body electrode 55 faces the bottom wall and the opening wall of the second via opening 63 via the via base electrode 54.

[0310] The via body electrode 55 has a portion that covers the base insulating film 30 via the via under electrode 54, a portion that covers the upper surface 35a of the base electrode 35 via the via under electrode 54, a portion that covers the side wall 35b of the base electrode 35 via the via under electrode 54, and a portion that covers the interlayer film 46 via the via under electrode 54.

[0311] The via body electrode 55 has a portion sandwiched between the side wall 35b of the base electrode 35 and the wall surface of the interlayer film 46 on the base insulating film 30. The via body electrode 55 is electrically connected to the upper surface 35a and side wall 35b of the base electrode 35 via the via under electrode 54. The via body electrode 55 is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, and forms the electrode surface of the second base via electrode 60.

[0312] The semiconductor device 1A includes a resistor unit RU. The resistor unit RU includes a base electrode 35, one or more (in this embodiment, more) first base via electrodes 50, and one or more (in this embodiment, more) second base via electrodes 60.

[0313] The resistor unit RU includes a gate resistor Rg partitioned in the base electrode 35 in a region between a plurality of first base via electrodes 50 and a plurality of second base via electrodes 60. The gate resistor Rg delays the switching speed of the gate of the transistor structure T, thereby suppressing erroneous oscillations of the transistor structure T caused by damped oscillations and noise caused by EMI (Electro Magnetic Interference).

[0314] The resistance value of the gate resistor Rg is appropriately adjusted by the resistance value of the base electrode 35 (polysilicon impurity concentration), the thickness of the base electrode 35, the surface area of ​​the base electrode 35 (width in the first direction X and width in the second direction Y), the distance between the first base via electrode 50 and the second base via electrode 60, etc.

[0315] The gate resistor Rg includes a main body and a side wall. The main body of the gate resistor Rg is divided into a region between the first connection portion 51 of the plurality of first base via electrodes 50 and the third connection portion 61 of the plurality of second base via electrodes 60, and forms a first current path I1 that extends in a second direction Y along the upper surface 35a of the base electrode 35.

[0316] The sidewall portion of the gate resistor Rg is divided into a region between the second connection portion 52 of the plurality of first base via electrodes 50 and the fourth connection portion 62 of the plurality of second base via electrodes 60, forming a second current path I2 that extends in the second direction Y along the sidewall 35b of the base electrode 35.

[0317] In the gate resistance Rg, current paths are formed along both the upper surface 35a and the side wall 35b of the base electrode 35, suppressing bypass current paths. This suppresses undesirable fluctuations in the gate resistance Rg caused by bypass currents. As a result, the stability of the gate resistance Rg (resistance value) is improved.

[0318] Furthermore, since multiple first base via electrodes 50 are connected to the side wall 35b of the base electrode 35, the effect of misalignment of the multiple first base via electrodes 50 relative to the base electrode 35 is reduced. This suppresses undesirable fluctuations in the gate resistance Rg caused by misalignment of the multiple first base via electrodes 50. As a result, the stability of the gate resistance Rg (resistance value) is improved.

[0319] Similarly, since multiple second base via electrodes 60 are connected to the side wall 35b of the base electrode 35, the effect of misalignment of the multiple second base via electrodes 60 relative to the base electrode 35 is reduced. This suppresses undesirable fluctuations in the gate resistance Rg caused by misalignment of the multiple second base via electrodes 60. As a result, the stability of the gate resistance Rg (resistance value) is improved.

[0320] In this configuration, the base pad electrode 36 is physically separated from the base electrode 35. Therefore, the electrical influence of the base pad electrode 36 on the base electrode 35 is reduced, and the stability of the gate resistance Rg (resistance value) is improved.

[0321] Similarly, the line electrode 40 is physically isolated from the base electrode 35. Therefore, the electrical influence of the line electrode 40 on the base electrode 35 is reduced, and the stability of the gate resistance Rg (resistance value) is improved. In particular, the island-shaped base electrode 35 reduces the electrical influence caused by the resistance values ​​of other conductors, thus appropriately improving the stability of the gate resistance Rg (resistance value).

[0322] The semiconductor device 1A includes one or more (in this embodiment, more) pad via electrodes 65 embedded in the interlayer film 46 in a pad region 9A. The multiple pad via electrodes 65 are metallic embeddings relative to the base pad electrode 36. The multiple pad via electrodes 65 have a resistivity lower than that of the base pad electrode 36.

[0323] The number of pad via electrodes 65 is arbitrary and can be adjusted as appropriate according to the flat area of ​​the base pad electrode 36. For example, the number of pad via electrodes 65 may be between 1 and 100.

[0324] The number of pad via electrodes 65 may be in at least one of the following ranges: 1 to 5, 5 to 10, 10 to 25, 25 to 50, 50 to 75, and 75 to 100. Of course, the number of pad via electrodes 65 may be greater than 100 (for example, 1000 or less). In this embodiment, semiconductor device 1A includes 3 pad via electrodes 65.

[0325] Multiple pad via electrodes 65 penetrate the interlayer film 46 and are mechanically and electrically connected to the base pad electrode 36. In this configuration, the multiple pad via electrodes 65 are unevenly distributed towards the periphery of the base pad electrode 36 relative to the central part of the base pad electrode 36.

[0326] Multiple pad via electrodes 65 are arranged at intervals from the inner side of the base pad electrode 36 toward the peripheral side of the base pad electrode 36, and each extends in a strip shape along the periphery of the base pad electrode 36. Each of the multiple pad via electrodes 65 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y.

[0327] In this configuration, each of the multiple pad via electrodes 65 is formed in a polygonal annular shape (a quadrilateral annular shape in this configuration) having four sides parallel to the periphery of the base pad electrode 36, and surrounds the inner part of the base pad electrode 36.

[0328] The layout of the multiple pad via electrodes 65 is arbitrary. The multiple pad via electrodes 65 may each extend in a strip-like manner in the first direction X and be arranged with gaps in the second direction Y. In other words, the multiple pad via electrodes 65 may extend in a stripe-like manner in the first direction X.

[0329] Multiple pad via electrodes 65 may be arranged with spacing in the first direction X and each extending in a strip-like manner in the second direction Y. In other words, multiple pad via electrodes 65 may extend in a stripe-like manner in the second direction Y. Multiple pad via electrodes 65 may be arranged with spacing in a dot-like manner (for example, in a matrix) in the first direction X and the second direction Y.

[0330] The pad via electrode 65 has a width less than the thickness of the interlaminar film 46 and an aspect ratio that extends vertically in the thickness direction Z of the interlaminar film 46. Alternatively, the pad via electrode 65 may have a width greater than the thickness of the interlaminar film 46 and an aspect ratio that extends horizontally in the width direction of the interlaminar film 46.

[0331] The width of the pad via electrode 65 may be greater than or less than the width of the gate structure 15. The width of the pad via electrode 65 may be greater than or less than the spacing of the gate structure 15. The width of the pad via electrode 65 is approximately equal to the width of the first base via electrode 50 (second base via electrode 60). The width of the pad via electrode 65 may be greater than or less than the width of the first base via electrode 50 (second base via electrode 60).

[0332] The width of the pad via electrode 65 may be greater than 0 μm and less than or equal to 2 μm. The width of the pad via electrode 65 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, between 0.75 μm and 1 μm, between 1 μm and 1.25 μm, between 1.25 μm and 1.5 μm, between 1.5 μm and 1.75 μm, and between 1.75 μm and 2 μm.

[0333] In this embodiment, the spacing between the multiple pad via electrodes 65 is greater than the width of the pad via electrode 65. The spacing between the pad via electrodes 65 may also be smaller than the width of the pad via electrode 65. The spacing between the pad via electrodes 65 may be greater than or smaller than the width of the gate structure 15. The spacing between the pad via electrodes 65 may be greater than or smaller than the spacing of the gate structure 15.

[0334] In this configuration, the spacing between the pad via electrodes 65 is greater than the width of the first base via electrode 50 (second base via electrode 60). The spacing between the pad via electrodes 65 may also be smaller than the width of the first base via electrode 50 (second base via electrode 60).

[0335] The spacing of the pad via electrodes 65 is approximately equal to the spacing of the first base via electrodes 50 (second base via electrodes 60). The spacing of the pad via electrodes 65 may be greater or less than the spacing of the first base via electrodes 50 (second base via electrodes 60).

[0336] The spacing between the pad via electrodes 65 may be greater than 0 μm and 5 μm or less. The spacing between the pad via electrodes 65 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0337] Multiple pad via electrodes 65 have lower ends connected to the upper surface of the base pad electrode 36. The lower ends of the pad via electrodes 65 are located on the main surface insulating film 25 (base insulating film 30) side of the height of the upper surface of the base pad electrode 36.

[0338] The lower end of the pad via electrode 65 is formed at a distance from the middle thickness position of the base pad electrode 36 to the upper surface side of the base pad electrode 36. The lower end of the pad via electrode 65 may also be formed at a height approximately equal to the upper surface of the base pad electrode 36.

[0339] The multiple pad via electrodes 65 are formed at intervals inward from the periphery (side wall) of the base pad electrode 36 and do not cross the periphery (side wall) of the base pad electrode 36. Of course, the multiple pad via electrodes 65 may have portions that cross the side wall of the base pad electrode 36 and are connected to the side wall of the base pad electrode 36, similar to the first base via electrode 50 (second base via electrode 60).

[0340] The pad via electrode 65 has an electrode surface exposed from the insulating surface of the interlayer film 46. The electrode surface is formed with a gap between the height of the insulating surface of the interlayer film 46 and the base pad electrode 36, exposing the insulating surface of the interlayer film 46. The electrode surface may have a recess facing the base pad electrode 36.

[0341] Multiple pad via electrodes 65 are embedded in multiple pad via openings 66 formed in the interlayer membrane 46. The pad via openings 66 form the walls of the pad via electrodes 65 and are demarcated by the interlayer membrane 46 and the base pad electrode 36. The width of the pad via electrode 65 corresponds to the opening width of the pad via opening 66.

[0342] The pad via opening 66 has an opening wall partitioned by the interlayer film 46 and a bottom wall partitioned by the base pad electrode 36. In this configuration, the opening wall is formed substantially perpendicular to the insulating surface of the interlayer film 46. The opening wall may also be inclined downwards from the insulating surface of the interlayer film 46 toward the base pad electrode 36. In other words, the pad via electrode 65 may be formed in a tapered shape (narrowing shape) in cross-section.

[0343] The bottom wall is defined by the upper surface of the base pad electrode 36. In this embodiment, the bottom wall is defined by a recess on the upper surface of the base pad electrode 36 that extends in the thickness direction Z from a height position on the upper surface of the base pad electrode 36. The presence or absence of the recess is optional.

[0344] The pad via electrode 65 may have a single-layer structure consisting of a single metal film, or a multilayer structure containing multiple metal films. The pad via electrode 65 may contain a metal film comprising at least one of aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, and tungsten-based metals.

[0345] The pad via electrode 65 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, and tungsten. The pad via electrode 65 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, and tungsten alloy.

[0346] In this embodiment, the pad via electrode 65 has a laminated structure similar to the first base via electrode 50, including a via base electrode 54 and a via body electrode 55 stacked in this order from the wall side of the pad via opening 66. The via base electrode 54 has a laminated structure including a first base electrode 56 and a second base electrode 57.

[0347] The first base electrode 56 covers the wall surface of the pad via opening 66 in a film-like manner. The first base electrode 56 has a portion that covers the upper surface of the base pad electrode 36 in a film-like manner, and a portion that covers the interlayer film 46 in a film-like manner.

[0348] The first base electrode 56 is mechanically and electrically connected to the upper surface of the base pad electrode 36. The first base electrode 56 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the pad via opening 66, and forms the edge of the electrode surface of the pad via electrode 65.

[0349] The second base electrode 57 covers the wall surface of the pad via opening 66 in a film-like manner via the first base electrode 56. The second base electrode 57 has a portion that covers the upper surface of the base pad electrode 36 in a film-like manner via the first base electrode 56, and a portion that covers the interlayer film 46 in a film-like manner via the first base electrode 56.

[0350] The second base electrode 57 is electrically connected to the base pad electrode 36 via the first base electrode 56. The second base electrode 57 is formed at a distance from the height of the insulating surface of the interlayer film 46 towards the first main surface 3 at the opening wall of the pad via opening 66, and forms the edge of the electrode surface of the pad via electrode 65.

[0351] The via body electrode 55 is embedded in the pad via opening 66 via a via base electrode 54, serving as the main body of the pad via electrode 65. The via body electrode 55 faces the bottom wall and the opening wall of the pad via opening 66 via the via base electrode 54.

[0352] The via body electrode 55 has a portion that covers the upper surface of the base pad electrode 36 via the via base electrode 54, and a portion that covers the interlayer film 46 via the via base electrode 54. The via body electrode 55 is electrically connected to the upper surface of the base pad electrode 36 via the via base electrode 54. The via body electrode 55 is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, and forms the electrode surface of the pad via electrode 65.

[0353] The semiconductor device 1A includes one or more (in this embodiment, more) gate via electrodes 67 embedded in the interlayer film 46 in an inactive region 9. The multiple gate via electrodes 67 are metallic embeddings relative to the line electrodes 40 (first to fifth line sections 41 to 45). The multiple gate via electrodes 67 have a resistivity lower than that of the line electrodes 40 (first to fifth line sections 41 to 45).

[0354] The number of gate via electrodes 67 may be between 1 and 20. The number of gate via electrodes 67 is the number of gate via electrodes 67 that appear when the gate via electrode 67 is cut in a direction perpendicular to the extending direction of the gate via electrode 67.

[0355] The number of gate via electrodes 67 may be a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, and 15 to 20. In this embodiment, semiconductor device 1A includes 3 gate via electrodes 67.

[0356] Multiple gate via electrodes 67 penetrate the interlayer film 46 and are mechanically and electrically connected to the line electrodes 40. Specifically, multiple gate via electrodes 67 are provided in a one-to-many relationship for each of the first to fifth line sections 41 to 45. Multiple gate via electrodes 67 are arranged at intervals in the width direction (orthogonal to the extension direction) of the first to fifth line sections 41 to 45 and each extends in a strip shape following the extension direction of the first to fifth line sections 41 to 45.

[0357] In this configuration, the multiple gate via electrodes 67 for the second line section 42 are integrally formed with the multiple gate via electrodes 67 for the first line section 41. The multiple gate via electrodes 67 for the second line section 42 may be formed at a distance from the multiple gate via electrodes 67 for the first line section 41.

[0358] Multiple gate via electrodes 67 for the third line section 43 are formed integrally with multiple gate via electrodes 67 for the first line section 41. Multiple gate via electrodes 67 for the third line section 43 may be formed at a distance from multiple gate via electrodes 67 for the first line section 41.

[0359] The multiple gate via electrodes 67 for the fourth line section 44 are formed at intervals from the multiple gate via electrodes 67 for the first line section 41. At least one of the multiple gate via electrodes 67 for the fourth line section 44 may be formed integrally with at least one of the multiple gate via electrodes 67 for the first line section 41.

[0360] The multiple gate via electrodes 67 for the fifth line section 45 are formed at intervals from the multiple gate via electrodes 67 for the fourth line section 44. At least one of the multiple gate via electrodes 67 for the fifth line section 45 may be formed integrally with at least one of the multiple gate via electrodes 67 for the fourth line section 44.

[0361] The gate via electrode 67 has a width less than the thickness of the interlayer film 46 and an aspect ratio that extends vertically in the thickness direction Z of the interlayer film 46. Alternatively, the gate via electrode 67 may have a width greater than the thickness of the interlayer film 46 and an aspect ratio that extends horizontally in the width direction of the interlayer film 46.

[0362] The width of the gate via electrode 67 may be greater than or less than the width of the gate structure 15. The width of the gate via electrode 67 may be greater than or less than the spacing of the gate structure 15. The width of the gate via electrode 67 is approximately equal to the width of the first base via electrode 50 (second base via electrode 60). The width of the gate via electrode 67 may be greater than or less than the width of the first base via electrode 50 (second base via electrode 60).

[0363] The width of the gate via electrode 67 may be greater than 0 μm and less than or equal to 2 μm. The width of the gate via electrode 67 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, between 0.75 μm and 1 μm, between 1 μm and 1.25 μm, between 1.25 μm and 1.5 μm, between 1.5 μm and 1.75 μm, and between 1.75 μm and 2 μm.

[0364] In this configuration, the spacing between the multiple gate via electrodes 67 is greater than the width of the gate via electrode 67. The spacing between the gate via electrodes 67 may also be smaller than the width of the gate via electrode 67. The spacing between the gate via electrodes 67 may be greater than or smaller than the width of the gate structure 15. The spacing between the gate via electrodes 67 may be greater than or smaller than the spacing of the gate structure 15.

[0365] In this configuration, the spacing between the gate via electrodes 67 is greater than the width of the first base via electrode 50 (second base via electrode 60). The spacing between the gate via electrodes 67 may also be smaller than the width of the first base via electrode 50 (second base via electrode 60).

[0366] The spacing of the gate via electrodes 67 is approximately equal to the spacing of the first base via electrodes 50 (second base via electrodes 60). The spacing of the gate via electrodes 67 may be greater or less than the spacing of the first base via electrodes 50 (second base via electrodes 60).

[0367] The spacing between the gate via electrodes 67 may be greater than 0 μm and 5 μm or less. The spacing between the gate via electrodes 67 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0368] Multiple gate via electrodes 67 may be formed at intervals in the direction of extension of the line electrode 40 (first to fifth line portions 41 to 45). In this case, the multiple gate via electrodes 67 may be formed in a polygonal or circular shape in plan view. The multiple gate via electrodes 67 may be formed in a square or hexagonal shape in plan view.

[0369] Multiple gate via electrodes 67 have lower ends connected to the upper surface of the line electrodes 40 (first to fifth line sections 41 to 45). The lower ends of the gate via electrodes 67 are located on the main surface insulating film 25 side of the height of the upper surface of the line electrodes 40.

[0370] The lower end of the gate via electrode 67 is formed at a distance from the middle thickness position of the line electrode 40 to the upper surface side of the line electrode 40. The lower end of the gate via electrode 67 may also be formed at a height approximately equal to the upper surface of the line electrode 40.

[0371] The multiple gate via electrodes 67 are formed at intervals inward from the periphery (sidewall) of the line electrode 40 and do not cross the periphery (sidewall) of the line electrode 40. Of course, the multiple gate via electrodes 67 may, like the first base via electrode 50 (second base via electrode 60), have portions that cross the sidewall of the line electrode 40 and are connected to the sidewall of the line electrode 40.

[0372] The gate via electrode 67 has an electrode surface exposed from the insulating surface of the interlayer film 46. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the line electrode 40, exposing the insulating surface of the interlayer film 46. The electrode surface may have a recess toward the line electrode 40.

[0373] Multiple gate via electrodes 67 are embedded in multiple gate via openings 68 formed in the interlayer membrane 46. The gate via openings 68 form the walls of the gate via electrodes 67 and are partitioned by the line electrodes 40 and the interlayer membrane 46. The width of the gate via electrodes 67 corresponds to the opening width of the gate via openings 68.

[0374] The gate via opening 68 has an opening wall partitioned by the interlayer film 46 and a bottom wall partitioned by the line electrode 40. In this configuration, the opening wall is formed substantially perpendicular to the insulating surface of the interlayer film 46. The opening wall may also be inclined downwards from the insulating surface of the interlayer film 46 toward the line electrode 40. In other words, the gate via electrode 67 may be formed in a tapered shape (narrowing shape) in cross-section.

[0375] The bottom wall is defined by the upper surface of the line electrode 40. In this configuration, the bottom wall is defined by a recess on the upper surface of the line electrode 40 that extends in the thickness direction Z from a height position on the upper surface of the line electrode 40. The presence or absence of the recess is optional.

[0376] The gate via electrode 67 may have a single-layer structure consisting of a single metal film, or a multilayer structure containing multiple metal films. The gate via electrode 67 may contain a metal film comprising at least one of aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, and tungsten-based metals.

[0377] The gate via electrode 67 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, and tungsten. The gate via electrode 67 may also include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, and tungsten alloy.

[0378] In this embodiment, the gate via electrode 67 has a laminated structure similar to the first base via electrode 50, including a via base electrode 54 and a via body electrode 55 stacked in that order from the wall side of the gate via opening 68. The via base electrode 54 has a laminated structure including a first base electrode 56 and a second base electrode 57.

[0379] The first base electrode 56 covers the wall surface of the gate via opening 68 in a film-like manner. The first base electrode 56 has a portion that covers the upper surface of the line electrode 40 in a film-like manner, and a portion that covers the interlayer film 46 in a film-like manner.

[0380] The first base electrode 56 is mechanically and electrically connected to the upper surface of the line electrode 40. The first base electrode 56 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the gate via opening 68, and forms the edge of the electrode surface of the gate via electrode 67.

[0381] The second base electrode 57 covers the wall surface of the gate via opening 68 in a film-like manner via the first base electrode 56. The second base electrode 57 has a portion that covers the upper surface of the line electrode 40 in a film-like manner via the first base electrode 56, and a portion that covers the interlayer film 46 in a film-like manner via the first base electrode 56.

[0382] The second base electrode 57 is electrically connected to the line electrode 40 via the first base electrode 56. The second base electrode 57 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the gate via opening 68, and forms the edge of the electrode surface of the gate via electrode 67.

[0383] The via body electrode 55 is embedded in the gate via opening 68 via a via base electrode 54, serving as the main body of the gate via electrode 67. The via body electrode 55 faces the bottom wall and the opening wall of the gate via opening 68 via the via base electrode 54.

[0384] The via body electrode 55 has a portion that covers the upper surface of the line electrode 40 via the via base electrode 54, and a portion that covers the interlayer film 46 via the via base electrode 54. The via body electrode 55 is electrically connected to the upper surface of the line electrode 40 via the via base electrode 54. The via body electrode 55 is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, and forms the electrode surface of the gate via electrode 67.

[0385] The semiconductor device 1A includes a plurality of source via electrodes 69 embedded in the interlayer film 46 in the active region 8. The plurality of source via electrodes 69 are metallic embeddings for a plurality of source regions 20 (a plurality of channels).

[0386] Multiple source via electrodes 69 are embedded in the interlayer film 46 in the region between the multiple gate structures 15 and are electrically connected to the multiple source regions 20 and the multiple contact regions 21. In this embodiment, the multiple source via electrodes 69 are formed at intervals in the first direction X in a one-to-one correspondence with respect to the region (mesa) between the multiple gate structures 15, and each extends in a strip shape in the second direction Y.

[0387] Multiple source via electrodes 69 may be arranged in a one-to-many correspondence with respect to a corresponding mesa portion. In this case, the multiple source via electrodes 69 may be spaced apart in the second direction Y, following the extending direction of the multiple gate structures 15.

[0388] Each of the multiple source via electrodes 69 has a width less than the mesa width between the multiple gate structures 15. In this embodiment, the source via electrodes 69 have a width greater than the thickness of the interlayer film 46 and have an aspect ratio that extends laterally in the width direction of the interlayer film 46. Alternatively, the source via electrodes 69 may have a width less than the thickness of the interlayer film 46 and have an aspect ratio that extends vertically in the thickness direction Z of the interlayer film 46.

[0389] In this configuration, the width of the source via electrode 69 is greater than the width of the first base via electrode 50 (second base via electrode 60). The width of the source via electrode 69 may also be smaller than the width of the first base via electrode 50 (second base via electrode 60). The width of the source via electrode 69 may also be approximately equal to the width of the first base via electrode 50 (second base via electrode 60).

[0390] The width of the source via electrode 69 may be greater than 0 μm and less than 10 μm. The width of the source via electrode 69 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and less than 10 μm.

[0391] Multiple source via electrodes 69 have lower ends connected to the first main surface 3. The lower ends of the source via electrodes 69 are located on the second main surface 4 side of the height position of the first main surface 3. The lower ends of the source via electrodes 69 are formed with a gap from the depth position of the bottom of the body region 10 toward the first main surface 3.

[0392] The lower end of the source via electrode 69 is formed at a distance from the depth position of the bottom of the source region 20 and the bottom of the contact region 21 toward the first main surface 3. The lower end of the source via electrode 69 may also be formed at a height position approximately equal to that of the first main surface 3.

[0393] The source via electrode 69 has an electrode surface exposed from the insulating surface of the interlayer film 46. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, exposing the insulating surface of the interlayer film 46. The electrode surface may have a recess toward the first main surface 3.

[0394] Multiple source via electrodes 69 are embedded in multiple source via openings 70 formed in the interlayer film 46. The source via openings 70 form the walls of the source via electrodes 69 and are demarcated by the first main surface 3, the main surface insulating film 25, and the interlayer film 46. The width of the source via electrode 69 corresponds to the opening width of the source via opening 70.

[0395] The source via opening 70 has an opening wall partitioned by the main surface insulating film 25 and the interlayer film 46, and a bottom wall partitioned by the first main surface 3 (mesa portion). In this configuration, the opening wall slopes diagonally downward from the insulating surface of the interlayer film 46 toward the chip 2 side. In other words, the source via electrode 69 is formed in a tapered shape (narrowing shape) in cross-sectional view.

[0396] The opening wall may be formed substantially perpendicular to the insulating surface of the interlayer film 46. The bottom wall exposes a plurality of source regions 20 and a plurality of contact regions 21. The bottom wall is demarcated by a recess in the thickness direction Z of the first main surface 3. The presence or absence of the recess is optional.

[0397] The source via electrode 69 may have a single-layer structure consisting of a single metal film, or a multilayer structure containing multiple metal films. The source via electrode 69 may contain a metal film comprising at least one of aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, and tungsten-based metals.

[0398] The source via electrode 69 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, and tungsten. The source via electrode 69 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, and tungsten alloy.

[0399] In this embodiment, the source via electrode 69 has a laminated structure similar to the first base via electrode 50, including a via base electrode 54 and a via body electrode 55 stacked in that order from the wall side of the source via opening 70. The via base electrode 54 has a laminated structure including a first base electrode 56 and a second base electrode 57.

[0400] The first base electrode 56 coats the wall surface of the source via opening 70 in a film-like manner. The first base electrode 56 has a portion that coats the first main surface 3 in a film-like manner and a portion that coats the interlayer film 46 in a film-like manner.

[0401] The first base electrode 56 is mechanically and electrically connected to a plurality of source regions 20 and a plurality of contact regions 21. The first base electrode 56 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the source via opening 70, and forms the edge of the electrode surface of the source via electrode 69.

[0402] The second base electrode 57 covers the wall surface of the source via opening 70 in a film-like manner via the first base electrode 56. The second base electrode 57 has a portion that covers the first main surface 3 in a film-like manner via the first base electrode 56, and a portion that covers the interlayer film 46 in a film-like manner via the first base electrode 56.

[0403] The second base electrode 57 is electrically connected to a plurality of source regions 20 and a plurality of contact regions 21 via the first base electrode 56. The second base electrode 57 is formed at a distance from the height of the insulating surface of the interlayer film 46 toward the first main surface 3 at the opening wall of the source via opening 70, and forms the edge of the electrode surface of the source via electrode 69.

[0404] The via body electrode 55 is embedded in the source via opening 70 via a via base electrode 54, serving as the main body of the source via electrode 69. The via body electrode 55 faces the bottom wall and the opening wall of the source via opening 70 via the via base electrode 54.

[0405] The via body electrode 55 has a portion that covers the first main surface 3 via the via base electrode 54, and a portion that covers the interlayer film 46 via the via base electrode 54. The via body electrode 55 is electrically connected to a plurality of source regions 20 and a plurality of contact regions 21 via the via base electrode 54. The via body electrode 55 is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, and forms the electrode surface of the source via electrode 69.

[0406] The semiconductor device 1A includes a plurality of outer via electrodes 71 embedded in the interlayer film 46 in the inactive region 9 (outer region 9B). The plurality of outer via electrodes 71 are metallic embedded objects in the well region 22 (outer contact region 23).

[0407] The number of outer via electrodes 71 (as determined from a cross-sectional view along the first direction X or the second direction Y) may be between 1 and 20. The number of outer via electrodes 71 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. In this embodiment, the semiconductor device 1A includes 3 outer via electrodes 71.

[0408] Multiple outer via electrodes 71 are formed with a gap between them from the line electrode 40 towards the periphery of the first main surface 3, and with a gap between them from the periphery of the first main surface 3 towards the inside of the first main surface 3. Multiple outer via electrodes 71 are formed with a gap between them towards the inside of multiple field regions 24.

[0409] Multiple outer via electrodes 71 are formed at intervals extending inward from the outer edge of the well region 22. The multiple outer via electrodes 71 penetrate the interlayer film 46 at intervals above the outer contact region 23 and are mechanically and electrically connected to the outer contact region 23. In other words, the multiple outer via electrodes 71 are electrically connected to the well region 22 (outer well region 22B) via the outer contact region 23.

[0410] In this embodiment, the multiple outer via electrodes 71 each extend in a strip-like shape following the direction of extension of the outer contact region 23. The multiple outer via electrodes 71 have a portion extending in a first direction X and a portion extending in a second direction Y.

[0411] In this embodiment, the multiple outer via electrodes 71 are formed in an ended or endless polygonal annular shape (a quadrangular annular shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surround the active region 8 (multiple gate structures 15). The multiple outer via electrodes 71 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0412] Multiple outer via electrodes 71 may be formed at intervals in the direction extending of the outer contact region 23. In this case, the multiple outer via electrodes 71 may be formed in a polygonal or circular shape in a plan view. The multiple outer via electrodes 71 may be formed in a square or hexagonal shape in a plan view.

[0413] The outer via electrode 71 has a width less than the thickness of the interlayer film 46 and an aspect ratio that extends vertically in the thickness direction Z of the interlayer film 46. Alternatively, the outer via electrode 71 may have a width greater than the thickness of the interlayer film 46 and an aspect ratio that extends horizontally in the width direction of the interlayer film 46.

[0414] The width of the outer via electrode 71 may be greater than or less than the width of the gate structure 15. The width of the outer via electrode 71 may be greater than or less than the spacing of the gate structure 15. The width of the outer via electrode 71 is approximately equal to the width of the first base via electrode 50 (second base via electrode 60). The width of the outer via electrode 71 may be greater than or less than the width of the first base via electrode 50 (second base via electrode 60).

[0415] The width of the outer via electrode 71 may be greater than 0 μm and less than or equal to 2 μm. The width of the outer via electrode 71 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, between 0.75 μm and 1 μm, between 1 μm and 1.25 μm, between 1.25 μm and 1.5 μm, between 1.5 μm and 1.75 μm, and between 1.75 μm and 2 μm.

[0416] In this configuration, the spacing between the multiple outer via electrodes 71 is greater than the width of the outer via electrode 71. The spacing between the outer via electrodes 71 may also be smaller than the width of the outer via electrode 71. The spacing between the outer via electrodes 71 may be greater than or smaller than the width of the gate structure 15. The spacing between the outer via electrodes 71 may be greater than or smaller than the spacing of the gate structure 15.

[0417] In this configuration, the spacing between the outer via electrodes 71 is greater than the width of the first base via electrode 50 (second base via electrode 60). The spacing between the outer via electrodes 71 may also be smaller than the width of the first base via electrode 50 (second base via electrode 60).

[0418] The spacing of the outer via electrodes 71 is approximately equal to the spacing of the first base via electrodes 50 (second base via electrodes 60). The spacing of the outer via electrodes 71 may be greater or less than the spacing of the first base via electrodes 50 (second base via electrodes 60).

[0419] Multiple outer via electrodes 71 have lower ends connected to the first main surface 3. The lower ends of the outer via electrodes 71 are located on the second main surface 4 side of the height position of the first main surface 3. The lower ends of the outer via electrodes 71 are formed with a gap from the depth position of the bottom of the well region 22 toward the first main surface 3.

[0420] The lower end of the outer via electrode 71 is formed at a distance from the depth position of the bottom of the outer contact region 23 toward the first main surface 3. The lower end of the outer via electrode 71 may also be formed at a height position approximately equal to that of the first main surface 3.

[0421] The outer via electrode 71 has an electrode surface exposed from the insulating surface of the interlayer film 46. The electrode surface is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the base pad electrode 36, exposing the insulating surface of the interlayer film 46. The electrode surface may have a recess toward the first main surface 3.

[0422] Multiple outer via electrodes 71 are embedded in multiple outer via openings 72 formed in the interlayer film 46. The outer via openings 72 form the wall surface of the outer via electrode 71 and are partitioned by the first main surface 3, the main surface insulating film 25, and the interlayer film 46. The width of the outer via electrode 71 corresponds to the opening width of the outer via opening 72.

[0423] The outer via opening 72 has an opening wall partitioned by the main surface insulating film 25 and the interlayer film 46, and a bottom wall partitioned by the first main surface 3. In this embodiment, the opening wall is formed substantially perpendicular to the insulating surface of the interlayer film 46.

[0424] The opening wall may be inclined downwards from the insulating surface of the interlayer film 46 toward the tip 2. In other words, the outer via electrode 71 may be formed in a tapered shape (narrowing shape) in cross-section. The bottom wall exposes the outer contact region 23. The bottom wall is demarcated by a recess in the thickness direction Z on the first main surface 3. The presence or absence of the recess is optional.

[0425] The outer via electrode 71 may have a single-layer structure consisting of a single metal film, or a multilayer structure containing multiple metal films. The outer via electrode 71 may contain a metal film comprising at least one of aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, and tungsten-based metals.

[0426] The outer via electrode 71 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, and tungsten. The outer via electrode 71 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, and tungsten alloy.

[0427] In this embodiment, the outer via electrode 71 has a laminated structure similar to the first base via electrode 50, including a via base electrode 54 and a via body electrode 55 stacked in that order from the wall side of the outer via opening 72. The via base electrode 54 has a laminated structure including a first base electrode 56 and a second base electrode 57.

[0428] The first base electrode 56 covers the wall surface of the outer via opening 72 in a film-like manner. The first base electrode 56 has a portion that covers the first main surface 3 in a film-like manner and a portion that covers the interlayer film 46 in a film-like manner.

[0429] The first base electrode 56 is mechanically and electrically connected to the outer contact region 23. The first base electrode 56 is formed at a distance from the height of the insulating surface of the interlayer film 46 towards the first main surface 3 at the opening wall of the outer via opening 72, and forms the edge of the electrode surface of the outer via electrode 71.

[0430] The second base electrode 57 covers the wall surface of the outer via opening 72 in a film-like manner via the first base electrode 56. The second base electrode 57 has a portion that covers the first main surface 3 in a film-like manner via the first base electrode 56, and a portion that covers the interlayer film 46 in a film-like manner via the first base electrode 56.

[0431] The second base electrode 57 is electrically connected to the outer contact region 23 via the first base electrode 56. The second base electrode 57 is formed at a distance from the height of the insulating surface of the interlayer film 46 towards the first main surface 3 at the opening wall of the outer via opening 72, and forms the edge of the electrode surface of the outer via electrode 71.

[0432] The via body electrode 55 is embedded in the outer via opening 72 via a via base electrode 54, serving as the main body of the outer via electrode 71. The via body electrode 55 faces the bottom wall and the opening wall of the outer via opening 72 via the via base electrode 54.

[0433] The via body electrode 55 has a portion that covers the first main surface 3 via the via base electrode 54, and a portion that covers the interlayer film 46 via the via base electrode 54. The via body electrode 55 is electrically connected to the outer contact region 23 via the via base electrode 54. The via body electrode 55 is formed with a gap from the height of the insulating surface of the interlayer film 46 toward the first main surface 3, and forms the electrode surface of the outer via electrode 71.

[0434] The semiconductor device 1A includes a gate pad electrode 74 (first electrode) disposed on the interlayer film 46 in the pad region 9A. The gate pad electrode 74 may also be referred to as the "gate electrode (terminal)," "first pad (electrode)," or "first terminal (electrode)." The gate pad electrode 74 is made of a metal film. The gate pad electrode 74 has a resistivity lower than that of the base electrode 35.

[0435] The gate pad electrode 74 is formed inwardly spaced from multiple field regions 24 in a plan view and faces the pad well region 22A in the thickness direction Z. In this embodiment, the gate pad electrode 74 is formed inwardly spaced from the outer contact region 23 in a plan view and does not face the outer contact region 23 in the thickness direction Z. The gate pad electrode 74 may face the outer contact region 23 in the thickness direction Z.

[0436] In this form, the gate pad electrode 74 is arranged at a distance from the plurality of gate structures 15 in a plan view and does not face the plurality of gate structures 15 in the thickness direction Z. The gate pad electrode 74 may have a portion facing the plurality of gate structures 15 in the thickness direction Z.

[0437] The gate pad electrode 74 is electrically connected to the base electrode 35 via a plurality of first base via electrodes 50 and is electrically connected to the base pad electrode 36 via a plurality of pad via electrodes 65.

[0438] The gate pad electrode 74 has a pad via connection portion 75, a pad portion 76, and a pad connection portion 77. The pad via connection portion 75 may be referred to as the "first base via connection portion", and the pad connection portion 77 may be referred to as the "first connection portion".

[0439] The pad via connection portion 75 is arranged on the peripheral side of the first main surface 3 in the pad region 9A and faces one end portion of the base electrode 35 via the interlayer film 46. In this form, the pad via connection portion 75 is formed in a polygonal shape (in this form, a square shape) having four sides parallel to the periphery of the first main surface 3.

[0440] In this form, the pad via connection portion 75 is formed in a strip shape (rectangular shape) extending in the first direction X. The pad via connection portion 75 has a periphery located outside the periphery of the base electrode 35 in a plan view. The pad via connection portion 75 has a width (length) larger than the width (length) of the plurality of first base via electrodes 50 with respect to the first direction X.

[0441] In this form, the pad via connection portion 75 has a planar area smaller than the planar area of the base electrode 35. The planar area of the pad via connection portion 75 may be larger than the planar area of the base electrode 35. In this form, the opposing area of the pad via connection portion 75 with respect to the base electrode 35 is smaller than the non-opposing area of the pad via connection portion 75 with respect to the base electrode 35. The opposing area may be larger than the non-opposing area.

[0442] The pad via connection portion 75 collectively covers a plurality of first base via electrodes 50 on the interlayer film 46, is mechanically and electrically connected to the plurality of first base via electrodes 50, and is electrically connected to one end of the base electrode 35 via the plurality of first base via electrodes 50.

[0443] Specifically, the pad via connection portion 75 is mechanically and electrically connected to the entire area of the first connection portion 51 of the plurality of first base via electrodes 50 and the entire area of the second connection portion 52 of the plurality of first base via electrodes 50.

[0444] The pad via connection portion 75 enters into a plurality of first via openings 53 from above the interlayer film 46 and is mechanically and electrically connected to the plurality of first base via electrodes 50 within the plurality of first via openings 53. The pad via connection portion 75 forms a connection boundary portion with the electrode surfaces of the plurality of first base via electrodes 50.

[0445] The pad portion 76 is disposed on the inner side of the first main surface 3 in the pad region 9A and faces the base pad electrode 36 via the interlayer film 46. In this form, the pad portion 76 is formed in a polygonal shape (in this form, a square shape) having four sides parallel to the periphery of the first main surface 3.

[0446] In this form, the pad portion 76 has a width (length) substantially equal to the width (length) of the pad via connection portion 75 in the first direction X. The width (length) of the pad portion 76 may be larger or smaller than the width (length) of the pad via connection portion 75.

[0447] The pad portion 76 has a planar area larger than the planar area of the pad via connection portion 75 and is provided as a connection portion for a conducting wire such as a bonding wire. That is, the conducting wire is joined to the pad portion 76 at a distance from the base electrode 35 and the plurality of first base via electrodes 50. In this form, the conducting wire is joined to an area surrounded by a plurality of pad via electrodes 65 in a plan view.

[0448] The area of ​​the pad portion 76 facing the base pad electrode 36 is larger than the area of ​​the pad via connection portion 75 facing the base electrode 35. In this configuration, the pad portion 76 has a larger planar area than the base pad electrode 36 and covers the entire base pad electrode 36 via the interlayer film 46. In other words, the pad portion 76 has a periphery that surrounds the periphery of the base pad electrode 36 in a plan view.

[0449] Of course, the pad portion 76 may have a flat area less than the flat area of ​​the base pad electrode 36 and may have a periphery surrounded by the periphery of the base pad electrode 36. In other words, the pad portion 76 does not necessarily have to face the entire area of ​​the base pad electrode 36, and may face only a part of the base pad electrode 36.

[0450] The pad portion 76 is mechanically and electrically connected to a plurality of pad via electrodes 65 on the interlayer film 46, and is electrically connected to the base pad electrode 36 via the plurality of pad via electrodes 65. Specifically, the pad portion 76 is mechanically and electrically connected to the entire area of ​​the plurality of pad via electrodes 65.

[0451] The pad portion 76 enters a plurality of pad via openings 66 from above the interlayer film 46 and is mechanically and electrically connected to a plurality of pad via electrodes 65 within the plurality of pad via openings 66. The pad portion 76 forms a connection boundary with the electrode surfaces of the plurality of pad via electrodes 65.

[0452] The pad connecting portion 77 extends in a strip shape in the second direction Y between the pad via connecting portion 75 and the pad portion 76, connecting the pad via connecting portion 75 and the pad portion 76. In this configuration, the pad connecting portion 77 has a side wall that curves inward in an arc shape (circular arc shape). The side wall of the pad connecting portion 77 may extend linearly in the second direction Y.

[0453] The pad connecting portion 77 crosses the gap between the base electrode 35 and the base pad electrode 36 in a plan view and faces the gap in the thickness direction Z (lamination direction) via the interlayer film 46. In other words, in this configuration, the pad connecting portion 77 faces the base insulating film 30 in the thickness direction Z. Furthermore, the pad connecting portion 77 faces the pad well region 22A (well region 22) via the base insulating film 30 in the thickness direction Z.

[0454] In this configuration, the pad connection portion 77 has a width (length) smaller than the width (length) of the pad via connection portion 75 with respect to the first direction X, and narrows the current path between the pad via connection portion 75 and the pad portion 76. Furthermore, the pad connection portion 77 demarcates the pad via connection portion 75 on one side in the second direction Y and the pad portion 76 on the other side in the second direction Y. The pad connection portion 77 separates the connection point of the conductor from the pad via connection portion 75 to the pad portion 76.

[0455] With respect to the first direction X, the width (length) of the pad connecting portion 77 is smaller than the width (length) of the pad portion 76. In this configuration, the width (length) of the pad connecting portion 77 is smaller than the width (length) of the multiple first base via electrodes 50 with respect to the first direction X. In other words, the pad connecting portion 77 narrows the current path between the multiple first base via electrodes 50 and the pad portion 76.

[0456] In this configuration, the width (length) of the pad connecting portion 77 is smaller than the width (length) of the base electrode 35. The width (length) of the pad connecting portion 77 may also be larger than the width (length) of the base electrode 35. Of course, the pad connecting portion 77 may have a width that is approximately equal to either or both of the width (length) of the pad via connecting portion 75 and the width (length) of the pad portion 76 with respect to the first direction X.

[0457] The pad connecting portion 77 has a width (length) smaller than the width (length) of the pad via connecting portion 75 with respect to the second direction Y. With respect to the second direction Y, the width (length) of the pad connecting portion 77 may be larger than the width (length) of the pad via connecting portion 75. With respect to the second direction Y, the width (length) of the pad connecting portion 77 is smaller than the width (length) of the pad portion 76.

[0458] With respect to the second direction Y, the width (length) of the pad connecting portion 77 may be greater than 0 μm and 20 μm or less. The width (length) of the pad connecting portion 77 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, and 15 μm or more and 20 μm or less.

[0459] The gate pad electrode 74 has a thickness greater than the thickness of the main surface insulating film 25. The thickness of the gate pad electrode 74 is greater than the thickness of the base insulating film 30. The thickness of the gate pad electrode 74 is greater than the thickness of the base electrode 35.

[0460] The thickness of the gate pad electrode 74 is greater than the thickness of the base pad electrode 36. In this embodiment, the thickness of the gate pad electrode 74 is greater than the thickness of the interlayer film 46. The thickness of the gate pad electrode 74 may be less than the thickness of the interlayer film 46. The thickness of the gate pad electrode 74 may be greater than 0 μm and 5 μm or less.

[0461] The thickness of the gate pad electrode 74 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0462] The gate pad electrode 74 may have a single-layer structure consisting of a single metal film, or a laminated structure containing multiple metal films. The gate pad electrode 74 may contain a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium (Pd)-based metals, silver (Ag)-based metals, tungsten-based metals, and gold (Au)-based metals.

[0463] The gate pad electrode 74 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The gate pad electrode 74 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0464] In this embodiment, the gate pad electrode 74 has a single-layer structure consisting of a main electrode 78. The main electrode 78 may contain a different conductor from either or both of the via base electrode 54 and the via main electrode 55. The main electrode 78 may contain a different conductor from either or both of the first base electrode 56 and the second base electrode 57.

[0465] In this embodiment, the main electrode 78 is made of an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0466] The semiconductor device 1A includes a gate wiring electrode 79 (second electrode) selectively routed on the interlayer film 46 in an inactive region 9. The gate wiring electrode 79 may also be referred to as a "wiring electrode (first wiring electrode)", "gate wiring", "gate finger electrode", "upper wiring (first upper wiring)", etc.

[0467] The gate wiring electrode 79 is made of a metal film. The gate wiring electrode 79 has a lower resistivity than the base electrode 35. The resistivity of the gate wiring electrode 79 is lower than the resistivity of the line electrode 40 (first to fifth line sections 41 to 45).

[0468] The gate wiring electrode 79 is positioned on the interlayer film 46 at a distance from the gate pad electrode 74 and does not have a mechanical connection to the gate pad electrode 74. In a plan view, the gate wiring electrode 79 is formed at a distance inward from a plurality of field regions 24 and faces the well region 22 in the thickness direction Z.

[0469] In this embodiment, the gate wiring electrode 79 is positioned at a distance from the multiple gate structures 15 in a plan view and does not face the multiple gate structures 15 in the thickness direction Z. The gate wiring electrode 79 may have a portion that faces the multiple gate structures 15 in the thickness direction Z.

[0470] The gate wiring electrode 79 is electrically connected to the base electrode 35 via a plurality of second base via electrodes 60 and electrically connected to the line electrode 40 via a plurality of gate via electrodes 67. In this embodiment, the gate pad electrode 74 has a plurality of portions electrically connected to the first to fifth line portions 41 to 45 via a plurality of corresponding gate via electrodes 67.

[0471] The gate wiring electrode 79 electrically connects the gate pad electrode 74 to the plurality of gate structures 15 via the base electrode 35 and the line electrode 40. The gate pad electrode 74 is electrically connected to the gate pad electrode 74 via a resistor unit RU (base electrode 35, a plurality of first base via electrodes 50 and a plurality of second base via electrodes 60), and the resistor unit RU is electrically connected to the plurality of gate structures 15 via the line electrode 40.

[0472] The gate wiring electrode 79 is positioned on the interlayer film 46 at a horizontal distance from the base pad electrode 36 (multiple pad via electrodes 65) and does not have a mechanical connection to the base pad electrode 36 (multiple pad via electrodes 65). The gate wiring electrode 79 may have a portion facing the base pad electrode 36 in the thickness direction Z.

[0473] The gate wiring electrode 79 has a wiring via connection portion 80, a first wiring portion 81, a second wiring portion 82, a third wiring portion 83, a fourth wiring portion 84, a fifth wiring portion 85, and a wiring connection portion 86. The wiring via connection portion 80 may be referred to as the "second base via connection portion," and the wiring connection portion 86 may be referred to as the "second connection portion."

[0474] The wiring via connection part 80 is arranged in the pad region 9A at a distance from the pad via connection part 75 to the peripheral side of the first main surface 3, and faces the other end of the base electrode 35 through the interlayer film 46. In this form, the wiring via connection part 80 is formed in a polygonal shape (in this form, a square shape) having four sides parallel to the periphery of the first main surface 3.

[0475] In this form, the wiring via connection part 80 is formed in a strip shape (rectangular shape) extending in the first direction X and faces the pad via connection part 75 (gate pad electrode 74) in the second direction Y. The wiring via connection part 80 has a periphery located outside the periphery of the base electrode 35 in a plan view.

[0476] The wiring via connection part 80 has a width (length) larger than the width (length) of the plurality of second base via electrodes 60 in the first direction X. The width (length) of the wiring via connection part 80 may be substantially equal to the width (length) of the pad via connection part 75. The width (length) of the wiring via connection part 80 may be larger or smaller than the width (length) of the pad via connection part 75.

[0477] In this form, the wiring via connection part 80 has a planar area smaller than the planar area of the base electrode 35. The planar area of the wiring via connection part 80 may be larger than the planar area of the base electrode 35. In this form, the planar area of the wiring via connection part 80 is substantially equal to the planar area of the pad via connection part 75. The planar area of the wiring via connection part 80 may be larger or smaller than the planar area of the pad via connection part 75.

[0478] In this form, the opposing area of the wiring via connection part 80 to the base electrode 35 is smaller than the non - opposing area of the wiring via connection part 80 to the base electrode 35. The opposing area may be larger than the non - opposing area.

[0479] The opposing area of the wiring via connection part 80 to the base electrode 35 is substantially equal to the opposing area of the pad via connection part 75 to the base electrode 35. The opposing area of the wiring via connection part 80 may be larger or smaller than the opposing area of the pad via connection part 75. The interval between the pad via connection part 75 and the wiring via connection part 80 is larger than the interval between the plurality of first base via electrodes 50 (the interval between the plurality of second base via electrodes 60).

[0480] The wiring via connection section 80 covers a plurality of second base via electrodes 60 collectively on the interlayer film 46 and is mechanically and electrically connected to the plurality of second base via electrodes 60. The wiring via connection section 80 is electrically connected to the other end of the base electrode 35 via the plurality of second base via electrodes 60.

[0481] In other words, the wiring via connection 80 is electrically connected to the pad via connection 75 via the base electrode 35. The wiring via connection 80 is mechanically and electrically connected to the entire area of ​​the third connection 61 of the plurality of second base via electrodes 60, and to the entire area of ​​the fourth connection 62 of the plurality of second base via electrodes 60.

[0482] The wiring via connection portion 80 enters a plurality of second via openings 63 from above the interlayer film 46 and is mechanically and electrically connected to a plurality of second base via electrodes 60 within the plurality of second via openings 63. The wiring via connection portion 80 forms a connection boundary with the electrode surfaces of the plurality of second base via electrodes 60.

[0483] The first wiring section 81 is positioned on the interlayer film 46 with a gap in the second direction Y from the wiring via connection section 80 (gate pad electrode 74) toward the peripheral edge of the first main surface 3, and faces the first line section 41 via the interlayer film 46. The first wiring section 81 extends in a strip shape in the first direction X following the extending direction of the first line section 41, and faces the gate pad electrode 74 in the second direction Y.

[0484] The first wiring section 81 is positioned at an inward spacing from the multiple field regions 24. The first wiring section 81 is positioned at an inward spacing from the outer edge of the outer well region 22B and faces the outer well region 22B in the thickness direction Z.

[0485] In this configuration, the first wiring section 81 is positioned at a distance from the outer edge of the outer contact region 23 and faces the outer contact region 23 in the thickness direction Z. The first wiring section 81 does not necessarily have to face the outer contact region 23 in the thickness direction Z.

[0486] The first wiring section 81 is mechanically and electrically connected to a plurality of corresponding gate via electrodes 67 on the interlayer film 46, and is electrically connected to the first line section 41 via the plurality of gate via electrodes 67. The first wiring section 81 enters a plurality of gate via openings 68 from above the interlayer film 46 and is mechanically and electrically connected to the plurality of gate via electrodes 67 within the plurality of gate via openings 68. The first wiring section 81 forms a connection boundary with the electrode surfaces of the plurality of gate via electrodes 67.

[0487] The second wiring section 82 is drawn out in a strip shape from the first wiring section 81 along the first active region 8A to the outer region 9B on the interlayer film 46, and faces the second line section 42 via the interlayer film 46. The second wiring section 82 has a portion that extends in a strip shape in a first direction X following the extending direction of the second line section 42, and a portion that extends in a strip shape in a second direction Y following the extending direction of the second line section 42.

[0488] The second wiring section 82 is positioned at an inward spacing from the multiple field regions 24. The second wiring section 82 is positioned at an inward spacing from the outer edge of the outer well region 22B and faces the outer well region 22B in the thickness direction Z.

[0489] In this configuration, the second wiring section 82 is positioned at a distance from the outer edge of the outer contact region 23 and faces the outer contact region 23 in the thickness direction Z. The second wiring section 82 does not necessarily have to face the outer contact region 23 in the thickness direction Z.

[0490] The second wiring section 82 is mechanically and electrically connected to a plurality of corresponding gate via electrodes 67 on the interlayer film 46, and is electrically connected to the second line section 42 via the plurality of gate via electrodes 67. The second wiring section 82 enters a plurality of gate via openings 68 from above the interlayer film 46 and is mechanically and electrically connected to the plurality of gate via electrodes 67 within the plurality of gate via openings 68. The second wiring section 82 forms a connection boundary with the electrode surfaces of the plurality of gate via electrodes 67.

[0491] In this configuration, the second wiring section 82 is positioned at a distance from the multiple gate structures 15 on the peripheral side of the first main surface 3 in a plan view, and does not face the multiple gate structures 15 in the thickness direction Z. The second wiring section 82 may face the multiple gate structures 15 in the thickness direction Z.

[0492] The third wiring portion 83 is drawn out in a strip shape from the first wiring portion 81 along the second active region 8B to the outer region 9B on the interlayer film 46, and faces the third line portion 43 via the interlayer film 46. The third wiring portion 83 has a portion that extends in a strip shape in a first direction X following the extending direction of the third line portion 43, and a portion that extends in a strip shape in a second direction Y following the extending direction of the third line portion 43.

[0493] The third wiring section 83 is positioned at an inward spacing from the multiple field regions 24. The third wiring section 83 is positioned at an inward spacing from the outer edge of the outer well region 22B and faces the outer well region 22B in the thickness direction Z.

[0494] In this configuration, the third wiring section 83 is positioned at a distance from the outer edge of the outer contact region 23 and faces the outer contact region 23 in the thickness direction Z. The third wiring section 83 does not necessarily have to face the outer contact region 23 in the thickness direction Z.

[0495] The third wiring section 83 is mechanically and electrically connected to a plurality of corresponding gate via electrodes 67 on the interlayer film 46, and is electrically connected to the third line section 43 via the plurality of gate via electrodes 67. The third wiring section 83 enters a plurality of gate via openings 68 from above the interlayer film 46 and is mechanically and electrically connected to the plurality of gate via electrodes 67 within the plurality of gate via openings 68. The third wiring section 83 forms a connection boundary with the electrode surfaces of the plurality of gate via electrodes 67.

[0496] In this configuration, the third wiring section 83 is positioned at a distance from the multiple gate structures 15 on the peripheral side of the first main surface 3 in a plan view, and does not face the multiple gate structures 15 in the thickness direction Z. The third wiring section 83 may face the multiple gate structures 15 in the thickness direction Z.

[0497] The fourth wiring section 84 is drawn out in a strip shape from the first wiring section 81 toward the boundary region 9C on the interlayer film 46 and faces the fourth line section 44 via the interlayer film 46. The fourth wiring section 84 has a portion that extends in a strip shape in a first direction X following the extending direction of the fourth line section 44, and a portion that extends in a strip shape in a second direction Y following the extending direction of the fourth line section 44.

[0498] In this configuration, the fourth wiring section 84 extends in a strip shape from one end of the first wiring section 81 along the periphery of the pad area 9A and is connected to the other end of the first wiring section 81. In other words, the fourth wiring section 84, together with the first wiring section 81, is formed in an annular shape (a rectangular annular shape in this configuration) that surrounds the gate pad electrode 74 and defines the pad area 9A.

[0499] The fourth wiring section 84 has a first portion 84A, a second portion 84B, and a third portion 84C. The first portion 84A of the fourth wiring section 84 is drawn out in a strip shape in the second direction Y from one end of the first wiring section 81 on the first active region 8A side, and faces the first portion 44A of the fourth line section 44 via the interlayer film 46.

[0500] The second portion 84B of the fourth wiring section 84 is drawn out in a strip shape in the second direction Y from the other end of the first wiring section 81 on the second active region 8B side, and faces the second portion 44B of the fourth line section 44 via the interlayer film 46.

[0501] The third portion 84C of the fourth wiring section 84 extends in a strip shape in the first direction X in the region on the boundary region 9C side and faces the third portion 44C of the fourth line section 44 via the interlayer film 46. The third portion 84C connects the end of the first portion 84A of the fourth wiring section 84 and the end of the second portion 84B of the fourth wiring section 84.

[0502] The fourth wiring section 84 (first to third portions 84A to 84C) is mechanically and electrically connected to a plurality of corresponding gate via electrodes 67 on the interlayer film 46, and is electrically connected to the fourth line section 44 (first to third portions 44A to 44C) via the plurality of gate via electrodes 67. The fourth wiring section 84 enters a plurality of gate via openings 68 from above the interlayer film 46 and is mechanically and electrically connected to a plurality of gate via electrodes 67 within the plurality of gate via openings 68. The fourth wiring section 84 forms a connection boundary with the electrode surfaces of the plurality of gate via electrodes 67.

[0503] The fifth wiring section 85 is drawn out in a strip shape from the fourth wiring section 84 (third section 84C) to the boundary region 9C and faces the fifth line section 45 via the interlayer film 46. In other words, the fifth wiring section 85 is electrically connected to the first wiring section 81 via the fourth wiring section 84. The fifth wiring section 85 extends in a strip shape in the second direction Y, following the direction of extension of the boundary region 9C.

[0504] The fifth wiring section 85 is mechanically and electrically connected to a plurality of corresponding gate via electrodes 67 on the interlayer film 46, and is electrically connected to the fifth line section 45 via the plurality of gate via electrodes 67. The fifth wiring section 85 enters a plurality of gate via openings 68 from above the interlayer film 46 and is mechanically and electrically connected to the plurality of gate via electrodes 67 within the plurality of gate via openings 68. The fifth wiring section 85 forms a connection boundary with the electrode surfaces of the plurality of gate via electrodes 67.

[0505] The wiring connection portion 86 extends in a strip shape in the second direction Y between the wiring via connection portion 80 and the first wiring portion 81, connecting the wiring via connection portion 80 and the first wiring portion 81. In this configuration, the wiring connection portion 86 has side walls that curve inward in an arc shape (circular arc shape). The side walls of the wiring connection portion 86 may extend linearly in the second direction Y.

[0506] The wiring connection portion 86 is arranged on the same straight line as the pad connection portion 77 with respect to the second direction Y. The wiring connection portion 86 may be positioned offset to one or the other side of the first direction X with respect to an imaginary line that crosses the center of the pad connection portion 77 in the second direction Y. The wiring connection portion 86 may be positioned at a distance from the location of the pad connection portion 77 to one or the other side of the first direction X.

[0507] The wiring connection portion 86 crosses the gap between the base electrode 35 and the line electrode 40 (first line portion 41) in a plan view, and faces the gap in the thickness direction Z (lamination direction) via the interlayer film 46. In other words, in this configuration, the wiring connection portion 86 faces the base insulating film 30 in the thickness direction Z. Furthermore, the wiring connection portion 86 faces the pad well region 22A (well region 22) via the base insulating film 30 in the thickness direction Z.

[0508] In this configuration, the wiring connection portion 86 has a width (length) smaller than the width (length) of the wiring via connection portion 80 with respect to the first direction X, and narrows the current path between the wiring via connection portion 80 and the first wiring portion 81. Furthermore, the wiring connection portion 86 demarcates the first wiring portion 81 on one side in the second direction Y, and the wiring via connection portion 80 on the other side in the second direction Y.

[0509] With respect to the first direction X, the width (length) of the wiring connection portion 86 is smaller than the width (length) of the multiple second base via electrodes 60 in this configuration. In other words, the wiring connection portion 86 narrows the current path between the multiple second base via electrodes 60 and the first wiring portion 81.

[0510] With respect to the first direction X, the width (length) of the wiring connection portion 86 is smaller than the width (length) of the base electrode 35 in this configuration. The width (length) of the wiring connection portion 86 may be larger than the width (length) of the base electrode 35.

[0511] With respect to the first direction X, the width (length) of the wiring connection portion 86 is approximately equal to the width (length) of the pad connection portion 77 in this configuration. The width (length) of the wiring connection portion 86 may be greater than or less than the width (length) of the pad connection portion 77. Of course, with respect to the first direction X, the width (length) of the wiring connection portion 86 may be approximately equal to the width (length) of the wiring via connection portion 80.

[0512] The wiring connection portion 86 has a width (length) smaller than the width (length) of the wiring via connection portion 80 with respect to the second direction Y. With respect to the second direction Y, the width (length) of the wiring connection portion 86 may be larger than the width (length) of the wiring via connection portion 80.

[0513] With respect to the second direction Y, the width (length) of the wiring connection portion 86 is approximately equal to the width (length) of the pad connection portion 77 in this configuration. With respect to the second direction Y, the width (length) of the wiring connection portion 86 may be greater than or less than the width (length) of the pad connection portion 77.

[0514] With respect to the second direction Y, the width (length) of the wiring connection portion 86 may be greater than 0 μm and 20 μm or less. The width (length) of the wiring connection portion 86 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, and 15 μm or more and 20 μm or less.

[0515] The wiring connection section 86 does not necessarily have to be connected to the first wiring section 81. The wiring connection section 86 may be connected to the fourth wiring section 84 (either the first section 84A and the second section 84B, or both) in addition to or instead of the first wiring section 81.

[0516] The gate wiring electrode 79 has a thickness greater than the thickness of the main surface insulating film 25. The thickness of the gate wiring electrode 79 is greater than the thickness of the base insulating film 30. The thickness of the gate wiring electrode 79 is greater than the thickness of the base electrode 35. The thickness of the gate wiring electrode 79 is greater than the thickness of the base pad electrode 36.

[0517] In this embodiment, the thickness of the gate wiring electrode 79 is greater than the thickness of the interlayer film 46. The thickness of the gate wiring electrode 79 may be less than the thickness of the interlayer film 46. In this embodiment, the thickness of the gate wiring electrode 79 is approximately equal to the thickness of the gate pad electrode 74. The thickness of the gate wiring electrode 79 may be greater than or less than the thickness of the gate pad electrode 74.

[0518] The thickness of the gate wiring electrode 79 may be greater than 0 μm and 5 μm or less. The thickness of the gate wiring electrode 79 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0519] The gate wiring electrode 79 may have a single-layer structure consisting of a single metal film, or a laminated structure containing multiple metal films. The gate wiring electrode 79 may include a metal film containing at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0520] The gate wiring electrode 79 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold.

[0521] The gate wiring electrode 79 may include an alloy film (metal film) containing at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy. In this embodiment, the gate wiring electrode 79 has a single-layer structure consisting of a main electrode 78, similar to the gate pad electrode 74.

[0522] The semiconductor device 1A includes a source pad electrode 87 disposed on the interlayer film 46 in the active region 8. The source pad electrode 87 may also be referred to as the "source electrode (terminal)," "second pad (electrode)," or "second terminal (electrode)." The source pad electrode 87 is made of a metal film.

[0523] The source pad electrode 87 is positioned on the interlayer film 46 at a distance from the gate pad electrode 74 and the gate wiring electrode 79, and covers the first active region 8A and the second active region 8B. In this embodiment, the source pad electrode 87 has a first source pad portion 87a and a second source pad portion 87b.

[0524] The first source pad portion 87a covers the first active region 8A on the interlayer film 46 and is surrounded by gate wiring electrodes 79 (second wiring portion 82, fourth wiring portion 84, and fifth wiring portion 85). The first source pad portion 87a is formed in a strip-like (rectangular) shape extending in the second direction Y.

[0525] The second source pad portion 87b covers the second active region 8B on the interlayer film 46 and is surrounded by gate wiring electrodes 79 (third wiring portion 83, fourth wiring portion 84, and fifth wiring portion 85). The second source pad portion 87b is formed in a strip-like (rectangular) shape extending in the second direction Y.

[0526] The source pad electrode 87 is mechanically and electrically connected to a plurality of source via electrodes 69 on the interlayer film 46, and is electrically connected to a plurality of source regions 20 and a plurality of contact regions 21 via the plurality of source via electrodes 69.

[0527] Specifically, the source pad electrode 87 enters the multiple source via openings 70 from above the interlayer film 46 and coats the multiple source via electrodes 69 in a film-like manner within the multiple source via openings 70. The source pad electrode 87 forms a connection boundary with the electrode surfaces of the multiple source via electrodes 69.

[0528] The source pad electrode 87 has a thickness greater than the thickness of the main surface insulating film 25. The thickness of the source pad electrode 87 is greater than the thickness of the base insulating film 30. The thickness of the source pad electrode 87 is greater than the thickness of the base electrode 35. The thickness of the source pad electrode 87 is greater than the thickness of the base pad electrode 36.

[0529] In this embodiment, the thickness of the source pad electrode 87 is greater than the thickness of the interlayer film 46. The thickness of the source pad electrode 87 may be less than the thickness of the interlayer film 46. In this embodiment, the thickness of the source pad electrode 87 is approximately equal to the thickness of the gate pad electrode 74. The thickness of the source pad electrode 87 may be greater than or less than the thickness of the gate pad electrode 74.

[0530] The thickness of the source pad electrode 87 may be greater than 0 μm and 5 μm or less. The thickness of the source pad electrode 87 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0531] The source pad electrode 87 may have a single-layer structure consisting of a single metal film, or a laminated structure containing multiple metal films. The source pad electrode 87 may contain a metal film comprising at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0532] The source pad electrode 87 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold.

[0533] The source pad electrode 87 may include an alloy film (metal film) containing at least one of the following: aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy. In this embodiment, the source pad electrode 87 has a single-layer structure consisting of the main electrode 78, similar to the gate pad electrode 74.

[0534] The semiconductor device 1A includes a source wiring electrode 88 disposed on the interlayer film 46 in an inactive region 9 (outer region 9B). The source wiring electrode 88 may also be referred to as a "wiring electrode (second wiring electrode)", "source wiring", "source finger electrode", "upper wiring (second upper wiring)", etc. The source wiring electrode 88 is made of a metal film.

[0535] The source wiring electrode 88 is positioned on the interlayer film 46 at a distance from the gate pad electrode 74 and gate wiring electrode 79 toward the periphery of the first main surface 3. In a plan view, the source wiring electrode 88 is formed at a distance inward from a plurality of field regions 24 and faces the outer well region 22B in the thickness direction Z. In this embodiment, the source wiring electrode 88 faces the outer contact region 23 in the thickness direction Z.

[0536] The source wiring electrode 88 is positioned on a plurality of outer via electrodes 71 and extends in a strip shape following the direction of extension of the plurality of outer via electrodes 71. In a plan view, the source wiring electrode 88 has a portion extending in a first direction X and a portion extending in a second direction Y.

[0537] The source wiring electrode 88 is formed in an endless or endless polygonal ring shape (a quadrilateral ring in this form) having four sides parallel to the periphery of the first main surface 3, and surrounds the gate pad electrode 74, the gate wiring electrode 79, and the source pad electrode 87.

[0538] The source wiring electrode 88 is connected to the source pad electrode 87 (first source pad portion 87a and second source pad portion 87b) on the third side surface 5C. The source wiring electrode 88 is formed as a lead-out electrode drawn out from the source pad electrode 87.

[0539] The source wiring electrode 88 is mechanically and electrically connected to a plurality of outer via electrodes 71 on the interlayer film 46, and is electrically connected to the outer contact region 23 via the plurality of outer via electrodes 71.

[0540] Specifically, the source wiring electrode 88 enters a plurality of outer via openings 72 from above the interlayer film 46 and coats the plurality of outer via electrodes 71 in a film-like manner within the plurality of outer via openings 72. The source wiring electrode 88 forms a connection boundary with the electrode surfaces of the plurality of outer via electrodes 71.

[0541] In this embodiment, the source wiring electrode 88 has an inner edge that extends over the line electrode 40 and faces the line electrode 40 via the interlayer film 46. The inner edge of the source wiring electrode 88 may be formed with a gap between it and the line electrode 40 on the peripheral side of the first main surface 3.

[0542] The source wiring electrode 88 has a thickness greater than the thickness of the main surface insulating film 25. The thickness of the source wiring electrode 88 is greater than the thickness of the base insulating film 30. The thickness of the source wiring electrode 88 is greater than the thickness of the base electrode 35. The thickness of the source wiring electrode 88 is greater than the thickness of the base pad electrode 36.

[0543] In this embodiment, the thickness of the source wiring electrode 88 is greater than the thickness of the interlayer film 46. The thickness of the source wiring electrode 88 may be less than the thickness of the interlayer film 46. In this embodiment, the thickness of the source wiring electrode 88 is approximately equal to the thickness of the source pad electrode 87. The thickness of the source wiring electrode 88 may be greater than or less than the thickness of the source pad electrode 87.

[0544] The thickness of the source wiring electrode 88 may be greater than 0 μm and 5 μm or less. The thickness of the source wiring electrode 88 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0545] The source wiring electrode 88 may have a single-layer structure consisting of a single metal film, or a multilayer structure including multiple metal films. The source wiring electrode 88 may include a metal film containing at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0546] The source wiring electrode 88 may include a metal film containing at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold.

[0547] The source wiring electrode 88 may include an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy. In this embodiment, the source wiring electrode 88 has a single-layer structure consisting of the main electrode 78, similar to the gate pad electrode 74.

[0548] The semiconductor device 1A includes a drain pad electrode 89 that covers the second main surface 4. The drain pad electrode 89 may also be referred to as a "drain electrode (terminal)," "third terminal electrode," etc. The drain pad electrode 89 is mechanically and electrically connected to the first semiconductor layer 6 on the second main surface 4.

[0549] The drain pad electrode 89 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 89 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0550] The breakdown voltage that can be applied between the source pad electrode 87 and the drain pad electrode 89 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0551] Figure 20 is an electrical circuit diagram showing the electrical configuration of the semiconductor device 1A shown in Figure 1. Referring to Figure 20, the semiconductor device 1A includes a transistor structure T, a gate pad electrode 74, a gate wiring electrode 79, a source pad electrode 87, and a drain pad electrode 89. The transistor structure T includes a gate (multiple gate structures 15), a source (multiple source regions 20), and a drain (first semiconductor layer 6 and second semiconductor layer 7).

[0552] The gate pad electrode 74 is electrically connected to the gate of the transistor structure T. The gate wiring electrode 79 is electrically interposed between the gate of the transistor structure T and the gate pad electrode 74. The source pad electrode 87 is electrically connected to the source of the transistor structure T. The drain pad electrode 89 is electrically connected to the drain of the transistor structure T.

[0553] The semiconductor device 1A includes a resistor unit RU electrically interposed between the gate and gate pad electrodes 74 of the transistor structure T. The resistor unit RU includes a gate resistor Rg partitioned in the base electrode 35 in a region between a plurality of first base via electrodes 50 and a plurality of second base via electrodes 60.

[0554] The gate resistor Rg is electrically connected to the gate pad electrode 74 via a plurality of first base via electrodes 50, which serve as first potential application terminals, and is electrically connected to the gate wiring electrode 79 via a plurality of second base via electrodes 60, which serve as second potential application terminals.

[0555] As described above, the semiconductor device 1A may include a base electrode 35, a first base via electrode 50 (first via electrode), and a first electrode (74). The base electrode 35 may have an upper surface 35a and a side wall 35b.

[0556] The first base via electrode 50 is positioned on the base electrode 35 and may have a first connection portion 51 to the upper surface 35a of the base electrode 35 and a second connection portion 52 to the side wall 35b of the base electrode 35. The first electrode (74) is positioned on the first base via electrode 50 and may be electrically connected to the base electrode 35 via the first base via electrode 50.

[0557] This configuration provides a semiconductor device 1A that contributes to improving electrical characteristics. For example, with this semiconductor device 1A, a current path originating from the first connection portion 51 of the first base via electrode 50 is formed along the upper surface 35a of the base electrode 35, and a current path originating from the second connection portion 52 of the first base via electrode 50 is formed along the side wall 35b of the base electrode 35.

[0558] As a result, the current path originating from the first base via electrode 50 is extended to the portion along the side wall 35b of the base electrode 35, and the bypass path of the current is suppressed. Consequently, unwanted fluctuations in the resistance value (wiring resistance) caused by the bypass current are suppressed.

[0559] Furthermore, this configuration reduces the influence of misalignment of the first base via electrode 50 relative to the base electrode 35, thereby suppressing variations in resistance values ​​caused by such misalignment. Consequently, the stability of the resistance value of the base electrode 35 is improved.

[0560] The first base via electrode 50 may contain a different conductor than the base electrode 35. The first electrode (74) may contain a different conductor than the base electrode 35. The first electrode (74) may contain a different conductor than the first base via electrode 50. The base electrode 35 may contain a conductor other than metal. The first base via electrode 50 may contain metal. The first electrode (74) may contain metal.

[0561] The first base via electrode 50 may have a width of 2 μm or less. Multiple first base via electrodes 50 may be arranged on the base electrode 35 at intervals. With this configuration, the stability of the resistance value of the base electrode 35 is improved by the multiple first base via electrodes 50.

[0562] The multiple first base via electrodes 50 may be arranged with a spacing greater than the width of each first base via electrode 50. This configuration appropriately reduces the effect of misalignment between the multiple first base via electrodes 50 (for example, variations in electrical characteristics due to contact). The multiple first base via electrodes 50 may be arranged with a spacing of 5 μm or less.

[0563] The base electrode 35 may be a resistive electrode. In this case, the first base via electrode 50 may have a lower resistivity than the base electrode 35. The first electrode (74) may have a lower resistivity than the base electrode 35. This configuration improves the stability of the resistance value of the base electrode 35 as a resistive electrode. As a result, the electrical characteristics of the electronic circuit including the base electrode 35 as a resistive electrode are improved.

[0564] The semiconductor device 1A may include an insulating interlayer film 46 that covers the base electrode 35. In this case, the first base via electrode 50 may be embedded in the interlayer film 46. The first electrode (74) may be connected to the first base via electrode 50 on the interlayer film 46.

[0565] With this configuration, the connection point of the first base via electrode 50 to the base electrode 35 is appropriately restricted by the interlayer film 46, and the connection point of the first electrode (74) to the first base via electrode 50 is appropriately restricted by the interlayer film 46. As a result, the stability of the resistance value of the base electrode 35 is appropriately improved.

[0566] The semiconductor device 1A may include a second base via electrode 60 and a second electrode (79). The second base via electrode 60 may be placed on the base electrode 35 at a distance from the first base via electrode 50.

[0567] The second electrode (79) may be positioned on the second base via electrode 60 at a distance from the first electrode (74) and electrically connected to the first electrode (74) via the base electrode 35. This configuration improves the stability of the resistance value of the base electrode 35 between the first base via electrode 50 (first electrode (74)) and the second base via electrode 60 (second electrode (79)).

[0568] The second base via electrode 60 may have a third connection portion 61 to the upper surface 35a of the base electrode 35 and a fourth connection portion 62 to the side wall 35b of the base electrode 35. With this configuration, the current path originating from the third connection portion 61 of the second base via electrode 60 is formed along the upper surface 35a of the base electrode 35, and the current path originating from the fourth connection portion 62 of the second base via electrode 60 is formed along the side wall 35b of the base electrode 35.

[0569] As a result, the current path originating from the second base via electrode 60 extends to the portion along the side wall 35b of the base electrode 35, suppressing the bypass path of the current. Consequently, unwanted fluctuations in the resistance value (wiring resistance) caused by bypass current between the first base via electrode 50 and the second base via electrode 60 are suppressed.

[0570] Furthermore, this configuration reduces the influence of the misalignment of the second base via electrode 60 relative to the base electrode 35, thereby suppressing the variation in resistance values ​​caused by this misalignment. As a result, the stability of the resistance value of the base electrode 35 between the first base via electrode 50 and the second base via electrode 60 is appropriately improved.

[0571] The third connection portion 61 of the second base via electrode 60 may be aligned with the upper surface 35a of the base electrode 35 and face the first connection portion 51 of the first base via electrode 50. The fourth connection portion 62 of the second base via electrode 60 may be aligned with the side wall 35b of the base electrode 35 and face the second connection portion 52 of the first base via electrode 50.

[0572] With this configuration, a current path is formed along the upper surface 35a of the base electrode 35 between the first connection portion 51 of the first base via electrode 50 and the third connection portion 61 of the second base via electrode 60, and a current path is formed along the side wall 35b of the base electrode 35 between the second connection portion 52 of the first base via electrode 50 and the fourth connection portion 62 of the second base via electrode 60. As a result, unwanted fluctuations in resistance values ​​caused by bypass currents between the first base via electrode 50 and the second base via electrode 60 are appropriately suppressed.

[0573] The semiconductor device 1A may include a line electrode 40 and a line via electrode (67). The line electrode 40 may be provided at a distance from the base electrode 35. The line via electrode (67) may be placed on top of the line electrode 40. In this case, the second electrode (79) may be placed on the second base via electrode 60 and the line via electrode (67), and the base electrode 35 may be electrically connected to the line electrode 40.

[0574] With this configuration, the resistance value of the base electrode 35 is applied to the line electrode 40. Furthermore, with this configuration, the stability of the resistance value of the base electrode 35 between the line electrode 40 and the first electrode (74) is appropriately improved.

[0575] The semiconductor device 1A may include a chip 2. In this case, the base electrode 35 may be placed on the chip 2. The chip 2 may include a wide-bandgap semiconductor. In this case, the chip 2 may include SiC. According to these configurations, a semiconductor device 1A as a novel wide-bandgap semiconductor device (SiC semiconductor device) is provided.

[0576] In wide-bandgap semiconductor devices, the electrical characteristics are appropriately improved by the physical properties of the wide-bandgap semiconductor. In particular, since wide-bandgap semiconductor devices are used in harsh environments (high voltage and / or high humidity environments), stabilizing the resistance value is effective in suppressing malfunctions caused by undesirable fluctuations in resistance value.

[0577] The semiconductor device 1A may include a base insulating film 30 that covers the chip 2. In this case, the base electrode 35 may be placed on top of the base insulating film 30. With this configuration, short circuits between the chip 2 and the base electrode 35 are appropriately suppressed by the base insulating film 30. This appropriately suppresses the electrical influence of the base electrode 35 on the chip 2, and the electrical influence of the chip 2 on the base electrode 35.

[0578] The second connection portion 52 of the first base via electrode 50 may be in contact with the base insulating film 30. With this configuration, since the design assumes that the second connection portion 52 is connected to the base insulating film 30, the second connection portion 52 is properly connected to the side wall 35b of the base electrode 35. In addition, the effect of misalignment of the first base via electrode 50 relative to the base electrode 35 is appropriately reduced.

[0579] The contact portion of the second connection portion 52 with respect to the base insulating film 30 may be located closer to the tip 2 than the contact portion of the base electrode 35 with respect to the base insulating film 30. With this configuration, the second connection portion 52 can be properly connected to the lower end of the side wall 35b of the base electrode 35.

[0580] The fourth connection portion 62 of the second base via electrode 60 may be in contact with the base insulating film 30. With this configuration, since the design assumes that the fourth connection portion 62 is connected to the base insulating film 30, the fourth connection portion 62 is properly connected to the side wall 35b of the base electrode 35. In addition, the effect of misalignment of the second base via electrode 60 relative to the base electrode 35 is appropriately reduced.

[0581] The contact portion of the fourth connection portion 62 with respect to the base insulating film 30 may be located closer to the tip 2 than the contact portion of the base electrode 35 with respect to the base insulating film 30. With this configuration, the second connection portion 52 can be properly connected to the lower end of the side wall 35b of the base electrode 35.

[0582] The semiconductor device 1A may include a main surface insulating film 25 that covers the chip 2. In this case, the base insulating film 30 may have a thickness greater than that of the main surface insulating film 25 and may be continuous with the main surface insulating film 25. With this configuration, the electrical influence of the base electrode 35 on the chip 2 is reduced by the relatively thick base insulating film 30, and at the same time, the electrical influence of the chip 2 on the base electrode 35 is reduced by the relatively thick base insulating film 30.

[0583] Furthermore, when the second connection portion 52 (first base via electrode 50) is in contact with the base insulating film 30, the base insulating film 30 functions as a stopper for the second connection portion 52. This effectively suppresses short circuits between the chip 2 and the first base via electrode 50.

[0584] Similarly, when the fourth connection portion 62 (second base via electrode 60) is in contact with the base insulating film 30, the base insulating film 30 functions as a stopper for the fourth connection portion 62. This effectively suppresses short circuits between the chip 2 and the second base via electrode 60. Thus, the stability of the resistance value of the base electrode 35 is improved by the relatively thick base insulating film 30. The base insulating film 30 may be connected to the main surface insulating film 25.

[0585] The semiconductor device 1A may include a pn junction (well region 22) formed on the surface layer of the chip 2. In this case, the base insulating film 30 may cover the pn junction on the chip 2. The base electrode 35 may face the pn junction via the base insulating film 30.

[0586] In this configuration, a depletion layer is formed in the region below the base electrode 35, starting from the pn junction. This reduces the electric field on the base insulating film 30 in the region below the base electrode 35, improving the electrical breakdown voltage.

[0587] The first electrode (74) may be a gate pad electrode 74. In this configuration, the base electrode 35 functions as a gate resistor Rg associated with the gate pad electrode 74. In this case, the second electrode (79) is a gate wiring electrode 79 electrically connected to the gate structure 15, and may be electrically connected to the gate pad electrode 74 via the base electrode 35 as a gate resistor Rg. This configuration improves the stability of the gate resistor Rg electrically interposed between the gate pad electrode 74 and the gate wiring electrode 79.

[0588] From a different perspective, the semiconductor device 1A may include a base electrode 35, a second base via electrode 60 (via electrode), and a wiring electrode (79). The second base via electrode 60 may be placed on top of the base electrode 35. The wiring electrode (79) may be placed on top of the second base via electrode 60.

[0589] The wiring electrode (79) may include a wiring via connection portion 80, a first wiring portion 81, and a wiring connection portion 86. The wiring via connection portion 80 may extend in a first direction X on the second base via electrode 60. The first wiring portion 81 may be spaced apart on one side of a second direction Y that intersects the first direction X from the second base via electrode 60. The first wiring portion 81 may have a portion that extends in the first direction X along the wiring via connection portion 80.

[0590] The wiring connection portion 86 may be connected to the wiring via connection portion 80 and the first wiring portion 81 between the wiring via connection portion 80 and the first wiring portion 81. The wiring connection portion 86 may have a length shorter than the length of the wiring via connection portion 80 with respect to the first direction X.

[0591] This configuration provides a semiconductor device 1A that contributes to improving electrical characteristics. For example, with this semiconductor device 1A, the current path between the wiring via connection portion 80 and the first wiring portion 81 is narrowed by the wiring connection portion 86, and the current spread between the wiring via connection portion 80 and the first wiring portion 81 is suppressed. As a result, unwanted fluctuations in the resistance value (wiring resistance) caused by current spread in the current path between the second base via electrode 60 and the first wiring portion 81 are suppressed.

[0592] The second base via electrode 60 may extend in a strip shape in the first direction X. In this case, the wiring connection portion 86 may have a length shorter than the length of the second base via electrode 60 with respect to the first direction X. With this configuration, the current path between the second base via electrode 60 and the first wiring portion 81 is narrowed by the wiring connection portion 86. This appropriately suppresses the current spread between the second base via electrode 60 and the first wiring portion 81.

[0593] The base electrode 35 may extend in a strip shape in the first direction X. In this case, the wiring connection portion 86 may have a length shorter than the length of the base electrode 35 with respect to the first direction X. With this configuration, the current path between the base electrode 35 and the first wiring portion 81 is narrowed by the wiring connection portion 86. This appropriately suppresses the current spread between the base electrode 35 and the first wiring portion 81.

[0594] The wiring connection portion 86 may have an arc-shaped curved side wall. The wiring connection portion 86 may have a straight-extending side wall. The first wiring portion 81 may be spaced apart from the base electrode 35 on one side in the second direction Y. In this case, the wiring connection portion 86 may have a portion facing the area outside the base electrode 35 in the stacking direction.

[0595] The base electrode 35 may have an upper surface 35a and a side wall 35b. In this case, the second base via electrode 60 may have a third connection portion 61 to the upper surface 35a of the base electrode 35 and a fourth connection portion 62 to the side wall 35b of the base electrode 35. The wiring via connection portion 80 may be connected to both the third connection portion 61 and the fourth connection portion 62.

[0596] In this configuration, the current path originating from the third connection portion 61 of the second base via electrode 60 is formed along the upper surface 35a of the base electrode 35, and the current path originating from the fourth connection portion 62 of the second base via electrode 60 is formed along the side wall 35b of the base electrode 35.

[0597] As a result, the current path originating from the second base via electrode 60 is extended to the portion along the side wall 35b of the base electrode 35, and the bypass path of the current is suppressed. Consequently, unwanted fluctuations in the resistance value (wiring resistance) caused by the bypass current are suppressed.

[0598] Furthermore, this configuration reduces the influence of misalignment of the second base via electrode 60 relative to the base electrode 35, thereby suppressing variations in resistance values ​​caused by such misalignment. Consequently, the stability of the resistance value of the base electrode 35 is improved.

[0599] The second base via electrode 60 may have a width of 2 μm or less. Multiple second base via electrodes 60 may be arranged on the base electrode 35 at intervals. In this case, the wiring via connection portion 80 may be arranged on the multiple second base via electrodes 60. With this configuration, unwanted fluctuations in the resistance value (wiring resistance) caused by current spreading in the current path between the multiple second base via electrodes 60 and the first wiring portion 81 are suppressed.

[0600] The multiple second base via electrodes 60 may be arranged with a spacing greater than the width of each second base via electrode 60. This configuration appropriately reduces the effect of misalignment between the multiple second base via electrodes 60 (for example, variations in electrical characteristics due to contact). The multiple second base via electrodes 60 may be arranged with a spacing of 5 μm or less.

[0601] The base electrode 35 may be a resistive electrode. In this case, the second base via electrode 60 may have a lower resistivity than the base electrode 35. The wiring electrode (79) may have a lower resistivity than the base electrode 35.

[0602] This configuration suppresses fluctuations in wiring resistance caused by current spread between the base electrode 35, which acts as a resistive electrode, and the first wiring section 81. As a result, the electrical characteristics of the electronic circuit, including the base electrode 35 as a resistive electrode, are improved.

[0603] The semiconductor device 1A may include a first base via electrode 50 and a pad electrode (74). The first base via electrode 50 may be placed on the base electrode 35. The pad electrode (74) may be placed on the first base via electrode 50. In this case, the second base via electrode 60 may be placed on the base electrode 35 with a gap between it and the first base via electrode 50 on one side in the second direction Y. The wiring electrode (79) may be placed on the second base via electrode 60 with a gap between it and the pad electrode (74).

[0604] With this configuration, a current path is formed between the pad electrode (74) and the first wiring section 81 via the base electrode 35. This suppresses undesirable fluctuations in the resistance value (wiring resistance) caused by current spreading in the current path between the pad electrode (74) and the first wiring section 81.

[0605] The pad electrode (74) includes a pad via connection portion 75, a pad portion 76, and a pad connecting portion 77. The pad via connection portion 75 may extend in a first direction X on the first base via electrode 50. The pad portion 76 may be spaced apart from the first base via electrode 50 on the other side in a second direction Y. The pad connecting portion 77 may be connected between the pad via connection portion 75 and the pad portion 76.

[0606] With this configuration, the joining points of conductors such as bonding wires can be limited to the pad portion 76. In other words, the conductors can be joined to the pad portion 76 that does not overlap with the first base via electrode 50 in the thickness direction Z.

[0607] This effectively suppresses stress on the first base via electrode 50 caused by the conductor (during conductor connection), and effectively suppresses fluctuations in the connection resistance of the first base via electrode 50 with respect to the base electrode 35. In this case, the wiring via connection portion 80 of the wiring electrode (79) may be spaced apart from the pad via connection portion 75 on one side in the second direction Y.

[0608] The pad portion 76 may be positioned at a distance from the base electrode 35 to the other side in the second direction Y. The pad connecting portion 77 may have a portion facing the area outside the base electrode 35 in the stacking direction.

[0609] The pad connecting portion 77 may have a length shorter than the length of the pad via connection portion 75 with respect to the first direction X. The second base via electrode 60 may extend in a strip shape in the first direction X. The pad connecting portion 77 may have a length shorter than the length of the second base via electrode 60 with respect to the first direction X. With this configuration, the boundary between the pad via connection portion 75 and the pad portion 76 is appropriately demarcated by the pad connecting portion 77.

[0610] The base electrode 35 may have an upper surface 35a and a side wall 35b. In this case, the first base via electrode 50 may have a first connection portion 51 connected to the upper surface 35a of the base electrode 35 and a second connection portion 52 connected to the side wall 35b of the base electrode 35. The pad via connection portion 75 may be connected to both the first connection portion 51 and the second connection portion 52.

[0611] In this configuration, the current path originating from the first connection portion 51 of the first base via electrode 50 is formed along the upper surface 35a of the base electrode 35, and the current path originating from the second connection portion 52 of the first base via electrode 50 is formed along the side wall 35b of the base electrode 35.

[0612] As a result, the current path originating from the first base via electrode 50 is extended to the portion along the side wall 35b of the base electrode 35, and the bypass path of the current is suppressed. Consequently, unwanted fluctuations in the resistance value (wiring resistance) caused by the bypass current are suppressed.

[0613] Furthermore, this configuration reduces the influence of misalignment of the first base via electrode 50 relative to the base electrode 35, thereby suppressing variations in resistance values ​​caused by such misalignment. Consequently, the stability of the resistance value of the base electrode 35 is improved.

[0614] The semiconductor device 1A may include an insulating interlayer film 46 that covers the base electrode 35. In this case, the second base via electrode 60 may be embedded in the interlayer film 46. The wiring electrode (79) may be connected to the second base via electrode 60 on the interlayer film 46.

[0615] With this configuration, the connection points of the second base via electrode 60 to the base electrode 35 are appropriately restricted by the interlayer film 46, and the connection points of the wiring electrode (79) to the second base via electrode 60 are appropriately restricted by the interlayer film 46. As a result, the stability of the resistance value of the base electrode 35 is appropriately improved.

[0616] The semiconductor device 1A may include a chip 2. In this case, the base electrode 35 may be placed on the chip 2. The chip 2 may include a wide-bandgap semiconductor. In this case, the chip 2 may include SiC. According to these configurations, a semiconductor device 1A as a novel wide-bandgap semiconductor device (SiC semiconductor device) is provided.

[0617] In wide-bandgap semiconductor devices, the electrical characteristics are appropriately improved by the physical properties of the wide-bandgap semiconductor. In particular, since wide-bandgap semiconductor devices are used in harsh environments (high voltage and / or high humidity environments), stabilizing the resistance value is effective in suppressing malfunctions caused by undesirable fluctuations in resistance value.

[0618] The semiconductor device 1A may include a base insulating film 30 that covers the chip 2. In this case, the base electrode 35 may be placed on top of the base insulating film 30. With this configuration, short circuits between the chip 2 and the base electrode 35 are appropriately suppressed by the base insulating film 30. This appropriately suppresses the electrical influence of the base electrode 35 on the chip 2, and the electrical influence of the chip 2 on the base electrode 35.

[0619] The semiconductor device 1A may include a main surface insulating film 25 that covers the chip 2. In this case, the base insulating film 30 may have a thickness greater than that of the main surface insulating film 25 and may be continuous with the main surface insulating film 25. With this configuration, the electrical influence of the base electrode 35 on the chip 2 is reduced by the relatively thick base insulating film 30, and at the same time, the electrical influence of the chip 2 on the base electrode 35 is reduced by the relatively thick base insulating film 30.

[0620] The semiconductor device 1A may include a pn junction (well region 22) formed on the surface layer of the chip 2. In this case, the base insulating film 30 may cover the pn junction on the chip 2. The base electrode 35 may face the pn junction via the base insulating film 30.

[0621] In this configuration, a depletion layer is formed in the region below the base electrode 35, starting from the pn junction. This reduces the electric field on the base insulating film 30 in the region below the base electrode 35, improving the electrical breakdown voltage.

[0622] The wiring electrode (79) may be a gate wiring electrode 79. With this configuration, unwanted fluctuations in the gate resistance Rg associated with the gate wiring electrode 79 are suppressed. The pad electrode (74) may be a gate pad electrode 74. With this configuration, unwanted fluctuations in the gate resistance Rg associated with the gate pad electrode 74 are suppressed.

[0623] Figure 21 is an enlarged plan view showing the pad area 9A of the semiconductor device 1B according to the second embodiment, along with an example of the electrode layout. Referring to Figure 21, the semiconductor device 1B has an embodiment in which the electrode layout of the semiconductor device 1A has been modified. Specifically, the semiconductor device 1B includes a line electrode 40 formed integrally with the base electrode 35. In this embodiment, the first line portion 41 of the line electrode 40 is formed integrally with the base electrode 35.

[0624] Of course, a fourth line portion 44 (either the first portion 44A and the second portion 44B, or both) may be formed integrally with the base electrode 35 in place of or in addition to the first line portion 41. The gate wiring electrode 79 includes a wiring via connection portion 80, first to fifth wiring portions 81 to 85, and a wiring connection portion 86, as in the first embodiment.

[0625] Figure 22 is an enlarged plan view showing the pad area 9A of the semiconductor device 1C according to the third embodiment, along with an example of electrode layout. Referring to Figure 22, the semiconductor device 1C has an embodiment in which the layout of the plurality of second base via electrodes 60 according to the semiconductor device 1B has been changed.

[0626] Specifically, the multiple second base via electrodes 60 in the semiconductor device 1C are formed as multiple gate via electrodes 67 relative to the line electrode 40. In other words, in this configuration, the multiple gate via electrodes 67 are formed as multiple second base via electrodes 60 relative to the base electrode 35, and together with the multiple first base via electrodes 50, they define a gate resistance Rg on the base electrode 35.

[0627] In this configuration, the gate wiring electrode 79 includes first to fifth wiring sections 81 to 85 and does not have a wiring via connection section 80 and a wiring linkage section 86. The first wiring section 81 also serves as a wiring via connection section 80 and is electrically connected to the base electrode 35 and the first line section 41 via a plurality of gate via electrodes 67 (a plurality of second base via electrodes 60).

[0628] Figure 23 is an enlarged plan view showing the pad area 9A of the semiconductor device 1D according to the fourth embodiment, along with an example of electrode layout. Referring to Figure 23, the semiconductor device 1D has an embodiment in which the layout of the base electrode 35 and base pad electrode 36 of the semiconductor device 1A has been changed.

[0629] Specifically, the semiconductor device 1D includes a base pad electrode 36 integrally formed with the base electrode 35. The base pad electrode 36 has a width approximately equal to the width of the base electrode 35. Of course, the width of the base pad electrode 36 may be greater or less than the width of the base electrode 35. In this case, the boundary between the base electrode 35 and the base pad electrode 36 is defined by the difference in width.

[0630] The gate pad electrode 74 includes a pad via connection portion 75, a pad portion 76, and a pad connecting portion 77, similar to the semiconductor device 1A. In this embodiment, the pad connecting portion 77 has a width smaller than the width of the pad via connection portion 75 and the width of the pad portion 76. Of course, the width of the pad connecting portion 77 may be approximately equal to either or both of the widths of the pad via connection portion 75 and the pad portion 76.

[0631] Figure 24 is an enlarged plan view showing the pad area 9A of the semiconductor device 1E according to the fifth embodiment, along with an example of electrode layout. Referring to Figure 24, the semiconductor device 1E has an embodiment in which the layout of the plurality of first base via electrodes 50 according to the semiconductor device 1D has been changed.

[0632] Specifically, the plurality of first base via electrodes 50 in the semiconductor device 1E are formed as a plurality of pad via electrodes 65 relative to the base pad electrode 36. In other words, in this configuration, the plurality of pad via electrodes 65 are formed as a plurality of first base via electrodes 50 relative to the base pad electrode 36, and together with the plurality of second base via electrodes 60, they define the gate resistance Rg on the base electrode 35.

[0633] In this embodiment, the gate pad electrode 74 has a pad portion 76 and does not include a pad via connection portion 75 and a pad connecting portion 77. Of course, the gate pad electrode 74 may include a pad via connection portion 75 and a pad connecting portion 77.

[0634] Figure 25 is an enlarged plan view showing the pad area 9A of the semiconductor device 1F according to the sixth embodiment, along with an example of electrode layout. Referring to Figure 25, the semiconductor device 1F has an embodiment in which the layout of the base electrode 35, base pad electrode 36, and line electrode 40 of the semiconductor device 1A has been changed.

[0635] Specifically, the semiconductor device 1F includes a base pad electrode 36 integrally formed with the base electrode 35, and a line electrode 40 integrally formed with the base electrode 35. In this embodiment, the first line portion 41 of the line electrode 40 is integrally formed with the base electrode 35.

[0636] The base pad electrode 36 has a width approximately equal to the width of the base electrode 35. Of course, the width of the base pad electrode 36 may be greater or less than the width of the base electrode 35. In this case, the boundary between the base electrode 35 and the base pad electrode 36 is defined by the difference in width.

[0637] The gate pad electrode 74 includes a pad via connection portion 75, a pad portion 76, and a pad connecting portion 77, similar to the case of semiconductor device 1A. In this embodiment, the gate wiring electrode 79 includes first to fifth wiring portions 81 to 85, a wiring connecting portion 86, and a wiring via connection portion 80.

[0638] Either the configuration in which the second base via electrode 60 is formed as a gate via electrode 67 (see Figure 22), or the configuration in which the first base via electrode 50 is formed as a pad via electrode 65 (see Figure 24), can also be applied to the semiconductor device 1F.

[0639] Figure 26 is an enlarged plan view showing the pad area 9A of the semiconductor device 1G according to the seventh embodiment, along with an example of electrode layout. Figure 27 is an electrical circuit diagram showing the electrical configuration of the semiconductor device 1G shown in Figure 26.

[0640] Referring to Figures 26 and 27, the semiconductor device 1G includes a plurality (two or more) of resistor units RU. In this embodiment, the plurality of resistor units RU are arranged on the base insulating film 30 with spacing between them in a first direction X in the pad region 9A.

[0641] The number of resistor units RU may be between 2 and 20. The number of resistor units RU may be in at least one of the following ranges: 2 to 4, 4 to 6, 6 to 8, 8 to 10, 10 to 12, 12 to 14, 14 to 16, 16 to 18, and 18 to 20. In this embodiment, semiconductor device 1G includes, as an example, three resistor units RU.

[0642] Each of the multiple resistor units RU includes, as in the semiconductor device 1A, a base electrode 35, one or more (in this embodiment, multiple) first base via electrodes 50, and one or more (in this embodiment, multiple) second base via electrodes 60. Each of the multiple resistor units RU includes a gate resistor Rg partitioned in the base electrode 35.

[0643] Each of the multiple first base via electrodes 50 has a first connection portion 51 and a second connection portion 52. Each of the multiple second base via electrodes 60 has a third connection portion 61 and a fourth connection portion 62.

[0644] Multiple gate resistors Rg may have equal resistance values ​​or different resistance values. Multiple base electrodes 35 may have approximately equal planar shapes (areas) or different planar shapes (areas). In multiple resistor units RU, the spacing between multiple first base via electrodes 50 and multiple second base via electrodes 60 may be approximately equal or different.

[0645] In this configuration, the pad via connection portion 75 of the gate pad electrode 74 is mechanically and electrically connected to a plurality of first base via electrodes 50 at one end of a plurality of base electrodes 35 (resistance unit RU), and is electrically connected to one end of the plurality of base electrodes 35 via the plurality of first base via electrodes 50.

[0646] In this configuration, the wiring via connection portion 80 of the gate wiring electrode 79 is mechanically and electrically connected to a plurality of second base via electrodes 60 at the other end of a plurality of base electrodes 35 (resistor units RU), and is electrically connected to the other end of the plurality of base electrodes 35 via the plurality of second base via electrodes 60. In other words, the gate wiring electrode 79 connects a plurality of resistor units RU in parallel together with the gate pad electrode 74.

[0647] In other words, the semiconductor device 1G includes a resistor parallel circuit RPC electrically interposed between the gate pad electrode 74 and the gate wiring electrode 79 (see Figure 27). The resistor parallel circuit RPC has a circuit configuration that includes a plurality of resistor units RU connected in parallel. Each of the plurality of resistor units RU includes a gate resistor Rg partitioned in the region between a plurality of first base via electrodes 50 and a plurality of second base via electrodes 60.

[0648] Since the resistance value of a parallel resistor circuit (RPC) is the combined resistance of multiple gate resistors Rg, a smaller resistance value can be achieved compared to the case where a single gate resistor Rg is used. In particular, by using multiple resistor units RU (base electrode 35), a relatively small resistance value can be achieved without forming a relatively small single resistor unit RU (base electrode 35).

[0649] Therefore, the resistor parallel circuit RPC is an effective means of lowering the resistance value by effectively utilizing a limited area (pad area 9A). Furthermore, the configuration of multiple first base via electrodes 50 is effective in improving the stability of relatively small resistance values. Furthermore, the configuration of multiple second base via electrodes 60 is effective in improving the stability of relatively small resistance values.

[0650] The configurations according to the second to sixth embodiments are also applicable to the semiconductor device 1G. For example, the semiconductor device 1G may include either or both of the following: line electrodes 40 (see Figure 21) integrally formed with the base electrodes 35 of the plurality of resistor units RU, and base pad electrodes 36 (see Figure 23) integrally formed with the base electrodes 35 of the plurality of resistor units RU.

[0651] Figure 28 is an enlarged plan view showing the pad area 9A of the semiconductor device 1H according to the eighth embodiment, along with an example of electrode layout. Figure 29 is an electrical circuit diagram showing the electrical configuration of the semiconductor device 1H shown in Figure 28. Referring to Figures 28 and 29, the semiconductor device 1H includes a base electrode 35 incorporated into a portion of the line electrode 40.

[0652] In this configuration, the base insulating film 30 has a portion in the outer region 9B that covers the first main surface 3, and the first line portion 41 of the line electrode 40 is arranged on the base insulating film 30 as the base electrode 35. The base insulating film 30 covers the outer well region 22B in the outer region 9B. The second to fifth line portions 42 to 45 may be arranged on the base insulating film 30 or on the main surface insulating film 25.

[0653] The second line section 42 is physically separated from the first line section 41 (base electrode 35) by the first gap section G1, and the third line section 43 is physically separated from the first line section 41 (base electrode 35) by the second gap section G2.

[0654] The first gap G1 has a width smaller than the width of the first line portion 41 and extends in the second direction Y. The width of the first gap G1 may be larger than the width of the first line portion 41. The first gap G1 exposes either or both of the base insulating film 30 and the main surface insulating film 25.

[0655] The second gap G2 has a width smaller than the width of the first line portion 41 and extends in the second direction Y. The width of the second gap G2 may be larger than the width of the first line portion 41. The second gap G2 exposes either or both of the base insulating film 30 and the main surface insulating film 25.

[0656] Multiple first base via electrodes 50 are arranged in the inner part (central part in this configuration) of the first line portion 41. The multiple first base via electrodes 50 are arranged with spacing in the first direction X and each extends in a strip shape in the second direction Y.

[0657] Each of the multiple first base via electrodes 50 has a first connection portion 51 to the upper surface 35a of the first line portion 41 and a second connection portion 52 to the side wall 35b of the first line portion 41. The configuration of the first connection portion 51 and the second connection portion 52 to the first line portion 41 is the same as the configuration of the first connection portion 51 and the second connection portion 52 to the base electrode 35 in semiconductor device 1A (i.e., the first direction X and the second direction Y are swapped).

[0658] The plurality of second base via electrodes 60 include one plurality of second base via electrodes 60A arranged on one end side of the first line portion 41, and the other plurality of second base via electrodes 60B arranged on the other end side of the first line portion 41.

[0659] Multiple second base via electrodes 60A are arranged at intervals from the multiple first base via electrodes 50 towards one end of the first line portion 41, and face the multiple first base via electrodes 50 in the first direction X. Multiple second base via electrodes 60B are arranged at intervals from the multiple first base via electrodes 50 towards the other end of the first line portion 41, and face the multiple first base via electrodes 50 in the first direction X.

[0660] Each of the multiple second base via electrodes 60 (60A, 60B) has a third connection portion 61 to the upper surface 35a of the first line portion 41 and a fourth connection portion 62 to the side wall 35b of the first line portion 41.

[0661] The third connection portions 61 of the multiple second base via electrodes 60 (60A, 60B) face the first connection portion 51 of the first base via electrode 50 in the first direction X along the upper surface 35a of the first line portion 41, and are electrically connected to the first connection portion 51 and the second connection portion 52 of the first base via electrode 50 via the first line portion 41.

[0662] The fourth connection portion 62 of the multiple second base via electrodes 60 (60A, 60B) faces the second connection portion 52 of the first base via electrode 50 in the first direction X along the side wall 35b of the first line portion 41, and is electrically connected to the first connection portion 51 and the second connection portion 52 of the first base via electrode 50 via the first line portion 41.

[0663] The configuration of the third connection portion 61 and the fourth connection portion 62 with respect to the first line portion 41 is the same as the configuration of the third connection portion 61 and the fourth connection portion 62 with respect to the base electrode 35 in semiconductor device 1A (i.e., the first direction X and the second direction Y are swapped).

[0664] The semiconductor device 1H includes a resistor unit RU. In this embodiment, the resistor unit RU includes a first line portion 41 as a base electrode 35, a plurality of first base via electrodes 50, and a plurality of second base via electrodes 60. The resistor unit RU also includes a first gate resistor Rg1 and a second gate resistor Rg2 (see also Figure 29).

[0665] The first gate resistor Rg1 is located in the region between the multiple first base via electrodes 50 and the multiple second base via electrodes 60A in the first line section 41. The second gate resistor Rg2 is located in the region between the multiple first base via electrodes 50 and the multiple second base via electrodes 60B in the first line section 41. The second gate resistor Rg2 is connected in parallel to the first gate resistor Rg1.

[0666] The resistance value of the second gate resistor Rg2 may be approximately equal to the resistance value of the first gate resistor Rg1, may be greater than the resistance value of the first gate resistor Rg1, or may be less than the resistance value of the first gate resistor Rg1.

[0667] The resistance value of the gate resistor Rg is appropriately adjusted by the resistance value of the first line portion 41 (polysilicon impurity concentration), the thickness of the base electrode 35, the flat area of ​​the first line portion 41 (length in the first direction X and width in the second direction Y), the distance between the first base via electrode 50 and the second base via electrode 60 (60A, 60B), etc.

[0668] The gate pad electrode 74 has a pad via connection portion 75, a pad portion 76, and a pad connecting portion 77, and is electrically connected to the first line portion 41 via a plurality of first base via electrodes 50 and electrically connected to the base pad electrode 36 via a plurality of pad via electrodes 65.

[0669] In this configuration, the pad via connection portion 75 is located in the outer region 9B and faces the inner portion (central portion in this configuration) of the first line portion 41 via the interlayer film 46. In this configuration, the pad via connection portion 75 is formed in a polygonal shape (a quadrilateral shape in this configuration) having four sides parallel to the periphery of the first main surface 3. In this configuration, the pad via connection portion 75 is formed in a strip-like (rectangular) shape extending in the second direction Y.

[0670] The pad via connection portion 75 is mechanically and electrically connected to a plurality of first base via electrodes 50 on the interlayer film 46, and is electrically connected to the inner portion of the first line portion 41 via the plurality of first base via electrodes 50.

[0671] In this configuration, the pad portion 76 has a width greater than the width of the pad via connection portion 75 with respect to the first direction X and is positioned in the pad region 9A. The pad portion 76 has a larger planar area than the pad via connection portion 75 and is provided as a connection portion for a conductor such as a bonding wire. The pad portion 76 is electrically connected to the base pad electrode 36 via a plurality of pad via electrodes 65, similar to the semiconductor device 1A.

[0672] In this configuration, the pad connecting portion 77 has a width smaller than the width of the pad portion 76 with respect to the first direction X, and connects the pad via connection portion 75 and the pad portion 76. In this configuration, the width of the pad connecting portion 77 is approximately equal to the width of the pad via connection portion 75. The pad connecting portion 77 separates the connection point of the conductor from the pad via connection portion 75 to the pad portion 76. The width of the pad connecting portion 77 may be larger or smaller than the width of the pad via connection portion 75.

[0673] In this configuration, the gate wiring electrode 79 does not have a first wiring section 81, but has second to fifth wiring sections 82 to 84. The second wiring section 82 is formed as a wiring via connection section 80 for a plurality of second base via electrodes 60A, and the third wiring section 83 is formed as a wiring via connection section 80 for a plurality of second base via electrodes 60B.

[0674] The second wiring section 82 is formed at a distance from the pad via connection section 75 on one side in the first direction X (the side of the first active region 8A) and extends in a strip shape along the second line section 42 in both the first direction X and the second direction Y. The second wiring section 82 faces one end of the first line section 41 and the second line section 42 via the interlayer film 46.

[0675] The second wiring section 82 is mechanically and electrically connected to a plurality of second base via electrodes 60A on the interlayer film 46, and is electrically connected to one end of the first line section 41 via the plurality of second base via electrodes 60A. The second wiring section 82 is mechanically and electrically connected to a plurality of gate via electrodes 67 on the interlayer film 46, and is electrically connected to the second line section 42 via the plurality of gate via electrodes 67.

[0676] The third wiring section 83 is formed at a distance from the pad via connection section 75 on the other side in the first direction X (towards the second active region 8B) and extends in a strip shape along the third line section 43 in both the first direction X and the second direction Y. The third wiring section 83 faces the other end of the first line section 41 and the third line section 43 via the interlayer film 46.

[0677] The third wiring section 83 is mechanically and electrically connected to a plurality of second base via electrodes 60B on the interlayer film 46, and is electrically connected to the other end of the first line section 41 via the plurality of second base via electrodes 60B. The third wiring section 83 is mechanically and electrically connected to a plurality of gate via electrodes 67 on the interlayer film 46, and is electrically connected to the third line section 43 via the plurality of gate via electrodes 67.

[0678] Thus, the semiconductor device 1H includes a resistor parallel circuit RPC electrically interposed between the transistor structure T and the gate pad electrode 74 (see Figure 29). The resistor parallel circuit RPC is composed of one resistor unit RU and includes a first gate resistor Rg1 and a second gate resistor Rg2 connected in parallel.

[0679] The first gate resistor Rg1 is electrically interposed between the gate pad electrode 74 and the second wiring section 82, and the second gate resistor Rg2 is electrically interposed between the gate pad electrode 74 and the third wiring section 83.

[0680] With this configuration, the base electrode 35 is formed using a portion of the line electrode 40, thus reducing the area occupied by the base electrode 35. Furthermore, the resistor parallel circuit RPC can achieve a lower resistance value than when a single gate resistor Rg is used. Therefore, the resistor parallel circuit RPC is an effective means of downwardly adjusting the resistance value of the gate resistor Rg in a limited area (pad area 9A).

[0681] Furthermore, the configuration of multiple first base via electrodes 50 is effective in improving the stability of relatively small resistance values. Similarly, the configuration of multiple second base via electrodes 60 is effective in improving the stability of relatively small resistance values.

[0682] Figure 30 is an enlarged plan view showing the pad area 9A of the semiconductor device 1I according to the ninth embodiment, along with an example of electrode layout. Referring to Figure 30, the semiconductor device 1I has an embodiment in which the layout of the line electrodes 40 of the semiconductor device 1H according to the eighth embodiment has been changed.

[0683] Specifically, in this configuration, the second line portion 42 is integrally formed with the first line portion 41, which serves as the base electrode 35, and is separated from the first line portion 41 by a plurality of second base via electrodes 60A.

[0684] Similarly, in this configuration, the third line portion 43 is integrally formed with the first line portion 41, which serves as the base electrode 35, and is separated from the first line portion 41 by a plurality of second base via electrodes 60B.

[0685] Figure 31 is an enlarged plan view showing a semiconductor device 1J according to the tenth embodiment, along with an example of electrode layout. Figure 32 is a cross-sectional view taken along the line XXXII-XXXII shown in Figure 31. Figure 33 is a cross-sectional view taken along the line XXXIII-XXXIII shown in Figure 31. Figure 34 is an electrical circuit diagram showing the electrical configuration of the semiconductor device 1J shown in Figure 31.

[0686] In semiconductor devices 1A to 1I according to the first to ninth embodiments, the base electrode 35 (resistance unit RU) was electrically interposed between the gate pad electrode 74 and the gate wiring electrode 79. In contrast, semiconductor device 1J includes a base electrode 35 (resistance unit RU) incorporated into a part of the line electrode 40. In other words, in semiconductor device 1J, the base electrode 35 (resistance unit RU) is incorporated into a part of the gate wiring electrode 79 as an internal resistance of the gate wiring electrode 79.

[0687] The location where the base electrode 35 is incorporated into the line electrode 40 is arbitrary. In other words, one or more base electrodes 35 can be incorporated into any region of the first to fifth line sections 41 to 45. Figures 31 to 33 show an example in which the base electrode 35 is incorporated into the portion of the line electrode 40 that extends in the first direction X (here, the first line section 41 as an example).

[0688] Of course, the base electrode 35 may be incorporated into the portion of the line electrode 40 that extends in the second direction Y (for example, the second to fifth line portions 42 to 45). The specific configuration in this case can be obtained by replacing "first direction X" with "second direction Y" in the following description.

[0689] In the semiconductor device 1J, the base insulating film 30 is selectively formed in either the outer region 9B or the boundary region 9C, or both, and line electrodes 40 (first to fifth line portions 41 to 45) are arranged on either the base insulating film 30 or the main surface insulating film 25, or both.

[0690] The semiconductor device 1J includes a first removal portion Rm1 provided at any location on the line electrode 40 (in this case, the first line portion 41). The first removal portion Rm1 is a region of the line electrode 40 from which the conductor has been removed.

[0691] The line electrode 40 includes a first line portion 40A partitioned on one side in the extending direction (first direction X) by the first removal portion Rm1, and a second line portion 40B partitioned on the other side in the extending direction (first direction X) by the first removal portion Rm1.

[0692] The semiconductor device 1J includes a base electrode 35 positioned in the first removal portion Rm1 of the line electrode 40. The base electrode 35 is positioned in the first removal portion Rm1 at a distance from the first line portion 40A and the second line portion 40B in the first direction X. The base electrode 35 faces the first line portion 40A on one side in the first direction X and faces the second line portion 40B on the other side in the first direction X.

[0693] The base electrode 35 separates the first line portion 40A from the first gap portion Gp1, and separates the second line portion 40B from the second gap portion Gp2. The first gap portion Gp1 exposes either or both of the base insulating film 30 and the main surface insulating film 25. The second gap portion Gp2 exposes either or both of the base insulating film 30 and the main surface insulating film 25.

[0694] In this embodiment, the first gap Gp1 has a width smaller than the width of the first line portion 40A (width of the second line portion 40B) and extends in a band shape in the second direction Y. The width of the first gap Gp1 may be larger than the width of the first line portion 40A (width of the second line portion 40B).

[0695] In this embodiment, the second gap Gp2 has a width smaller than the width of the first line portion 40A (width of the second line portion 40B) and extends in a band shape in the second direction Y. The width of the second gap Gp2 may be larger than the width of the first line portion 40A (width of the second line portion 40B).

[0696] The base electrode 35 extends in a strip shape in the first direction X, following the extending direction of the first line portion 40A and the second line portion 40B. The base electrode 35 has one end on one side of the first direction X (the side of the first line portion 40A) and the other end on the other side of the first direction X (the side of the second line portion 40B).

[0697] The base electrode 35 has a width that is approximately equal to the width of the first line portion 40A and the width of the second line portion 40B with respect to the direction perpendicular to the extending direction of the first line portion 40A and the second line portion 40B (second direction Y). The width of the base electrode 35 may be greater than or less than the width of the first line portion 40A. The width of the base electrode 35 may be greater than or less than the width of the second line portion 40B.

[0698] The semiconductor device 1J, like the semiconductor device 1A, includes one or more (in this embodiment, more) first base via electrodes 50. The multiple first base via electrodes 50 penetrate the interlayer film 46 and are mechanically and electrically connected to one end of the base electrode 35 (the end on the first line portion 40A side).

[0699] In this configuration, the multiple first base via electrodes 50 are unevenly distributed towards one end of the base electrode 35 relative to the central part of the base electrode 35. The multiple first base via electrodes 50 are arranged at intervals in the first direction X and each extends in a strip shape in the second direction Y.

[0700] Each of the multiple first base via electrodes 50 has a first connection portion 51 to the upper surface 35a of the base electrode 35 and a second connection portion 52 to the side wall 35b of the base electrode 35, similar to the semiconductor device 1A.

[0701] The configuration of the first connection portion 51 and the second connection portion 52 to the base electrode 35 is the same as the configuration of the first connection portion 51 and the second connection portion 52 to the base electrode 35 in semiconductor device 1A (i.e., the first direction X and the second direction Y are swapped).

[0702] The semiconductor device 1J, like the semiconductor device 1A, includes one or more (in this embodiment, more) second base via electrodes 60. The multiple second base via electrodes 60 penetrate the interlayer film 46 and are mechanically and electrically connected to the other end (the end on the second line portion 40B side) of the base electrode 35.

[0703] In this configuration, the multiple second base via electrodes 60 are unevenly distributed on the other end side of the base electrode 35 relative to the central part of the base electrode 35. The multiple second base via electrodes 60 are arranged with spacing in the first direction X and each extends in a strip shape in the second direction Y.

[0704] The multiple second base via electrodes 60 each have a third connection portion 61 to the upper surface 35a of the base electrode 35 and a fourth connection portion 62 to the side wall 35b of the base electrode 35, similar to the case of semiconductor device 1A.

[0705] The third connection portion 61 faces the first connection portion 51 of the first base via electrode 50 in the first direction X along the upper surface 35a of the base electrode 35. The fourth connection portion 62 faces the second connection portion 52 of the first base via electrode 50 in the first direction X along the side wall 35b of the base electrode 35.

[0706] The configuration of the third connection portion 61 and the fourth connection portion 62 to the base electrode 35 is the same as the configuration of the third connection portion 61 and the fourth connection portion 62 to the base electrode 35 in semiconductor device 1A (i.e., the first direction X and the second direction Y are swapped).

[0707] The semiconductor device 1J includes a resistor unit RU. The resistor unit RU includes a base electrode 35, a plurality of first base via electrodes 50, and a plurality of second base via electrodes 60. The plurality of resistor units RU include a gate resistor Rg. The gate resistor Rg is partitioned by the base electrode 35 between the plurality of first base via electrodes 50 and the plurality of second base via electrodes 60.

[0708] The semiconductor device 1J includes a gate wiring electrode 79, similar to the semiconductor device 1A. The gate wiring electrode 79 may be electrically connected to the gate pad electrode 74 via a base electrode 35, similar to the semiconductor device 1A. Unlike the semiconductor device 1A, the gate wiring electrode 79 may be formed integrally with the gate pad electrode 74.

[0709] In this embodiment, the gate wiring electrode 79 (here referred to as the first wiring portion 81) includes a second removal portion Rm2 provided above the base electrode 35. The second removal portion Rm2 is a region from which the conductive material of the gate wiring electrode 79 has been removed, and is provided in the region between the plurality of first base via electrodes 50 and the plurality of second base via electrodes 60.

[0710] The gate wiring electrode 79 includes a first wiring via connection portion 79A (first electrode) partitioned on the first line portion 40A side by the second removal portion Rm2, and a second wiring via connection portion 79B (second electrode) partitioned on the second line portion 40B side by the second removal portion Rm2.

[0711] The first wiring via connection portion 79A extends in a first direction X following the extending direction of the base electrode 35 and the extending direction of the first line portion 40A, and is connected to one end of the base electrode 35 and opposite the first line portion 40A via the interlayer film 46.

[0712] The first wiring via connection section 79A is mechanically and electrically connected to a plurality of first base via electrodes 50 on the interlayer film 46, and is electrically connected to one end of the base electrode 35 via the plurality of first base via electrodes 50. The first wiring via connection section 79A is mechanically and electrically connected to a plurality of gate via electrodes 67 on the interlayer film 46, and is electrically connected to the first line section 40A via the plurality of gate via electrodes 67.

[0713] The second wiring via connection portion 79B extends in the first direction X, following the extending direction of the base electrode 35 and the extending ...

Claims

1. An electronic component comprising: a base electrode having a top surface and side walls; a first via electrode disposed on the base electrode and having a first connection portion to the top surface of the base electrode and a second connection portion to the side walls of the base electrode; and a first electrode disposed on the first via electrode and electrically connected to the base electrode via the first via electrode.

2. The electronic component according to claim 1, wherein the first via electrode includes a conductor different from the base electrode.

3. The electronic component according to claim 1 or 2, wherein the first electrode includes a conductor different from the first via electrode.

4. The electronic component according to any one of claims 1 to 3, wherein the base electrode includes a conductor other than a metal, the first via electrode includes a metal, and the first electrode includes a metal.

5. The electronic component according to any one of claims 1 to 4, wherein the first via electrode extends in a strip shape in a plan view.

6. The electronic component according to any one of claims 1 to 5, wherein a plurality of the first via electrodes are arranged at intervals on the base electrode.

7. The electronic component according to claim 6, wherein the plurality of first via electrodes are arranged at intervals greater than the width of each first via electrode.

8. The electronic component according to any one of claims 1 to 7, wherein the base electrode is a resistive electrode, the first via electrode has a lower resistivity than the base electrode, and the first electrode has a lower resistivity than the base electrode.

9. The electronic component according to any one of claims 1 to 8, further comprising an insulating interlayer film covering the base electrode, wherein the first via electrode is embedded in the interlayer film, and the first electrode is connected to the first via electrode on the interlayer film.

10. The electronic component according to any one of claims 1 to 9, further comprising: a second via electrode disposed on the base electrode at a distance from the first via electrode; and a second electrode disposed on the second via electrode at a distance from the first electrode and electrically connected to the first electrode via the base electrode.

11. The electronic component according to claim 10, wherein the second via electrode has a third connection portion to the upper surface of the base electrode and a fourth connection portion to the side wall of the base electrode.

12. The electronic component according to claim 10 or 11, further comprising: a wiring electrode provided at a distance from the base electrode; and a wiring via electrode disposed on the wiring electrode, wherein the second electrode is disposed on the second via electrode and the wiring via electrode, and the base electrode is electrically connected to the wiring electrode.

13. The electronic component according to any one of claims 1 to 12, further comprising a chip and a base insulating film covering the chip, wherein the base electrode is disposed on the base insulating film.

14. The electronic component according to claim 13, wherein the chip includes a wide-bandgap semiconductor.

15. The electronic component according to claim 14, wherein the chip includes SiC.

16. The electronic component according to any one of claims 13 to 15, wherein the second connection portion of the first via electrode is in contact with the base insulating film.

17. The electronic component according to claim 16, wherein the contact portion of the second connection portion with respect to the base insulating film is located closer to the chip than the contact portion of the base electrode with respect to the base insulating film.

18. The electronic component according to any one of claims 13 to 17, further comprising an insulating film covering the chip, wherein the base insulating film has a thickness greater than the thickness of the insulating film and is connected to the insulating film.

19. The electronic component according to any one of claims 13 to 18, further comprising a pn junction formed on the surface layer of the chip, wherein the base insulating film covers the pn junction on the chip, and the base electrode faces the pn junction via the base insulating film.

20. An electronic component comprising: a resistive electrode having a top surface and side walls; a first via electrode disposed on the resistive electrode and having a first connection portion to the top surface of the resistive electrode and a second connection portion to the side walls of the resistive electrode; and a second via electrode disposed on the resistive electrode at a distance from the first via electrode and having a third connection portion to the top surface of the resistive electrode and a fourth connection portion to the side walls of the resistive electrode.

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