Multi-level cell memory with ferroelectric superlattice

Abstract

A transistor device includes a substrate, a channel layer supported by the substrate, and a ferroelectric superlattice layer adjacent the channel layer. The ferroelectric superlattice layer includes a plurality of ferroelectric III-nitride alloy sub-layers. The plurality of ferroelectric III-nitride alloy sub-layers have different Group IIIB content levels.

Description

Atty. Docket No. 10110-23023AMULTI-LEVEL CELL MEMORY WITH FERROELECTRIC SUPERLATTICECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of U.S. provisional application entitled “MultiLevel Cell Memory with Ferroelectric Superlattice,” filed November 12, 2024, and assigned Serial No. 63 / 719,492, the entire disclosure of which is hereby expressly incorporated by reference.BACKGROUND OF THE DISCLOSUREField of the Disclosure

[0002] The disclosure relates generally to ferroelectric memory and other transistor devices.Brief Description of Related Technology

[0003] The amount of data being produced worldwide is growing at an astonishing rate. Approximately 64 zettabytes of data are generated in 2020, and this amount is expected to exceed 180 zettabytes by 2025. Currently, information and communication technology consumes 4-6% of the world's electricity, and this number is only going to increase.Therefore, there is a high demand for advanced memory technologies that can provide high data density and high energy efficiency.

[0004] Multi-level cell (MLC) memory devices have emerged in recent years to address these needs. MLC memory devices store multiple bits of information per memory cell, effectively increasing the amount of data that can be stored in one device and lowering the manufacturing costs. In addition, MLC memory devices enable computations based on higher numeric systems (such as quaternary and octal systems), which will have higher energy efficiency due to reduced electrical components and clock networks.

[0005] MLC memory devices have been based on ferroelectric materials, in which the partial polarization of the ferroelectric material is used to represent the intermediate states of the memory. However, due to the domain inhomogeneity and stochasticity of domain switching, the variation induced by the partial polarization switching is hard to control. As aAtty. Docket No. 10110-23023A result, the programmed states in the MLC memory device suffer from severe overlapping with one another, especially in scaled devices with limited numbers of domains and large device-to-device variations.

[0006] To address this problem, ferroelectric laminate or superlattice structures based on doped hafnium oxide have been explored recently. However, in each individual hafnia layer, the coercive fields are approximately the same. This means that the distribution of the coercive field still has only one peak, similar to homogeneous ferroelectric materials. As a result, it is challenging to achieve well-separated intermediate states.SUMMARY OF THE DISCLOSURE

[0007] In accordance with one aspect of the disclosure, a transistor device includes a substrate, a channel layer supported by the substrate, and a ferroelectric superlattice layer adjacent the channel layer. The ferroelectric superlattice layer includes a plurality of ferroelectric Ill-nitride alloy sub-layers. The plurality of ferroelectric Ill-nitride alloy sub-layers have different Group 11 IB content levels.

[0008] In accordance with another aspect of the disclosure, a transistor device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a channel layer and a ferroelectric superlattice layer adjacent the channel layer. The ferroelectric superlattice layer has a plurality of ferroelectric Ill-nitride alloy sub-layers. The plurality of ferroelectric Ill-nitride alloy sub-layers have different Group 111 B content levels.

[0009] In connection with any one of the aforementioned aspects, the devices described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features. The channel layer includes a van der Waals semiconductor material. The channel layer is supported by the ferroelectric superlattice layer. The transistor device further includes a gate insulator layer supported by the channel layer. The transistor device further includes a gate between the ferroelectric superlattice layer and the substrate. The ferroelectric superlattice layer is supported by the channel layer. The transistor device further includes a gate supported by the ferroelectric superlattice layer. The transistor device further includes an insulator layer between the channel layer and the substrate. The transistor device further includes first and second insulator layers disposed between the channel layer and the substrate, and an embedded gate disposed between the first and second insulator layers. Each ferroelectric Ill-nitride alloy sub-layer of the plurality of ferroelectric Ill-nitride alloy sub-layers includes ScxAli.xN, ScxGai-xN, or Scxlni.xN, or an alloy thereof, with x denoting the different Group 111 B contentAtty. Docket No. 10110-23023A levels. The different Group 111 B content levels vary stepwise. Each ferroelectric Ill-nitride alloy sub-layer of the plurality of ferroelectric Ill-nitride alloy sub-layers has a thickness falling in range from about 3 nm to about 20 nm. The different Group 111 B content levels fall in a range from about 0.1 to about 0.4. The plurality of ferroelectric sub-layers are arranged contiguously in a stack. Adjacent sub-layers of the plurality of ferroelectric Ill-nitride alloy sub-layers are in contact with one another. The ferroelectric superlattice layer further includes a plurality of non-ferroelectric Ill-nitride sub-layers, each non-ferroelectric Ill-nitride sub-layer being disposed between a respective pair of adjacent sub-layers of the plurality of ferroelectric Ill-nitride alloy sub-layers. The transistor device further includes a Ill-nitride semiconductor layer disposed between the ferroelectric superlattice layer and the substrate. The transistor device further includes a Ill-nitride conductive layer disposed between the Ill-nitride semiconductor layer and the ferroelectric superlattice layer. The transistor device further includes a metal conductive layer disposed between the Ill-nitride semiconductor layer and the ferroelectric superlattice layer. The transistor device further includes source and drain electrodes coupled to one another via the channel layer. The different Group 111 B content levels between adjacent sub-layers of the plurality of ferroelectric Ill-nitride alloy sublayers exhibit a discrete step having a concentration gradient that falls between about 3% and about 5%. The different Group 11 IB content levels are continuously graded across the plurality of ferroelectric Ill-nitride alloy sub-layers. The heterostructure further includes a Ill-nitride semiconductor layer between the ferroelectric superlattice layer and the substrate. The heterostructure further includes a gate layer between the ferroelectric superlattice layer and the substrate. The ferroelectric superlattice layer is in contact with the gate layer. The heterostructure further includes an insulator layer between the ferroelectric superlattice layer and the substrate.BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0010] For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawing figures, in which like reference numerals identify like elements in the figures.

[0011] Figure 1 depicts a comparison of conventional homogenous ferroelectric materials and example ferroelectric superlattices based on Ill-nitride materials, including (a) a schematic illustration of a conventional homogenous ferroelectric material, (b) a graphical plot of polarization versus electric field for the conventional homogenous ferroelectric material, (c) a graphical plot of the distribution of coercive field in a conventional ferroelectric capacitor, (d) a schematic illustration of an example ferroelectric superlattice based on Ill-Atty. Docket No. 10110-23023A nitride materials, with each sub-layer having a different alloy (e.g., Sc) composition, which leads to different coercive fields, (e) a graphical plot of polarization versus electric field for the example ferroelectric superlattice, in which multiple coercive fields exist, and (f) a graphical plot of the distribution of coercive field in the example ferroelectric superlattice, in which multiple peaks are present.

[0012] Figure 2 depicts a comparison of a conventional MLC memory device and an example MLC memory device with a ferroelectric superlattice, including (a) a schematic illustration of a conventional MLC memory device with a homogenous ferroelectric structure, (b) a graphical plot of the channel threshold voltage for the conventional MLC memory device as a function of program voltage amplitude, in which eight different program voltages (Vo^V7) correspond to eight different states of the memory device (state “0” — > state “7”), (c) a graphical plot of the distribution of the threshold voltages for the eight states of the conventional MLC memory device, (d) a schematic illustration of an example MLC memory device having a ferroelectric superlattice, (e) a graphical plot of the channel threshold voltage for the example MLC memory device as a function of program voltage amplitude, and (f) a graphical plot of the distribution of the threshold voltage for the eight states in the example MLC memory device with a ferroelectric superlattice. The discrete conduction levels in the example MLC memory device with a superlattice allow a digital reading of the multiple states with high accuracy and strong immunity to noise.

[0013] Figure 3 is a schematic, sectional view of a multi-level cell (MLC) memory device having a ferroelectric superlattice in accordance with one example.

[0014] Figure 4 is a schematic, sectional view of a multi-level cell (MLC) memory device having a ferroelectric superlattice in accordance with another example.

[0015] Figure 5 is a schematic, sectional view of a multi-level cell (MLC) memory device having a ferroelectric superlattice in accordance with yet another example.

[0016] Figure 6 is a schematic, sectional view of a multi-level cell (MLC) memory device having a ferroelectric superlattice in accordance with still another example.

[0017] Figure 7 is a schematic, sectional view of a multi-level cell (MLC) memory device having a ferroelectric superlattice in accordance with yet still another example.

[0018] Figure 8 depicts polarization testing results of a ferroelectric ScxAli.xN structure, including (a) a graphical plot of remnant polarization versus coercive field of a Sc-lll-N ferroelectric structure relative to other ferroelectric materials, in which the ScxAh.xN structure exhibits superior remanent polarization and high coercive field, (b) graphical plots showingAtty. Docket No. 10110-23023A the dependence of mean coercive field, breakdown field, and remnant polarization on the Sc content of ScxAli.xN films, and STEM-HAADF images of (c) one monolayer GaN and (d) GaN / AIN superlattices.

[0019] Figure 9 depicts a STEM image of a Sco 1sAlo82N layer grown on a GaN / sapphire template, with an inset showing the corresponding fast Fourier transform patterns of the dashed square, and in which the Sco i8Alo82N layer exhibits an atomically smooth sharp interface.

[0020] The embodiments of the disclosed devices may assume various forms. Specific embodiments are illustrated in the drawing and hereafter described with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.DETAILED DESCRIPTION OF THE DISCLOSURE

[0021] Transistor devices having a ferroelectric superlattice layer are described. The ferroelectric superlattice layer. Sub-layers of the ferroelectric superlattice layer are composed of, or otherwise include, a Ill-nitride alloy. The Ill-nitride alloy sub-layers have different Group 11 IB content levels. As described herein, the different content levels establish multiple threshold voltages for the transistor devices. The multiple threshold voltages of the disclosed devices may, in turn, be used to realize a multi-level cell (MLC) memory device.

[0022] Example MLC memory devices based on ferroelectric superlattices with stepwise composition are described below. The ferroelectric superlattices are or include Ill-nitride alloys, including, for instance, ScxAh.xN, ScxGai-xN or Scxlni.xN. The compositions of Sc in each sub-layer of the superlattices are different (x1#= %2■■■ *xn )> which will lead to different coercive fields in each sub-layer. As a result, the distribution of the coercive field will have multiple peaks, in contrast to the single peak in conventional homogenous ferroelectric materials. These multiple coercive fields will result in multiple discrete values of the threshold voltages in the MLC memory. Such multi-bit, digital storage and reading of the data can significantly increase accuracy and improve the immunity to device variations and noise.

[0023] The multi-bit storage of the disclosed devices enhances memory density, and also allows for computation with higher numeric systems such as quaternary and octal systems, as compared to the traditional binary system. As a result, clock circuitry may be simplified, and the number of bus lines may be reduced, thereby lowering energy consumption and circuit footprint. The disclosed devices also provide higher data density and lower error rate than conventional MLC memory devices based on a homogenous ferroelectric material. TheAtty. Docket No. 10110-23023A disclosed memory devices are accordingly useful in a wide variety of applications, including, for instance, machine learning, artificial intelligence, robots, mobile devices, sensing networks, self-driving vehicles, and data centers.

[0024] In some cases, the different Group 111 B content levels in the sub-layers of the ferroelectric superlattice layer vary discretely. The content levels may thus exhibit discrete steps in Group 111 B content or concentration. For instance, each discrete step may have a concentration gradient that falls between about 3% and about 5%. Thus, in one example having a concentration gradient of 4%, the different Group 11 IB content layers may proceed as follows: the first sub-layer has 0.10 Sc, the second sub-layer has 0.14 Sc, the third sublayer has 0.18 Sc, and so on. In other cases, the different Group 111 B content levels are continuously graded across the sub-layers of the ferroelectric superlattice layer.

[0025] Although the ferroelectric superlattices of the example devices are based on Ill-nitrides, such as ScxAh-xN, ScxGai-xN or Scxlni.xN, with stepwise composition, other Ill-nitride materials may be used. For instance, quaternary alloys of the above-referenced materials may be used. The disclosed devices may thus include or involve the incorporation of scandium into a variety of Ill-nitride materials. Still other Ill-nitride materials may be used, including, for instance, AIBN, AIGaN, and InAIN.

[0026] The configuration, construction, fabrication, and other characteristics of the heterostructures of the disclosed devices may also vary from the examples described. For instance, the heterostructures may include additional or alternative epitaxially grown layers of ferroelectric and non-ferroelectric nature.

[0027] The disclosed methods and devices are not limited to Ill-nitride alloys including scandium. For instance, the Ill-nitride alloys may include additional or alternative group II IB elements, such as yttrium (Y) and lanthanum (La).

[0028] Although described in connection with memory devices, the ferroelectric superlattices and other structures of the disclosed devices may be useful in other devices and applications. For instance, the disclosed devices may be used as transistor devices in non-memory applications, such as high temperature, high power and high frequency electronics.

[0029] The composition of other structures or layers of the devices may also vary from the examples described herein. For instance, a variety of substrate materials may be used in addition or alternative to sapphire, including, for instance, silicon, germanium, lll-V semiconductors, sapphire, quartz, polyethylene terephthalate (PET), polymide, and poly(dimethyl siloxane) (PDMS). Although described in connection with supporting GaNAtty. Docket No. 10110-23023A layers, alternative or additional semiconductor materials may be used in the heterostructures, including, for instance, other Ill-nitride materials, such as AIGaN, InGaN, and AIBN, and other lll-V semiconductors, such as GaAs and GaSb.

[0030] Although described in connection with examples having heterostructures with solely Ill-nitride-based layers, the disclosed methods and devices may involve or include one or more layers (e.g., a buffer or template layer) composed of other semiconductor materials, such as GaAs, InP, and alloys thereof. Still other types of materials may alternatively or additionally be used in the heterostructures of the disclosed devices, including, for instance, two-dimensional transition metal dichalcogenides, oxide materials (e.g., gallium oxide or gallium oxide-based materials), diamond, silicon carbide, and silicon.

[0031] Further details regarding the growth and formation of Ill-nitride alloy layers, as well as Ill-nitride-based heterostructures of transistor devices, are set forth in WO 2023 / 022768 ("Epitaxial Nitride Ferroelectronics"), WO 2023 / 167709 ("Semiconductor Heterostructures with Scandium Ill-Nitride Layer"), WO 2023 / 164071 ("Epitaxial Nitride Ferroelectronic Devices"), and WO 2024 / 148361 ("Epitaxial Nitride Ferroelectronic Devices"), the entire disclosures of which are hereby incorporated by reference. The disclosed transistor devices may have one or more layers, structures, or other elements or aspects in common with the devices described in the above-referenced patent publications.

[0032] Still further details regarding the growth of Ill-nitride alloy layers on different types of template or other layers, such as silicon and other non-l ll-nitride semiconductors, and various metals, are set forth in WO 2024 / 010848 ("Ferroelectric Ill-Nitride Heterostructures") and WO 2024 / 096966 ("Heterostructures With Ferroelectric Ill-Nitride Layer On Metal"), the entire disclosures of which are hereby incorporated by reference.

[0033] Figure 1 shows a comparison of a conventional homogenous ferroelectric material and a device having ferroelectric superlattices based on Ill-nitride materials in accordance with one example. The composition of the conventional ferroelectric film is homogeneous, as shown in Figure 1 , part a. In that case, the polarization of the ferroelectric field switches at a given coercive field and the distribution of the coercive field exhibits only a single peak, as illustrated in Figure 1 , parts b and c. The polarization direction (“up” and “down”) can naturally represent a single bit, or binary information (“0” and “1”). It is difficult to encode multi-bit information in such ferroelectric cells. Partial polarization in the homogenous ferroelectric materials has been used to represent intermediate states. However, due to the stochastic nature of the polarization switching in the ferroelectric domains and device-to-Atty. Docket No. 10110-23023A device variation, such intermediate states suffer from severe overlap, which leads to large error rates in the MLC memory device.

[0034] The example device having a ferroelectric superlattice based on Ill-nitride materials, such as ScxAli-xN and ScxGai-xN, overcomes the challenges described above. The compositions of Sc in each sub-layer of the superlattice are different¥= %2■■■ *xn), as illustrated in Figure 1 , part d. The different compositions establish respective, or distinct, coercive fields in each sub-layer (Figure 1 , part e). As a result, the distribution of the coercive field exhibits multiple peaks (Figure 1 , part f), in contrast to the single peak in conventional devices having a homogenous ferroelectric layer (Figure 1 , part c). These multiple coercive fields allow the polarization to have multiple discrete values, which is useful for encoding multiple-bit information in a single memory device.

[0035] Figure 2 shows a comparison of a conventional MLC memory device and a MLC memory device having a ferroelectric superlattice in accordance with one example. Figure 2, parts a and d, illustrate the conventional MLC device having a homogenous ferroelectric layer and the example MLC device having a ferroelectric superlattice. In the conventional MLC memory device, the threshold voltage increases continuously with increasing program pulse amplitude, as shown in Figure 2, part b, because there is only a single coercive field peak. In contrast, with the example MLC device having a ferroelectric superlattice, the threshold voltage of the transistor device takes on discrete values when the program voltage increases due to the multiple coercive field peaks established via the superlattice, as shown in Figure 2, part e. In the conventional MLC memory device, the intermediate states suffer from severe overlap due to the stochastic nature of the polarization switching and device-to-device variations, as shown in Figure 2, part c. For the example MLC device having a ferroelectric superlattice, however, because each sublayer switches at a different electric field, the intermediate states are well separated, as shown in Figure 2, part f. This “spikelike” threshold voltage distribution allows the example MLC device to implement digital-like storage and read-out of intermediate states, which significantly reduces error rates and improves the immunity to device variation and noise.

[0036] Figures 3-7 illustrate MLC memory devices 100 (Figure 3), 102 (Figure 4), 104 (Figure 5), 106 (Figure 6), and 108 (Figure 7) having a ferroelectric superlattice layer 120 in accordance with several examples. The MLC memory devices may have one or more structures, layers, or other features in common. For instance, each device 100 (Figure 3), 102 (Figure 4), 104 (Figure 5), 106 (Figure 6), and 108 (Figure 7) may include a channel layer 140 composed of, or otherwise including, a van der Waals (vdW) semiconductorAtty. Docket No. 10110-23023A material (referred to herein as "the vdW semiconducting layer 140" or "the vdW channel layer 140"), as well as source and drain electrodes 130, 132.

[0037] The disclosed devices are not limited to the examples depicted in Figures 3-7. For instance, any structures, layers, features, and / or other characteristics of the depicted devices may be combined in various ways. For instance, the compositions and other characteristics of the layers in one example may be applicable to one or more other examples.

[0038] The composition of the ferroelectric superlattice layer 120 may vary stepwise in each of the examples. In some cases, the ferroelectric superlattice layer 120 is composed of, or otherwise includes, ScxAli.xN, ScxGai-xN, or Scxlni.xN, and any alloys thereof. The compositions of Sc in each sub-layer of the superlattices are different¥= %2■■■ *xn )■ Still other ferroelectric Ill-nitride alloys may be used, including, for instance, AIGaN, InGaN, and AIBN.

[0039] The composition of the vdW channel layer 140 may vary in each of the examples. In some cases, the vdW channel layer 140 is composed of, or otherwise includes, black phosphorous, MoTe2, WSe2, HfS2, ZrS2, TiS2, Moi-xWxTe2, MoS2-2xTe2X, MoSe2-2x Te2x, WS2-2x Te2x, WSe2-2x Te2x, Hf2CO2, SC2CF2, Ti2CO2, Zr2CO2, germanane, and heterostructures based on these materials.

[0040] Alternatively, the channel layer 140 does not include a van der Waals semiconductor material. For instance, the channel layer 140 may be composed of, or otherwise include, non-vdW semiconductor materials, such as InSe, InSb, InN, GaSb, and InGaAs, as well as alloys thereof, in other cases. Still other types of materials may be used, including semiconductor oxides, such as InZnO or I n2O3, or semiconductor membranes, such as a Si membrane.

[0041] While the source electrode 130 and the drain electrode 132 may be in contact with the vdW channel layer 140 in each example, the positioning and / or other characteristics of the layers, structures, and other components of the devices may vary between the examples. For instance, the ferroelectric superlattice layer 120 supports the vdW semiconducting layer 140 in the devices 100, 102, and 104. In contrast, the vdW semiconducting layer 140 supports the ferroelectric superlattice layer 120 in the devices 106 and 108. Further details regarding each example MLC device are provided in turn below.

[0042] In the example MLC memory device 100 shown in Figure 3, the ferroelectric superlattice 120 is supported by an n-type GaN layer 114, a GaN layer 112, and a sapphire substrate 110. The n-type GaN layer 114 is configured as an embedded or back gate in thisAtty. Docket No. 10110-23023A case. The channel layer 140 is disposed on (e.g., grown or transferred onto), or otherwise supported by, the ferroelectric superlattice layer 120. The source electrode 130 and the drain electrode 132 are formed supported by the channel layer 140. An insulator layer 150 is supported by the vdW semiconductor 140 and an upper (or top) gate 160 is disposed on (or otherwise supported by) the insulator layer 150. The insulator layer 150 may be composed of, or otherwise include, a variety of dielectric materials, including, for instance, SiC>2, SisN4, AI2O3, HfC>2, ZrC>2, or a combination thereof.

[0043] In the example MLC memory device 102 shown in Figure 4, an embedded gate 170 is disposed on (or otherwise supported by) an insulator layer 118. The insulator layer 118 is, in turn, disposed on (or otherwise supported by) a substrate 116. The vdW channel layer 140 is disposed on (e.g., grown or transferred onto), or otherwise supported by, the ferroelectric superlattice layer 120. The source electrode 130 and the drain electrode 132 may be disposed on (e.g., in contact with) the vdW channel layer 140 as shown.

[0044] The embedded gate 170 may be composed of, or otherwise include, a doped Ill-nitride material, such as n-type GaN. Other semiconductor and non-semiconductor materials may be used, including, for instance, metal layers, such as Mo, Al and Pt, or semiconductor materials, such as Si and SiC.

[0045] The substrate 116 may be composed of, or otherwise include, a variety of materials, including, for instance, semiconductor materials, such as silicon, germanium, and lll-V materials, as well as non-semiconductor materials, such as sapphire, and quartz, polyethylene terephthalate (PET), polymide, and poly(dimethyl siloxane) (PDMS).

[0046] The insulator layer 118 may be composed of, or otherwise include, SiC>2, SisN4, AI2O3, HfC>2, ZrC>2, or a combination of these materials. The ferroelectric superlattice 120 is disposed on, or otherwise supported by, the insulator layer 118. In this example, the ferroelectric superlattice 120 is in contact with the insulator layer 118. In other cases, the ferroelectric superlattice 120 is grown on a nucleation or template layer, such as GaN or AIN.

[0047] In the example MLC memory device 104 shown in Figure 5, an embedded gate 170 is disposed on (or otherwise supported by) an insulator layer 118. The insulator layer 118 is, in turn, disposed on (or otherwise supported by) a substrate 116. The ferroelectric superlattice 120 is disposed on (or otherwise supported by) the insulator layer 118. The VdW channel layer 140 is disposed on (e.g., grown or transferred onto), or otherwise supported by, the ferroelectric superlattice layer 120. The source electrode 130 and the drain electrode 132 are disposed on the vdW channel layer 140 as shown. An insulatorAtty. Docket No. 10110-23023A layer 150 is disposed on (or otherwise supported by) the vdW channel layer 140, and a top gate 160 is disposed on (or otherwise supported by) the insulator layer 150.

[0048] In the example MLC memory device 106 shown in Figure 6, the vdW channel layer 140 is disposed on (or otherwise supported by) an insulator layer 118. The insulator layer 118 is, in turn, disposed on (or otherwise supported by) a substrate 116. In this example, the ferroelectric superlattice 120 is disposed on (or otherwise supported by) the vdW channel layer 140 as shown. The top gate 160 is disposed on (or otherwise supported by) the ferroelectric superlattice 120. The source electrode 130 and the drain electrode 132 are disposed on the vdW channel layer 140, as shown.

[0049] In the example MLC memory device 108 shown in Figure 7, an embedded gate 170 is disposed on (or otherwise supported by) an insulator layer 118. The insulator layer 118 is, in turn, disposed on (or otherwise supported by) a substrate 116. An insulator layer 119 is disposed on (or otherwise supported by) the embedded gate 170. The vdW channel layer 140 is disposed on (or otherwise supported by) the insulator layer 119. The source electrode 130 and the drain electrode 132 are disposed on (or otherwise supported by) the vdW channel layer 140 as shown. The ferroelectric superlattice 120 is disposed on (or otherwise supported by) the vdW channel layer 140. The top gate 160 is disposed on (or otherwise supported by) the ferroelectric superlattice 120

[0050] Figure 8 shows testing results on ferroelectric ScxAli.xN layers having single crystalline ferroelectric ScAIN and ScGaN fabricated via molecular-beam epitaxy (MBE). Figure 8, part a, shows the remnant polarization versus coercive field of Sc-lll-N ferroelectrics relative to other ferroelectric materials. ScxAh.xN shows superior remanent polarization and high coercive field. Figure 8, part b, shows the dependence of mean coercive field, breakdown field, and remnant polarization on the Sc content of ScxAh.xN films. The ferroelectricity in ScxAh.xN with Sc content from 0.05 to 0.36 exhibits a wide tunable coercive field window from about 6 MV / cm continuously to about 2 MV / cm. Atomic-level controllable epitaxy of Sc composition-tunable wurtzite ScxAh.xN films with sharp interface is essential for realizing high-performance MLC. Using the thickness control in MBE, a monolayer of GaN and two monolayers of GaN may be grown and embedded in the AIN matrix. Figure 8, parts c and d, show the STEM-HAADF images of one monolayer GaN and GaN / AIN superlattices. This methodology may be used to produce high-quality ScxAh.xN multilayers with precise thickness control down to nanometer scale, which may be useful in connection with forming, for instance, a gate dielectric layer in a MLC memory device.Atty. Docket No. 10110-23023A

[0051] Figure 9 shows a STEM image of a Sco i8Alo82N layer grown on a GaN / sapphire template. The inset depicts the corresponding fast Fourier transform pattern of the dashed, square-shaped area in the image. The Sco i8Alo82N layer exhibits an atomically smooth and sharp interface. Such high-quality single-phase wurtzite ScxAli.xN films with tunable Sc composition are useful for realizing the disclosed devices and other high-performance MLC memory devices. By configuring the growth conditions, controllable growth of ScxAh.xN with varying Sc content on the GaN / sapphire template is realized.

[0052] Atomically smooth surfaces are useful for the controllable growth of ScxAh.xN-based heterostructures with sharp interfaces, which, in turn, is useful for reducing the interface trap density to stabilize the switching process in the MLC memory device. Phase separation and in-plane misorientation are some of the main challenges for the growth of ScxAh.xN films, especially for ScxAh.xN with a relatively high Sc content.

[0053] The commonly used (002) plane XRD 20-co scans can show the texture structure along the c-axis but couldn’t uncover the in-plane domain orientation. In this regard, the XRD pole figure can be employed to explore the orientation distribution of the crystallographic lattice. On the other hand, the cubic domain has been observed in ScxAh.xN with 40% ScN. Electron backscatter diffraction (EBSD) pole figure can be applied to explore the presence of any cubic phase and the related domain distribution, and further provides supports for suppressing the cubic phase formation and improving the domain uniformity in ScxAh.xN with higher Sc contents. The microscopic atomic structure and interface of ScxAh.xN MLC can be characterized using highly spatially resolved STEM. As shown in Figure 9, the ScxAh.xN layer with lower Sc content (about 18%) has a sharp ScxAh.xN / GaN interface, while the ScxAh-xN layer with higher Sc content (about 34%) shows a slightly rough interface, which is mainly due to the degeneration of crystal quality. The interfacial quality of ScxAh.xN-based MLC may be improved via structural characterization using STEM.

[0054] The ferroelectric layers of the disclosed devices are not limited to layers composed of ScAIN. Other ferroelectric Ill-nitride alloys may be used, including, various ternary alloys (e.g., ScGaN) and quaternary alloys (e.g., ScAIGaN). Further details regarding example the growth of ferroelectric quaternary alloys are set forth in P. Wang et al., "Quaternary alloy ScAIGaN: A promising strategy to improve the quality of ScAIN," Applied Physics Letters, vol. 120, no. 1, (2022), and WO 2023 / 214993 ("Semiconductor Heterostructures with Quaternary Ill-Nitride Alloy"), the entire disclosures of which are hereby incorporated by reference.Atty. Docket No. 10110-23023A

[0055] Described above are examples of multi-level cell (MLC) memory devices having ferroelectric superlattices. The ferroelectric superlattices of the example devices are composed of, or otherwise include, Ill-nitride materials, including, for instance, ScxAli.xN, ScxGai-xN and Scxlni.xN, with stepwise composition (x1#= %2■■■ *xn )■ Each sub-layer of the ferroelectric superlattices has, or exhibits, a respective, or distinct, coercive field, resulting in discrete values of threshold voltages for the MLC memory device. The disclosed MLC memory devices are accordingly capable of implementing digital-like storage of multiple bits per cell, which, in turn, increases data accuracy and enhances immunity to device variations.

[0056] Differences in crystal quality evidenced via x-ray diffraction rocking curve line widths may be used to distinguish between monocrystalline and polycrystalline structures. As used herein, the term "polycrystalline" refers to structures having x-ray diffraction rocking curve line widths on the order of a few degrees or higher. As used herein, the terms "monocrystalline" or "single crystalline" refer to structures having x-ray diffraction rocking curve line widths at least one order of magnitude lower than the order of a few degrees.

[0057] As used herein, the terms "atomically smooth" or "atomically smooth surface" may be used herein in connection with a layer of a heterostructure to indicate that the layer has a surface roughness (e.g., a root mean square, or RMS, roughness) less than or on the order of 1 nm. In some cases, the RMS roughness of such atomically smooth layers is less than 1% of the thickness of the layer. The surface roughness may vary in accordance with the growth conditions, parameters, and other aspects of the fabrication processes described and / or referenced herein and / or other processes.

[0058] The term "about" is used herein in a manner to include deviations from a specified value that would be understood by one of ordinary skill in the art to effectively be the same as the specified value due to, for instance, the absence of appreciable, detectable, or otherwise effective difference in operation, outcome, characteristic, or other aspect of the disclosed methods and devices.

[0059] The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not to be limiting of the disclosure. Changes, additions and / or deletions may be made to the examples without departing from the spirit and scope of the disclosure.

[0060] The foregoing description is given for clearness of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

Atty. Docket No. 10110-23023A What is Claimed is:

1. A transistor device comprising:a substrate;a channel layer supported by the substrate; anda ferroelectric superlattice layer adjacent the channel layer;wherein:the ferroelectric superlattice layer comprises a plurality of ferroelectric Ill-nitride alloy sub-layers; andthe plurality of ferroelectric Ill-nitride alloy sub-layers have different Group I IIB content levels.

2. The transistor device of claim 1 , wherein the channel layer comprises a van der Waals semiconductor material.

3. The transistor device of claim 1 , wherein the channel layer is supported by the ferroelectric superlattice layer.

4. The transistor device of claim 3, further comprising a gate insulator layer supported by the channel layer.

5. The transistor device of claim 3, further comprising a gate between the ferroelectric superlattice layer and the substrate.

6. The transistor device of claim 1 , wherein the ferroelectric superlattice layer is supported by the channel layer.

7. The transistor device of claim 6, further comprising a gate supported by the ferroelectric superlattice layer.

8. The transistor device of claim 6, further comprising an insulator layer between the channel layer and the substrate.

9. The transistor device of claim 6, further comprising:first and second insulator layers disposed between the channel layer and the substrate; andan embedded gate disposed between the first and second insulator layers.Atty. Docket No. 10110-23023A 10. The transistor device of claim 1 , wherein each ferroelectric Ill-nitride alloy sub-layer of the plurality of ferroelectric Ill-nitride alloy sub-layers comprises ScxAli.xN, ScxGai-xN, or Scxlni-xN, or an alloy thereof, with x denoting the different Group 11 IB content levels.

11. The transistor device of claim 1 , wherein the different Group I IIB content levels vary stepwise.

12. The transistor device of claim 1 , wherein each ferroelectric Ill-nitride alloy sub-layer of the plurality of ferroelectric Ill-nitride alloy sub-layers has a thickness falling in range from about 3 nm to about 20 nm.

13. The transistor device of claim 1 , wherein the different Group I IIB content levels fall in a range from about 0.1 to about 0.4.

14. The transistor device of claim 1 , wherein the plurality of ferroelectric sub-layers are arranged contiguously in a stack.

15. The transistor device of claim 1 , wherein adjacent sub-layers of the plurality of ferroelectric Ill-nitride alloy sub-layers are in contact with one another.

16. The transistor device of claim 1 , wherein the ferroelectric superlattice layer further comprises a plurality of non-ferroelectric Ill-nitride sub-layers, each non-ferroelectric Ill-nitride sub-layer being disposed between a respective pair of adjacent sub-layers of the plurality of ferroelectric Ill-nitride alloy sub-layers.

17. The transistor device of claim 1 , further comprising a Ill-nitride semiconductor layer disposed between the ferroelectric superlattice layer and the substrate.

18. The transistor device of claim 17, further comprising a Ill-nitride conductive layer disposed between the Ill-nitride semiconductor layer and the ferroelectric superlattice layer.

19. The transistor device of claim 17, further comprising a metal conductive layer disposed between the Ill-nitride semiconductor layer and the ferroelectric superlattice layer.

20. The transistor device of claim 1 , further comprising source and drain electrodes coupled to one another via the channel layer.

21. The transistor device of claim 1 , wherein the different Group I IIB content levels between adjacent sub-layers of the plurality of ferroelectric Ill-nitride alloy sub-layers exhibit a discrete step having a concentration gradient that falls between about 3% and about 5%.Atty. Docket No. 10110-23023A 22. The transistor device of claim 1 , wherein the different Group 111 B content levels are continuously graded across the plurality of ferroelectric Ill-nitride alloy sub-layers.

23. A transistor device comprising:a substrate; anda heterostructure supported by the substrate, the heterostructure comprising:a channel layer; anda ferroelectric superlattice layer adjacent the channel layer;wherein:the ferroelectric superlattice layer has a plurality of ferroelectric Ill-nitride alloy sub-layers; andthe plurality of ferroelectric Ill-nitride alloy sub-layers have different Group 111 B content levels.

24. The transistor device of claim 23, wherein the heterostructure further comprises a Ill-nitride semiconductor layer between the ferroelectric superlattice layer and the substrate.

25. The transistor device of claim 23, wherein the heterostructure further comprises a gate layer between the ferroelectric superlattice layer and the substrate.

26. The transistor device of claim 25, wherein the ferroelectric superlattice layer is in contact with the gate layer.

27. The transistor device of claim 23, wherein the heterostructure further comprises an insulator layer between the ferroelectric superlattice layer and the substrate.

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