Data burning and self-test method and apparatus for display panel, and flash integrated circuit (flash IC)

Abstract

The present application relates to the technical field of display screens, and relates to a data burning and self-test method and apparatus for a display panel, and a flash integrated circuit (Flash IC), a computer-readable storage medium and a computer program product. The method comprises: when it is detected that a Flash IC has received a burning drive signal, outputting an output voltage having at least one voltage state; on the basis of the voltage state and an addressing region mapping table, determining, from the Flash IC, an addressing region to be subjected to burning that corresponds to the output voltage of a timing control module, and controlling other regions to be in a latched state; after data burning is finished, acquiring current cyclic redundancy check values of all the regions in the Flash IC; and comparing the current cyclic redundancy check values with a preset cyclic redundancy check value for verification, so as to obtain a data burning self-test result. During two consecutive burning operations, and in the presence of an external interference signal, the present method can reduce the impact on data of other address regions in a Flash IC.

Description

Methods and devices for data burning and self-testing of display panels, and Flash IC flash memory chips.

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411670121.7, filed on November 20, 2024, entitled “Data Burning and Self-Testing Method, Apparatus and Flash IC Flash Memory Chip for Display Panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a method, apparatus, Flash IC flash memory chip, computer-readable storage medium, and computer program product for data burning and self-testing of a display panel. Background Technology

[0004] With the rapid development of mobile devices and smart terminals, applying TDDI (Touch and Display Driver Integration) technology to OLED (Organic Light Emitting Diode) display devices can improve the reliability of display devices.

[0005] In typical OLED display designs, the TP (touch panel) firmware data is burned into the TP IC (touch panel integrated circuit), while the Demura (color correction) compensation data is burned into the Flash IC (flash memory chip). However, in TDDI technology applications, both types of data are burned into the same area. If there are interference signals in the external environment, the data can easily be accidentally erased or rewritten, thus affecting the reliability of the display device.

[0006] Therefore, there is an urgent need for a data burning and self-testing method, device, Flash IC flash memory chip, computer-readable storage medium, and computer program product for display panels that can reduce the impact on data in other address areas of the Flash IC during two consecutive burning operations and in the presence of external interference signals. Summary of the Invention

[0007] Therefore, it is necessary to provide a method, apparatus, Flash IC flash memory chip, computer-readable storage medium, and computer program product for data programming and self-testing of a display panel, which can reduce the impact on data in other address areas of the Flash IC during two programming operations and in the presence of external interference signals.

[0008] Firstly, this application provides a method for data programming and self-testing of a display panel, including:

[0009] When the timing control module detects that the Flash IC flash memory chip has received a programming drive signal, it outputs an output voltage with at least one voltage state.

[0010] Based on the voltage state and address area mapping table, the address area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module is determined, and other areas except the address area to be programmed are controlled to be in a latched state.

[0011] The corresponding data to be burned is burned into the address area to be burned, and the data to be burned includes first data and second data;

[0012] After the data burning is completed, obtain the current cyclic redundancy check value of all areas in the Flash IC flash memory chip;

[0013] The current cyclic redundancy check value is compared and verified with the preset cyclic redundancy check value to obtain the data burning self-test result.

[0014] Secondly, this application also provides a data programming and self-testing device for a display panel, comprising:

[0015] The timing control module is used to output an output voltage with at least one voltage state when it detects that the Flash IC flash memory chip has received a programming drive signal.

[0016] The processing module is used to determine the addressable area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and addressable area mapping table, and control other areas except the addressable area to be programmed to be in a latched state.

[0017] A programming module is used to program corresponding data to be programmed into the address area to be programmed, wherein the data to be programmed includes first data and second data.

[0018] The acquisition module is used to acquire the current cyclic redundancy check value of all areas in the Flash IC flash memory chip after the data burning is completed.

[0019] The self-test module is used to compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result.

[0020] Thirdly, this application also provides a Flash IC flash memory chip, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above method.

[0021] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0022] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0023] The aforementioned display panel data programming and self-testing method, apparatus, Flash IC flash memory chip, computer-readable storage medium, and computer program product, by precisely controlling the addressable area to be programmed in the Flash IC during the programming process while simultaneously placing other areas in a latched state, effectively prevent external interference signals from affecting data in non-programmed areas, thereby improving the reliability of data programming. By reducing the risk of accidentally erasing or rewriting data in non-programmed areas, this scheme enhances the stability of OLED display devices and reduces the equipment failure rate due to data corruption. Precise control of the programming process is achieved through a timing control module and an addressable area mapping table, making the programming operation more efficient and simplifying the programming process. After data programming is completed, the cyclic redundancy check (CRC) values ​​of all areas in the Flash IC are obtained and compared with preset values ​​to achieve self-testing of the programmed data, ensuring data integrity and correctness. Due to the optimization of the programming process and the implementation of the self-test function, the number of reprogramming attempts required due to data errors can be reduced, thereby saving time and costs and improving production efficiency. The self-test function enables rapid detection and correction of programming errors during production, simplifying fault diagnosis and testing processes and reducing subsequent maintenance and testing workload. It maintains data programming accuracy even in the presence of external interference signals, ensuring stable performance of the display device under various environmental conditions.

[0024] In summary, this application improves the reliability and accuracy of display panel data programming by precisely controlling the programming process and implementing a self-test function, thereby enhancing the stability and production efficiency of OLED display devices. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 is a schematic diagram of the data burning structure of the display panel in the traditional Normal solution;

[0027] Figure 2 is a flowchart illustrating the data burning and self-testing method for the display panel in one embodiment;

[0028] Figure 3 is a flowchart illustrating the data burning and self-testing method for the display panel in another embodiment;

[0029] Figure 4 is a schematic diagram of the main data partitions of the flash memory chip in a TDDI project in one embodiment;

[0030] Figure 5 is a flowchart illustrating the data burning and self-testing method for the display panel in another embodiment;

[0031] Figure 6 is an expanded structural block diagram of the timing control module in one embodiment;

[0032] Figure 7 is a schematic diagram of the circuit structure of the gating circuit in another embodiment;

[0033] Figure 8 is a signal timing diagram of TP firmware data and Demura compensation data in another embodiment;

[0034] Figure 9 is a flowchart illustrating the data burning and self-testing method for the display panel in another embodiment;

[0035] Figure 10 is a schematic diagram of a display device in one embodiment;

[0036] Figure 11 is a structural block diagram of a data burning and self-testing device for a display panel in one embodiment;

[0037] Figure 12 is an internal structure diagram of a Flash IC flash memory chip in one embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] As shown in Figure 1, in a traditional solution, the firmware data of the touch panel (TP) is burned into the touch panel integrated circuit (TP IC). Simultaneously, the Demura (color correction) compensation data is burned into the flash memory chip (Flash IC). In this solution, the TP firmware data and Demura compensation data are stored separately, burned independently, and do not interfere with each other. To further reduce the cost of the display panel and improve the integration of the touch display device, TDDI (Touch and Display Driver Integration) technology is adopted. TDDI technology integrates touch functionality and display driver functionality onto a single chip. In the TDDI solution, due to the lack of a separate TP IC, both the TP firmware data and Demura compensation data need to be burned into the same Flash IC. This means that the Flash IC needs to perform two burning operations: first, burning the TP firmware data, and second, burning the Demura compensation data.

[0040] In the TDDI scheme, the Flash IC requires two programming operations. If external interference signals exist between the first and second programming, these signals may affect the Flash IC's storage state. If the interference causes abnormalities in the Flash IC's control logic, it may accidentally erase or incorrectly write areas of the Flash IC that should not be modified. This could lead to the first programming data (TP firmware data) being overwritten or lost, or problems with the second programming data (Demura compensation data). Incorrect erasure or overwriting of data in the Flash IC may cause the display device to malfunction, as the TP firmware data or Demura compensation data is essential for the device's operation. Such data loss or overwriting reduces the reliability of the display device, increases maintenance costs, and negatively impacts the user experience.

[0041] Based on the problems existing in the above-mentioned traditional technologies, as shown in Figure 2, a method for data programming and self-testing of a display panel is provided, including the following steps S202 to S210. Wherein:

[0042] In step S202, when the Flash IC flash memory chip receives a programming drive signal, the timing control module outputs an output voltage with at least one voltage state.

[0043] Specifically, at the start of the programming process, it is first necessary to check whether the Flash IC has received the programming drive signal. This signal is the instruction to start the programming operation, indicating that the programming operation is about to begin. The timing control module is a key component in the programming system. Its main function is to control the timing during the programming process, ensuring that data is written to the Flash IC at the correct time and in the correct order.

[0044] Based on the detected programming drive signal, the timing control module outputs an output voltage with at least one voltage state. This output voltage is a power signal used to control the internal operation of the Flash IC, determining its operating state. Different output voltage states typically correspond to different operating modes within the Flash IC, such as erase, program (write), or read. By controlling the output voltage, the timing control module can precisely control the Flash IC to enter a specific operating mode.

[0045] Step S204: Based on the voltage state and address area mapping table, determine the address area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module, and control other areas except the address area to be programmed to be in a latched state.

[0046] Specifically, the addressing area mapping table is a data structure that defines the correspondence between different voltage states and different memory areas within the Flash IC. Through this mapping table, the timing control module can determine the addressing area to be programmed in the Flash IC corresponding to the output voltage. This addressing area is a pre-defined memory area within the Flash IC, already set to receive new data. After determining the addressing area to be programmed, the timing control module controls other areas in the Flash IC to be in a latched state. The latched state is a protective state that prevents these areas from being affected by accidental erase or write operations.

[0047] Step S206: Burn the corresponding data to be burned into the address area to be burned. The data to be burned includes the first data and the second data.

[0048] Specifically, by using the output voltage of the timing control module and the address area mapping table, the area to be programmed is determined to be selected and placed in a programmable (writable) state. The programming operation refers to the process of writing data into the Flash IC. Data is written to the address area to be programmed in a predetermined order and format.

[0049] The data to be programmed typically contains two different types of data. Depending on the programming process design, the first and second data may need to be programmed into the Flash IC in a specific order. This could involve programming all of the first data first, followed by the second data; or programming the first and second data alternately in different address areas.

[0050] Step S208: After the data burning is completed, obtain the current cyclic redundancy check value of all areas in the Flash IC flash memory chip.

[0051] Specifically, after each part of the data is burned, a verification step is usually performed to ensure that the data is written correctly into the Flash IC flash memory chip, that is, to calculate and verify the CRC (Cyclic Redundancy Check) values ​​of the first and second data that have just been written.

[0052] CRC (Corrective Chronology) is an error detection algorithm that generates a fixed-length checksum by performing polynomial division. This checksum detects errors in data during transmission or storage. The basic idea of ​​CRC is to treat the data as a polynomial, divide this polynomial by a predetermined generator polynomial, and the remainder is the CRC checksum. This value is then appended to the data to verify its integrity. CRC calculations can be implemented in hardware or software. For example, the STM32 microcontroller has a built-in CRC calculation unit that can automatically perform CRC calculations on data.

[0053] Step S210: Compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result.

[0054] Specifically, the calculated current CRC value is compared with a preset CRC value. If the two values ​​are the same, it means the data was not corrupted during the programming process, and the programming was successful. If the two values ​​are different, it means the data being programmed may have been interfered with or damaged during the programming process, and an error occurred. This process is an automatic detection mechanism that can verify the correctness of the programming operation without manual intervention. In this way, the data in the Flash IC can be ensured to be reliable and stable, thereby improving the performance and reliability of the entire system.

[0055] In the aforementioned data programming and self-testing method for the display panel, precise control of the addressable area to be programmed in the Flash IC during the programming process, while simultaneously placing other areas in a latched state, effectively prevents external interference signals from affecting the data in non-programmed areas, thereby improving the reliability of data programming. By reducing the risk of accidentally erasing or rewriting data in non-programmed areas, this scheme enhances the stability of OLED display devices and reduces the equipment failure rate caused by data corruption. Precise control of the programming process is achieved through a timing control module and an addressable area mapping table, making the programming operation more efficient and simplifying the programming process. After data programming is completed, the cyclic redundancy check (CRC) values ​​of all areas in the Flash IC are obtained and compared with preset values ​​to perform a self-test of the programmed data, ensuring data integrity and correctness. Due to the optimization of the programming process and the implementation of the self-testing function, the number of reprogramming attempts required due to data errors can be reduced, thereby saving time and costs and improving production efficiency. The self-testing function enables rapid detection and correction of programming errors during production, simplifying fault diagnosis and testing processes and reducing the workload of subsequent maintenance and testing. It can maintain the accuracy of data burning even in the presence of external interference signals, enabling the display device to maintain stable performance under various environmental conditions.

[0056] In an exemplary embodiment, the first data is TP firmware data, the second data is Demura compensation data, and the type of the addressable area to be burned includes TP firmware addressable area and Demura compensation addressable area.

[0057] As shown in Figure 3, the corresponding data to be programmed is programmed into the address area to be programmed, including steps S302 to S304. Wherein:

[0058] Step S302: After burning TP firmware data into the TP firmware addressing area, burn Demura compensation data into the Demura compensation addressing area.

[0059] Step S304, or, after burning Demura compensation data in the Demura compensation addressing area, burning TP firmware data in the TP firmware addressing area.

[0060] Specifically, Figure 4 illustrates the main data partitioning of the TDDI flash memory chip. First, TP firmware data is burned into the TP firmware addressing area (i.e., the FW addressing area shown in Figure 4). This is achieved by coordinating with the EN (Enable) timing signal, ensuring that only the FW (Firmware) addressing area is operated. After burning, the CRC1 value of this area is calculated and compared with the CRC1 value of the original firmware before burning. If the comparison result matches (OK), the CRC1 value is burned into a blank area within the TP firmware addressing area. In this way, the CRC1 value can be used for subsequent integrity checks.

[0061] In another embodiment, Demura compensation data is first programmed into the Demura compensation addressing area. This is also achieved by coordinating with the EN timing signal to ensure that only the Demura compensation addressing area is operated on. After programming, the CRC2 value of this area is calculated and compared with the original CRC2 value before programming. If the comparison result matches (OK), the CRC2 value is programmed into a blank area within the Demura compensation addressing area. In this way, the CRC2 value can be used for subsequent integrity checks.

[0062] The solution allows for two burning orders, which can be flexibly selected based on actual needs and system configuration. For example, if TP firmware data has higher priority, it may be chosen to burn TP firmware data first; conversely, if Demura compensation data needs to be processed more quickly, it may be burned first.

[0063] In this embodiment, by calculating and verifying the CRC value after each programming, the security and reliability of the data programming process are significantly improved. Even under external interference, it can ensure that the data programmed into the Flash IC is correct and complete.

[0064] In an exemplary embodiment, as shown in Figure 5, after data burning is completed, the current cyclic redundancy check (CRC) values ​​of all regions in the Flash IC flash memory chip are obtained, including steps S502 to S504. Wherein:

[0065] Step S502: After burning the TP firmware data and after burning the Demura compensation data, obtain the current cyclic redundancy check value of all areas in the Flash IC flash memory chip respectively.

[0066] Step S504, or, after burning the TP firmware data and Demura compensation data, obtain the current cyclic redundancy check value for all regions in the Flash IC flash memory chip.

[0067] Specifically, immediately after burning the TP firmware data, the CRC values ​​(denoted as CRC1) of all areas in the Flash IC are obtained. Similarly, after burning the Demura compensation data, the CRC values ​​(denoted as CRC2) of all areas in the Flash IC are obtained again. This is accomplished by executing step S503. The advantage of this method is that each burning operation can be verified individually, allowing for the timely detection and correction of errors that may occur during each burning process. This reduces the problem of relying on erroneous data in subsequent burning operations.

[0068] Alternatively, the TP firmware data can be programmed first, but the CRC value is not immediately obtained. Then, the Demura compensation data is programmed, again without immediately obtaining the CRC value. After all programming operations are completed, the CRC values ​​of all areas in the Flash IC are obtained all at once. This is done by executing step S504. The advantage of this method is that it provides a comprehensive data integrity check after all programming operations are completed. This method may be more suitable if there are dependencies between programming operations, or if it is necessary to ensure the consistency of all data as a whole.

[0069] In practical applications, the choice of strategy depends on various factors, including the complexity of the programming operation, the importance of the data, and the system's error recovery capabilities. For example, if the programming operation is relatively simple and the system can tolerate a certain risk of error, a one-time verification might be performed after all programming is complete. Conversely, if the programming operation is more complex, or the system needs to ensure the accuracy of each step, verification might be performed after each programming operation.

[0070] In this embodiment, by setting different verification strategies according to actual applications, it can be ensured that the data programmed into the Flash IC is accurate, thereby guaranteeing the reliability and stability of the system. By acquiring and verifying the CRC value, errors can be detected and corrected in a timely manner during the programming process, thus improving the overall data processing quality.

[0071] In an exemplary embodiment, the timing control module is electrically connected to at least one of the output pins of an integrated circuit (IC) or a flexible printed circuit board (FPC), and is used to output an output voltage having at least one voltage state according to a programming drive signal.

[0072] Specifically, the timing control module is electrically connected to the output pins of the integrated circuit (IC) or the FPC. These pins are the wiring leads from the internal circuitry of the chip to the external circuitry, forming the chip's interface.

[0073] Electrical connection means that the timing control module is connected to the output pin of the IC or FPC via a conductive path. This connection can be a direct physical connection or can be achieved through traces on the circuit board or other types of electrical connections.

[0074] The output pins of an integrated circuit (IC) serve as the interface between the IC and external circuits. These pins can transmit control signals, data signals, or power supply voltages. During the programming process, the timing control module uses these output pins to control the programming timing of the Flash IC. A flexible printed circuit board (FPC) is a flexible circuit board that also has pins for connecting electronic components. Due to its flexibility, FPCs can be bent and folded, making them suitable for applications with limited space or requiring flexible connections.

[0075] The timing control module must be electrically connected to at least one of the output pins of the IC or the FPC. Alternatively, it can be connected to both simultaneously as needed to achieve more complex timing control or to provide a more stable power and signal path. Through this electrical connection, the timing control module can precisely control the voltage state and timing during the programming process, ensuring that the Flash IC is programmed with data under the correct voltage and timing. This electrical connection can be achieved through soldering, socket connections, fixture fixation, or the use of conductive adhesive, among other methods. The specific connection method depends on factors such as design requirements, space constraints, and production costs.

[0076] In this embodiment, by setting different electrical connection methods for the timing control modules, the programming operation is ensured to be performed under precisely controlled voltage and timing conditions, thereby improving the reliability of programming and the integrity of data.

[0077] In an exemplary embodiment, the timing control module includes: a programming drive signal receiving submodule for receiving programming drive signals, a programming drive signal identification submodule for identifying programming drive signals, and a voltage output submodule for outputting an output voltage having at least one voltage state.

[0078] As shown in Figure 6, the timing control module is a key component of the programming system, responsible for managing the voltage and timing during the Flash IC programming process. This module consists of three sub-modules, each performing a different function to ensure the correctness of the programming operation and the integrity of the data. The following is a detailed explanation of these three sub-modules:

[0079] The function of the programming driver signal receiving submodule is to receive external programming driver signals. The programming driver signal is the instruction to start the programming operation; it notifies the timing control module to begin the programming process. The programming driver signal may originate from the system's main controller, microcontroller, or other control logic, triggering the start of the programming process.

[0080] The function of the programming driver signal recognition submodule is to detect and verify the validity of received programming driver signals. This may include checking whether the signal format, frequency, or voltage level meets the expected standards. If the programming driver signal does not meet the requirements, the recognition submodule may reject the signal and send an error indication, thereby preventing incorrect programming operations.

[0081] The function of the voltage output submodule is to output an output voltage with at least one voltage state based on the received and recognized programming drive signal. These voltage states meet the voltage requirements of the Flash IC at different programming stages. The output voltage may include different voltage levels for erase, program (write), and read operations. The voltage output submodule ensures that these voltages are applied to the Flash IC at the correct timing.

[0082] The workflow of the timing control module is as follows:

[0083] When the programming operation needs to begin, the programming driver signal receiving submodule receives a start signal. The programming driver signal recognition submodule verifies the validity of this signal. Once the signal is confirmed as valid, the voltage output submodule outputs the corresponding voltage state to the Flash IC according to the preset timing and voltage requirements. During the programming process, the voltage output submodule may switch between different voltage states as needed to complete data erasure, writing, and other operations. After programming is complete, the voltage output submodule outputs another voltage state to end the programming process and enter read or other modes.

[0084] In this embodiment, the timing control module is designed to ensure that the Flash IC can be programmed under precisely controlled voltage and timing conditions, thereby improving the reliability of programming and the integrity of data. This modular design also contributes to the flexibility and maintainability of the programming system.

[0085] In one exemplary embodiment, the timing control module is connected to a gating circuit;

[0086] The control terminal of the gating circuit is electrically connected to the voltage output submodule. It is used to determine the address area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and address area mapping table, and to select either the first output terminal or the second output terminal of the gating circuit.

[0087] The first output of the gating circuit is electrically connected to the signal line of the TP firmware addressing area; the second output of the gating circuit is electrically connected to the signal line of the Demura compensation addressing area.

[0088] Specifically, Figure 7 illustrates the gating circuit, where the timing control module manages the voltage and timing during the Flash IC programming process. It is electrically connected to the control terminal of the gating circuit, controlling its behavior. The control terminal of the gating circuit receives signals from the voltage output submodule (i.e., the data-IC shown in the figure). The voltage output submodule outputs specific voltage states according to the instructions from the timing control module. These states are associated with an address area mapping table to determine the specific address area in the Flash IC to be programmed.

[0089] The gating circuit selectively connects to either its first or second output terminal based on the voltage status signal received from the control terminal. This selective connection is called "gating" because it allows current to flow to a specific addressable area in the Flash IC. For example, the SW1 signal gating the first output terminal and the SW2 signal gating the second output terminal.

[0090] For example, the first output of the gating circuit is electrically connected to the storage TP firmware addressing area (i.e., the FW addressing area). When TP firmware data needs to be programmed, the gating circuit will select its first output (i.e., data-F, FW data in the diagram). The second output of the gating circuit is electrically connected to the storage Demura compensation addressing area. When Demura compensation data needs to be programmed, the gating circuit will select its second output (i.e., data-D, Demura data in the diagram).

[0091] The gating circuit ensures that during the programming process, only the selected addressable area (TP firmware addressable area or Demura compensation addressable area) receives programming data, while other addressable areas remain unchanged. This helps prevent data conflicts and ensures data accuracy.

[0092] In this embodiment, the timing control module precisely selects a specific address area in the Flash IC for programming by controlling the gating circuit. This design allows the system to switch between different address areas to program different types of data, while ensuring data integrity and the reliability of the Flash IC.

[0093] In an exemplary embodiment, before programming the corresponding data to be programmed into the address area to be programmed, the method further includes:

[0094] When the voltage state is the first gradient voltage, the gating circuit controls the TP firmware addressing area to be in the open state, and the other areas except the TP firmware addressing area to be in the latched state; when the voltage state is the second gradient voltage, the gating circuit controls the Demura compensation addressing area to be in the open state, and the other areas except the Demura compensation addressing area to be in the latched state.

[0095] Alternatively, when the voltage state is the first gradient voltage, the gating circuit controls the Demura compensation addressing area to be in the open state, and the other areas except the Demura compensation addressing area to be in the latched state; when the voltage state is the second gradient voltage, the gating circuit controls the TP firmware addressing area to be in the open state, and the other areas except the TP firmware addressing area to be in the latched state.

[0096] Specifically, the first gradient voltage and the second gradient voltage correspond to different addressing regions and programming processes, respectively. Figure 8 shows the signal timing diagrams of TP firmware data and Demura compensation data. The waveforms of the EN signal and data (DATA) show the timing of the programming process. The high and low changes of the EN signal correspond to different programming stages, while the DATA signal represents the actual programmed data.

[0097] For example, as shown in Figure 8, the EN timing signal is used to control the start of the programming process. When EN is high, it indicates the start of programming TP firmware data; when EN is low, it indicates the start of programming Demura compensation data. The voltage status is output by the timing control module and is used by a gating circuit to control which addressing area is activated.

[0098] Under high voltage, the TP firmware addressing area is enabled by the gating circuit, allowing the programming operation, while other areas (such as the Demura compensation addressing area) are latched to prevent accidental data modification. Under low voltage, the Demura compensation addressing area is enabled by the gating circuit, allowing the programming operation, while other areas (such as the TP firmware addressing area) are latched.

[0099] It should be noted that in other embodiments, when EN is high voltage, it indicates the start of burning TP firmware data; when EN is low voltage, it indicates the start of burning Demura compensation data.

[0100] In this embodiment, precise timing control and voltage timing management enable independent programming of different address areas in the Flash IC, improving the safety and reliability of the programming process and ensuring the accuracy of the programmed data.

[0101] In one exemplary embodiment, the gating circuit is integrated inside the display panel or inside the flexible printed circuit board (FPC).

[0102] Specifically, the gating circuit is integrated directly into the internal circuitry of the display panel as part of its design. This allows the gating circuit to work closely with other electronic components on the panel to achieve precise timing control and data programming.

[0103] Flexible printed circuit boards (FPCs) are bendable circuit boards commonly used in applications where space is limited or flexible wiring is required. Alternatively, gating circuitry can be integrated inside the FPC to work with other circuit elements on the FPC, such as connectors and signal cables, to provide the necessary signal control for the display panel.

[0104] It should be noted that integrating the gating circuit inside the display panel or FPC requires consideration of the circuit board layout, signal path optimization, and compatibility with other system components.

[0105] In this embodiment, integrating the gating circuit into the display panel or FPC is a design method that directly embeds the necessary functions into the main components, which helps to achieve the goal of being compact, efficient and more cost-effective.

[0106] In one exemplary embodiment, the effective burning period for receiving the burning drive signal includes the burning period for TP firmware data and the burning period for Demura compensation data.

[0107] Specifically, the programming drive signal is the signal that initiates and controls the programming operation. It is typically issued by the system's main controller or programmer to instruct the Flash IC to begin the data programming process. The effective programming period refers to the time interval during which the programming drive signal is in an effective state (e.g., high or low level). During this period, the Flash IC receives and processes the programming data.

[0108] TP firmware data refers to the firmware data of the touch panel, which controls the touch functionality. The burning period refers to the time interval specifically allocated for burning TP firmware data within the effective burning period. Demura compensation data is used to improve the color uniformity of the display panel. The burning period refers to the time interval specifically allocated for burning Demura compensation data within the effective burning period.

[0109] The programming process involves multiple different data types, each potentially requiring different programming conditions or sequences. Therefore, the entire effective programming period is subdivided into multiple sub-periods, each corresponding to the programming of a specific data type. The timing control module manages the transitions and coordination between these different programming periods, ensuring that data is programmed into the appropriate address area of ​​the Flash IC in the correct order. The timing of the programming drive signals is directly related to the accuracy and integrity of the data programming. Accurate timing control prevents data misalignment, loss, or corruption.

[0110] In this embodiment, during the burning process, there are specific and controlled burning periods for different types of data (such as TP firmware data and Demura compensation data). By precisely controlling these periods, the burning operation can be ensured to proceed smoothly, while maintaining the integrity of the data and the reliability of the system.

[0111] In one exemplary embodiment, at least one of the burning period for TP firmware data or the burning period for Demura compensation data is included.

[0112] Specifically, during the operation cycle, there is at least one burning period for TP firmware data or Demura compensation data, and this burning period can be continuous or staggered.

[0113] For example, the burning time intervals can be continuous, one after another without interruption. For instance, TP firmware data can be burned continuously first, followed immediately by Demura compensation data. The burning time intervals can also be staggered, meaning that the burning of TP firmware data and Demura compensation data alternates during the burning process. For instance, the burning of Demura compensation data can be inserted between the burning of TP firmware data.

[0114] An example of continuous programming is as follows: Suppose a programming cycle for a display panel includes two main steps: programming the TP firmware data and programming the Demura compensation data. If, within a certain cycle, the TP firmware data is programmed first, and then the Demura compensation data is programmed after completion...

[0115] An example of interleaved burning is: if you pause burning TP firmware data in the middle and start burning Demura compensation data, and then continue burning the remaining TP firmware data.

[0116] The programming process is typically precisely controlled by a timing control module to ensure that the correct programming operation is performed at the correct time. The gating circuit plays a crucial role in this process; based on signals from the timing control module, it selectively enables the corresponding programming period while keeping other areas in a latched state to prevent erroneous operations.

[0117] In this embodiment, at least one data type's programming session is executed within a programming cycle, and this programming session can be continuous or interleaved. This design provides flexibility in the programming operation to adapt to different production needs and optimize programming efficiency.

[0118] In an exemplary embodiment, as shown in FIG9, the corresponding data to be programmed is programmed into the address area to be programmed, including:

[0119] Step S902: Obtain the data capacity of the data to be burned;

[0120] Step S904: Based on the data capacity, determine the target addressing area in the addressing area to be burned that is suitable for accommodating the data to be burned;

[0121] Step S906: Burn the corresponding data to be burned into the target addressing area.

[0122] Specifically, before programming, the size or capacity of the data to be programmed must first be known. This is to ensure there is sufficient space to store the data and to avoid overflow or insufficiency. Based on the obtained data capacity, the system determines which part of the addressable area to be programmed (the target addressable area) has enough space to accommodate this data. This may involve analyzing the Flash IC's storage structure and used space. Once the target addressable area is determined, the next step is to actually program the corresponding data to be programmed into that area, that is, to write the data into specific memory cells.

[0123] Example illustration: Suppose there is a display panel with Flash storage that needs to update TP firmware data and Demura compensation data:

[0124] Step 1: First, measure or determine the size of the TP firmware data and Demura compensation data to be burned.

[0125] Step 2: Based on the size of this data, check the Flash storage to determine which area can accommodate it. For example, if the TP firmware data requires 2MB of space and the Demura data requires 1MB, the system will look for an unused area that is large enough.

[0126] Step 3: Perform data burning in the designated area (such as the TP firmware addressing area and the Demura compensation addressing area). This may involve erasing old data and writing new data.

[0127] In this embodiment, by determining the target addressing area suitable for accommodating the data to be programmed within the addressing area to be programmed based on the data capacity, it can be ensured that the data is programmed to the correct location and that all related data is properly processed, thereby ensuring that the function and performance of the display panel are not affected. At the same time, proper addressing and programming process management helps prevent data loss and ensure system stability.

[0128] In one exemplary embodiment, obtaining the current cyclic redundancy check (CRC) value for all regions in the Flash IC flash memory chip includes:

[0129] The Cyclic Redundancy Check (CRBC) register in the Flash IC flash memory chip is initialized to obtain an initial CRBC value. Data blocks are read sequentially from all areas of the Flash IC flash memory chip. The first read data block is processed bit by bit with the initial CRBC value to obtain the processing result. Based on the processing result, the initial CRBC value is updated, and the next read data block is processed bit by bit with the updated CRBC value. The updated CRBC value corresponding to the last read data block is used as the current CRBC value.

[0130] Specifically, first, the CRC register in the Flash IC is initialized by setting an initial CRC value, which is usually predefined, such as 0xFFFFFFFF or 0x00000000000.

[0131] The system then reads data blocks sequentially from all areas of the Flash IC. A data block is a segment of data of a certain size stored in Flash. The first data block read is processed bit by bit with the initial CRC value, involving a CRC algorithm that calculates a result based on a specific polynomial and data bits. The CRC value is updated based on the result of the first data block. This updated CRC value is used for the CRC calculation of the next data block. The next data block read is then processed bit by bit with the updated CRC value, and the CRC value is updated again. This process is repeated until all data blocks have been processed.

[0132] Finally, the updated CRC value corresponding to the read data block will be used as the current CRC value of the Flash IC. This value reflects the CRC check results of all read data blocks.

[0133] Example illustration: Assume that the Flash storage is divided into three data blocks A, B, and C:

[0134] Step 1: Initialize the CRC value to 0xFFFFFFFF.

[0135] Step 2: Read data block A and perform CRC algorithm processing with the initial CRC value. Assume the result is 0xABCD EFGH.

[0136] Step 3: Read data block B and process it with 0xABCD EFGH to obtain a new CRC value 0xIJKL MNO.

[0137] Step 4: Read data block C and process it with 0xIJKL MNOP to obtain the final CRC value 0xQRS TUV.

[0138] The final CRC value, 0xQRS TUV, represents the CRC check result of all data blocks in the Flash IC. This value is used for subsequent data integrity checks or error detection. If it matches the expected CRC value, it indicates that the data is intact and error-free; if it does not match, it indicates that the data may be corrupted or that an error occurred during transmission.

[0139] In this embodiment, by calculating and comparing CRC values, it can be verified whether the data stored in the Flash IC is complete and has not been accidentally modified or damaged. By ensuring the correct burning and storage of data, the stability and performance of the entire system can be improved.

[0140] In an exemplary embodiment, the addressable area to be programmed includes a data occupancy area and a region to be used. The data occupancy area is used to store the data to be programmed. After comparing and verifying the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data programming self-test result, the method further includes:

[0141] If the current cyclic redundancy check value and the preset cyclic redundancy check value are consistent based on the data burning self-test results, the current cyclic redundancy check value will be burned into the area to be used.

[0142] Specifically, the programming addressing area is divided into two parts: the data occupancy area and the unused area. The data occupancy area is the area actually used to store the programmed data.

[0143] After data is burned, the system calculates the Cyclic Redundancy Check (CRC) value of the current data. This CRC value is used to verify the integrity and correctness of the burned data. The calculated current CRC value is compared with a preset CRC value (preset CRC value) to verify whether the burned data is correct. If the current CRC value matches the preset CRC value, it indicates that the burned data is complete and undamaged. In this case, the system burns the current CRC value to the unused area. The unused area is the unused portion of the burning address area, used to store or process additional information, such as the CRC value. The purpose of this is to record the result of the burning operation for future verification or diagnostics.

[0144] In this embodiment, data integrity protection is enhanced by burning the CRC value into the area to be used. Subsequently, the CRC value of this area can be read to verify whether the data has been tampered with or corrupted during subsequent storage or transmission.

[0145] In an exemplary embodiment, after comparing and verifying the current cyclic redundancy check value with a preset cyclic redundancy check value to obtain the data burning self-test result, the method further includes:

[0146] If the current cyclic redundancy check value and the preset cyclic redundancy check value are inconsistent based on the data burning self-test results, clear the data to be burned stored in the data occupancy area and re-execute the step of burning the corresponding data to be burned in the address area to be burned; obtain the cumulative number of consecutive inconsistent verifications; if the cumulative number reaches the preset number threshold, adjust the preset cyclic redundancy check value.

[0147] Specifically, after data is programmed, the system calculates the current Cyclic Redundancy Check (CRC) value and compares it with a preset CRC value to obtain a self-check result for data programming. If the self-check result shows that the current CRC value is inconsistent with the preset value, it indicates that the programmed data may contain errors. In this case, the system will clear the data to be programmed stored in the data occupancy area, that is, delete or erase those potentially erroneous data. Then, the system will re-execute the programming step, that is, re-program the data to be programmed into the address area to be programmed, and attempt to perform the programming operation again.

[0148] The system records the cumulative number of consecutive verification inconsistencies, i.e., how many consecutive CRC value comparisons result in inconsistencies. When the cumulative number of verification inconsistencies reaches a preset threshold, the system will take corresponding adjustment measures. This includes adjusting the preset value of cyclic redundancy check to adapt to possible changes in data or programming conditions. This design ensures high accuracy and reliability of data programming. Through CRC value comparison verification, programming errors are detected and corrected in a timely manner. The reprogramming mechanism provides a second chance for correct data storage, reducing system failures or performance problems caused by programming errors. The recording of cumulative counts and the adjustment measures after reaching the threshold provide the system with adaptability to cope with possible environmental changes or changes in data characteristics, maintaining long-term stability and reliability.

[0149] In this embodiment, a closed-loop data integrity protection mechanism is formed through CRC verification, error reprogramming, and condition adjustment, which significantly improves the reliability of the data programming process and the stability of the system.

[0150] In one exemplary embodiment, the regions other than the addressable area to be burned include at least one buffer for temporarily storing the data to be burned; wherein each addressable area to be burned is connected to at least one buffer.

[0151] Specifically, the addressable area to be programmed is a specific region within the Flash IC designated for storing programmed data. Besides the addressable area, the Flash IC contains other regions, including at least one buffer for temporarily storing data to be programmed. The buffer serves as temporary data storage during the programming process, which helps manage data flow and ensures the stability and efficiency of programming. The buffer can temporarily store data to be programmed into the Flash IC or store intermediate data generated during the programming process. Each addressable area to be programmed is connected to at least one buffer, facilitating rapid access and processing of data during programming. The buffer provides necessary data support to the addressable area to be programmed, ensuring the continuity and efficiency of the programming operation.

[0152] Example illustration: Assume a Flash IC design has three addressable areas to be programmed, each connected to a buffer. During the programming operation, data is first written to the buffer, and then transferred from the buffer to the addressable area to be programmed, completing the programming process.

[0153] In this embodiment, by configuring at least one buffer in the addressable area to be programmed, the efficiency and reliability of data programming are improved, ensuring the smooth progress of the programming operation. The use of a buffer can optimize the programming process, especially when processing large amounts of data, by balancing the data flow and avoiding programming bottlenecks.

[0154] In one exemplary embodiment, after the data burning is complete, the method further includes:

[0155] Receive a data retrieval command for the Flash IC flash memory chip; in response to the data retrieval command, transfer the target data in the corresponding address area to be programmed to the buffer; and retrieve the target data from the buffer according to the data retrieval method in the data retrieval command.

[0156] Specifically, after data programming is complete, the system receives data retrieval instructions for the Flash IC. These instructions request to read or retrieve data stored in the Flash IC. In response to the received data retrieval instructions, the Flash IC transfers the target data from the address area to be programmed to the buffer. This step prepares the data for further processing or transfer to other system components. Depending on the method specified in the data retrieval instructions, the system retrieves the target data from the buffer. Data retrieval methods may include reading a specific portion of the data, all of the data, or data organized in a certain format.

[0157] Example illustration: Suppose an embedded system needs to verify the update after updating the firmware in the Flash IC:

[0158] Step 1: The system sends a data retrieval command to the Flash IC, requesting to read the newly burned firmware data.

[0159] Step 2: The Flash IC recognizes the instruction and transfers the firmware data from its storage area to the internal buffer.

[0160] Step 3: The system retrieves data from the buffer according to the instructions, and may perform verification or execute it in memory to ensure that the firmware update is correct.

[0161] In this embodiment, data can be effectively managed and retrieved after burning to meet the system's reading or further processing needs. By using a buffer as intermediate storage, the data transmission process is optimized, improving the speed and efficiency of data access. Flexible data retrieval methods are allowed, enabling the system to obtain data in different ways according to specific needs, increasing the adaptability and flexibility of the operation.

[0162] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages, and these steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages of other steps.

[0163] Based on the same inventive concept, this application also provides a display panel data programming and self-testing device for implementing the above-mentioned display panel data programming and self-testing method. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations of one or more display panel data programming and self-testing device embodiments provided below can be found in the limitations of the display panel data programming and self-testing method above, and will not be repeated here.

[0164] The display device can be a mobile phone, tablet computer, or similar device. Specifically, referring to Figure 10, a schematic diagram of a display device in one embodiment is shown. The display device 100 may include a display panel 1002. The display panel may be an organic light-emitting diode (OLED) display panel.

[0165] In an exemplary embodiment, as shown in FIG10, a data programming and self-testing device for a display panel is provided, including: a timing control module 1102, which is used to output an output voltage having at least one voltage state when it detects that the Flash IC flash memory chip receives a programming drive signal;

[0166] The processing module 1104 is used to determine the address area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module 1102 according to the voltage state and address area mapping table, and control other areas except the address area to be programmed to be in a latched state.

[0167] The programming module 1106 is used to program corresponding data to be programmed in the address area to be programmed, the data to be programmed includes first data and second data;

[0168] The acquisition module 1108 is used to acquire the current cyclic redundancy check value of all areas in the Flash IC flash memory chip after the data burning is completed.

[0169] The self-test module 1110 is used to compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result.

[0170] In an exemplary embodiment, the first data is TP firmware data, the second data is Demura compensation data, and the type of the addressable area to be burned includes TP firmware addressable area and Demura compensation addressable area.

[0171] The programming module 1106 is specifically used to program TP firmware data in the TP firmware addressing area and then program Demura compensation data in the Demura compensation addressing area; or, after programming Demura compensation data in the Demura compensation addressing area, program TP firmware data in the TP firmware addressing area.

[0172] In an exemplary embodiment, the acquisition module 1108 is specifically used to acquire the current cyclic redundancy check value of all regions in the Flash IC flash memory chip after burning TP firmware data and after burning Demura compensation data; or, after burning TP firmware data and Demura compensation data, to acquire the current cyclic redundancy check value of all regions in the Flash IC flash memory chip.

[0173] In an exemplary embodiment, the timing control module 1102 is electrically connected to at least one of the output pins of an integrated circuit IC or a flexible printed circuit board FPC, and is used to output an output voltage having at least one voltage state according to a programming drive signal.

[0174] In an exemplary embodiment, the timing control module 1102 includes: a programming drive signal receiving submodule for receiving programming drive signals, a programming drive signal identification submodule for identifying programming drive signals, and a voltage output submodule for outputting an output voltage having at least one voltage state.

[0175] In an exemplary embodiment, the timing control module 1102 is connected to a gating circuit; the control terminal of the gating circuit is electrically connected to the voltage output submodule, and is used to determine the addressable area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module 1102 according to the voltage state and addressable area mapping table, and to select either the first output terminal or the second output terminal of the gating circuit; the first output terminal of the gating circuit is electrically connected to the signal line of the TP firmware addressable area; the second output terminal of the gating circuit is electrically connected to the signal line of the Demura compensation addressable area.

[0176] In an exemplary embodiment, the processing module 1104 is further configured to: when the voltage state is a first gradient voltage, control the TP firmware addressing area to be in an enabled state and other areas other than the TP firmware addressing area to be in a latched state; when the voltage state is a second gradient voltage, control the Demura compensation addressing area to be in an enabled state and other areas other than the Demura compensation addressing area to be in a latched state; or, when the voltage state is a first gradient voltage, control the Demura compensation addressing area to be in an enabled state and other areas other than the Demura compensation addressing area to be in a latched state; when the voltage state is a second gradient voltage, control the TP firmware addressing area to be in an enabled state and other areas other than the TP firmware addressing area to be in a latched state.

[0177] In one exemplary embodiment, the gating circuit is integrated inside the display panel or inside the flexible printed circuit board (FPC).

[0178] In one exemplary embodiment, the effective burning period for receiving the burning drive signal includes the burning period for TP firmware data and the burning period for Demura compensation data.

[0179] In one exemplary embodiment, at least one of the burning period for TP firmware data or the burning period for Demura compensation data is included.

[0180] In an exemplary embodiment, the programming module 1106 is further configured to obtain the data capacity of the data to be programmed; determine a target addressing area suitable for accommodating the data to be programmed in the addressing area to be programmed based on the data capacity; and program the corresponding data to be programmed in the target addressing area.

[0181] In an exemplary embodiment, the acquisition module 1108 is specifically used to initialize the Cyclic Redundancy Check (CRRC) register in the Flash IC flash memory chip to obtain an initial CRRC value; sequentially read data blocks from all areas of the Flash IC flash memory chip; perform bit-by-bit processing between the first read data block and the initial CRRC value to obtain a processing result; update the initial CRRC value according to the processing result, and perform bit-by-bit processing between the next read data block and the updated CRRC value; and use the updated CRRC value corresponding to the last read data block as the current CRRC value.

[0182] In an exemplary embodiment, the addressing area to be programmed includes a data occupancy area and a region to be used. The data occupancy area is used to store the data to be programmed. The programming module 1106 is also used to program the current cyclic redundancy check value into the region to be used when the current cyclic redundancy check value and the preset cyclic redundancy check value are verified to be consistent based on the data programming self-test result.

[0183] In an exemplary embodiment, the programming module 1106 is further configured to, when the current cyclic redundancy check value and the preset cyclic redundancy check value are inconsistent based on the data programming self-test result, clear the data to be programmed stored in the data occupancy area and re-execute the step of programming the corresponding data to be programmed in the address area to be programmed.

[0184] The acquisition module 1108 is also used to acquire the cumulative number of consecutive verification inconsistencies;

[0185] The processing module 1104 is also used to adjust the preset value of the cyclic redundancy check when the cumulative number of times reaches the preset number threshold.

[0186] In one exemplary embodiment, the regions other than the addressable area to be burned include at least one buffer for temporarily storing the data to be burned; wherein each addressable area to be burned is connected to at least one buffer.

[0187] In an exemplary embodiment, the processing module 1104 is configured to receive a data retrieval instruction for a Flash IC flash memory chip; in response to the data retrieval instruction, transfer the target data in the corresponding addressable area to be programmed to a buffer; and retrieve the target data from the buffer according to the data retrieval method in the data retrieval instruction.

[0188] Each module in the aforementioned display panel data programming and self-testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor within the Flash IC flash memory chip in hardware form, or stored in the memory of the Flash IC flash memory chip in software form, so that the processor can call and execute the corresponding operations of each module.

[0189] In an exemplary embodiment, a Flash IC flash memory chip is provided, the internal structure of which can be shown in Figure 12. The Flash IC flash memory chip includes a processor, memory, input / output interface, communication interface, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface and input device are connected to the system bus via the input / output interface. The processor of the Flash IC flash memory chip provides computing and control capabilities. The memory of the Flash IC flash memory chip includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the Flash IC flash memory chip is used for exchanging information between the processor and external devices. The communication interface of the Flash IC flash memory chip is used for wired or wireless communication with external terminals. Wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a data burning and self-test method for a display panel.

[0190] Those skilled in the art will understand that the structure shown in Figure 12 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the Flash IC flash memory chip to which the present application is applied. A specific Flash IC flash memory chip may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0191] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0192] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0193] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0194] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0195] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0196] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for data programming and self-testing of a display panel, the method comprising: When the timing control module detects that the Flash IC flash memory chip has received a programming drive signal, it outputs an output voltage with at least one voltage state. Based on the voltage state and address area mapping table, the address area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module is determined, and other areas except the address area to be programmed are controlled to be in a latched state. The corresponding data to be burned is burned into the address area to be burned, and the data to be burned includes first data and second data; After the data burning is completed, obtain the current cyclic redundancy check value of all areas in the Flash IC flash memory chip; The current cyclic redundancy check value is compared and verified with the preset cyclic redundancy check value to obtain the data burning self-test result.

2. The method according to claim 1, wherein, The first data is TP firmware data, the second data is Demura compensation data, and the type of the addressable area to be burned includes TP firmware addressable area and Demura compensation addressable area; The step of burning the corresponding data to be burned into the address area to be burned includes: After burning the TP firmware data into the TP firmware addressing area, burn the Demura compensation data into the Demura compensation addressing area. Alternatively, after burning the Demura compensation data into the Demura compensation addressing area, the TP firmware data can be burned into the TP firmware addressing area.

3. The method according to claim 2, wherein, After the data burning is completed, the step of obtaining the current cyclic redundancy check (CRC) values ​​of all regions in the Flash IC flash memory chip includes: After burning the TP firmware data and after burning the Demura compensation data, the current cyclic redundancy check value of all regions in the Flash IC flash memory chip is obtained respectively. Alternatively, after burning the TP firmware data and the Demura compensation data, obtain the current cyclic redundancy check value for all regions in the Flash IC flash memory chip.

4. The method according to claim 1, wherein, The timing control module is electrically connected to at least one of the output pins of an integrated circuit (IC) or a flexible printed circuit board (FPC), and is used to output an output voltage having at least one voltage state according to the programming drive signal.

5. The method according to claim 1, wherein, The timing control module includes: a programming drive signal receiving submodule for receiving the programming drive signal, a programming drive signal identification submodule for identifying the programming drive signal, and a voltage output submodule for outputting an output voltage having at least one voltage state.

6. The method according to claim 5, wherein, The timing control module is connected to a gating circuit; The control terminal of the gating circuit is electrically connected to the voltage output submodule, and is used to determine the address area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and address area mapping table, and to select any one of the first output terminal and the second output terminal of the gating circuit. The first output terminal of the gating circuit is electrically connected to the signal line of the TP firmware addressing area; the second output terminal of the gating circuit is electrically connected to the signal line of the Demura compensation addressing area.

7. The method according to claim 6, wherein, Before burning the corresponding data to be burned into the addressable area to be burned, the method further includes: When the voltage state is the first gradient voltage, the gating circuit controls the TP firmware addressing area to be in the open state, and the other areas except the TP firmware addressing area to be in the latched state; when the voltage state is the second gradient voltage, the gating circuit controls the Demura compensation addressing area to be in the open state, and the other areas except the Demura compensation addressing area to be in the latched state. Alternatively, when the voltage state is a first gradient voltage, the gating circuit controls the Demura compensation addressing area to be in an enabled state, and other areas except the Demura compensation addressing area to be in a latched state; when the voltage state is a second gradient voltage, the gating circuit controls the TP firmware addressing area to be in an enabled state, and other areas except the TP firmware addressing area to be in a latched state.

8. The method according to claim 6, wherein, The gating circuit is integrated inside the display panel or the flexible printed circuit board (FPC).

9. The method according to claim 2, wherein, The effective burning period for receiving the burning drive signal includes the burning period for TP firmware data and the burning period for Demura compensation data.

10. The method according to claim 9, wherein, At least one of the following is true: the burning period of the TP firmware data or the burning period of the Demura compensation data.

11. The method according to claim 1, wherein, The step of burning the corresponding data to be burned into the address area to be burned includes: Obtain the data capacity of the data to be burned; Based on the data capacity, determine the target addressing area in the addressing area to be burned that is suitable for accommodating the data to be burned; The corresponding data to be burned is burned into the target addressing area.

12. The method according to claim 1, wherein, The step of obtaining the current cyclic redundancy check (CRC) value for all regions in the Flash IC flash memory chip includes: The cyclic redundancy check register in the Flash IC flash memory chip is initialized to obtain an initial cyclic redundancy check value; Read data blocks sequentially from all regions of the Flash IC flash memory chip; The first read data block is processed bit by bit with the initial cyclic redundancy check value to obtain the processing result; Based on the processing result, the initial cyclic redundancy check value is updated, and the next data block to be read is processed bit by bit with the updated cyclic redundancy check value. Use the updated cyclic redundancy check value corresponding to the last read data block as the current cyclic redundancy check value.

13. The method according to claim 1, wherein, The addressing area to be burned includes a data occupancy area and a region to be used. The data occupancy area is used to store the data to be burned. After comparing the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result, the process further includes: If the current cyclic redundancy check value is found to be consistent with the preset cyclic redundancy check value based on the data burning self-test results, the current cyclic redundancy check value is burned into the area to be utilized.

14. The method according to claim 13, wherein, After comparing the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result, the process further includes: If the current cyclic redundancy check value and the preset cyclic redundancy check value are inconsistent based on the data burning self-test result, the data to be burned stored in the data occupancy area is cleared, and the step of burning the corresponding data to be burned in the addressing area to be burned is re-executed. Get the cumulative number of consecutive verification inconsistencies; If the cumulative number of times reaches a preset threshold, the preset value of the cyclic redundancy check is adjusted.

15. The method according to claim 1, wherein, The other areas besides the addressable area to be burned include at least one buffer for temporarily storing the data to be burned; wherein each addressable area to be burned is connected to at least one buffer.

16. The method according to claim 15, wherein, After the data burning process is complete, the process also includes: Receive a data retrieval command for the FlashIC flash memory chip; In response to the data retrieval command, the target data in the corresponding addressable area to be burned is transferred to the buffer; According to the data retrieval method in the data retrieval instruction, the target data is retrieved from the buffer.

17. A data programming and self-testing device for a display panel, the device comprising: The timing control module is used to output an output voltage with at least one voltage state when it detects that the Flash IC flash memory chip has received a programming drive signal. The processing module is used to determine the addressable area to be programmed in the Flash IC flash memory chip corresponding to the output voltage of the timing control module according to the voltage state and addressable area mapping table, and control other areas except the addressable area to be programmed to be in a latched state. A programming module is used to program corresponding data to be programmed into the address area to be programmed, wherein the data to be programmed includes first data and second data. The acquisition module is used to acquire the current cyclic redundancy check value of all areas in the Flash IC flash memory chip after the data burning is completed. The self-test module is used to compare and verify the current cyclic redundancy check value with the preset cyclic redundancy check value to obtain the data burning self-test result.

18. A Flash IC flash memory chip, comprising a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 16.

19. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 16.

20. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 16.

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