Chip packaging structure and electronic device

Abstract

Embodiments of the present application relate to the technical field of chip packaging, and provide a chip packaging structure and an electronic device, aiming to improve the performance of the chip packaging structure. The chip packaging structure comprises a first chip, a second chip, a first metal wire, a second metal wire, and a first bump and a second bump which are connected to the first chip. The first metal wire connects the first bump and the second chip. The second metal wire connects the second bump and the second chip. The second metal wire and the first metal wire are adjacent to each other. The first metal wire comprises a first sub-segment. The first sub-segment is adjacent to the side of the second bump away from the first chip, and there is a gap between the first sub-segment and the second bump. In the embodiments of the present application, there is a mutual capacitance between the first sub-segment and the second bump, so that far-end crosstalk between chip interconnection signals is reduced, thereby ensuring chip interconnection efficiency, and also reducing the design gap between the metal wires, improving integration level, and improving the performance of the chip packaging structure.

Description

Chip packaging structure and electronic devices

[0001] This application claims priority to Chinese patent application filed on November 29, 2024, with application number 202411746134.8 and entitled "Chip Packaging Structure and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip packaging technology, and more particularly to a chip packaging structure and an electronic device. Background Technology

[0003] Moore's Law is approaching its physical limits, but the demand for chip computing power is increasing. The traditional practice of integrating multiple circuit modules on a single chip is placing increasingly higher demands on chip manufacturing processes. Chiplet technology, on the other hand, separates multiple circuit modules onto multiple independent chips (dies), and uses advanced packaging (AP) technology to encapsulate these chips together, enabling die-to-die (D2D) interconnection. This technology offers advantages such as high design flexibility, high chip yield, low cost, and short design cycle, and is therefore gradually gaining widespread application.

[0004] However, the path to performance improvement also presents significant challenges with chip-neck technology. For example, in chip-neck technology using 2.5D packaging, the interconnect density between chips is high. If prioritizing the integration of the chip package structure, far-end crosstalk can easily occur between chip interconnect signals, leading to a decrease in the transmission quality of interconnect signals and potentially even data loss, thus degrading the performance of the chip package structure. If minimizing far-end crosstalk is prioritized, sufficient design clearance is required between the interconnect traces (or metal lines) used to implement chip interconnects. However, this limits the scale and integration of interconnect traces, making it difficult to increase the total interconnect bandwidth between chips and thus restricting the performance improvement of the chip package structure. Therefore, for chip package structures using chip-neck technology, it is often difficult to maintain high integration while minimizing far-end crosstalk in the chip interconnect signals, hindering the performance improvement of the chip package structure.

[0005] Therefore, how to improve the performance of chip packaging structure is an urgent problem that technical personnel need to solve. Summary of the Invention

[0006] This application provides a chip packaging structure and an electronic device, the main purpose of which is to improve the performance of the chip packaging structure.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a chip packaging structure, which includes a first chip, a second chip, a first metal line, a second metal line, and a plurality of bumps. The plurality of bumps are connected to the first chip, and the plurality of bumps include a first bump and a second bump. Both ends of the first metal line are connected to the first bump and the second chip, respectively. Both ends of the second metal line are connected to the second bump and the second chip, respectively. At least a portion of the second metal line is adjacent to at least a portion of the first metal line. The first metal line has a first sub-segment, which is adjacent to the side of the second bump away from the first chip and spaced apart from the second bump.

[0009] In the chip package structure provided in some embodiments of the first aspect, firstly, a first metal line connects a first bump and a second chip, and the first bump is connected to the first chip, thereby achieving interconnection between the first chip and the second chip using the first metal line. Similarly, a second metal line can also achieve interconnection between the first chip and the second chip. The adjacent proximity of the first and second metal lines helps to reduce the package area occupied by the metal lines and improve the integration density of the chip package structure. Secondly, although mutual inductance may exist between the first and second metal lines, such mutual inductance can cause far-end crosstalk to the chip interconnect signals. However, in the chip packaging structure provided in this application embodiment, the first segment of the first metal line is spaced apart on the side of the second bump away from the first chip. There is capacitive coupling between the first segment and the second bump, or in other words, there is mutual capacitance between the first metal line and the second bump. This can significantly increase the mutual capacitance between the first bump and the second bump. Thus, it can partially or completely achieve a balance between the two types of crosstalk caused by mutual capacitance and mutual inductance, thereby reducing or eliminating far-end crosstalk of chip interconnect signals. While ensuring the transmission quality of chip interconnect signals, it can reduce the design gap of interconnect traces (including the first metal line and the second metal line), improve the integration of the chip packaging structure, and thus increase the total interconnect bandwidth between chips under the same size. As a result, the performance of the chip packaging structure is improved.

[0010] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes a third metal line, and the plurality of bumps also include a third bump. The two ends of the third metal line are respectively connected to the third bump and the second chip. At least a portion of the third metal line is adjacent to at least a portion of the first metal line. In this implementation, the interconnection between the first chip and the second chip is achieved by connecting the third metal line to the third bump and the second chip. The adjacency of the first and third metal lines helps to reduce the package area occupied by the metal lines and improve the integration density of the chip package structure.

[0011] In this implementation, the first metal line further includes a second segment connected to the first segment. The second segment is adjacent to the third bump on the side away from the first chip and is spaced apart from the third bump. Thus, mutual capacitance exists between the first metal line and the third bump, while the first metal line is connected to the first bump. This increases the mutual capacitance between the first and third bumps, thereby partially or completely balancing the crosstalk caused by mutual capacitance between the first and second metal lines, and the crosstalk caused by mutual inductance between the first and second metal lines. This reduces or eliminates far-end crosstalk of the chip interconnect signals transmitted between the first and third metal lines, contributing to improved chip package performance.

[0012] In conjunction with the first aspect, in one possible implementation, multiple bumps are arranged along a first direction, and multiple bumps are arranged along a second direction. The first direction and the second direction intersect. Any two bumps among the multiple bumps arranged along the first direction are designated as the first bump and the second bump, and any two bumps among the multiple bumps arranged along the second direction are designated as the first bump and the third bump.

[0013] In this implementation, the second and third bumps are located on different sides of the first bump. For example, if the first segment is adjacent to the second bump, increasing the mutual capacitance between the first and second bumps can reduce the mutual capacitance between bumps arranged along the first direction, thereby reducing far-end crosstalk between chip interconnect signals transmitted by bumps arranged along the first direction. Similarly, if the second segment is adjacent to the third bump, increasing the mutual capacitance between the first and third bumps can reduce the mutual capacitance between bumps arranged along the second direction, thereby reducing far-end crosstalk between chip interconnect signals transmitted by bumps arranged along the second direction. Therefore, this implementation can reduce far-end crosstalk between chip interconnect signals transmitted by bumps arranged in different directions, more comprehensively ensuring the transmission quality of chip interconnect signals, and improving the total interconnect bandwidth between chips, thus improving the performance of the chip packaging structure.

[0014] In conjunction with the first aspect, in one possible implementation, the first bump is adjacent to the second bump. The second bump is adjacent to the third bump.

[0015] In this implementation, the second bump and the third bump are adjacent bumps located on different sides of the first bump. This reduces the mutual capacitance between adjacent bumps arranged along the first or second direction. The metal lines connected to the adjacent bumps are also adjacent, which facilitates the avoidance between the metal lines and makes the wiring of the metal lines easier. This helps to further improve the integration of the chip packaging structure and thus improve the performance of the chip packaging structure.

[0016] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes a fourth metal line. The fourth metal line is insulated relative to a plurality of bumps. The fourth metal line has a third segment and a fourth segment connected to each other. The third segment is adjacent to and spaced from the first bump on the side of the first bump away from the first chip, and the fourth segment is adjacent to and spaced from the second bump on the side of the second bump away from the first chip.

[0017] In this implementation, the third segment is located on the side of the first bump away from the first chip, and the third segment has mutual capacitance with the first bump. The fourth segment is located on the side of the second bump away from the first chip, and the fourth segment has mutual capacitance with the second bump. Connecting the third and fourth segments increases the mutual capacitance between the first and second bumps. The first metal line is connected to the first bump, and the second metal line is connected to the second bump. This partially or completely balances the crosstalk caused by mutual capacitance and mutual inductance between the first and second metal lines, reducing or eliminating far-end crosstalk between the chip interconnect signals transmitted by the first and third metal lines. This ensures the transmission quality of the chip interconnect signals while reducing the design gap of the interconnect traces, improving the integration of the chip package structure, and thus increasing the total interconnect bandwidth between chips within the same size. Therefore, the performance of the chip package structure is improved.

[0018] In conjunction with the first aspect, in one possible implementation, a plurality of bumps are arranged along a first direction, and a plurality of bumps are arranged along a second direction. The first direction and the second direction intersect. The plurality of bumps also include a third bump. A second bump is adjacent to a first bump and located on the side of the first bump along the first direction, and a third bump is adjacent to a first bump and located on the side of the first bump along the second direction. The chip package structure also includes a third metal line. The two ends of the third metal line are respectively connected to the third bump and the second chip. At least a portion of the third metal line is adjacent to at least a portion of the first metal line. A fourth metal line also has a fifth sub-segment, which is connected to the third sub-segment. The fifth sub-segment is adjacent to the side of the third bump away from the first chip and is spaced apart from the third bump.

[0019] In this implementation, the fifth segment is adjacent to the third bump on the side furthest from the first chip and is spaced apart from the third bump. Combined with the above implementation, the third segment and the first bump have mutual capacitance, and the connection between the third segment and the fifth segment increases the mutual capacitance between the first and third bumps. This partially or completely balances the crosstalk caused by mutual capacitance between the first and second metal lines, and the crosstalk caused by mutual inductance between the first and second metal lines, reducing or eliminating far-end crosstalk between the chip interconnect signals transmitted by the first and third metal lines. In this implementation, for arrayed bumps, far-end crosstalk between chip interconnect signals transmitted by bumps arranged in different directions can be reduced. While ensuring the transmission quality of chip interconnect signals, the design gap of interconnect traces is reduced, improving the integration of the chip package structure. This increases the total interconnect bandwidth between chips within the same size, thereby improving the performance of the chip package structure.

[0020] In conjunction with the first aspect, in one possible implementation, the first metal line further has a sixth sub-segment. The two ends of the sixth sub-segment are connected to the first sub-segment and the second chip, respectively. Along the direction from the first chip toward the bump, at least a portion of the sixth sub-segment overlaps with at least a portion of the fourth metal line and is spaced apart.

[0021] In this implementation, in the direction of the first chip toward the first bump, the first metal line can avoid the fourth metal line that overlaps with the sixth sub-segment, so that the first metal line and the fourth metal line exist simultaneously, so that the first metal line and the fourth metal line can play the role of reducing far-end crosstalk between chip interconnect signals in a synchronized manner, and through the spacing relationship between the first metal line and the fourth metal line, the fourth metal line is prevented from having an adverse effect on the chip interconnection function implemented by the first metal line.

[0022] In conjunction with the first aspect, in one possible implementation, any one of the first, second, third, fourth, and fifth sub-segments is a straight line segment.

[0023] In this implementation, the sub-segments of the metal line adjacent to the bump (including the first sub-segment, the second sub-segment, the third sub-segment, the fourth sub-segment, and the fifth sub-segment) are set as straight segments. The straight segments obstruct less of the surface of the bump away from the chip, thereby helping to reserve space for the connection between the bump and other components.

[0024] In conjunction with the first aspect, in one possible implementation, any one of the first, second, third, fourth, and fifth sub-segments includes a zigzag or curved line segment.

[0025] In this implementation, the sub-segment of the metal line adjacent to the bump is set as a bent segment or a curved segment. The bent segment or curved segment can have a greater length in a limited space. The larger the length of the sub-segment of the metal line adjacent to the bump, the stronger the capacitive coupling between the metal line and the bump, thereby further improving the mutual capacitance between the bumps and strengthening the elimination of far-end crosstalk of the chip interconnect signal, which in turn helps to further improve the performance of the chip packaging structure.

[0026] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes an interconnect layer. The first chip and the second chip are located on the same side of the interconnect layer and arranged along its extension direction. A first metal line is disposed in the interconnect layer with both ends exposed, and a second metal line is disposed in the interconnect layer with both ends exposed.

[0027] In this implementation, the chip packaging structure uses an interposer layer to encapsulate the interconnect traces of the chip. Furthermore, the first chip and the second chip are arranged along the extension direction of the interposer layer, thereby enabling 2.5D packaging. This allows for the integration of more pins within a limited size, further improving the integration and performance of the chip packaging structure.

[0028] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes a fourth bump and a fifth bump. The fourth bump and the fifth bump are connected to the second chip. Both ends of the first metal line are connected to the first bump and the fourth bump, respectively, and both ends of the second metal line are connected to the second bump and the fifth bump, respectively. A portion of the second metal line is also adjacent to the side of the fourth bump away from the second chip and is spaced apart from the fourth bump.

[0029] In this implementation, since the segments in the second metal line are spaced apart on the side of the fourth bump away from the second chip, capacitive coupling exists between the second metal line and the fourth bump. This significantly increases the mutual capacitance between the fourth and fifth bumps. The capacitive coupling current and the inductive coupling current are superimposed in opposite directions. Therefore, if the second chip is the signal transmitter and the first chip is the signal receiver, the crosstalk caused by the mutual capacitance between the first and second metal lines, and the crosstalk caused by the mutual inductance between the first and second metal lines, can be partially or completely balanced, thereby reducing or eliminating far-end crosstalk of the chip interconnect signals. Furthermore, when combined with the above implementation, this implementation can further ensure the transmission quality of chip interconnect signals transmitted between chips, reduce the design gap of interconnect traces, save wiring resources, achieve higher density chip interconnects, and balance the integration of the chip package structure and signal transmission quality, further improving the performance of the chip package structure at low cost and high efficiency.

[0030] Secondly, embodiments of this application provide yet another chip packaging structure, which includes a first chip, a second chip, a first metal line, a second metal line, a fourth metal line, and a plurality of bumps. The plurality of bumps are connected to the first chip, and the plurality of bumps include a first bump and a second bump. Both ends of the first metal line are connected to the first bump and the second chip, respectively. Both ends of the second metal line are connected to the second bump and the second chip, respectively. At least a portion of the second metal line is adjacent to at least a portion of the first metal line. The fourth metal line is insulated relative to the plurality of bumps. The fourth metal line has a third sub-segment and a fourth sub-segment connected together. The third sub-segment is adjacent to the side of the first bump away from the first chip and is spaced apart from the first bump; the fourth sub-segment is adjacent to the side of the second bump away from the first chip and is spaced apart from the second bump.

[0031] In some embodiments of the second aspect, the chip packaging structure provided includes a third segment located on the side of the first bump away from the first chip, with mutual capacitance between the third segment and the first bump; and a fourth segment located on the side of the second bump away from the first chip, with mutual capacitance between the fourth segment and the second bump. The connection between the third and fourth segments increases the mutual capacitance between the first and second bumps. The first metal line is connected to the first bump, and the second metal line is connected to the second bump. This allows for a partial or complete balance between the two types of crosstalk caused by mutual capacitance and mutual inductance, reducing or eliminating far-end crosstalk between the chip interconnect signals transmitted by the first and third metal lines. This ensures the transmission quality of the chip interconnect signals while reducing the design gap of the interconnect traces, improving the integration of the chip packaging structure, and thus increasing the total interconnect bandwidth between chips within the same size. Ultimately, this improves the performance of the chip packaging structure.

[0032] In conjunction with the second aspect, in one possible implementation, multiple bumps are arranged along a first direction, and multiple bumps are arranged along a second direction. The first direction and the second direction intersect. The multiple bumps also include a third bump. The second bump is adjacent to the first bump and located on the side of the first bump along the first direction, and the third bump is adjacent to the first bump and located on the side of the first bump along the second direction. The fourth metal line also has a fifth sub-segment, which is connected to the third sub-segment. The fifth sub-segment is adjacent to the third bump on the side away from the first chip and is spaced apart from the third bump.

[0033] In this implementation, the fifth segment is located on the side of the third bump furthest from the first chip, and the fifth segment and the third bump are mutually compliant. Combined with the above implementation, the mutual compliance between the third segment and the first bump, and the connection between the third segment and the fifth segment, increases the mutual compliance between the first and third bumps. This partially or completely balances the crosstalk caused by the mutual compliance between the first and second metal lines, and the crosstalk caused by the mutual inductance between the first and second metal lines. It reduces or eliminates far-end crosstalk between the chip interconnect signals transmitted by the first and third metal lines, ensuring the transmission quality of the chip interconnect signals while reducing the design gap of the interconnect traces and improving the integration of the chip package structure. This increases the total interconnect bandwidth between chips within the same size, thereby improving the performance of the chip package structure.

[0034] Thirdly, embodiments of this application provide an electronic device, which includes a circuit board and the chip packaging structure described in the above embodiments. The chip packaging structure is connected to the circuit board.

[0035] The technical effects of the design approach in the third aspect can be seen in the technical effects of different design approaches in the first or second aspect, and will not be repeated here. Attached Figure Description

[0036] Figure 1 is a top view of a chip packaging structure provided in an embodiment of this application;

[0037] Figure 2 is a cross-sectional view along the FF' direction of the chip packaging structure provided in the embodiment shown in Figure 1;

[0038] Figure 3 is another cross-sectional view of the chip packaging structure provided in the embodiment shown in Figure 1 along the FF' direction;

[0039] Figure 4 is a side view of a chip packaging structure provided in an embodiment of this application;

[0040] Figure 5 is a bottom view of a chip packaging structure provided in an embodiment of this application;

[0041] Figure 6 is a bottom-view perspective of the metal lines of the chip packaging structure shown in Figure 4.

[0042] Figure 7 is a side perspective view of the metal wire shown in Figure 4;

[0043] Figure 8 is a top-view perspective of the metal wire shown in Figure 4;

[0044] Figure 9 is a diagram of the coupling current on the metal lines shown in Figures 6 to 8;

[0045] Figure 10 is the equivalent circuit diagram of the coupling current shown in Figure 9;

[0046] Figure 11 is a frequency domain crosstalk curve provided in an embodiment of this application;

[0047] Figure 12 is a pulse signal diagram provided in an embodiment of this application;

[0048] Figure 13 is a time-domain crosstalk curve provided in an embodiment of this application;

[0049] Figure 14 is a bottom view of a metal wire provided in an embodiment of this application;

[0050] Figure 15 is a bottom view of another type of metal wire provided in an embodiment of this application;

[0051] Figure 16 is a top-view perspective view of the metal wire shown in Figure 15;

[0052] Figure 17 is a perspective view of the metal wire described in Figure 16 from the bottom after it has been flipped over;

[0053] Figure 18 is a structural diagram of a metal wire provided in an embodiment of this application;

[0054] Figure 19 is another structural diagram of the metal wire provided in the embodiment of this application.

[0055] Explanation of reference numerals in the attached drawings: 1000, electronic device; 100, chip package structure; 200, screen; 300, mid-frame; 400, back cover; 500, circuit board; 600... Camera; 1. Adapter layer; 2. Encapsulation layer; 3. Bridging layer; 4. Local bridging area; 10. Chip; 11. First chip; 12. Second chip; 20. Bump; 21. First bump; 22. Second bump; 23. Third bump; 24. Fourth bump; 25. Fifth bump; 30. Metal wire; 31. First metal wire; 32. Second metal wire; 33. Third metal wire; 34. Fourth metal wire; 311. First segment; 321. Second segment; 341. Third segment; 342. Fourth segment; 343. Fifth segment; 312. Sixth segment; X, First direction; Y, Second direction; Z, Third direction; 210. First metal disk; 220. Second metal disk; 211. First metal pillar. Detailed Implementation

[0056] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0057] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] Unless otherwise specified, "at least part" includes two possibilities: a part or all.

[0059] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0060] In describing some embodiments, the term "connection" and its derivative expressions are used. The term "connection" should be interpreted broadly; for example, "connection" can be an electrical connection or a structural connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0061] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0062] In this application embodiment, the terms "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts used for description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts shown do not reflect actual dimensional proportions. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, exemplary embodiments should not be construed as limited to the shape of the areas shown in this application, but rather include shape deviations caused, for example, by manufacturing processes.

[0063] In the embodiments of this application, "far-end crosstalk" refers to a concept relative to "near-end" in chip interconnection relationships. For example, in a chip package structure, a first chip and a second chip are interconnected. If the first chip is considered the near-end in the chip interconnection relationship, then the second chip is considered the far-end. For example, far-end crosstalk of the first chip can refer to crosstalk noise that occurs at the location where the second chip receives the signal during the transmission of chip interconnection signals from the first chip to the second chip.

[0064] This application provides an electronic device, which includes a circuit board and a chip package structure. The chip package structure is connected to the circuit board.

[0065] The aforementioned electronic devices include, but are not limited to, electronic devices in the fields of information technology (IT) and communications technology (CT), such as switches, routers, base stations, supercomputing devices, artificial intelligence devices, servers, optical communication devices, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, laptops, in-vehicle devices, wearable devices, augmented reality (AR) glasses, AR headsets, virtual reality (VR) glasses, or VR headsets, and other devices that require data processing / storage / transmission / reception. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0066] Taking a switch as an example, the circuit board can be the motherboard of the switch, and the chip package structure can be the switching chip.

[0067] In this embodiment, the chip package structure can also be referred to as an integrated circuit. The chip package structure is disposed on a circuit board and electrically connected to the circuit board. For example, the chip package structure can be electrically connected to the circuit board through a ball grid array (BGA) or multiple arrays of bumps on the chip package structure, thereby enabling the chip package structure to transmit signals with other devices on the circuit board. For example, the bumps in this embodiment can be selected as micro bumps. Since the material of the bumps is usually copper, the bumps can also be copper pillar bumps (CPB).

[0068] The aforementioned circuit board can be a printed circuit board (PCB), such as a rigid circuit board or a flexible circuit board. The number of chip package structures connected to the circuit board can be one, two, or more, and this application embodiment does not limit this.

[0069] The above embodiments specifically illustrate the application of this chip packaging structure integrated into electronic devices. In fact, the chip packaging structure provided in this application can also be used independently of electronic devices; detailed implementation methods will be described below.

[0070] Figure 1 is a top view of a chip packaging structure provided in an embodiment of this application. Figure 2 is a cross-sectional view of the chip packaging structure provided in the embodiment shown in Figure 1 along the FF' direction, and Figure 3 is another cross-sectional view of the chip packaging structure provided in the embodiment shown in Figure 1 along the FF' direction.

[0071] As shown in Figure 1, in this embodiment of the application, the chip package structure 100 can employ chip-to-chip technology, that is, the chip package structure 100 includes multiple interconnected chips 10. Chip interconnect signals are transmitted between the chips 10. The chip interconnect signals can be transmitted at high speeds, for example, the transmission rate of the chip interconnect signals can be as high as 10Gbps or even higher.

[0072] In some optional embodiments, the chip package structure 100 may employ 2.5D advanced packaging to package multiple chips together. For example, as shown in FIG1, multiple chips 10 are arranged along the extension direction of the circuit board 500. For instance, the multiple chips 10 may be arranged in one or more rows. As another example, the multiple chips 10 may be arranged in an array.

[0073] As shown in Figure 2, in some optional embodiments, the chip package structure 100 can adopt an interposer package form.

[0074] In this embodiment, the chip package structure 100 includes an adapter layer 1, a plurality of chips 10, and a plurality of metal lines 30. The plurality of chips 10 are located on the same side of the adapter layer 1 and are arranged along the extending direction of the adapter layer 1. The plurality of metal lines 30 are disposed in the adapter layer 1, and both ends of each metal line 30 are exposed in the adapter layer 1.

[0075] As shown in Figure 2, in this embodiment, the chip package structure 100 further includes a plurality of bumps 20. Any one of the plurality of chips 10 is connected to one end of the metal line 30 through a bump 20 disposed on one side of the chip, and another chip 10 is connected to the other end of the metal line 30 through a bump 20 disposed on one side of the chip, thereby achieving interconnection of the chips 10 through the adapter layer 1.

[0076] In the above embodiment, the chip package structure 100 uses the transition layer 1 to encapsulate the interconnect traces of the chip 10. Furthermore, the chips 10 are arranged along the extension direction of the transition layer 1, and traces are routed within the transition layer 1 to achieve interconnection between the chips 10. Therefore, the above embodiment can achieve 2.5D packaging of the chip 10. 2.5D packaging allows for the integration of more pins within a limited size, improving the integration density and performance of the chip package structure 100.

[0077] In some alternative implementations, transition layer 1 may be replaced by a bridging layer.

[0078] As shown in Figure 3, in some optional embodiments, the chip package structure 100 can also adopt a bridge die package form. In this embodiment, the chip package structure 100 includes a bridging layer 3, a plurality of chips 10, a plurality of bumps 20, and a plurality of metal lines 30. The bridging layer 3 has a partial bridging region 4, and the metal lines 30 are disposed in the partial bridging region 4. In the partial bridging region 4, any one of the plurality of chips 10 is connected to one end of the metal line 30 through a bump 20 disposed on one side of the chip, and another chip 10 is connected to the other end of the metal line 30 through a bump 20 disposed on one side of the chip, thereby achieving interconnection of the chips 10 through the partial bridging region 4.

[0079] It is understandable that Figure 3 uses the extension direction of the circuit board 500 as a horizontal plane. For the sake of convenience in showing multiple metal lines 30, the metal lines 30 in Figure 3 are not on the same horizontal plane. In reality, multiple metal lines 30 can be arranged on the same horizontal plane.

[0080] In the above examples, both the transition package and the bridging package can use silicon-based materials as the packaging material. For example, the substrate of the transition layer 1 can be a silicon-based material, and the substrate of the local bridging region 4 can also be a silicon-based material.

[0081] In the embodiments of this application, chip 10 can be various chips or chips that need to be interconnected in a package, such as central processing unit (CPU) chips, graphics processing unit (GPU) chips, high bandwidth memory (HBM) chips, neural processing unit (NPU) chips, etc.

[0082] As shown in Figure 2 or Figure 3, in some optional embodiments, the chip packaging structure 100 may further include a packaging layer 2.

[0083] As shown in Figure 2, in some examples, the package layer 2 is located on the side of the adapter layer 1 away from the chip and is connected to the adapter layer 1 by an array of solder balls or multiple bumps.

[0084] As shown in Figure 3, in some other examples, the package layer 2 is located on the side of the bridging layer 3 away from the chip and is connected to the bridging layer 3 by an array of solder balls or multiple bumps.

[0085] In some implementation examples, the chip package structure 100 can be connected to the circuit board 500 via the package layer 2. For example, the package layer 2 is connected to the circuit board 500 via an array of solder balls or multiple bumps. Exemplarily, the package layer 2 can be made of conventional packaging materials, such as polymer plastics or ceramics.

[0086] As shown in Figure 2 or Figure 3, in the chip packaging structure 100 of the above embodiment, in order to enable the interconnection of numerous signals between chips 10 using metal lines 30, the arrangement density of metal lines 30 is often very high, resulting in relatively large far-end crosstalk between the chip interconnection signals transmitted by the metal lines 30. Specifically, this process involves inductive coupling, also known as mutual inductance, between adjacent metal lines 30. The stronger the mutual inductance between metal lines 30, the greater the far-end interference to the chip interconnection signals transmitted between them.

[0087] Related technologies have proposed several solutions to eliminate far-end crosstalk, mainly by increasing the spacing of the metal lines 30 or adding circuits to cancel far-end crosstalk. However, these solutions all occupy more wiring space, reduce the integration density of the chip package structure 100, and are detrimental to the performance improvement of the chip package structure 100. Furthermore, adding additional circuits to cancel far-end crosstalk also increases the power consumption and manufacturing cost of the chip package structure 100.

[0088] Figures 4 and 5 are further structural diagrams of the chip package structure 100 provided in the embodiments of this application. Figure 4 is a side view of the chip package structure 100, and Figure 5 is a bottom view of the chip package structure 100.

[0089] In view of this, this application provides a chip packaging structure 100, as shown in FIG4. The chip packaging structure 100 includes multiple chips 10, multiple bumps 20 and multiple metal lines 30.

[0090] It is understandable that Figure 4 uses the extension direction of the circuit board 500 as a horizontal plane. For ease of showing the first metal line 31 and the second metal line 32, the first metal line 31 and the second metal line 32 in Figure 4 are not on the same horizontal plane. In reality, the first metal line 31 and the second metal line can be set on the same horizontal plane.

[0091] In some alternative embodiments, the material of the metal wire 30 may be the same as the material of the bump 20. For example, the material of the metal wire 30 may include copper.

[0092] As shown in Figure 5, the plurality of chips 10 include a first chip 11 and a second chip 12, and the plurality of bumps 20 include a first bump 21 and a second bump 22. The plurality of metal lines 30 include a first metal line 31 and a second metal line 32.

[0093] In the embodiments of this application, unless otherwise specified, the same metal wire 30 is a continuous conductor, or in other words, the two ends of the same metal wire 30 are electrically connected.

[0094] In some optional embodiments, the first chip 11 and the second chip 12 are located on the same side of the transition layer 1 and arranged along the extending direction of the transition layer 1. A first metal line 31 is disposed in the transition layer 1 with both ends exposed, and a second metal line 32 is disposed in the transition layer 1 with both ends exposed. This enables 2.5D packaging, which helps improve the integration and performance of the chip package structure 100.

[0095] As shown in Figure 5, in this embodiment of the application, both the first bump 21 and the second bump 22 are connected to the first chip 11. The chip package structure 100 also includes a fourth bump 24 and a fifth bump 25, both of which are connected to the second chip 12.

[0096] As shown in Figure 5, the two ends of the first metal line 31 are connected to the first bump 21 and the fourth bump 24, respectively. Since the first bump 21 is connected to the first chip 11 and the fourth bump 24 is connected to the second chip 12, the first metal line 31 can realize the signal interconnection between the first chip 11 and the second chip 12.

[0097] In some alternative embodiments, bump 20 has metal pillars and a metal disk, with the metal disk located on the side of the metal pillars away from chip 10. The metal disk is used to implement advanced packaging and is therefore also referred to as an AP disk.

[0098] As shown in Figure 4, for example, the first bump 21 has a first metal disk 210 and a first metal post 211, with the first metal disk 210 located on the side of the first metal post 211 away from the first chip 11. The first bump 21 is connected to the first metal line 31 through the first metal disk 210 at its end.

[0099] As shown in Figure 5, the two ends of the second metal line 32 are connected to the second bump 22 and the fifth bump 25, respectively. Since the second bump 22 is connected to the first chip 11 and the fifth bump 25 is connected to the second chip 12, the second metal line 32 can also realize the signal interconnection between the first chip 11 and the second chip 12.

[0100] As shown in Figure 5, in this embodiment of the application, at least a portion of the second metal line 32 is adjacent to at least a portion of the first metal line 31. Exemplarily, the first metal line 31 and the second metal line 32 are insulated from each other, and at least a portion of the second metal line 32 is arranged parallel to at least a portion of the first metal line 31. For example, the portions of the second metal line 32 and the first metal line 31 arranged parallel to each other are spaced equidistant from the first chip 11 or the second chip 12, to achieve in-layer wiring in the stacked structure of the chip package structure 100.

[0101] In the above embodiments, the first metal line 31 connects the first bump 21 and the fourth bump 24. The first bump 21 is connected to the first chip 11, and the fourth bump 24 is connected to the second chip 12. Therefore, the first metal line 31 can interconnect the first chip 11 and the second chip 12. Similarly, the second metal line 32 can also interconnect the first chip 11 and the second chip 12. The adjacent arrangement of the first metal line 31 and the second metal line 32 helps to reduce the packaging area occupied by the metal line 30 and improve the integration density of the chip package structure 100.

[0102] Figures 6 to 8 are perspective views of the metal lines of the chip package structure 100 shown in Figure 4. Figure 6 mainly shows the bottom of the bump 20 and the metal line 30, Figure 7 mainly shows the side of the bump 20 and the metal line 30, and Figure 8 mainly shows the top of the bump 20 and the metal line 30.

[0103] For example, the "bottom" view refers to the view formed at the end where the chip package structure 100 is connected to the circuit board 500, and the "top" view refers to the view formed at the end of the chip package structure 100 away from the circuit board 500.

[0104] As shown in Figure 6, the first metal line 31 has a first segment 311, which is adjacent to the side of the second bump 22 away from the first chip 11, and the first segment 311 and the second bump 22 are spaced apart. Alternatively, the first segment 311 is adjacent to the end of the second bump 22 away from the first chip 11, and the first segment 311 and the second bump 22 are spaced apart.

[0105] In some alternative embodiments, at least a portion of the orthographic projection of the first segment 311 on the encapsulation layer 2 overlaps with at least a portion of the orthographic projection of the second bump 22 on the encapsulation layer 2; or, at least a portion of the orthographic projection of the first segment 311 on the circuit board 500 overlaps with at least a portion of the orthographic projection of the second bump 22 on the circuit board 500; or, at least a portion of the orthographic projection of the first segment 311 on a preset plane overlaps with at least a portion of the orthographic projection of the second bump 22 on a preset plane.

[0106] The preset plane extends along the first direction X and the second direction Y, or in other words, the normal direction of the preset plane is the third direction Z. For example, the first direction X and the second direction Y are the directions in which the chips 10 are arranged, and the third direction Z is the direction in which the bumps 20 face the chips 10 or the thickness direction of the transition layer 1.

[0107] For example, the length of the first segment 311 is not less than a preset value, and the orthographic projection of the first segment 311 on the preset plane falls into the orthographic projection of the second protrusion 22 on the preset plane, thereby enhancing the mutual compatibility effect between the first segment 311 and the second protrusion 22. For example, the preset value is equal to the end dimension of the second protrusion 22. For example, if the end of the second protrusion 22 is a square, the preset value is the side length of the square.

[0108] As shown in Figure 6, in some optional embodiments, the first metal line 31 is connected to the first metal disk 210 at the end of the first bump 21, and the first sub-segment 311 is adjacent to the side of the first metal disk 210 away from the first chip 11 and is spaced apart from the first metal disk 210.

[0109] In some examples, along the arrangement direction of the multiple bumps 20 or along the arrangement direction of the multiple chips 10, the area of ​​the metal disk of the bump 20 is larger than the radial area of ​​the metal pillar. Therefore, by increasing the area of ​​the end of the bump 20 away from the chip 10, the length of the line segment adjacent to the bump 20 of the metal line 30 can be increased, thereby helping to enhance the mutual capacitance between the bump 20 and the metal line 30. Exemplarily, the shape of the metal disk and the radial cross-sectional shape of the metal pillar can be the same or different. For example, the metal disk can be square, and the metal pillar can be cylindrical.

[0110] As shown in Figure 7, in some optional embodiments, the distance between the first segment 311 and the second protrusion 22 is always equal as the first segment 311 extends to maintain mutual compatibility stability. In some examples, the distance between the first segment 311 and the second protrusion 22 is less than 1 μm and greater than 0.

[0111] As shown in Figure 8, in some optional embodiments, the first metal line 31 extends from the end connected to the first chip 11 to the end connected to the second chip 12. During the extension of the first metal line 31, the first metal line 31 can first extend into a first segment 311 adjacent to the second bump 22, and then extend to be adjacent to the second metal line 32. For example, if the first chip 11 is the signal transmitting end and the second chip 12 is the signal receiving end, the capacitive coupling current generated on the first metal line 31 flows from the first segment 311 to the second chip 12, and the inductive coupling current generated by the first metal line 31 and the second metal line 32 flows to the first chip 11. The total coupling current flowing to the second chip 12 is the difference between the capacitive coupling current and the inductive coupling current.

[0112] This application embodiment compensates for the inductive coupling current between metal lines 30 by increasing the capacitive coupling current on the metal line 30, thereby reducing or avoiding distortion of chip interconnect signals without increasing the design gap between metal lines 30 or adding additional compensation circuits.

[0113] Figure 9 shows the coupling current diagram on the metal lines shown in Figures 6 to 8. Figure 10 is the equivalent circuit diagram of the coupling current shown in Figure 9.

[0114] As shown in Figure 9, taking the far-end crosstalk caused by the first metal line 31 to the second metal line 32 as an example, the signal transmitting end M1 transmits the chip interconnect signal T1 to the signal receiving end N1 through the first metal line 31.

[0115] In this configuration, the signal transmitter M1 can be considered the near end, and the signal receiver N1 can be considered the far end. For example, the first chip 11 is the signal transmitter M1, and the second chip 12 is the signal receiver N1.

[0116] As shown in Figure 9, the second metal line 32 has mutual inductance with the first metal line 31 due to their proximity. The second metal line 32 has an inductive coupling current A1 along the signal receiving end N1 toward the signal transmitting end M1. The inductive coupling current A1 is opposite in direction to the current of the chip interconnect signal T2 transmitted from the signal transmitting end M1 to the signal receiving end N1 on the second metal line 32. In related technologies, the capacitive coupling current A2 transmitted from the signal transmitting end M1 to the signal receiving end N1 on the second metal line 32 is opposite in direction to the inductive coupling current A1. There is a difference between the inductive coupling current A1 and the capacitive coupling current A2. For example, the inductive coupling current A1 is greater than the capacitive coupling current A2. This means that the crosstalk caused by the mutual inductance between the first metal line 31 and the second metal line 32 will be greater than the crosstalk caused by the mutual capacitance. The imbalance of the two types of crosstalk will have a negative impact on the chip interconnect signal T2.

[0117] As shown in Figure 10, if the first metal line 31 is taken as the attack line, the calculation method of the far-end crosstalk FEXT on the second metal line 32 can be referred to formula (1):

[0118] Among them, L s The self-inductance per unit length of the metal wire is 30, L m It is the sum of the mutual inductance between the first metal wire 31 and the second metal wire 32 per unit length, and the mutual inductance between the first metal wire 31 and the second protrusion 22, C g It is the capacitance to ground per unit length of the 30mm metal wire, C. mIt is the sum of the mutual capacitance between the first metal line 31 and the second metal line 32 per unit length, and the mutual capacitance between the first metal line 31 and the second bump 22. Tr is the rise time of the attack signal from the first metal line 31 to the second metal line 32. Len is the coupling length between the metal lines 30, and vp is the propagation speed of the attack signal. The coupling length between the metal lines can be determined based on the lengths of adjacent segments of the first metal line 31 and the second metal line 32.

[0119] From formula (1), it can be concluded that, with the coupling length between metal lines 30 and the rise time Tr of the attack signal remaining constant, the crosstalk caused by the mutual capacitance between the first metal line 31 and the second metal line 32 is weaker than the crosstalk caused by the mutual inductance between the first metal line 31 and the second metal line 32. This crosstalk imbalance will cause far-end crosstalk (FEXT) in the chip interconnect signal. Therefore, by increasing the total mutual capacitance C per unit length... m Or reduce the total mutual inductance per unit length L m Both can reduce far-end crosstalk (FEXT). However, to ensure the integration density of the chip package structure 100, the design gap of the metal lines 30 cannot be arbitrarily increased, and the mutual inductance between the first metal line 31 and the second metal line 32 is difficult to change. Therefore, in this embodiment, increasing the mutual capacitance between the first metal line 31 and the first bump 21 is equivalent to increasing the mutual capacitance between the first bump 21 and the second bump 22, or in other words, the total mutual capacitance C... m This reduces far-end crosstalk (FEXT).

[0120] By increasing the mutual capacitance between the first metal line 31 and the second bump 22, as shown in Figure 9, the capacitive coupling current A2 can be increased, which can absorb or compensate for the inductive coupling current A1, reducing far-end crosstalk between chip interconnect signals and improving the signal-to-ground ratio of the bump. Therefore, the quality of chip interconnect signals can be guaranteed and the stability of chip interconnect can be improved without adding additional compensation circuitry.

[0121] Figure 11 is a frequency domain crosstalk curve provided in an embodiment of this application.

[0122] As shown in Figure 11, C1 is the frequency domain crosstalk curve of the chip package structure 100 in this embodiment. C2 is the frequency domain crosstalk curve of the chip package structure 100 in the related art. L1 is the insertion loss curve. In the frequency domain, in some examples, when transmitting 10GHz chip interconnect signals, compared with the chip package structure 100 in the related art, the chip package structure 100 in this embodiment significantly reduces frequency domain crosstalk, with a far-end crosstalk improvement of approximately 8dB. Furthermore, when transmitting chip interconnect signals below 30GHz, the insertion loss of the chip package structure 100 in this embodiment shows virtually no deterioration. Therefore, it is also suitable for high-speed chip interconnect scenarios that transmit high-frequency signals.

[0123] Figure 12 is a pulse signal diagram provided in an embodiment of this application. Figure 13 is a time-domain crosstalk curve provided in an embodiment of this application.

[0124] Please refer to Figure 9. If a single pulse signal is injected at the port where the signal transmitting end M1 in Figure 9 is connected to the first metal line 31, the single pulse signal has a single pulse waveform as shown in Figure 12. The first metal line 31 transmits the single pulse signal to the port where the signal receiving end N1 is connected to the first metal line 31. By detecting the far-end crosstalk noise at the port where the signal receiving end N1 is connected to the first metal line 31, the time-domain crosstalk curve of the chip package structure 100 can be obtained.

[0125] As shown in Figure 13, C3 is the time-domain crosstalk curve of the chip packaging structure 100 in this embodiment. C4 is the time-domain crosstalk curve of the chip packaging structure 100 in the related art.

[0126] As shown in Figure 13, in the time domain, in some examples, the peak-to-peak value of the time-domain crosstalk noise of the chip package structure 100 in the related art is higher than the peak-to-peak value of the time-domain crosstalk noise of the chip package structure 100 in the embodiments of this application. For example, the peak-to-peak value of the time-domain crosstalk noise of the chip package structure 100 in the embodiments of this application can be reduced by 67mV compared to the chip package structure 100 in the related art.

[0127] Through the above embodiments, although there is mutual inductance between the first metal line 31 and the second metal line 32, and this mutual inductance can cause far-end crosstalk to the chip interconnect signals, the first segment 311 of the first metal line 31 is spaced apart on the side of the second bump 22 away from the first chip 11. There is capacitive coupling between the first segment 311 and the second bump 22, or in other words, there is mutual capacitance between the first metal line 31 and the second bump 22. This significantly increases the mutual capacitance between the first bump 21 and the second bump 22. The capacitive coupling current and the inductive coupling current are superimposed in opposite directions. Therefore, if the first chip 11 is the signal transmitter and the second chip 12 is the signal receiver, the crosstalk caused by the mutual capacitance between the first metal line 31 and the second metal line 32 is effectively reduced. The crosstalk caused by the mutual inductance between 31 and the second metal line 32 can partially or completely balance the two types of crosstalk caused by mutual inductance and mutual capacitance, thereby reducing or eliminating far-end crosstalk of chip interconnect signals. While ensuring the transmission quality of chip interconnect signals, it can reduce the design gap of interconnect traces, save wiring resources, and achieve higher density chip interconnection. This not only improves the integration of the chip package structure 100, thereby increasing the total interconnect bandwidth between chips within the same size, but also eliminates the need for additional crosstalk compensation circuits, thus achieving a low-cost and efficient performance improvement of the chip package structure 100.

[0128] As shown in Figure 5, in some optional embodiments, the fourth bump 24 and the fifth bump 25 are connected to the second chip 12. The two ends of the first metal line 31 are connected to the first bump 21 and the fourth bump 24, respectively, and the two ends of the second metal line 32 are connected to the second bump 22 and the fifth bump 25, respectively.

[0129] In this embodiment, a portion of the second metal line 32 is also adjacent to the side of the fourth bump 24 away from the second chip 12 and is spaced apart from the fourth bump 24.

[0130] Therefore, since the segments in the second metal line 32 are spaced apart on the side of the fourth bump 24 away from the second chip 12, there is capacitive coupling between the second metal line 32 and the fourth bump 24. This significantly increases the mutual capacitance between the fourth bump 24 and the fifth bump 25. The capacitive coupling current and the inductive coupling current are superimposed in opposite directions. Thus, if the second chip 12 is the signal transmitting end and the first chip 11 is the signal receiving end, the crosstalk caused by the mutual capacitance between the first metal line 31 and the second metal line 32, and the crosstalk caused by the mutual inductance between the first metal line 31 and the second metal line 32, can be partially or completely balanced, thereby reducing or eliminating far-end crosstalk of the chip interconnect signals. Furthermore, when combined with the above embodiments, the embodiments of this application can ensure the transmission quality of chip interconnect signals transmitted between chips, reduce the design gap of interconnect traces, save wiring resources, achieve higher density chip interconnects, and balance the integration of the chip package structure 100 and the signal transmission quality, further improving the performance of the chip package structure 100 at low cost and high efficiency.

[0131] Furthermore, the combination of the above embodiments can also help improve the symmetry of the interconnection design between the first chip 11 and the second chip 12, thereby further reducing the design and manufacturing difficulty of the chip package structure 100 and improving the stability of chip interconnection signal transmission.

[0132] Figure 14 is a bottom view of a metal wire provided in an embodiment of this application.

[0133] As shown in Figure 14, in some optional embodiments, the metal line 30 further includes a third metal line 33, and the plurality of bumps 20 further includes a third bump 23.

[0134] In this embodiment, the two ends of the third metal line 33 are connected to the third bump 23 and the second chip 12, respectively. At least a portion of the third metal line 33 is adjacent to at least a portion of the first metal line 31.

[0135] Thus, the third metal line 33 connects the third bump 23 and the second chip 12, enabling the interconnection of the first chip 11 and the second chip 12. The adjacent proximity of the first metal line 31 and the third metal line 33 helps to reduce the package area occupied by the metal line 30 and improve the integration density of the chip package structure 100.

[0136] In this embodiment, the first metal line 31 further has a second sub-segment 321, which is connected to the first sub-segment 311. The second sub-segment 321 is adjacent to the third bump 23 on the side away from the first chip 11 and is spaced apart from the third bump 23.

[0137] In some alternative embodiments, at least a portion of the orthographic projection of the second segment 321 on the encapsulation layer 2 overlaps with at least a portion of the orthographic projection of the third bump 23 on the encapsulation layer 2; or, at least a portion of the orthographic projection of the second segment 321 on the circuit board 500 overlaps with at least a portion of the orthographic projection of the third bump 23 on the circuit board 500; or, at least a portion of the orthographic projection of the second segment 321 on a preset plane overlaps with at least a portion of the orthographic projection of the third bump 23 on a preset plane.

[0138] In some alternative implementations, the distance between the second segment 321 and the third protrusion 23 is equal everywhere as the second segment 321 extends. In some examples, the distance between the second segment 321 and the third protrusion 23 is less than 1 μm and greater than 0.

[0139] As shown in Figure 14, in some optional embodiments, the end 301 of the metal line 30 used to connect with the second chip 12 can be selected to extend on the same layer as the first sub-segment 311 or the second sub-segment 321, or it can be selected to be set on a different layer from the first sub-segment 311 or the second sub-segment 321. This application embodiment does not limit this.

[0140] Taking the extension of the first metal line 31 as an example, in some examples, the first metal line 31 is set in the transition layer 1. During the extension of the first metal line 31, the first metal line 31 can first extend from the end connected to the first chip 11 to the first sub-segment 311. The first sub-segment 311 extends along the thickness direction of the transition layer 1 through the lower hole provided in the transition layer 1, thereby increasing the distance between the first metal line 31 and the chip 10, and then extends to the end 301 connected to the second chip 12, thereby realizing the avoidance of other lines (such as the fourth metal line) by the first metal line 31.

[0141] In the above embodiments, there is mutual capacitance between the first metal line 31 and the third bump 23, and the first metal line 31 is connected to the first bump 23. This increases the mutual capacitance between the first bump 21 and the third bump 23, thereby compensating for crosstalk caused by mutual inductance between the first metal line 31 and the third metal line 33. Consequently, for crosstalk caused by mutual capacitance between the first metal line 31 and the second metal line 32, and crosstalk caused by mutual inductance between the first metal line 31 and the second metal line 32, a balance between the two types of crosstalk caused by mutual inductance and mutual capacitance can be partially or completely achieved, reducing or eliminating far-end crosstalk of the chip interconnect signals transmitted by the first metal line 31 and the third metal line 33. By reducing the far-end crosstalk of the chip interconnect signals transmitted by the bumps in different directions of the first bump 21, the performance of the chip package structure 100 can be improved more comprehensively.

[0142] As shown in Figure 14, in some optional embodiments, a plurality of protrusions 20 are arranged along a first direction and a second direction Y. The first direction X intersects the second direction Y. Exemplarily, the first direction X and the second direction Y are perpendicular to each other.

[0143] Any two of the multiple protrusions 20 arranged along the first direction X are designated as the first protrusion 21 and the second protrusion 22, and any two of the multiple protrusions 20 arranged along the second direction Y are designated as the first protrusion 21 and the third protrusion 23.

[0144] For example, the second protrusion 22 is located on the side of the first protrusion 21 along the first direction X, and the third protrusion 23 is located on the side of the first protrusion 21 along the second direction Y.

[0145] In the above embodiments, the second bump 22 and the third bump 23 are bumps located on different sides of the first bump 21. The first sub-segment 311 is adjacent to the second bump 22, increasing the mutual capacitance between the first bump 21 and the second bump 22, which can reduce the mutual capacitance between the bumps 20 arranged along the first direction X, thereby reducing the far-end crosstalk between the chip interconnect signals transmitted by the bumps arranged along the first direction X. The second sub-segment 321 is adjacent to the third bump 23, increasing the mutual capacitance between the first bump 21 and the third bump 23, which can reduce the mutual capacitance between the bumps 20 arranged along the second direction Y, thereby reducing the far-end crosstalk between the chip interconnect signals transmitted by the bumps arranged along the second direction Y. Therefore, this embodiment can reduce the far-end crosstalk between the chip interconnect signals transmitted by bumps arranged in different directions, more comprehensively ensure the transmission quality of chip interconnect signals, and improve the total interconnect bandwidth between chips, thereby improving the performance of the chip package structure 100.

[0146] In some optional embodiments, the first protrusion 21 is adjacent to the second protrusion 22, and the second protrusion 22 is adjacent to the third protrusion 23.

[0147] For example, among the plurality of protrusions 20 arranged along the first direction X, the first protrusion 20 and the second protrusion 20 are respectively the first protrusion 21 and the second protrusion 22, the second protrusion 20 and the third protrusion 20 are respectively the first protrusion 21 and the second protrusion 22, and so on.

[0148] For example, among the plurality of protrusions 20 arranged along the second direction Y, the first protrusion 20 and the second protrusion 20 are respectively the first protrusion 21 and the third protrusion 23, the second protrusion 20 and the third protrusion 20 are respectively the first protrusion 21 and the second protrusion 22, and so on.

[0149] Therefore, the second bump 22 and the third bump 23 are adjacent bumps 20 located on different sides of the first bump 21, which can reduce the mutual capacitance between adjacent bumps arranged along the first direction X or the second direction Z. The metal lines 30 connected to the adjacent bumps 20 are also adjacent, which is conducive to the avoidance between the metal lines 30, thereby facilitating the wiring of the metal lines 30. This helps to further improve the integration of the chip packaging structure 100 and realize the performance improvement of the chip packaging structure 100.

[0150] For example, as shown in Figure 14, bump S1 serves as both a first bump 21 and a second bump 22, mutually accommodating with adjacent bumps facing the first direction X and the second direction Y. Bump S1 also serves as a third bump 23, mutually accommodating with adjacent bumps facing away from the first direction X. The double-headed arrows in Figure 14 schematically indicate mutual accommodating bumps 20.

[0151] Therefore, among the multiple bumps 20 arranged in the array, any bump S1 can be mutually compliant with bumps 20 in different directions. Thus, for the chip package structure 100, the far-end crosstalk of chip interconnect signals can be reduced in all directions, thereby further improving the performance of the chip package structure 100.

[0152] As shown in Figure 14, in some optional embodiments, the first sub-segment 311 or the second sub-segment 321 is a straight segment. Thus, by setting the sub-segment of the first metal line 31 adjacent to the bump as a straight segment, the straight segment causes less obstruction to the surface of the bump 20 away from the chip 10, thereby helping to reserve space for the connection between the bump 20 and other components.

[0153] As shown in Figure 14, in some optional embodiments, the first segment 311 extends along the first direction X, and the second segment 321 extends along the first direction X.

[0154] Figure 15 is a bottom view of another type of metal wire provided in an embodiment of this application. Figures 16 and 17 are perspective views of the metal wire shown in Figure 15. For ease of illustration, Figure 16 mainly shows a top perspective view of the protrusion 20 and the metal wire 30. For ease of illustration, Figure 17 is a perspective view of the protrusion 20 and the metal wire 30 in Figure 16 with their bottoms facing upwards after being flipped over.

[0155] As shown in Figure 15, in some optional embodiments, the chip package structure 100 further includes a fourth metal line 34. The fourth metal line 34 is insulated relative to the plurality of bumps 20.

[0156] In some alternative embodiments, the fourth metal line 34 extends parallel to the direction of the bump array 20 and is spaced apart from the bumps 20 as a whole. For example, the fourth metal line 34 can be considered to be suspended relative to the bumps 20.

[0157] As shown in Figure 15, the fourth metal wire 34 has a third sub-segment 341 and a fourth sub-segment 342 that are connected to each other.

[0158] The third sub-segment 341 is adjacent to the first bump 21 on the side away from the first chip 11 and is spaced apart from the first bump 21. The fourth sub-segment 342 is adjacent to the second bump 22 on the side away from the first chip 11 and is spaced apart from the second bump 22.

[0159] In some optional embodiments, the distance between the third segment 341 and the first bump 21 is equal everywhere. In some examples, the distance between the third segment 341 and the first bump 21 is less than 1 μm and greater than 0.

[0160] In some optional embodiments, the distance between the fourth segment 342 and the second bump 22 is always equal. In some examples, the distance between the fourth segment 342 and the second bump 22 is less than 1 μm and greater than 0.

[0161] As shown in Figure 15, in some optional embodiments, at least a portion of the orthographic projection of the third segment 341 on the encapsulation layer 2 overlaps with at least a portion of the orthographic projection of the first bump 21 on the encapsulation layer 2; or, at least a portion of the orthographic projection of the third segment 341 on the circuit board 500 overlaps with at least a portion of the orthographic projection of the first bump 21 on the circuit board 500; or, at least a portion of the orthographic projection of the third segment 341 on a preset plane overlaps with at least a portion of the orthographic projection of the first bump 21 on a preset plane.

[0162] In some alternative embodiments, at least a portion of the orthographic projection of the fourth segment 342 on the encapsulation layer 2 overlaps with at least a portion of the orthographic projection of the second bump 22 on the encapsulation layer 2; or, at least a portion of the orthographic projection of the fourth segment 342 on the circuit board 500 overlaps with at least a portion of the orthographic projection of the second bump 22 on the circuit board 500; or, at least a portion of the orthographic projection of the fourth segment 342 on a preset plane overlaps with at least a portion of the orthographic projection of the second bump 22 on a preset plane.

[0163] In the above embodiments, the third sub-segment 341 is adjacent to the first bump 21 on the side away from the first chip, and the third sub-segment 341 and the first bump 21 are mutually compliant. The fourth sub-segment 342 is adjacent to the second bump 22 on the side away from the first chip, and the fourth sub-segment 342 and the second bump 22 are mutually compliant. The connection between the third sub-segment 341 and the fourth sub-segment 342 can increase the mutual compliance between the first bump 21 and the second bump 22. The first metal line 31 is connected to the first bump 21, and the second metal line is connected to the second bump 22. This allows for a partial or complete balance between the two types of crosstalk caused by mutual capacitance and mutual inductance between the first metal line 31 and the second metal line 32. This reduces or eliminates far-end crosstalk between the chip interconnect signals transmitted by the first metal line 31 and the third metal line 33. While ensuring the transmission quality of the chip interconnect signals, this reduces the design gap of the interconnect traces and improves the integration of the chip package structure 100. As a result, the total interconnect bandwidth between chips is increased within the same size, thereby improving the performance of the chip package structure 100.

[0164] As shown in Figure 15, in some optional embodiments, the fourth metal line 34 cooperates with the first segment 311 in the above embodiment to jointly reduce far-end crosstalk of chip interconnect signals and further improve the performance of chip packaging structure 100.

[0165] For example, the orthographic projection of the first segment 311 on the second protrusion 22 does not overlap with the orthographic projection of the fourth metal line 34 on the second protrusion 22.

[0166] In some alternative embodiments, the first metal line 31 further has a sixth segment 312. The two ends of the sixth segment 312 are connected to the first segment 311 and the second chip 12, respectively.

[0167] In this embodiment, at least a portion of the sixth segment 312 overlaps with at least a portion of the fourth metal line 34 and is spaced apart along the direction of the first chip 11 toward the bump 20. Exemplarily, the direction of the first chip 11 toward the bump 20 is parallel to the third direction Z.

[0168] In some optional embodiments, the distance between the sixth segment 312 and the bump 20 along the direction from the first chip 11 toward the bump 20 is greater than the distance between the fourth metal line 34 and the bump 20. For example, the distance between the sixth segment 312 and the bump 20 is greater than 1 μm.

[0169] In some examples, the first metal line 31 is disposed in the transition layer 1. During the extension of the first metal line 31, the first metal line 31 can first extend from the end connected to the first chip 11 to the first sub-segment 311. The first sub-segment 311 extends along the thickness direction of the transition layer 1 through the lower hole provided in the transition layer 1, thereby increasing the distance between the first metal line 31 and the chip 10, and then extends to the sixth sub-segment 312, thereby realizing the overlap and spacing between the sixth sub-segment 312 and the fourth metal line 34, and realizing the wiring avoidance of the fourth metal line 34.

[0170] Through the above embodiments, in the direction of the first chip 11 toward the first bump 21, the first metal line 31 can avoid the fourth metal line 34 that overlaps with the sixth sub-segment 312, thereby facilitating the wiring of the first metal line 31 and the fourth metal line 34, so that the first metal line 31 and the fourth metal line 34 can simultaneously play the role of reducing far-end crosstalk between chip interconnect signals, and through the spacing relationship between the first metal line 31 and the fourth metal line 34, the fourth metal line 34 is prevented from causing adverse effects on the chip interconnection function achieved by the first metal line 31.

[0171] As shown in Figure 15, in some optional embodiments, a plurality of bumps 20 are arranged in an array. Specifically, the plurality of bumps 20 are arranged along a first direction X, and the plurality of bumps 20 are arranged along a second direction Y. The first direction X and the second direction Y intersect.

[0172] As shown in Figure 15, in some optional embodiments, the first direction X is not perpendicular to the second direction Y.

[0173] As shown in Figure 16, in some optional embodiments, the plurality of protrusions 20 further includes a third protrusion 23. The second protrusion 22 is adjacent to the first protrusion 21 and is located on the side of the first protrusion 21 along the first direction X, and the third protrusion 23 is adjacent to the first protrusion 21 and is located on the side of the first protrusion 21 along the second direction Y.

[0174] As shown in Figure 15, in some optional embodiments, the chip package structure 100 further includes a third metal line 33.

[0175] In this embodiment, the two ends of the third metal line 33 are connected to the third bump 23 and the second chip 12, respectively. At least a portion of the third metal line 33 is adjacent to at least a portion of the first metal line 31.

[0176] As shown in Figure 17, in some optional embodiments, the fourth metal wire 34 also has a fifth sub-segment 343, which is connected to the third sub-segment 341.

[0177] In this embodiment, the fifth segment 343 is adjacent to the end of the third bump 23 that is away from the first chip 11.

[0178] In some alternative implementations, the distance between the fifth segment 343 and the third protrusion 23 is always equal. In some examples, the distance between the fifth segment 343 and the third protrusion 23 is less than 1 μm and greater than 0.

[0179] In some optional embodiments, the fourth metal line 34 is a mesh structure that extends along the first direction X and the second direction Y, so that the fourth metal line 34 can be compatible with the array of bumps 20.

[0180] In some examples, the fourth metal wire 34 encloses multiple closed patterns, and any one of the third sub-segment 341, the fourth sub-segment 342, or the fifth sub-segment 343 can enclose one of the multiple closed patterns.

[0181] In some alternative embodiments, at least a portion of the orthographic projection of the fifth segment 343 on the encapsulation layer 2 overlaps with at least a portion of the orthographic projection of the third bump 23 on the encapsulation layer 2; or, at least a portion of the orthographic projection of the fifth segment 343 on the circuit board 500 overlaps with at least a portion of the orthographic projection of the third bump 23 on the circuit board 500; or, at least a portion of the orthographic projection of the fifth segment 343 on a preset plane overlaps with at least a portion of the orthographic projection of the third bump 23 on a preset plane.

[0182] In the above embodiments, the fifth segment 343 is located on the side of the third bump 23 away from the first chip, and the fifth segment 343 and the third bump 23 have mutual capacitance. In conjunction with the above embodiments, the third segment 341 has mutual capacitance with the first bump 21, and the third segment 341 is connected to the fifth segment 343. This increases the mutual capacitance between the first bump 21 and the third bump 23, thereby partially or completely achieving a balance between the two types of crosstalk caused by mutual capacitance and mutual inductance, reducing or eliminating far-end crosstalk between the chip interconnect signals transmitted by the first metal line 31 and the third metal line 33.

[0183] In this embodiment, for the array of bumps 20, the far-end crosstalk between chip interconnect signals transmitted by bumps 20 arranged in different directions can be reduced. While ensuring the transmission quality of chip interconnect signals, the design gap of interconnect traces can be reduced, and the integration of chip package structure 100 can be improved. Thus, the total interconnect bandwidth between chips 10 can be increased under the same size, thereby improving the performance of chip package structure 100.

[0184] As shown in Figure 17, in some optional embodiments, any one of the third sub-segment 341, the fourth sub-segment 342, and the fifth sub-segment 343 is a straight line segment.

[0185] Therefore, the sub-segment of the fourth metal line 34 adjacent to the bump 20 is set as a straight segment. The straight segment obstructs less of the surface of the bump 20 away from the chip 10, which helps to reserve space for the connection between the bump 20 and other components.

[0186] Figure 18 is a structural diagram of a metal wire provided in an embodiment of this application.

[0187] As shown in Figure 18, in some alternative embodiments, the segment adjacent to the bump 20 of the metal line 30 includes a bent segment. For example, the segment is composed of multiple straight segments forming the bent segment, and the extension directions of the multiple straight segments are not exactly the same.

[0188] As shown in Figure 18, in some examples, the sub-segment of the metal line 30 adjacent to the bump 20 includes three straight line segments.

[0189] Figure 19 is another structural diagram of the metal wire provided in the embodiment of this application.

[0190] As shown in Figure 19, in some examples, the sub-segment of the metal line 30 adjacent to the bump 20 includes five straight line segments.

[0191] In some alternative embodiments, the segment of metal line 30 adjacent to bump 20 includes a curved segment. Exemplarily, the segment of metal line 30 adjacent to bump 20 includes an arc segment. For example, the arc segment may be a circular arc segment.

[0192] In some alternative embodiments, the segments of the metal line 30 adjacent to the bump 20 can also form a closed pattern. Exemplarily, the segments of the metal line 30 adjacent to the bump 20 can also form a rectangle, a circle, or an ellipse, etc.

[0193] In some specific examples, any one of the first sub-segment 311, the second sub-segment 321, the third sub-segment 341, the fourth sub-segment 342, and the fifth sub-segment 343 includes a zigzag or curved line segment.

[0194] Through the above embodiments, the bent or curved line segment can have a greater length in a limited space. The longer the sub-segment length of the metal line 30 arranged adjacent to the bump 20, the stronger the capacitive coupling between the metal line 30 and the bump 20, thereby further improving the mutual capacitance between the bumps 20 and strengthening the elimination of far-end crosstalk of the chip interconnect signal, which in turn helps to further improve the performance of the chip package structure 100.

[0195] As shown in Figure 18 or Figure 19, in some alternative embodiments, the two ends of the segments of the metal wire 30 and the bump 20 extend in the same direction.

[0196] This allows for the maintenance of the regularity of the arrangement and extension of the metal lines 30, reducing the design and manufacturing difficulty of the chip interconnection traces within the chip packaging structure 100.

[0197] In some alternative implementations, the two ends of the segments adjacent to the bump 20 of the metal line 30 extend in different directions. This helps to further increase the length of the segments adjacent to the bump 20 of the metal line 30 while ensuring the flexibility of the chip interconnect routing design.

[0198] As shown in Figure 17, this application embodiment also provides a chip packaging structure 100, which mainly utilizes the fourth metal line 34 to reduce far-end crosstalk of chip interconnect signals.

[0199] In the application embodiment, the chip packaging structure 100 includes a first chip 11, a second chip 12, a first metal line 31, a second metal line 32, a fourth metal line 34, and a plurality of bumps 20.

[0200] In the embodiment of the application, a plurality of bumps 20 are connected to a first chip 11, and the plurality of bumps 20 include a first bump 21 and a second bump 22. The two ends of a first metal line 31 are respectively connected to the first bump 21 and the second chip 12. The two ends of a second metal line 32 are respectively connected to the second bump 22 and the second chip 12. At least a portion of the second metal line 32 is adjacent to at least a portion of the first metal line 31.

[0201] As shown in Figure 17, the fourth metal wire 34 is insulated relative to the plurality of bumps 20. The fourth metal wire 34 has a third sub-segment 341 and a fourth sub-segment 342 connected to each other.

[0202] In the application embodiment, the third sub-segment 341 is adjacent to the side of the first bump 21 away from the first chip 11 and is spaced apart from the first bump 21, and the fourth sub-segment 342 is adjacent to the side of the second bump 22 away from the first chip 11 and is spaced apart from the second bump 22.

[0203] In the above embodiments, the third segment 341 is located on the side of the first bump 21 away from the first chip, and the third segment 341 and the first bump 21 have mutual capacitance. The fourth segment 342 is located on the side of the second bump 22 away from the first chip, and the fourth segment 342 and the second bump 22 have mutual capacitance. The connection between the third segment 341 and the fourth segment 342 can increase the mutual capacitance between the first bump 21 and the second bump 22. The first metal line 31 is connected to the first bump 21, and the second metal line is connected to the second bump 22. This allows for a partial or complete balance between the two types of crosstalk caused by mutual capacitance and mutual inductance between the first metal line 31 and the second metal line 32. This reduces or eliminates far-end crosstalk between the chip interconnect signals transmitted by the first metal line 31 and the third metal line 33. While ensuring the transmission quality of the chip interconnect signals, this reduces the design gap of the interconnect traces and improves the integration of the chip package structure 100. As a result, the total interconnect bandwidth between chips is increased within the same size, thereby improving the performance of the chip package structure 100.

[0204] As shown in Figure 17, in some optional embodiments, a plurality of bumps 20 are arranged along a first direction X and a second direction Y. The first direction X and the second direction Y intersect. The plurality of bumps 20 also include a third bump 23. A second bump 22 is adjacent to a first bump 21 and located on the side of the first bump 21 along the first direction X, and a third bump 23 is adjacent to a first bump 21 and located on the side of the first bump 21 along the second direction Y. The fourth metal wire 34 also has a fifth segment 343, which is connected to the third segment 341.

[0205] In this embodiment, the fifth segment 343 is adjacent to the side of the third bump 23 away from the first chip 11 and is spaced apart from the third bump 23.

[0206] In the above embodiments, the fifth segment 343 is located on the side of the third bump 23 away from the first chip, and the fifth segment 343 and the third bump 23 are mutually compliant. In conjunction with the above embodiments, the third segment 341 is mutually compliant with the first bump 21, and the third segment 341 is connected to the fifth segment 343. This increases the mutual compliance between the first bump 21 and the third bump 23, thereby partially or completely balancing the crosstalk caused by the mutual compliance between the first metal line 31 and the second metal line 32, and the crosstalk caused by the mutual inductance between the first metal line 31 and the second metal line 32. This reduces or eliminates far-end crosstalk between the chip interconnect signals transmitted by the first metal line 31 and the third metal line 33, ensuring a high level of integration in the chip package structure 100 and reducing far-end crosstalk between the chip interconnect signals transmitted by the first metal line 31 and the second metal line 32. This reduces limitations on the scale and integration of interconnect traces, helping to improve the total interconnect bandwidth between chips and the performance of the chip package structure 100.

[0207] This application also provides an electronic device, which includes the chip packaging structure 100 in any of the above embodiments.

[0208] For ease of description, some directional markings are shown in some of the accompanying drawings of the embodiments of this application. For example, the first direction X and the second direction Y are the extension directions of the transition layer 1, and the third direction Z is the thickness direction of the transition layer 1.

[0209] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Furthermore, with the evolution of architectures and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: First chip; Second chip; Multiple bumps are connected to the first chip; the multiple bumps include a first bump and a second bump; A first metal wire, the two ends of which are respectively connected to the first bump and the second chip; A second metal wire, the two ends of which are respectively connected to the second bump and the second chip; at least a portion of the second metal wire is adjacent to at least a portion of the first metal wire; The first metal line has a first sub-segment, which is adjacent to the second bump on the side away from the first chip and is spaced apart from the second bump.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a third metal line, and the plurality of bumps further includes a third bump; The two ends of the third metal wire are respectively connected to the third bump and the second chip; at least a portion of the third metal wire is adjacent to at least a portion of the first metal wire. The first metal line also has a second sub-segment connected to the first sub-segment, the second sub-segment being adjacent to the third bump on the side away from the first chip and spaced apart from the third bump.

3. The chip packaging structure according to claim 2, characterized in that, The plurality of protrusions are arranged along a first direction and the plurality of protrusions are arranged along a second direction; the first direction and the second direction intersect. Any two of the plurality of protrusions arranged along the first direction are designated as the first protrusion and the second protrusion, and any two of the plurality of protrusions arranged along the second direction are designated as the first protrusion and the third protrusion.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that, The first bump is adjacent to the second bump, and the first bump is adjacent to the third bump.

5. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes a fourth metal line; The fourth metal wire is insulated relative to the plurality of bumps; the fourth metal wire has a connected third sub-segment and a fourth sub-segment; The third sub-segment is adjacent to the first bump on the side away from the first chip and is spaced apart from the first bump; the fourth sub-segment is adjacent to the second bump on the side away from the first chip and is spaced apart from the second bump.

6. The chip packaging structure according to claim 5, characterized in that, The plurality of protrusions are arranged along a first direction and along a second direction; the plurality of protrusions further include a third protrusion; the third protrusion is adjacent to the first protrusion and located on the side of the first protrusion along the second direction; the second protrusion is adjacent to the first protrusion and located on the side of the first protrusion along the first direction; The chip packaging structure further includes a third metal line; the two ends of the third metal line are respectively connected to the third bump and the second chip; at least a portion of the third metal line is adjacent to at least a portion of the first metal line. The fourth metal line also has a fifth sub-segment, which is connected to the third sub-segment; the fifth sub-segment is adjacent to the third bump on the side away from the first chip and is spaced apart from the third bump.

7. The chip packaging structure according to claim 6, characterized in that, The first metal line also has a sixth sub-segment; the two ends of the sixth sub-segment are respectively connected to the first sub-segment and the second chip; Along the direction of the first chip toward the bump, at least a portion of the sixth sub-segment overlaps with at least a portion of the fourth metal line and is spaced apart.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that, Any one of the first sub-segment, the second sub-segment, the third sub-segment, the fourth sub-segment, and the fifth sub-segment is a straight line segment; or, Any one of the first sub-segment, the second sub-segment, the third sub-segment, the fourth sub-segment, and the fifth sub-segment includes a zigzag line segment or a curved line segment.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The chip packaging structure also includes an adapter layer; The first chip and the second chip are located on the same side of the adapter layer and are arranged along the extension direction of the adapter layer; the first metal wire is disposed in the adapter layer and its two ends are exposed in the adapter layer, and the second metal wire is disposed in the adapter layer and its two ends are exposed in the adapter layer.

10. The chip packaging structure according to any one of claims 1 to 9, characterized in that, The chip packaging structure also includes a fourth bump and a fifth bump; The fourth bump and the fifth bump are connected to the second chip; the two ends of the first metal wire are respectively connected to the first bump and the fourth bump, and the two ends of the second metal wire are respectively connected to the second bump and the fifth bump; A portion of the second metal line is also located adjacent to the fourth bump on the side away from the second chip and is spaced apart from the fourth bump.

11. A chip packaging structure, characterized in that, The chip packaging structure includes: First chip; Second chip; Multiple bumps are connected to the first chip; the multiple bumps include a first bump and a second bump; A first metal wire, the two ends of which are respectively connected to the first bump and the second chip; A second metal wire, the two ends of which are respectively connected to the second bump and the second chip; at least a portion of the second metal wire is adjacent to at least a portion of the first metal wire; A fourth metal wire is insulated relative to the plurality of bumps; the fourth metal wire has a third sub-segment and a fourth sub-segment connected to each other; The third sub-segment is adjacent to the first bump on the side away from the first chip and is spaced apart from the first bump; the fourth sub-segment is adjacent to the second bump on the side away from the first chip and is spaced apart from the second bump.

12. The chip packaging structure according to claim 11, characterized in that, The plurality of protrusions are arranged along a first direction and the plurality of protrusions are arranged along a second direction; the first direction and the second direction intersect; the plurality of protrusions further include a third protrusion; The second protrusion is adjacent to the first protrusion and located on one side of the first protrusion along the first direction; the third protrusion is adjacent to the first protrusion and located on one side of the first protrusion along the second direction. The fourth metal line also has a fifth sub-segment, which is connected to the third sub-segment; the fifth sub-segment is adjacent to the third bump on the side away from the first chip and is spaced apart from the third bump.

13. An electronic device, characterized in that, The electronic device includes: Circuit board; The chip packaging structure as described in any one of claims 1 to 12; the chip packaging structure is connected to the circuit board.

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