Method for optimizing SRAM performance based on mathematical optimization through automatic deformation circuit generation and apparatus therefor

Abstract

According to various embodiments of the present invention, an apparatus for optimizing SRAM performance based on mathematical optimization may set at least one initial design variable for designing an SRAM circuit, simulate using the at least one initial design variable, train at least one probabilistic model for power consumption or constraint conditions of the SRAM circuit on the basis of a simulation result, and select a subsequent design variable for designing the optimized SRAM circuit by using an acquisition function based on the probabilistic model.

Description

Method for optimizing SRAM performance based on mathematical optimization through automatic transformation circuit generation and apparatus for the same

[0001] The present invention relates to a method for optimizing SRAM performance based on mathematical optimization and an apparatus for the same.

[0002] The research related to the present invention is related to the research project 'Core Development of PIM AI Semiconductor (No. RS-2023-00222085)', which was conducted with funding from the Ministry of Science and ICT and support from the Korea Institute of Information and Communication Technology Planning and Evaluation, and the lead organization is the Yonsei University Industry-Academic Cooperation Foundation. The research project title is 'Development of Memory Module and Memory Compiler for Non-Volatile PIM Optimized for Data Characteristics and Data Access Characteristics of AI Processors', and the research period is from April 1, 2023 to December 31, 2026.

[0003] In addition, the research related to the present invention is related to the 'Nano Device Application Research Institute (No. 2018R1A6A1A03025242)', which is a Basic Research Project in Science and Engineering, Basic Research Infrastructure Establishment Project, and University Key Research Institute Support Project funded by the Ministry of Education and supported by the National Research Foundation of Korea, and the lead institution is the Industry-Academic Cooperation Foundation of Kwangwoon University. The research period is from June 1, 2018 to February 28, 2027.

[0004] Finally, the research related to the present invention is related to the 'Research and Development of Neuro-chip Design Technology Mimicking the Human Nervous System and Neuro-computing Platform (No. 2710007997)', a University ICT Research Center Development Support Project funded by the Ministry of Science and ICT and supported by the Korea Institute of Information and Communication Technology Planning and Evaluation, and the lead organization is the Industry-Academic Cooperation Foundation of Kwangwoon University. The research period is from January 1, 2024 to December 31, 2024.

[0005] The content described in this section merely provides background information regarding the present embodiment and does not constitute prior art.

[0006] Static Random Access Memory (SRAM) is a high-speed memory that uses a transistor flip-flop structure to store data and retains data as long as power is supplied. Unlike DRAM, it does not require a refresh process, providing fast data access speeds, and is primarily used in cache memory or embedded systems. Although SRAM is faster than DRAM, it has the disadvantage of higher manufacturing costs and lower storage capacity per unit area due to the structural requirement of more transistors. Therefore, while it is suitable for tasks requiring high speed, DRAM is preferred for large-scale data storage.

[0007] In SRAM design, the leaf cell is a fundamental component of the memory block and serves as the unit forming the memory cell array. Generally, a leaf cell is based on a flip-flop structure composed of six transistors and performs data storage, reading, and writing operations. Optimizing high-speed operation and power consumption is a key challenge in leaf cell design, which is achieved by minimizing cell size and optimizing signal transmission paths. Furthermore, the arrangement method and wiring layout of the leaf cells significantly influence the performance and area efficiency of the SRAM.

[0008] In SRAM design, compilers are used as tools to automate the design of SRAMs that meet specific requirements. When a user inputs requirements such as desired memory size, speed, and power consumption, the compiler automatically designs and integrates key components—including optimized memory cell arrays, address decoders, sense amplifiers, and output buffers—accordingly. Compilers are useful for shortening design time and reducing iteration, while providing high reproducibility through standardized design methods. This enables designers to rapidly customize SRAMs for various applications.

[0009] (Patent Document 0001) Republic of Korea Registered Patent Publication No. 10-2024-0128520 (August 26, 2024)

[0010] The objective of the present invention is to provide a method for optimizing SRAM performance based on mathematical optimization through automatic modified circuit generation, which utilizes machine learning and automated circuit generation technology to effectively optimize the power consumption, speed, and leakage current of SRAM, and enables detailed design optimization that conventional compilers cannot provide, as well as an apparatus for such optimization.

[0011] Other unspecified objects of the present invention may be further considered to the extent that they can be easily inferred from the following detailed description and effects.

[0012] An SRAM performance optimization device based on mathematical optimization according to an embodiment of the present invention for achieving the above-described purpose comprises: a memory storing one or more programs for optimizing SRAM performance based on a mathematical optimization technique; and one or more processors that perform operations according to the one or more programs. The processors may set at least one initial design variable for designing an SRAM circuit, simulate using the at least one initial design variable, learn at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results, and select subsequent design variables for an optimized SRAM circuit design using an acquisition function based on the probabilistic model.

[0013] The above initial design variable is characterized by including a first initial design variable which is an integer type design variable or a second initial design variable which is a real number type design variable.

[0014] The first initial design variable includes the number of inverters or stacks, and the second initial design variable includes the transistor size or threshold voltage.

[0015] The above processor is characterized by performing a first simulation to obtain power or performance of an SRAM circuit or a second simulation to obtain timing or yield of an SRAM circuit during the process of simulating at least one initial design variable.

[0016] The processor is characterized by normalizing at least one initial design variable or subsequent design variable within a predetermined numerical range.

[0017] The above processor is characterized by, in the process of learning at least one probabilistic model for power consumption or constraints of an SRAM circuit based on simulation results, learning a first probabilistic model for power or performance of an SRAM circuit or learning a second probabilistic model for constraints of an SRAM circuit using the normalized initial design variable or the normalized subsequent design variable.

[0018] The processor is characterized by repeating a mathematical optimization process more than a predetermined standard number of times, in which it simulates again using the subsequent design variables, further trains the probabilistic model based on the simulation results, and selects the subsequent design variables with a high probability of optimization again using an acquisition function based on the further trained probabilistic model.

[0019] The processor is characterized by, if the mathematical optimization process is not repeated more than a predetermined reference number of times, denormalizing the re-selected subsequent design variable, adjusting values ​​less than 1 for at least one of the denormalized subsequent design variables to integers, and performing the mathematical optimization process again by performing the simulation again using the integerized subsequent design variable.

[0020] The above processor is characterized by determining the re-selected subsequent design variable as the final design variable for SRAM circuit optimization when the above mathematical optimization process is repeated more than a predetermined reference number of times.

[0021] A method performed in a device comprising a memory storing one or more programs for optimizing SRAM performance based on a mathematical optimization technique according to an embodiment of the present invention for achieving the above-described purpose, and one or more processors performing operations according to said one or more programs, may include: a step of setting at least one initial design variable for designing an SRAM circuit and simulating using said at least one initial design variable; a step of learning at least one probabilistic model for power consumption or constraints of said SRAM circuit based on said simulation results; and a step of selecting a subsequent design variable for designing an optimized SRAM circuit using an acquisition function based on said probabilistic model.

[0022] The step of simulating using at least one initial design variable is characterized by including: a first simulation execution step for obtaining power or performance of the SRAM circuit; or a second simulation execution step for obtaining timing or yield of the SRAM circuit.

[0023] The step of training at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results above is characterized by including the step of normalizing at least one initial design variable or subsequent design variable within a predetermined numerical range.

[0024] The step of learning at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results above is characterized by including: a step of learning a first probabilistic model for power or performance of the SRAM circuit using the normalized initial design variables or the normalized subsequent design variables; or a step of learning a second probabilistic model for constraints of the SRAM circuit.

[0025] Herein, the method further comprises the step of repeating a mathematical optimization process more than a predetermined standard number of times, wherein the subsequent design variable is simulated again using the aforementioned subsequent design variable, the probabilistic model is further trained based on the simulation results, and the subsequent design variable with a high probability of optimization is selected again using an acquisition function based on the additionally trained probabilistic model.

[0026] A computer program according to one embodiment of the present invention for achieving the above-described purpose is stored in a computer-readable recording medium and executes any one of the mathematical optimization-based SRAM performance optimization methods described above on a computer.

[0027] As described above, according to one embodiment of the present invention, by applying a mathematical optimization-based SRAM performance optimization method and an apparatus for the same through automatic deformation circuit generation, the power consumption, speed, and leakage current of the SRAM are effectively optimized by utilizing machine learning and automated circuit generation technology, and detailed design optimization that conventional compilers cannot provide is possible.

[0028] Even if an effect is not explicitly mentioned herein, the effects and potential effects described in the following specification expected by the technical features of the present invention are treated as described in the specification of the present invention.

[0029] FIG. 1 is a flowchart illustrating a method for optimizing SRAM performance based on mathematical optimization through automatic deformation circuit generation according to an embodiment of the present invention.

[0030] FIG. 2 is a detailed flowchart for explaining step S100 in more detail in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention illustrated in FIG. 1.

[0031] FIG. 3 is a detailed flowchart for explaining step S200 in more detail in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention illustrated in FIG. 1.

[0032] FIG. 4 is a detailed flowchart for explaining step S300 in more detail in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention illustrated in FIG. 1.

[0033] Figure 5 is a diagram showing the operation process of a compiler.

[0034] FIG. 6 is a diagram schematically illustrating the operation process of a mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to an embodiment of the present invention.

[0035] FIG. 7 is a diagram showing the process of performing Bayesian optimization used in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention.

[0036] Figure 8 is a diagram illustrating the automatic layout mechanism of a deformation inverter chain.

[0037] Figure 9 is a diagram illustrating the automatic layout mechanism of stack deformation.

[0038] Figure 10 is a diagram illustrating the automatic layout mechanism of critical voltage variation.

[0039] FIG. 11 is a table showing the results of optimizing power consumption by applying a mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention.

[0040] FIG. 12 is a table showing the results of optimizing access time by applying a mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention.

[0041] FIG. 13 is a table showing the results of optimizing current leakage by applying a mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention.

[0042] FIG. 14 is a diagram illustrating the hardware configuration of an SRAM performance optimization device based on mathematical optimization through automatic deformation circuit generation according to an embodiment of the present invention.

[0043] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The advantages and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the attached drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning that is commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0044] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, terms such as “have,” “may have,” “include,” or “may include” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Terms including ordinal numbers, such as “second,” “first,” etc., may be used to describe various components, but said components are not limited by said terms.

[0045] The above terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. The term "and / or" includes a combination of a plurality of related described items or any of a plurality of related described items.

[0046] In this specification, identification symbols (e.g., a, b, c, etc.) for each step are used for convenience of explanation and do not indicate the order of the steps; the steps may occur differently from the specified order unless the context clearly indicates a specific order. That is, the steps may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

[0047] This specification discloses a machine learning-based method for optimizing SRAM power, speed, and leakage current through the generation of automatic modified circuits. The present invention relates to a method for implementing design optimization based on SRAM size, which is not supported by existing SRAM compilers, using machine learning and automatic layout modification, and for reducing power and leakage current while increasing speed.

[0048] The present invention relates to a method capable of solving performance problems of SRAM circuits created using conventionally used SRAM compilers. This methodology involves modified circuit generation and V th By using changes to optimize the important PPA (power performance area) and leakage current in semiconductors, the problem of inefficient SRAM compilers can be solved.

[0049] The method disclosed in this invention allows not only general users of compilers to optimize circuit designs for desired SRAM instance sizes, but also companies manufacturing compilers to produce compilers that generate SRAMs with optimized designs for each SRAM instance size by utilizing this method. This can subsequently improve the energy efficiency, area, operating speed, and leakage current of many integrated circuits that use compilers.

[0050] This technology is applicable to memory designs such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), and has the potential for partial application in various electronic devices, including mobile phones, wireless earphones, IoT home appliances, computers, and autonomous vehicles. Recently, the demand for integrated circuits has been expanding due to the increased use of cutting-edge systems such as mobile phones, computers, and autonomous vehicles. As SRAM is utilized as a critical memory in integrated circuits, interest in technologies to reduce power consumption is continuously growing.

[0051] Various embodiments of the mathematical optimization-based SRAM performance optimization method and apparatus for the same (hereinafter also referred to as the mathematical optimization-based SRAM performance optimization method and apparatus) according to the present invention will be described in detail below with reference to the attached drawings.

[0052] FIG. 1 is a flowchart illustrating a method for optimizing SRAM performance based on mathematical optimization through automatic deformation circuit generation according to an embodiment of the present invention.

[0053] A mathematical optimization-based SRAM performance optimization method may be performed in a device comprising a memory that stores one or more programs for optimizing SRAM performance based on a mathematical optimization technique and one or more processors that perform operations according to one or more programs. For example, a mathematical optimization-based SRAM performance optimization method may be performed in a mathematical optimization-based SRAM performance optimization device illustrated in FIG. 14.

[0054] In step S100, the processor can set at least one initial design variable for designing an SRAM circuit and simulate using at least one initial design variable.

[0055] The simulation used in the present invention may be SPICE (Simulation Program with Integrated Circuit Emphasis), but is not necessarily limited thereto.

[0056] The initial design variables may include a first initial design variable that is an integer design variable or a second initial design variable that is a real number design variable.

[0057] The first initial design variable includes the number of inverters or stacks, and the second initial design variable may include the transistor size or threshold voltage.

[0058] In step S200, the processor can learn at least one probabilistic model of the power consumption or constraints of the SRAM circuit based on the simulation results.

[0059] In step S300, the processor can select subsequent design variables for an optimized SRAM circuit design using an acquisition function based on a probabilistic model.

[0060] FIG. 2 is a detailed flowchart for explaining step S100 in more detail in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention illustrated in FIG. 1.

[0061] In step S110, the processor can determine initial design variables.

[0062] In step S120, the processor can perform a first simulation to obtain the power or performance of the SRAM circuit.

[0063] In step S130, the processor may perform a second simulation to obtain the timing or yield of the SRAM circuit.

[0064] Unlike what is shown in FIG. 2, steps S120 and S130 may be performed optionally.

[0065] FIG. 3 is a detailed flowchart for explaining step S200 in more detail in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention illustrated in FIG. 1.

[0066] In step S210, the processor may normalize at least one initial design variable or subsequent design variable within a predetermined numerical range (e.g., 0 or greater, less than 1). Here, the processor normalizing and processing the subsequent design variable may be normalizing and processing the most recently determined subsequent design variable, i.e., the latest subsequent design variable. All subsequent design variables referred to herein may mean the latest subsequent design variable.

[0067] In step S220, the processor can train a first probabilistic model for the power or performance of the SRAM circuit using normalized initial design variables or normalized subsequent design variables.

[0068] In step S230, the processor can train a second probabilistic model for the constraints of the SRAM circuit.

[0069] In the present invention, a Gaussian Process (GP) model may be applied as the probabilistic model, but it is not necessarily limited thereto.

[0070] The processor can utilize the values ​​output from the simulation results as input data to train a probabilistic model. The simulation results can be used as a criterion for determining subsequent design variables during the mathematical optimization process. The probabilistic model can learn the relationship between initial design variables and results by using the simulation results as data. The learned probabilistic model can subsequently be utilized to predict power or performance in the design space and to recommend optimal design variables in mathematical optimization.

[0071] The simulation result may refer to a function value derived by evaluating the performance and constraints of an SRAM circuit through simulation, applying a specific combination of design variables, namely a first initial design variable, or a first subsequent design variable (t) corresponding to the first initial design variable, or a second initial design variable, or a second subsequent design variable (x) corresponding to the second initial design variable. For example, if the design variable t is set to 4 inverters and 2 stacks, and x is set to a transistor size of 30 nanometers and a threshold voltage of 0.7 volts, the simulation result may be expressed as the following figures. First, as performance indicators, dynamic power consumption can be measured as 10 microwatts and access time as 2 nanoseconds. Second, as constraints, the timing delay satisfies 3 nanoseconds or less, and the yield can be calculated as 95 percent. These results are used for training a Gaussian Process model and can serve as a criterion for predicting and improving optimal design variables during the Bayesian Optimization process.

[0072] The first probabilistic model is utilized to achieve optimization goals, such as minimizing power consumption or improving performance, by learning design variables—specifically the first and second initial design variables—as well as power or performance values ​​based on simulation results. Second, the second probabilistic model models design constraints such as timing, yield, and power. It learns constraint values ​​derived from simulations to predict whether specific design variables satisfy these constraints and is used to limit candidate design variables during the optimization process.

[0073] FIG. 4 is a detailed flowchart for explaining step S300 in more detail in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention illustrated in FIG. 1.

[0074] In step S310, the processor can determine whether the mathematical optimization process has been repeated more than a predetermined reference number of times. If the mathematical optimization process has been repeated more than a predetermined reference number of times, step S320 may be performed subsequently, and if the mathematical optimization process has not been repeated more than a predetermined reference number of times, step S330 may be performed subsequently.

[0075] Subsequent design variables may include a first subsequent design variable corresponding to a first initial design variable or a second subsequent design variable corresponding to a second initial design variable.

[0076] The first subsequent design variable is a variable used to adjust the structural characteristics of the SRAM circuit, such as the number of inverters or stacks, and is derived based on the first initial design variable. The first initial design variable evaluates circuit performance indicators (e.g., power consumption, access time) through simulation, and the Gaussian Process performance model learns from these evaluation results. Bayesian Optimization utilizes the learned performance model and the acquisition function to propose a new combination of structural variables with high optimization potential, defining this as the first subsequent design variable.

[0077] The second subsequent design variables are used to adjust the physical characteristics of the SRAM circuit, such as transistor size or threshold voltage, and are derived based on the second initial design variables. The second initial design variables evaluate circuit constraints (e.g., timing delay, yield) through simulation, and the Gaussian Process constraint model learns from these evaluation results. Based on the learned constraint model and the acquisition function, Bayesian Optimization proposes a new combination of physical variables that can maintain or improve performance while satisfying the constraints, and defines this as the second subsequent design variables.

[0078] In the present invention, the mathematical optimization process may refer to a process of re-simulating using subsequent design variables, further training a probabilistic model based on the simulation results, and re-selecting subsequent design variables with a high probability of optimization using an acquisition function based on the additionally trained probabilistic model. That is, in the present invention, the mathematical optimization process may refer to the operations performed in steps S330 through S370. In the present invention, mathematical optimization may refer to Bayesian optimization, but is not necessarily limited thereto.

[0079] The processor can generate a modified circuit based on subsequent design variables (e.g., threshold voltage) in each iteration of mathematical optimization.

[0080] In step S320, the processor may output design variables that satisfy performance goals or constraints derived by iteratively performing a mathematical optimization process. Here, the output design variables may be final design variables.

[0081] In step S330, the processor can select subsequent design variables using the acquisition function.

[0082] Here, the acquisition function (acq WEI (t, x), where t is the first initial design variable and x is the second initial design variable, may represent the expected improvement calculated based on the first or second probabilistic model. The subsequent design variable may be set to the point where the gain function is maximized.

[0083] Bayesian optimization uses a trained GP model to predict the relationships between design variables and power, performance, and constraints, and selects the next candidate design variable with the highest potential for optimization through an acquisition function. The mathematical model supports efficient exploration by providing predictions that include the uncertainty of the design space. The processor iteratively performs this to explore the optimal SRAM design variables.

[0084] In step S340, the processor can normalize the selected subsequent design variables.

[0085] In step S350, the processor may convert the denormalized subsequent design variable into an integer by adjusting the values ​​less than 1. The processor may convert the subsequent design variable into an integer by adjusting the decimal places of the values ​​less than 1 using rounding, truncation, ceiling, or flooring.

[0086] For example, since decimal values ​​may occur when a processor denormalizes a normalized value, it can round them to convert them to integers. V th Variables such as and t must be treated as integers, but V th is an integer value with limited options, such as the threshold voltage option of a MOSFET, and t is a variable clearly expressed as an integer, such as the number of inverters or the number of stacks. However, denormalization from the normalized range can result in decimal values ​​like 4.7, and this is rounded to 5 to satisfy physical meaning and design conditions. In other words, it is not a process of rounding an already integer value again, but rather a process of converting the decimal value generated during the denormalization process back into an integer.

[0087] In step S360, the processor can generate a modified circuit using integerized subsequent design variables.

[0088] At step S370, the processor may resume operations from step S100. When resuming operations from step S100, that is, after processing the initial design variables, subsequent design variables may be processed instead of the initial design variables. In other words, the initial design variables are processed only once, and subsequent design variables may be newly updated and processed in subsequent processes.

[0089] To summarize the operations described through Figures 1 to 4, in the start and initialization phase, the process begins by randomly setting initial design variables t and x. Here, t is a structural design variable such as the number of inverters and the number of stacks, and x is a physical variable representing transistor size and threshold voltage. The initial design variables serve as the starting point for Bayesian Optimization and are gradually improved through optimization.

[0090] In the SPICE simulation execution phase, the SPICE simulation is run in two directions based on the initial design variables t and x.

[0091] In power and performance evaluation, the processor assesses the power consumption and performance of the circuit through simulation. Power includes dynamic power and static power (leakage current), while performance refers to indicators such as data access time and processing speed.

[0092] In timing and yield evaluation, the processor assesses timing constraints and yield through simulation. Timing refers to data transmission delay time, while yield represents stability against process variability.

[0093] In the variable normalization step, the design variables t and x are normalized to a common range between 0 and 1 based on the simulation results. This step aligns variables with different units to the same range, enabling the Gaussian Process model to train efficiently. The normalized values ​​are used to determine the optimal search point during the Bayesian Optimization process.

[0094] In the Gaussian Process model training phase, two Gaussian Process models are trained based on normalized design variables and simulation results.

[0095] In performance model training, the Gaussian Process model fs learns the relationship between design variables and power or performance. This allows for the prediction of the impact of specific variable values ​​on circuit performance.

[0096] In constraint model learning, the Gaussian Process model ci learns the relationships between design variables and constraints such as timing and yield. Through this, it predicts whether the design variables satisfy the constraints.

[0097] In the selection of new variables based on the gain function, new design variables t and x are selected using the gain function based on the prediction results of the Gaussian Process model. The gain function identifies the point with the highest potential for optimization using criteria such as the expected improvement value. Through this, the optimal design point is efficiently explored while maintaining a balance between exploration and exploitation.

[0098] In the denormalization and rounding steps, the design variables selected in the acquisition function are converted to their original design ranges through the denormalization process. At this stage, if integer variables such as the number of inverters and stacks have decimal values, they are converted into physically valid integer values ​​through the rounding process. The converted values ​​are used as specific input values ​​for circuit design.

[0099] In the circuit variation generation step, new circuit variations are generated based on the denormalized and rounded design variables t and x. These modified circuits are re-evaluated through SPICE simulation to calculate metrics such as power, performance, timing, and yield. This process enables the iterative exploration of optimization.

[0100] In the iteration verification step, after the simulation, Gaussian Process model training, and design variable selection are completed, it is checked whether sufficient iterations have been performed. If the set threshold number of iterations or the convergence condition has not been reached, new design variables are selected to continue the optimization process. If the criteria are met, the optimization process terminates.

[0101] In the optimal circuit topology return step, when the optimal combination of design variables satisfying power, performance, and constraints is derived through an iterative process, the final optimal circuit topology is returned. This result is a value verified through Bayesian Optimization and SPICE simulation, signifying a circuit design with optimized power consumption, speed, and leakage current for the SRAM.

[0102] The operation according to the present invention describes the entire process of deriving an optimal SRAM circuit design by combining SPICE simulation and a Gaussian Process model based on Bayesian Optimization. Through the normalization and denormalization of variables, search based on acquisition functions, and the iteration of simulation and model training, an optimized circuit is efficiently identified while simultaneously considering performance and constraints.

[0103] Although FIGS. 1 to 4 describe each process as being executed sequentially, this is merely an illustrative description, and a person skilled in the art may modify and adapt the process in various ways without departing from the essential characteristics of the embodiments of the present invention, such as changing the order described in FIGS. 1 to 4, executing one or more processes in parallel, or adding other processes.

[0104] FIG. 5 is a diagram showing the operation process of a compiler. FIG. 6 is a diagram schematically illustrating the operation process of a mathematical optimization-based SRAM performance optimization method through automatic transformation circuit generation according to an embodiment of the present invention.

[0105] The present invention relates to the number of inverters, the number of stacks, and V optimized according to instance size, based on Bayesian Optimization (BO), one of the machine learning techniques. thThis relates to a method for designing BO. BO assumes an unknown objective function that receives input values, finds the optimal input value based on probabilistic estimation results, and recommends a candidate for the next input value. A leaf cell is a single unit that groups parts performing the same operation among the circuits constituting an SRAM. Generally used SRAM compilers create SRAM using leaf cells that are pre-designed to match the instance size. The SRAM created in this way consists entirely of the same leaf cells that are not optimized for the instance size. In this invention, the design of the leaf cell is optimized according to the instance size, thereby reducing power and leakage current and increasing speed without sacrificing various margins, operating time, size, and other constraints.

[0106] FIG. 7 is a diagram showing the process of performing Bayesian optimization used in the mathematical optimization-based SRAM performance optimization method through automatic deformation circuit generation according to one embodiment of the present invention.

[0107] Bayesian optimization (BO) requires two initial values ​​to recommend the following values. These initial values ​​are typically the basic transistor size designed in the SRAM circuit, V. th Set (x*), the number of inverters, the number of stacks (t*), and two cases of x* and t* with values ​​slightly smaller than that (or two random x* and t* values).

[0108] Subsequently, the optimization targets (power, speed, or leakage current) and constraints are extracted through simulation, and their values ​​are input into BO (Train GP model). At this time, t* and V thUnlike transistor sizes, which typically have values ​​in nm units, is used mapped to integer values. Therefore, to reduce numerical discrepancies regarding recommended values, it is normalized to a common range of [0,1]. Recommended values ​​normalized through BO (acq in Fig. 7) WEI If (x,t) is the highest point is received, all recommended values ​​are denormalized. Also, V having integer values th , t* is rounded, and a modified circuit corresponding to the parameter value is generated. Subsequently, the optimization target and constraint values ​​are extracted again through simulation. This process is executed for a specified number of iterations, and after all iterations are completed, the MOSFET size, V, that has the minimum power (or speed or leakage current) while satisfying the constraints among the power (or speed or leakage current) values ​​obtained so far is selected. th It provides the number of inverters and stacks, the optimal modified circuit, and the minimum power. x* and t* allow for the use of a large number of transistors and inverters, and enable more effective performance optimization by simultaneously optimizing many parameters while satisfying various constraints.

[0109] Figure 8 is a diagram illustrating the automatic layout mechanism of a deformation inverter chain.

[0110] Figure 8 illustrates the process of removing two connected inverters, INV[m] and INV[m+1], in the layout. In Figures 8(a) and 8(b), the coordinates of INV[m] and INV[m+1], TRCoord[TR m[i:] ], TRCoord[TR m+1[j:] Extract ] and the OD area corresponding to each inverter OD groupArea [m], OD groupArea Defined as [m+1]. In (c), (d), and (e), OD groupArea [m], OD groupAreaThe metal layers connected to [m+1] are defined as SDRoute[m] and SDRoute[m+1], respectively. Among these, the metal layer connected to the power line (VDD or VSS) is defined as PowerRoute[m], and the metal layers excluding PowerRoute[m] are defined as outRoute[m] and outRoute[m+1]. Next, (f) removes OD and CO connected to outRoute[m], INV[m], and INV[m+1]. Subsequently, in (g), TRCoord[TR m[i:] PO connected to ] first Find and PO first Store the CO and metal layers in contact with inRoute[m]. Then, in (h), connect inRoute[m] and outRoute[m+1] with a metal layer.

[0111] Figure 9 is a diagram illustrating the automatic layout mechanism of stack deformation.

[0112] Figure 9 shows a transistor stack structure (TR) in the layout. m , TR m+1 , TR m+2 TR in ) m This is an example of removing. In Fig. 9(a), TR is removed through LVS. m , TR m+1 , TR m+2 TRCoord[TR [m:m+2] Extract ] and the OD region corresponding to each transistor OD Area [m], OD Area [m+1], OD Area Defined as [m+2]. Then, in (b) and (c), OD Area [m] and OD Area OD, the region shared by [m+1] sharedArea Define [m], and OD AreaThe region excluding this from [m] is defined as DelOD[m]. Then, the CO layer above DelOD[m] is defined as listCO[m]. In (d), OD Area Identify the CO and metal layers connected to the source and drain regions of [m], and store them in SNet[m] and DNet[m] along with the source and drain regions. OD Area This is repeated in [m+1] as well. (e) is TR m and TR m+1 The layer above the common region among the source and drain regions is defined as CNet[m]. Then, in (f) and (g), the remaining metal layer after removing DelOD[m] and listCO[m] from DNet[m] is defined as M1onCO[m], and newCO[m] is created in CNet[m]. Finally, in (h), newMetal[m] is created on newCO[m], and M1onCO[m] and newMetal[m] are connected.

[0113] Figure 10 is a diagram illustrating the automatic layout mechanism of critical voltage variation.

[0114] TR in the layout of Fig. 10 target The V above th This is an example of selectively changing the layer, and low-V th high-V in (LVT) th It illustrates the process of changing to (HVT). In Fig. 10(a), TR through LVS target TRCoord[TR target Find ] and TR target TR sharing OD share , TR target The OD and LVT layers in contact with each other are OD target , LVT cover It is defined as such. In (b) and (c), LVT cover The PO layer in contact with PO intersect Lo, POintersect Contacting and OD target Define the OD layer excluding as listOD. In (d), OD target POs on both sides of PO, respectively Left , PO Right Defined as. OD target and PO Left or PO Right Space, the distance between PO_Vth is V th It is used to determine the size of the area to be changed. In (e) and (f), V is considered by taking design rules into account. th Find the chopArea, which is the region to be changed, and V th Change . At this time, Space ODano_Vth If the length is smaller than the design rule, chop Area OD another must be included.

[0115] FIG. 11 is a table showing the results of optimizing power consumption by applying a mathematical optimization-based SRAM performance optimization method through automatic transformation circuit generation according to an embodiment of the present invention. FIG. 12 is a table showing the results of optimizing access time by applying a mathematical optimization-based SRAM performance optimization method through automatic transformation circuit generation according to an embodiment of the present invention. FIG. 13 is a table showing the results of optimizing current leakage by applying a mathematical optimization-based SRAM performance optimization method through automatic transformation circuit generation according to an embodiment of the present invention.

[0116] In Figure 11, which aims to minimize power consumption, power consumption can be reduced by an average of about 31.51%, and in Figure 12, which shows the results aimed at minimizing the access time, which is the time it takes to retrieve data stored in SRAM, it can be seen that it is reduced by an average of 36.01%.

[0117] In Figure 13, it can be seen that the leakage current is reduced by an average of 32.33%. Even as the performance of power, time, and leakage current increases, it can be confirmed that there is no degradation in performance for performance other than the optimization target, without violating the specified values ​​set as constraints. From the experimental results, it can be confirmed that the present invention can optimize MOSFET size, number of stacks, number of inverters, and Vth according to SRAM instance size, which requires a significant investment of manpower and time, without performance degradation.

[0118] FIG. 14 is a diagram illustrating the hardware configuration of an SRAM performance optimization device based on mathematical optimization through automatic deformation circuit generation according to an embodiment of the present invention.

[0119] An SRAM performance optimization device (100) based on mathematical optimization through automatic deformation circuit generation includes at least one processor (110), a computer-readable storage medium (120), and a communication bus (150).

[0120] The processor (110) can be controlled to operate as a mathematical optimization-based SRAM performance optimization device (100) through automatic transformation circuit generation. For example, the processor (110) can execute one or more programs (121) stored in a computer-readable storage medium (120). One or more programs (121) may include one or more computer-executable instructions, and the computer-executable instructions may be configured to cause the mathematical optimization-based SRAM performance optimization device (100) through automatic transformation circuit generation to perform operations according to an exemplary embodiment when executed by the processor (110).

[0121] A computer-readable storage medium (120) is configured to store computer-executable instructions or program code, program data and / or other suitable forms of information. Computer-executable instructions or program code, program data and / or other suitable forms of information may also be provided through an input / output interface (130) or a communication interface (140). A program (121) stored in a computer-readable storage medium (120) includes a set of instructions executable by a processor (110). In one embodiment, the computer-readable storage medium (120) may be memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other forms of storage media that can store desired information and be accessed by a mathematical optimization-based SRAM performance optimization device (100) through automatic transformation circuit generation, or a suitable combination thereof.

[0122] The communication bus (150) interconnects various other components of the mathematical optimization-based SRAM performance optimization device (100), including the processor (110) and the computer-readable storage medium (120), through automatic deformation circuit generation.

[0123] The SRAM performance optimization device (100) based on mathematical optimization through automatic transformation circuit generation may also include one or more input / output interfaces (130) and one or more communication interfaces (140) that provide interfaces for one or more input / output devices. The input / output interface (130) and the communication interface (140) are connected to a communication bus (150). An input / output device (not shown) may be connected to other components of the SRAM performance optimization device (100) based on mathematical optimization through automatic transformation circuit generation via the input / output interface (130).

[0124] The processor (110) can set at least one initial design variable for designing an SRAM circuit, simulate using at least one initial design variable, learn at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results, and select subsequent design variables for an optimized SRAM circuit design using an acquisition function based on the probabilistic model.

[0125] The processor (110) can perform a first simulation to obtain power or performance of the SRAM circuit or a second simulation to obtain timing or yield of the SRAM circuit in the process of simulating at least one initial design variable.

[0126] The processor (110) can normalize at least one initial design variable or subsequent design variable within a predetermined numerical range.

[0127] In the process of learning at least one probabilistic model for power consumption or constraints of an SRAM circuit based on simulation results, the processor (110) may learn a first probabilistic model for power or performance of an SRAM circuit or learn a second probabilistic model for constraints of an SRAM circuit using normalized initial design variables or normalized subsequent design variables.

[0128] The processor (110) can repeat a mathematical optimization process more than a predetermined number of times, which involves simulating again using subsequent design variables, additionally training a probabilistic model based on the simulation results, and selecting subsequent design variables with a high probability of optimization again using an acquisition function based on the additionally trained probabilistic model.

[0129] If the mathematical optimization process is not repeated more than a predetermined number of times, the processor (110) can denormalize the selected subsequent design variable, adjust values ​​less than 1 for at least one of the denormalized subsequent design variables to integers, and perform the mathematical optimization process again by performing the simulation again using the integerized subsequent design variable.

[0130] If the mathematical optimization process is repeated more than a predetermined reference number of times, the processor (110) can determine the subsequently selected design variable as the final design variable for SRAM circuit optimization.

[0131] Not all blocks shown in FIG. 14 are essential components, and in other embodiments, some blocks connected to the mathematical optimization-based SRAM performance optimization device (100) through automatic deformation circuit generation may be added, changed, or deleted.

[0132] The present application also provides a computer storage medium. Program instructions are stored in the computer storage medium, and when the program instructions are executed by a processor, the mathematical optimization-based SRAM performance optimization method described above is realized.

[0133] A computer storage medium according to one embodiment of the present invention may be a U disk, SD card, PD optical drive, mobile hard disk, large capacity floppy drive, flash memory, multimedia memory card, server, etc., but is not necessarily limited thereto.

[0134] Although it is described that all components constituting the embodiments of the present invention described above are combined or operate in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all such components may be selectively combined in one or more ways to operate. Furthermore, while all such components may each be implemented as a single independent piece of hardware, they may also be implemented as a computer program having a program module that performs some or all of the combined functions in one or more pieces of hardware by selectively combining some or all of the components. Additionally, such a computer program may be stored on a computer-readable media such as a USB memory, CD disk, or flash memory, and read and executed by a computer to implement the embodiments of the present invention. Magnetic recording media, optical recording media, etc., may be included as recording media for the computer program.

[0135] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications, changes, and substitutions within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments and accompanying drawings. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

Claims

1. A memory storing one or more programs for optimizing SRAM performance based on mathematical optimization techniques; and one or more processors that perform operations according to the one or more programs; wherein the processors, At least one initial design variable for designing an SRAM circuit is set, and a simulation is performed using the at least one initial design variable. Based on the above simulation results, at least one probabilistic model for power consumption or constraints of the SRAM circuit is trained, and A mathematical optimization-based SRAM performance optimization device that selects subsequent design variables for an optimized SRAM circuit design using an acquisition function based on the above probabilistic model.

2. In Paragraph 1, The above initial design variables are, A mathematical optimization-based SRAM performance optimization device characterized by including a first initial design variable which is an integer design variable or a second initial design variable which is a real number design variable.

3. In Paragraph 2, The above first initial design variable is, Includes the number of inverters or stacks, A mathematical optimization-based SRAM performance optimization device characterized in that the above-mentioned second initial design variable includes transistor size or threshold voltage.

4. In Paragraph 1, The above processor is, In the process of simulating at least one initial design variable mentioned above, A mathematical optimization-based SRAM performance optimization device characterized by performing a first simulation to obtain power or performance of an SRAM circuit or a second simulation to obtain timing or yield of an SRAM circuit.

5. In Paragraph 1, The above processor is, A mathematical optimization-based SRAM performance optimization device characterized by normalizing at least one initial design variable or subsequent design variable within a predetermined numerical range.

6. In Paragraph 5, The above processor is, In the process of training at least one probabilistic model for power consumption or constraints of an SRAM circuit based on simulation results, A mathematical optimization-based SRAM performance optimization device characterized by training a first probabilistic model for the power or performance of an SRAM circuit or training a second probabilistic model for the constraints of an SRAM circuit using the normalized initial design variables or the normalized subsequent design variables.

7. In Paragraph 1, The above processor is, A mathematical optimization-based SRAM performance optimization device characterized by repeating a mathematical optimization process more than a predetermined reference number of times, wherein the subsequent design variables are simulated again using the aforementioned subsequent design variables, the probabilistic model is further trained based on the simulation results, and the subsequent design variables with a high probability of optimization are selected again using an acquisition function based on the further trained probabilistic model.

8. In Paragraph 7, The above processor is, If the above mathematical optimization process is not repeated more than a predetermined standard number of times, A mathematical optimization-based SRAM performance optimization device characterized by denormalizing the aforementioned re-selected subsequent design variable, adjusting values ​​less than 1 for at least one of the denormalized subsequent design variable to integers, and performing the mathematical optimization process again by performing a simulation again using the integerized subsequent design variable.

9. In Paragraph 7, The above processor is, If the above mathematical optimization process is repeated more than a predetermined standard number of times, A mathematical optimization-based SRAM performance optimization device characterized by determining the aforementioned re-selected subsequent design variable as the final design variable for SRAM circuit optimization.

10. A method performed in a device comprising a memory storing one or more programs for optimizing SRAM performance based on mathematical optimization techniques and one or more processors performing operations according to said one or more programs, A step of setting at least one initial design variable for designing an SRAM circuit and simulating using the at least one initial design variable; A step of training at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results above; and A method for optimizing SRAM performance based on mathematical optimization, comprising the step of selecting subsequent design variables for an optimized SRAM circuit design using an acquisition function based on the above probabilistic model.

11. In Paragraph 10, The step of simulating using the above-mentioned at least one initial design variable is, A mathematical optimization-based SRAM performance optimization method characterized by comprising: a first simulation execution step for obtaining power or performance of an SRAM circuit; or a second simulation execution step for obtaining timing or yield of an SRAM circuit.

12. In Paragraph 10, The step of training at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results above is, A mathematical optimization-based SRAM performance optimization method characterized by including the step of normalizing at least one initial design variable or subsequent design variable within a predetermined numerical range.

13. In Paragraph 12, The step of training at least one probabilistic model for power consumption or constraints of the SRAM circuit based on the simulation results above is, A step of training a first probabilistic model for the power or performance of an SRAM circuit using the normalized initial design variables or the normalized subsequent design variables; or A mathematical optimization-based SRAM performance optimization method characterized by including the step of training a second probabilistic model for constraints of an SRAM circuit.

14. In Paragraph 10, A method for optimizing SRAM performance based on mathematical optimization, further comprising the step of repeating a mathematical optimization process more than a predetermined number of times, wherein the subsequent design variable is simulated again using the aforementioned subsequent design variable, the probabilistic model is further trained based on the simulation results, and the subsequent design variable with a high probability of optimization is selected again using an acquisition function based on the additionally trained probabilistic model.

15. A computer program stored on a computer-readable recording medium for executing on a computer the mathematical optimization-based SRAM performance optimization method described in any one of paragraphs 10 through 14.

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